GAT transistor based on si / sic heterostructure and its cell structure

Abstract

The application discloses a GAT transistor based on a Si / SiC heterostructure and a cell structure thereof. The transistor comprises a core structure and a conductive trench structure, and both the structures comprise a drain, a SiC N+ substrate, a SiC N- epitaxial layer, a first deep P+ region and a second deep P+ region distributed at two ends of the SiC N- epitaxial layer, two gates located on the trench surfaces in the first deep P+ region and the second deep P+ region respectively, a Si N- epitaxial layer located on the SiC N- epitaxial layer between the first deep P+ region and the second deep P+ region, and a P- region located on the Si N- epitaxial layer. The core structure further comprises an N+ region, two dielectric layers and an emitter, the N+ region is located in the P- region, and the emitter is located on the N+ region between the two dielectric layers. The conductive trench structure further comprises a metal layer, a deep N+ region and two trenches, one trench penetrates through the P- region, the deep N+ region is located below the trench, the other trench is located in the central region of the deep N+ region, and the metal layer is located on the surface of the trench. The application can meet the comprehensive requirements of high-voltage and high-power scenes.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor device technology, specifically relating to a GAT-type transistor based on a Si / SiC heterostructure and its cell structure. Background Technology

[0002] As power electronics technology develops towards high voltage, high power, high frequency, and miniaturization, fields such as new energy, rail transportation, and aerospace are placing stringent demands on power semiconductor devices, requiring high voltage resistance, low loss, high temperature adaptability, and high reliability.

[0003] As a composite power device combining BJT and FET, gate-connected transistors (GATs) have been used in low-to-medium voltage scenarios below 800V due to their advantages such as wide safe operating area and strong resistance to secondary breakdown. However, existing Si-based GATs are limited by the characteristics of Si materials, resulting in significant bottlenecks: 1) Si has a small breakdown electric field and bandgap, requiring thicker substrates for high-voltage adaptation, leading to a surge in on-resistance and static losses, making it impossible to balance high voltage and low loss; 2) Low electron saturation drift velocity and significant carrier storage effect result in large dynamic losses at high frequencies, limiting the switching frequency; 3) Low thermal conductivity, with a maximum junction temperature not exceeding 150℃, leading to decreased reliability at high temperatures and high heat dissipation costs; 4) Unstable avalanche breakdown characteristics, weak surge and short-circuit resistance, requiring additional protection circuitry.

[0004] Existing alternatives in the industry still have shortcomings: IGBTs suffer from high high-frequency losses and weak resistance to secondary breakdown; SiC MOSFETs have low current density, high on-state voltage drop, and unresolved gate reliability issues, all of which fail to meet the comprehensive requirements of high-voltage, high-power applications. Therefore, overcoming the performance bottlenecks of Si-based GATs has become an urgent technical problem to be solved in this field. Summary of the Invention

[0005] To address the aforementioned problems in the prior art, this invention provides a GAT-type transistor based on a Si / SiC heterostructure and its cell structure.

[0006] The technical problem to be solved by this invention is achieved through the following technical solution: This invention provides a GAT-type transistor based on a Si / SiC heterostructure, comprising: a core structure and a conductive trench structure; Both the core structure and the conductive trench structure include: A drain electrode, a SiC N+ substrate, and a SiC N- epitaxial layer distributed from bottom to top along a first direction; The first deep P+ region and the second deep P+ region are symmetrically distributed at both ends of the SiC N- epitaxial layer along the second direction, which is perpendicular to the first direction. The first gate and the second gate are respectively located in the trench in the first deep P+ region and the sidewall and bottom surface of the trench in the second deep P+ region; Si N- epitaxial layer, located on the upper surface of a portion of the SiC N- epitaxial layer between the first deep P+ region and the second deep P+ region; The P-region is located on the upper surface of the Si N-epitaxial layer; The core structure further includes: an N+ region, a first dielectric layer, a second dielectric layer, and an emitter, wherein the N+ region is located within the P- region, and the emitter is in contact with the upper surface of a portion of the N+ region located between the first dielectric layer and the second dielectric layer; The conductive trench structure further includes: a metal layer, a deep N+ region, a trench, and a channel, wherein the channel penetrates the P- region and its bottom contacts the upper surface of the Si N- epitaxial layer, the deep N+ region is located below the channel, the channel is located in the central region of the deep N+ region, and the metal layer is located on the sidewalls and bottom surface of the channel.

[0007] In some embodiments, the first dielectric layer, the second dielectric layer, and the emitter constitute a first structure, the metal layer, the deep N+ region, the trench, and the trench constitute a second structure, and the first structure and the second structure are spaced apart along a third direction, which is perpendicular to both the second direction and the first direction.

[0008] In some embodiments, along the first direction, the thicknesses of both the first deep P+ region and the second deep P+ region are greater than the thickness of the Si N- epitaxial layer.

[0009] In some embodiments, along the second direction, the width of the trench is less than the width of the first deep P+ region, and the width of the trench is less than the width of the second deep P+ region; along the first direction, the depth of the trench is less than the depth of the first deep P+ region, and the depth of the trench is less than the depth of the second deep P+ region.

[0010] In some embodiments, along the first direction, the thickness of the P-region is greater than or equal to the thickness of the Si N-epitaxial layer.

[0011] In some embodiments, the first dielectric layer simultaneously covers a portion of the upper surface of the P- region, a portion of the upper surface of the first deep P+ region, and a portion of the upper surface of the N+ region; the second dielectric layer simultaneously covers a portion of the upper surface of the P- region, a portion of the upper surface of the second deep P+ region, and a portion of the upper surface of the N+ region.

[0012] In some embodiments, the deep N+ region penetrates the Si N- epitaxial layer along the first direction and extends downward into the interior of the SiC N- epitaxial layer.

[0013] In some embodiments, the trench is symmetrical about the central axis of the deep N+ region, and the depth of the trench is less than or equal to the depth of the deep N+ region along the first direction.

[0014] In some embodiments, the material of the metal layer is Ni.

[0015] The present invention also provides a cell structure of a GAT-type transistor based on a Si / SiC heterostructure, comprising: two or more GAT-type transistors based on the Si / SiC heterostructure, wherein, in two adjacent GAT-type transistors based on the Si / SiC heterostructure, there is a gap between the first structure of one GAT-type transistor and the second structure of the other GAT-type transistor along the third direction, and the gap exposes a portion of the N+ region.

[0016] Compared with the prior art, the beneficial effects of the present invention are as follows: 1) High breakdown voltage performance: This invention utilizes the high breakdown electric field of SiC material (about 10 times that of Si), combined with the deep P+ region and cross-layer trench gate design, so that the device breakdown voltage can easily exceed 1200V, and the high voltage application requirements can be met without thickening the substrate. 2) Low loss characteristics: This invention utilizes the Si / SiC heterostructure to significantly reduce the on-resistance. At the same time, combined with the efficient control of charge carriers by the trench gate, the static loss is significantly reduced. Meanwhile, the high electron saturation drift velocity of SiC suppresses the charge carrier storage effect, reducing high-frequency dynamic loss and significantly increasing the switching frequency compared to Si-based GAT. 3) High temperature adaptability: This invention utilizes the thermal conductivity of SiC material (approximately 3 times that of Si) to improve the maximum junction temperature of the device, resulting in minimal performance degradation at high temperatures and significantly reducing heat dissipation costs, making it suitable for harsh high-temperature operating conditions. 4) Strong surge protection capability: This invention utilizes the stable avalanche breakdown characteristics of SiC and the current dispersion design of the deep N+ region to enhance the device's resistance to secondary breakdown, short circuit and surge protection capabilities, eliminating the need for additional complex protection circuits and simplifying system design; 5) Good process compatibility: This invention retains the compatibility between Si epitaxial layers and traditional mature processes such as ion implantation and trench deposition, reducing the difficulty of mass production and manufacturing costs, and combining performance advantages with industrialization feasibility.

[0017] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of a GAT-type transistor based on a Si / SiC heterostructure provided in an embodiment of the present invention; Figure 2 This is a schematic cross-sectional view of a GAT-type transistor based on a Si / SiC heterostructure obtained by slicing along the A-A' direction according to an embodiment of the present invention. Figure 3 This is another cross-sectional structural diagram obtained by slicing a GAT-type transistor based on a Si / SiC heterostructure along the B-B' direction, as provided in an embodiment of the present invention. Figure 4 This is a top view of the cell structure of a GAT-type transistor based on a Si / SiC heterostructure provided in an embodiment of the present invention; Figures 5-12 This is a schematic diagram of the fabrication process of a GAT-type transistor based on a Si / SiC heterostructure provided in an embodiment of the present invention.

[0019] Explanation of reference numerals in the attached figures 1-SiC N+ substrate; 2-SiC N- epitaxial layer; 3-First deep P+ region; 4-Second deep P+ region; 5-First gate; 6-Second gate; 7-Si N- epitaxial layer; 8-P- region; 9-N+ region; 10-Drain; 11-Trench; 12-Trench; 13-First dielectric layer; 14-Second dielectric layer; 15-Emitter; 16-Ohmic contact metal; 17-Deep N+ region; 18-Trench; 19-Trench. Detailed Implementation

[0020] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0021] Current technologies do not combine SiC materials with GAT structures, but SiC has advantages over Si in key properties such as breakdown electric field and thermal conductivity. Therefore, using SiC as the N-type composite material for GAT is a viable option. - The substrate can overcome the performance bottleneck of Si-based GATs. Based on this, the present invention designs a GAT-type transistor and its cell structure based on a Si / SiC heterostructure.

[0022] The GAT-type transistor based on a Si / SiC heterostructure provided by this invention includes a core structure and a conductive trench structure. For example, Figure 1 This is a top view of a GAT-type transistor based on a Si / SiC heterostructure. Figure 2 This is a schematic cross-sectional structure diagram obtained by cutting a GAT-type transistor based on a Si / SiC heterostructure along the A-A' direction. Figure 3 This is another cross-sectional structural diagram obtained by slicing a GAT-type transistor based on a Si / SiC heterostructure along the B-B' direction. Combined with... Figure 1 , Figure 2 and Figure 3As shown, both the core structure and the conductive trench structure include: a SiC N+ substrate 1, a SiC N- epitaxial layer 2, a first deep P+ region 3, a second deep P+ region 4, a first gate 5, a second gate 6, a SiN- epitaxial layer 7, and a P- region 8. Along the first direction D1, the drain 10 is located on the lower surface of the SiC N+ substrate 1, and the SiC N- epitaxial layer 2 is located on the upper surface of the SiC N+ substrate 1. The first deep P+ region 3 and the second deep P+ region 4 are symmetrically distributed at both ends of the SiC N- epitaxial layer 2 along the second direction D2, and the second direction D2 is perpendicular to the first direction D1. The first gate 5 and the second gate 6 are located on the sidewall and bottom surface of the trench 11 in the first deep P+ region 3 and the trench 12 in the second deep P+ region 4, respectively. The SiN- epitaxial layer 7 is located on the upper surface of the portion of the SiC N- epitaxial layer 2 between the first deep P+ region 3 and the second deep P+ region 4. The P- region 8 is located on the upper surface of the SiN- epitaxial layer 7.

[0023] Continue to refer to the above. Figure 1 and Figure 2 The core structure also includes: an N+ region 9, a first dielectric layer 13, a second dielectric layer 14, and an emitter 15. The N+ region 9 is located within the P- region 8. The first dielectric layer 13 simultaneously covers a portion of the upper surface of the P- region 8, a portion of the upper surface of the first deep P+ region 3, and a portion of the upper surface of the N+ region 9. The second dielectric layer 14 simultaneously covers a portion of the upper surface of the P- region 8, a portion of the upper surface of the second deep P+ region 4, and a portion of the upper surface of the N+ region 9. The emitter 15 is in contact with the portion of the upper surface of the N+ region 9 located between the first dielectric layer 13 and the second dielectric layer 14.

[0024] Continue to refer to the above. Figure 1 and Figure 3 The conductive trench structure also includes: an ohmic contact metal 16, a deep N+ region 17, a trench 18, and a trench 19. The trench 18 penetrates the P- region 8 and its bottom contacts the upper surface of the Si N-epitaxial layer 7. The deep N+ region 17 is located below the trench 18; specifically, the deep N+ region 17 penetrates the Si N-epitaxial layer 7 along a first direction D1 and extends downward into the interior of the SiC N-epitaxial layer 2. The trench 19 is located in the central region of the deep N+ region 17; specifically, the trench 19 is symmetrical along the central axis of the deep N+ region 17. The ohmic contact metal 16 is located on the sidewalls and bottom surface of the trench 19.

[0025] Continue to refer to the above. Figure 1 The first dielectric layer 13, the second dielectric layer 14 and the emitter 15 constitute the first structure, the ohmic contact metal 16, the deep N+ region 17, the trench 18 and the trench 19 constitute the second structure, and the first structure and the second structure are spaced apart along the third direction D3, and the third direction D3 is perpendicular to both the second direction D2 and the first direction D1, and a portion of the N+ region 9 is exposed through this gap.

[0026] In some embodiments, such as Figure 2 or Figure 3 As shown, along the first direction D1, the thicknesses of the first deep P+ region 3 and the second deep P+ region 4 are both greater than the thickness of the Si N- epitaxial layer 7.

[0027] In some embodiments, such as Figure 2 or Figure 3 As shown, along the second direction D2, the width of trench 11 is less than the width of the first deep P+ region 3, and the width of trench 12 is less than the width of the second deep P+ region 4. Along the first direction D1, the depth of trench 11 is less than the depth of the first deep P+ region 3, and the depth of trench 12 is less than the depth of the second deep P+ region 4.

[0028] In some embodiments, along the first direction D1, the thickness of the P-region 8 is greater than or equal to the thickness of the Si N-epitaxial layer 7.

[0029] In some embodiments, along the first direction D1, the depth of the trench 19 is less than or equal to the depth of the deep N+ region 17.

[0030] In some embodiments, the SiC N+ substrate 1 is made of 4H-SiC with a thickness ranging from 300 to 500 μm and a doping concentration ranging from 1 × 10¹. 8 ~5×10¹ 9 cm - ³, its lower surface forms an ohmic contact with the drain electrode 10.

[0031] In some embodiments, the thickness of the SiC N-epitaxial layer 2 ranges from 5 to 10 μm, and the doping concentration ranges from 1 × 10¹. 6 ~5×10¹ 6 cm - ³, which serves as the core layer for high-voltage blocking.

[0032] In some embodiments, the depth of the first deep P+ region 3 and the second deep P+ region 4 ranges from 6 to 8 μm, the width ranges from 3 to 5 μm, and the doping concentration ranges from 1 × 10¹. 9 ~5×10¹ 9 cm - ³.

[0033] In some embodiments, the first gate 5 and the second gate 6 are made of Ni with a purity of ≥99.99%, the electrode height is consistent with the depth of the trench, and the first gate 5 simultaneously forms ohmic contact with the trench sidewall and bottom in the first deep P+ region 3. Similarly, the first gate 6 simultaneously forms ohmic contact with the trench sidewall and bottom in the second deep P+ region 4.

[0034] In some embodiments, the thickness of the Si N-epitaxial layer 7 ranges from 2 to 4 μm, and the doping concentration ranges from 5 × 10¹. 5 ~1×10¹ 6 cm - ³, which constitutes the conductive region on the surface of the heterogeneous structure.

[0035] In some embodiments, the doping concentration of P-region 8 ranges from 1 × 10¹ 7 ~5×10¹ 7 cm - The doping concentration range of region 9 in the N+ region is 1×10¹. 9 ~5×10¹ 9 cm - ³, the width of P-region 8 ranges from 4 to 6 μm.

[0036] In some embodiments, the drain electrode 10 is made of Ni with a purity of ≥99.99%.

[0037] In some embodiments, the width of the first groove 11 and the second groove 12 are both in the range of 2~3μm, the depth is both in the range of 4~6μm, and the verticality of the sidewall is ≥89°.

[0038] In some embodiments, the first dielectric layer 13 and the second dielectric layer 14 are both made of SiO2, the thickness of the first dielectric layer 13 is in the range of 0.3~0.5μm, the thickness of the second dielectric layer 14 is in the range of 0.3~0.5μm, and the spacing width between the first dielectric layer 13 and the second dielectric layer 14 is in the range of 1~2μm.

[0039] In some embodiments, the emitter 15 is made of Al with a purity ≥99.99% and a thickness ranging from 1 to 2 μm, and it forms an ohmic contact with the N+ region 9.

[0040] In some embodiments, the ohmic contact metal 16 is made of Ni with a purity ≥ 99.99%, forming an ohmic contact with the trench sidewalls and bottom of the deep N+ region 17, and the upper surface of the Si N- epitaxial layer 7, with a contact resistance ≤ 5 × 10⁻⁶. -7 Ω·cm².

[0041] In some embodiments, the doping concentration of the deep N+ region 17 ranges from 5 × 10¹. 9 ~1×10² 0 cm - ³, with a depth range of 5~8μm and a lateral extension width range of 3~5μm; for example, the deep N+ region 17 can be in the form of a columnar structure.

[0042] In some embodiments, the width of the third trench 18 ranges from 2 to 3 μm, the depth ranges from 1 to 2 μm (which can be 1 / 2 to 2 / 3 of the thickness of the Si N-epitaxial layer 7), and the bottom is flush with the upper surface of the Si N-epitaxial layer 7.

[0043] In some embodiments, the width of the fourth trench 19 ranges from 0.4 to 0.6 μm, and the depth ranges from 2 to 3 μm.

[0044] The present invention also provides a cell structure for a GAT-type transistor based on a Si / SiC heterostructure, the cell structure comprising two or more GAT-type transistors based on a Si / SiC heterostructure, wherein, in two adjacent GAT-type transistors based on a Si / SiC heterostructure, a first structure of one GAT-type transistor and a second structure of the other GAT-type transistor are spaced along a third direction D3, and the space exposes a portion of the N+ region 9; exemplarily, Figure 4 This is a top view of the cell structure of a GAT-type transistor based on a Si / SiC heterostructure provided in an embodiment of the present invention. Figure 4 As shown, the cell structure contains three GAT-type transistors based on Si / SiC heterostructure distributed along the third direction D3, and the first and second structures of these three GAT-type transistors based on Si / SiC heterostructure are alternately distributed along the third direction D3.

[0045] For example, in combination Figure 4 and the above Figure 2 , 3 As shown, along the third direction D3, the lengths of trenches 11 and 12 range from 100 to 500 μm (adjusted according to the device's rated current requirements). Along the second direction D2, the spacing between trenches 11 and 12 ranges from 5 to 10 μm. The first deep P+ region 3 and the second deep P+ region 4 extend along the third direction D3 and completely surround the outer edges of trenches 11 and 12. Furthermore, along the second direction D2, the spacing between the first deep P+ region 3 and trench 11 ranges from 0.5 to 1 μm, and the spacing between the second deep P+ region 4 and trench 12 also ranges from 0.5 to 1 μm. Figure 4 and Figure 3As shown, ohmic contact metal 16 and trench 18 are alternately arranged along the third direction D3 between trench 11 and trench 12; along the second direction D2, the width of ohmic contact metal 16 ranges from 1 to 2 μm, and along the third direction D3, the length of ohmic contact metal 16 and trench 18 is the same. Along the second direction D2, the width of trench 18 is 2 to 3 μm, and along the third direction D3, the length of trench 18 is 0.8 to 1.2 μm; along the second direction D2, the spacing between adjacent ohmic contact metal 16 and trench 18 ranges from 0.5 to 1 μm. P-region 8 extends along the third direction D3 and along the second direction D2, with a width ranging from 4 to 6 μm, completely surrounding deep N+ region 17, forming lateral electrical isolation to deep N+ region 17. The deep N+ region 17 extends along the third direction D3, and its width along the second direction D2 ranges from 3 to 5 μm. The distance between the deep N+ region 17 and the boundary of the P- region 8 along the second direction D2 ranges from 0.5 to 1 μm. Along the second direction D2, the trench 19 has a width ranging from 0.4 to 0.6 μm, its length is the same as that of the trench 18, and its central axis coincides with that of the deep N+ region 17.

[0046] This invention also provides a method for fabricating a GAT-type transistor based on a Si / SiC heterostructure. For example, Figures 5-12 This is a schematic diagram of the fabrication process of a GAT-type transistor based on a Si / SiC heterostructure.

[0047] Step 1, please refer to Figure 5 , providing SiC N+ substrate layer 1.

[0048] Step 2, please refer to Figure 5 An epitaxial layer 2 is formed on a SiC N+ substrate 1 by epitaxial growth along the first direction D1. The SiC N- epitaxial layer 2 grows along the second direction D2, and the first direction D1 is perpendicular to the second direction D2.

[0049] Step 3, please refer to Figure 6 An N-Si epitaxial layer 7 is grown on the surface of the material after completing step 2 using a chemical vapor deposition process.

[0050] Step 4, please refer to Figure 6 A mask pattern is formed on the SiN-epitaxial layer 7 by photolithography etching. Then, deep P-region ion implantation is performed on the upper surface of the SiN-epitaxial layer 7 to form a first deep P+ region 3 and a second deep P+ region 4. The first deep P+ region 3 and the second deep P+ region 4 extend along a third direction D3 and have a width along a first direction D1. The third direction D3 is perpendicular to both the first direction D1 and the second direction D2.

[0051] Step 5, please refer to Figure 6A mask pattern is formed on the SiN-epitaxial layer 7 by photolithography etching. Then, P- region ion implantation is performed on the surface of the SiN-epitaxial layer 7 to form P- region 8, and N+ region implantation is performed on the surface of the SiN-epitaxial layer 7 to form N+ region 9.

[0052] Step 6, please refer to Figure 7 The first deep P+ region 3 is etched to form a trench 11, and the second deep P+ region 4 is etched to form a trench 12. The trenches 11 and 12 extend along the third direction D3 and have a width along the first direction D1.

[0053] Step 7, please refer to Figure 8 Along the first direction D1, the P-region 8 is etched to form a trench 18. A mask pattern is formed at the bottom of the trench 18 by photolithography etching. Then, ion implantation is performed at the bottom of the trench 18 to form a deep N+ region 17.

[0054] Step 8, please refer to Figure 9 Along the first direction D1, the deep N+ region 17 is etched to form a trench 19.

[0055] Step 9, please refer to Figure 10 An oxide layer is grown over the first deep P+ region 3, the second deep P+ region 4, the P- region 8 and the N+ region 9 to form the first dielectric layer 13 and the second dielectric layer 14; then pure Al is deposited on the upper surface of the gate dielectric layer to form the emitter 15.

[0056] Step 10, please refer to Figure 11 and Figure 12 The back and front sides of the fabricated structure are cleaned, and pure Ni is deposited on the back side to form the drain 10 of the ohmic contact. Pure Ni is deposited in the inner and outer regions of trenches 11, 12, and 19 to form the first gate 5, the second gate 6, and the electrode 16 of the ohmic contact.

[0057] The present invention has the following beneficial effects: 1) High breakdown voltage performance: Utilizing the high breakdown electric field of SiC material (about 10 times that of Si), combined with the deep P+ region and cross-layer trench gate design, the device breakdown voltage can easily exceed 1200V, meeting the high voltage application requirements without the need to thicken the substrate. 2) Low loss characteristics: The Si / SiC heterostructure significantly reduces the on-resistance. Combined with the efficient control of charge carriers by the trench gate, it significantly reduces static losses. At the same time, the high electron saturation drift velocity of SiC suppresses the charge carrier storage effect, reduces high-frequency dynamic losses, and the switching frequency is more than 30% higher than that of Si-based GAT. 3) High temperature adaptability: The thermal conductivity of SiC material (about 3 times that of Si) allows the maximum junction temperature of the device to be increased to over 200℃. The performance degradation is small at high temperatures, the heat dissipation cost is reduced by 50%, and it can be adapted to harsh high temperature conditions. 4) Strong surge resistance: The stable avalanche breakdown characteristics of SiC and the current dispersion design of the deep N+ region enhance the device's resistance to secondary breakdown, short circuit and surge, eliminating the need for additional complex protection circuits and simplifying system design; 5) Good process compatibility: It retains the compatibility between Si epitaxial layers and traditional mature processes such as ion implantation and trench deposition, reducing the difficulty of mass production and manufacturing costs, and combining performance advantages with industrialization feasibility.

[0058] It should be noted that the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, features defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0059] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Furthermore, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0060] In this specification, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude multiple instances. While different embodiments may describe certain measures, this does not mean that these measures cannot be combined to produce a good effect.

[0061] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A GAT-type transistor based on a Si / SiC heterostructure, characterized in that, include: Core structure and conductive trench structure; Both the core structure and the conductive trench structure include: A drain electrode (10), a SiC N+ substrate (1), and a SiC N- epitaxial layer (2) are distributed from bottom to top along the first direction; The first deep P+ region (3) and the second deep P+ region (4) are symmetrically distributed at both ends of the SiC N- epitaxial layer (2) along the second direction, which is perpendicular to the first direction; The first gate (5) and the second gate (6) are located on the sidewall and bottom surface of the trench (11) in the first deep P+ region (3) and the trench (12) in the second deep P+ region (4), respectively. Si N- epitaxial layer (7), located on the upper surface of a portion of SiC N- epitaxial layer (2) between the first deep P+ region (3) and the second deep P+ region (4); The P-region (8) is located on the upper surface of the Si N-epitaxial layer (7); The core structure further includes: an N+ region (9), a first dielectric layer (13), a second dielectric layer (14), and an emitter (15), wherein the N+ region (9) is located within the P- region (8), and the emitter (15) is in contact with the upper surface of a portion of the N+ region (9) located between the first dielectric layer (13) and the second dielectric layer (14); The conductive trench structure further includes: an ohmic contact metal (16), a deep N+ region (17), a trench (18), and a trench (19), wherein the trench (18) penetrates the P- region (8) and contacts the upper surface of the Si N- epitaxial layer (7) at its bottom, the deep N+ region (17) is located below the trench (18), the trench (19) is located in the central region of the deep N+ region (17), and the ohmic contact metal (16) is located on the sidewall and bottom surface of the trench (19).

2. The GAT-type transistor based on Si / SiC heterostructure according to claim 1, characterized in that, The first dielectric layer (13), the second dielectric layer (14) and the emitter (15) constitute a first structure, the ohmic contact metal (16), the deep N+ region (17), the trench (18) and the trench (19) constitute a second structure, and the first structure and the second structure are spaced apart along a third direction, which is perpendicular to both the second direction and the first direction.

3. The GAT-type transistor based on Si / SiC heterostructure according to claim 2, characterized in that, Along the first direction, the thicknesses of the first deep P+ region (3) and the second deep P+ region (4) are both greater than the thickness of the Si N- epitaxial layer (7).

4. The GAT-type transistor based on Si / SiC heterostructure according to claim 2, characterized in that, Along the second direction, the width of the trench (11) is less than the width of the first deep P+ region (3), and the width of the trench (12) is less than the width of the second deep P+ region (4); along the first direction, the depth of the trench (11) is less than the depth of the first deep P+ region (3), and the depth of the trench (12) is less than the depth of the second deep P+ region (4).

5. The GAT-type transistor based on Si / SiC heterostructure according to claim 2, characterized in that, Along the first direction, the thickness of the P-region (8) is greater than or equal to the thickness of the Si N-epitaxial layer (7).

6. The GAT-type transistor based on Si / SiC heterostructure according to claim 2, characterized in that, The first dielectric layer (13) simultaneously covers part of the upper surface of the P-region (8), part of the upper surface of the first deep P+region (3), and part of the upper surface of the N+region (9); the second dielectric layer (14) simultaneously covers part of the upper surface of the P-region (8), part of the upper surface of the second deep P+region (4), and part of the upper surface of the N+region (9).

7. The GAT-type transistor based on Si / SiC heterostructure according to claim 2, characterized in that, The deep N+ region (17) penetrates the Si N- epitaxial layer (7) along the first direction and extends downward into the interior of the SiC N- epitaxial layer (2).

8. The GAT-type transistor based on a Si / SiC heterostructure according to claim 2 or 7, characterized in that, The trench (19) is symmetrical about the central axis of the deep N+ region (17), and the depth of the trench (19) along the first direction is less than or equal to the depth of the deep N+ region (17).

9. The GAT-type transistor based on Si / SiC heterostructure according to claim 2, characterized in that, The ohmic contact metal (16) is made of Ni.

10. A cell structure for a GAT-type transistor based on a Si / SiC heterostructure, characterized in that, include: Two or more GAT-type transistors based on Si / SiC heterostructures according to any one of claims 2 to 9, wherein, in two adjacent GAT-type transistors based on Si / SiC heterostructures, there is a gap between the first structure of one GAT-type transistor and the second structure of the other GAT-type transistor along the third direction, and the gap exposes a portion of the N+ region (9).

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