A method for improving the intrinsic thermal conductivity of a semiconductor

Abstract

The application discloses a method for improving intrinsic thermal conductivity of a semiconductor, and belongs to the technical field of the semiconductor, and discloses a semiconductor heterostructure which comprises a semiconductor material and a modified layer which are arranged in a laminated mode; an interface between the semiconductor material and the modified layer is a coherent hetero-interface; the semiconductor material and the modified layer are matched in acoustic phonons and are not matched in optical phonons; and the semiconductor material and the modified layer each independently comprises a III-V semiconductor material. The semiconductor heterostructure with the coherent hetero-interface is constructed, the phonon transport near the interface is in a non-equilibrium state, the phonon-phonon scattering process is regulated and controlled, the thermal resistance caused by high-order phonon scattering is reduced, the phonon relaxation time is prolonged, and the intrinsic thermal conductivity of the material is improved. The application only needs to utilize the interface engineering, does not need to introduce a new material, the preparation process of the semiconductor heterostructure is compatible with an existing chip preparation process, and the engineering has strong realizability.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology, and in particular relates to a method for improving the intrinsic thermal conductivity of semiconductors. Background Technology

[0002] In recent years, with the rapid development of industries such as high-performance computing, artificial intelligence, 5G communication, and new energy vehicles, the functional integration density and power consumption of integrated circuits have continued to increase. Thermal management has become a key issue limiting chip performance release, lifespan, and reliability improvement. Currently, the local heat flux density of high-performance chips has reached 1000 W·cm². -2 Chip thermal runaway occurs frequently, directly threatening device lifespan and stability. Therefore, effectively improving chip heat dissipation capabilities is urgently needed.

[0003] Semiconductor materials, as the foundation of chips, primarily rely on lattice vibrations (i.e., phonons) for internal heat conduction. Therefore, the intrinsic thermal conductivity of semiconductor materials is determined by phonon-phonon interactions, generally including three-phonon scattering and higher-order four-phonon scattering. Intrinsic phonon scattering is widely considered an uncontrollable source of thermal resistance, thus semiconductor materials exhibit an intrinsic limit to their thermal conductivity. Any form of doping, nanostructure manipulation, or other methods inevitably introduces additional scattering mechanisms, such as impurities, defects, and boundary conditions that contribute to phonon dissipation, further increasing thermal resistance and reducing thermal conductivity. Existing methods for optimizing chip heat dissipation include developing high thermal conductivity semiconductor materials and material purification.

[0004] Among these, high thermal conductivity semiconductor materials can better dissipate heat, reduce the temperature of local hot spots in chips, and mitigate thermal failure problems. Current methods include: Slack's rule (1970s), which relies on light atoms, high bond strength, simple crystal structure, and weakly anharmonic materials, with diamond being a typical example; and phonon band engineering (2010s), which uses unconventional phonon spectrum structures to suppress phonon scattering and achieve high thermal conductivity, with boron arsenide being a typical example. These methods have the following drawbacks: 1) These methods all rely on the intrinsic properties of the material to determine thermal conductivity, and cannot break through its intrinsic limit; 2) Material selection cycles are long and costly; 3) The preparation conditions are harsh (high temperature, high pressure, strict growth window); 4) Poor compatibility with chip fabrication systems, and high interfacial thermal resistance leads to limited heat dissipation effects in devices.

[0005] Another approach is to prepare high-quality, isotopically purified materials, typically high-purity silicon carbide and isotopically enriched cubic boron nitride materials. However, its drawbacks are: 1) it can only approach the intrinsic thermal conductivity limit of the material and cannot break through that limit; 2) the process is complex and difficult to scale up for industrialization, and the integration with chip manufacturing processes needs to be considered.

[0006] In summary, existing technologies have the following drawbacks: 1) Three-phonon and four-phonon scattering are considered inherent properties of materials, and the intrinsic thermal conductivity of materials is considered an insurmountable physical limit. Existing technologies cannot control the intrinsic phonon scattering of materials, thus failing to improve the intrinsic thermal conductivity; 2) Existing technologies for developing high thermal conductivity materials all rely on the material itself, lacking universality. Each material requires a new crystal and re-preparation process; 3) High thermal conductivity materials developed using existing technologies need to consider the difficulty of material preparation and integration with chip manufacturing processes. Summary of the Invention

[0007] In order to overcome at least one of the problems existing in the prior art, one of the objectives of the present invention is to provide a semiconductor heterostructure that, by introducing a coherent heterostructure interface, suppresses the intrinsic high-order thermal resistance of phonons and achieves a significant improvement in the intrinsic thermal conductivity of the material.

[0008] The second objective of this invention is to provide a method for improving the intrinsic thermal conductivity of semiconductors.

[0009] The third objective of this invention is to provide a chip.

[0010] The fourth objective of this invention is to provide an electronic device.

[0011] To achieve the above objectives, the technical solution adopted by the present invention is as follows: A first aspect of the present invention provides a semiconductor heterostructure comprising a semiconductor material and a modified layer stacked thereon; the interface between the semiconductor material and the modified layer is a coherent heterostructure interface; the semiconductor material and the modified layer are acoustically phonon matched but optically phonon mismatched; the semiconductor material and the modified layer each independently comprise a III-V group semiconductor material.

[0012] This invention, based on coherent heterointerface engineering, proposes a semiconductor with thermal conductivity exceeding the intrinsic limit, namely a hopping conductor. Its core mechanism is the non-equilibrium phonon transport induced by the coherent heterointerface. Specifically, in the coherent heterointerface, the acoustic phonon frequency ranges of the materials forming the interface are well matched, including sound velocity and phonon density of states. This allows acoustic phonons to penetrate the interface with extremely low interfacial thermal resistance without disrupting phonon coherence; that is, acoustic phonon matching ensures that acoustic phonons penetrate the interface with almost no thermal resistance. In contrast, optical phonon mismatch at the two ends of the material results in a lack of corresponding phonon energy levels, preventing them from penetrating the interface and causing them to accumulate near the interface. This leads to optical phonons deviating from their local thermal equilibrium state, forming a local phonon non-equilibrium state. In this non-equilibrium state, optical phonons are more easily converted into acoustic phonons through attenuation processes, such as one optical phonon splitting into two acoustic phonons, thus becoming the main pathway to weaken higher-order phonon-phonon scattering (mainly four-phonon scattering) in the material. After four-phonon scattering is suppressed, the relaxation time of phonons in the material is significantly prolonged, ultimately leading to an increase in thermal conductivity exceeding its intrinsic limit in the material near the interface region. This invention is applicable to a variety of semiconductor materials and can simultaneously improve the intrinsic thermal conductivity of materials at both ends of the interface.

[0013] This invention achieves a breakthrough in the intrinsic thermal conductivity limit of semiconductor materials, primarily by effectively reducing the intrinsic thermal resistance caused by four-phonon scattering. In III-V semiconductors with significant atomic mass differences, the three-phonon scattering channel is significantly suppressed due to the wide bandgap between the optical and acoustic branches, making four-phonon scattering the main limiting factor. Therefore, this invention exhibits outstanding thermal conductivity enhancement in such material systems.

[0014] In this invention, the dispersion relation between the energy (angular frequency ω) and wave vector q of acoustic phonons and optical phonons constitutes the phonon spectrum. Acoustic phonon matching refers to the overlap of the phonon spectra of acoustic phonons from two materials, specifically including sound velocity matching and phonon density of states matching. Optical phonon mismatch refers to the lack of overlap or minimal overlap of the phonon spectra of optical phonons from two materials, with significant differences.

[0015] In some embodiments of the present invention, the interface between the semiconductor material and the modified layer is an atomically flat interface.

[0016] In some embodiments of the present invention, the depth of the interface diffusion layer of the atomically flat interface is ≤3nm, specifically it can be 0.01~1nm; for example, it can be any value of 0.1nm, 0.5nm, 1nm, 2nm, or 3nm or a range between any two.

[0017] In this invention, an atomically flat interface ensures that the material interface is in a low-defect or defect-free state, thereby enabling the formation of a coherent heterojunction interface. This ensures non-equilibrium phonon transport at the interface, effectively improving the intrinsic thermal conductivity of the material. The atoms at this interface are arranged in an ordered manner due to the high lattice matching between the materials on both sides of the interface. The atoms at the interface may diffuse to form a continuous interface diffusion layer in terms of composition and structure, within which the atoms are arranged in an ordered manner.

[0018] In some embodiments of the present invention, the lattice mismatch rate between the semiconductor material and the modified layer is ≤5%, specifically 0.1% to 5%; for example, it can be any value or a range between 0.1%, 0.5%, 1%, 2%, 3%, 4%, or 5%. In some specific embodiments of the present invention, the lattice mismatch rate between the semiconductor material and the modified layer is ≤2%. This ensures that a low lattice mismatch rate can form a coherent heterojunction interface.

[0019] In some embodiments of the present invention, the III-V semiconductor material includes at least one of AlAs, GaAs, InP, AlGaAs, or InGaAs.

[0020] In some embodiments of the present invention, the semiconductor material includes at least one of AlAs, GaAs, InP, AlGaAs, or InGaAs; in some specific embodiments of the present invention, the semiconductor material includes at least one of AlAs, GaAs, or InP.

[0021] In some embodiments of the present invention, the modified layer comprises at least one of AlAs, GaAs, InP, AlGaAs, or InGaAs; in some embodiments of the present invention, the modified layer comprises at least one of GaAs, AlAs, AlGaAs, or InGaAs.

[0022] In some embodiments of the present invention, the semiconductor material and the modified layer comprise at least one of the following combinations: the semiconductor material is AlAs and the modified layer is GaAs; the semiconductor material is GaAs and the modified layer is AlAs; the semiconductor material is AlAs and the modified layer is AlGaAs; or the semiconductor material is InP and the modified layer is InGaAs.

[0023] In some embodiments of the present invention, in the semiconductor heterostructure, the modified layer is disposed on at least one surface of the semiconductor material; specifically, the modified layer may be disposed on one side surface of the semiconductor material or on both sides surface of the semiconductor material.

[0024] In some embodiments of the present invention, the modified layer in the semiconductor heterostructure can be a crystal layer or an alloy layer.

[0025] In some embodiments of the present invention, the thickness of the modified layer is ≥8nm, specifically 8~100nm; for example, it can be any value of 8nm, 20nm, 30nm, 50nm, 70nm, or 100nm or a range between any two.

[0026] In some embodiments of the present invention, when the modified layer is disposed on one side surface of the semiconductor material, the semiconductor material has a region whose thermal conductivity exceeds its intrinsic thermal conductivity limit, and the thickness of the region is ≤3 μm; specifically, it can be 0.1~3 μm; for example, it can be any value or a range between any two of 0.1 μm, 0.3 μm, 0.5 μm, 0.7 μm, 1 μm, 1.5 μm, 2 μm, 2.5 μm or 3 μm; or, the thickness of the semiconductor material is ≤ the phonon mean free path of the semiconductor material, specifically, the thickness of the semiconductor material can be ≤3 μm, such as 0.1~3 μm; for example, it can be any value or a range between any two of 0.1 μm, 0.3 μm, 0.5 μm, 0.7 μm, 1 μm, 1.5 μm, 2 μm, 2.5 μm or 3 μm; in some specific embodiments of the present invention, the thickness of the semiconductor material is 1~2 μm.

[0027] This invention enhances the intrinsic thermal conductivity of materials within a micrometer-scale range near the interface, applicable to nanoscale thin film structures and even bulk materials. The effect of the coherent heterojunction is related to the mean free path of interfacial phonons, which in turn is related to the material type. To ensure that the entire semiconductor material is within the effective range, the semiconductor material must not be too thick when the modified layer is only applied to one side of the semiconductor material; for example, the thickness of the semiconductor material should be ≤3 μm, or more specifically, 1~2 μm.

[0028] In some embodiments of the present invention, the semiconductor material has a layered structure or a bulk structure. Specifically, the layered structure may be a thin film structure.

[0029] In some embodiments of the present invention, the method for preparing the modified layer includes molecular beam epitaxy, atomic layer deposition, or a combination thereof.

[0030] A second aspect of the present invention provides a method for improving the intrinsic thermal conductivity of a semiconductor, comprising the steps of: depositing a modification layer on the surface of a semiconductor material to improve the intrinsic thermal conductivity of the semiconductor material, thereby obtaining a semiconductor heterostructure as described in the first aspect of the present invention.

[0031] In some embodiments of the present invention, the application environment temperature of the semiconductor heterostructure is ≥290K, specifically 290~1300K; for example, it can be any value or a range between any two of 290K, 300K, 400K, 500K, 600K, 700K, 800K, 900K or 1000K; in some specific embodiments of the present invention, the application environment temperature of the semiconductor heterostructure is 300~600K.

[0032] Given that four-phonon scattering becomes more pronounced with increasing temperature, this invention can function in the range from room temperature to high temperature, and its effect is more obvious under high temperature conditions.

[0033] A third aspect of the present invention provides a chip comprising the semiconductor heterostructure described in the first aspect of the present invention.

[0034] The semiconductor heterostructure of this invention possesses high intrinsic thermal conductivity, resulting in chips with excellent heat dissipation. Compared to existing development paths for high thermal conductivity materials, this invention provides a revolutionary paradigm for developing such materials. It only requires interface engineering and does not rely on new material screening. Since semiconductors are the core material of chips, traditional heat dissipation technologies rely on integrated high thermal conductivity substrates. However, this method can be implemented directly within existing semiconductor systems, directly improving the thermal conductivity of the semiconductor material itself, providing a fundamental optimization of chip heat dissipation. This method requires only heterostructure interface engineering, and the entire process is based on mature semiconductor epitaxial systems, compatible with existing chip fabrication processes, and easily industrially compatible. Furthermore, the operating temperature range can extend from room temperature to high temperatures, matching the chip's operating temperature range and demonstrating engineering applicability.

[0035] A fourth aspect of the present invention provides an electronic device comprising the semiconductor heterostructure described in the first aspect of the present invention, or the chip described in the third aspect of the present invention.

[0036] In some embodiments of the present invention, the electronic device includes an integrated circuit; the integrated circuit includes the semiconductor heterostructure or the chip.

[0037] In some embodiments of the present invention, the electronic device is applied in the fields of high-performance computing, artificial intelligence, 5G communication, or new energy vehicles.

[0038] The beneficial effects of this invention are as follows: This invention proposes a semiconductor heterostructure based on coherent heterointerface engineering, whose thermal conductivity exceeds the intrinsic limit of semiconductor materials. By constructing a semiconductor heterostructure with a coherent heterointerface, phonon transport near the interface is placed in a non-equilibrium state, thereby modulating the phonon-phonon scattering process, reducing the thermal resistance caused by higher-order phonon scattering, prolonging the phonon relaxation time, and improving the intrinsic thermal conductivity of the material. This invention only requires the use of interface engineering and does not require the introduction of new materials. The fabrication process of the semiconductor heterostructure is compatible with existing chip fabrication processes, and its engineering feasibility is high. Attached Figure Description

[0039] Figure 1 This is a schematic diagram of the implementation method in an embodiment of the present invention.

[0040] Figure 2 The diagram shows the structure of structure 1 in Example 1 and structure 2 in Comparative Example 1.

[0041] Figure 3 The results show the thermal conductivity of the AlAs layer in structure 1 of Example 1 and structure 2 of Comparative Example 1.

[0042] Figure 4 The diagram shows the structure of structure 3 in Example 2 and structure 4 in Comparative Example 2.

[0043] Figure 5 The results show the thermal conductivity test results of the AlAs layer and GaAs substrate in structure 3 of Example 2.

[0044] Figure 6 The thermal conductivity test results are for the GaAs substrate with structure 4 in Comparative Example 2.

[0045] Figure 7 This is a schematic diagram of structure 5 in Example 3.

[0046] Figure 8 The results show the thermal conductivity test results of the AlAs layer in structure 5 of Example 3 and structure 3 of Example 2.

[0047] Figure 9 The diagram shows the structure of structure 6 in Example 4 and structure 7 in Comparative Example 3.

[0048] Figure 10 The results are the thermal conductivity test results of the InP layer of structure 6 in Example 4.

[0049] Figure 11 The results show the thermal conductivity of the InP layer in structure 7 of Comparative Example 3.

[0050] Figure 12 This is a schematic diagram of structure 8 in Comparative Example 4.

[0051] Figure 13 The results show the thermal conductivity of the InP layer in structure 8 of Comparative Example 4. Detailed Implementation

[0052] The following specific embodiments further illustrate the content of the present invention in detail. It should also be understood that the following embodiments are only for further explanation of the present invention and should not be construed as limiting the scope of protection of the present invention. Non-essential improvements and adjustments made by those skilled in the art based on the principles described herein are all within the scope of protection of the present invention. The specific process parameters, etc., in the following examples are merely examples within a suitable range; that is, those skilled in the art can make selections within a suitable range based on the description herein, and are not intended to be limited to the specific data in the examples below. Unless otherwise specified, the raw materials, reagents, or apparatus used in the following embodiments and comparative examples can be obtained from conventional commercial sources or by existing known methods.

[0053] Figure 1 This is a schematic diagram of the implementation method in the embodiments of the present invention, including the design and preparation of coherent heterogeneous interfaces, the mechanism of action, and the effects and universality of the present invention.

[0054] Example 1 An AlAs / GaAs heterostructure, denoted as Structure 1, includes a GaAs substrate, an AlAs layer (semiconductor material), and a GaAs layer (modification layer) stacked together, used to improve the thermal conductivity of AlAs. Its structural schematic diagram is shown below. Figure 2 As shown in (A) above, the specific preparation method is as follows: First, in the molecular beam epitaxy system, a 4.7 μm AlAs layer is grown on a GaAs(001) substrate via molecular beam epitaxy, followed by an in-situ growth of a 10 nm GaAs layer to stabilize the AlAs surface. Second, in the magnetron sputtering deposition system, an 80-100 nm metal layer, specifically an aluminum film, is deposited as a metal transducer for thermal characterization using a time-domain thermal reflection system.

[0055] Comparative Example 1 An AlAs / GaAs heterostructure, denoted as Structure 2, includes a GaAs substrate and an AlAs layer (semiconductor material) stacked together, as shown in the schematic diagram below. Figure 2 As shown in (B) above, the specific preparation method is as follows: First, in the molecular beam epitaxy system, 4.3 μm AlAs is grown on a GaAs(001) substrate via molecular beam epitaxy, followed by in-situ deposition of an amorphous arsenic (As) layer to stabilize the AlAs surface. Second, in the magnetron sputtering deposition system, the As layer on the surface is removed by high-temperature heating, followed by in-situ deposition of an 80-100 nm metal layer, specifically an aluminum film, as a metal transducer for thermal characterization using a time-domain thermal reflection system.

[0056] Using time-domain thermal reflectometry, variable-temperature tests were conducted on the AlAs layers of structure 1 in Example 1 and structure 2 in Comparative Example 1. The test temperature range was from room temperature to 600K, and the test area was 1-2 μm deep at the upper GaAs / AlAs interface. Specifically, the test area for structure 1 was the region of the AlAs layer near the upper GaAs / AlAs interface and far from the lower AlAs / GaAs interface, where the upper GaAs / AlAs interface exists; the test area for structure 2 was the region of the AlAs layer near the upper Al / AlAs interface and far from the lower AlAs / GaAs interface, where no AlAs / GaAs interface exists.

[0057] Figure 3 The results show the thermal conductivity test results of the AlAs layer for structure 1 in Example 1 and structure 2 in Comparative Example 1; wherein, at 300K, the test depth of structure 1 is 1.37 μm and the test depth of structure 2 is 1.26 μm. From... Figure 3 As can be seen, in structure 2, the thermal conductivity of the upper AlAs layer (without interfacial interaction) is 84 W·m at room temperature. -1 ·K -1 The intrinsic thermal conductivity of AlAs measured in previous literature is consistent with that of AlAs; however, in structure 1, the thermal conductivity of the upper AlAs layer (with interfacial interaction) is 104 W·m at room temperature. -1 ·K -1 The thermal resistance is 24% higher than the intrinsic value of AlAs. Furthermore, in structure 2, the thermal resistance of the upper AlAs (without interface effect) is the sum of the three-phonon and four-phonon thermal resistances in the temperature range; while in structure 1, the thermal resistance of the upper AlAs (with interface effect) is only the three-phonon thermal resistance in the temperature range.

[0058] The results show that coherent heterostructures help to overcome the intrinsic thermal conductivity limit of materials and improve it by suppressing the thermal resistance of higher-order phonons inside the material.

[0059] Table 1 shows the specific AlAs thermal conductivity data for structure 1 in Example 1 and structure 2 in Comparative Example 1. As can be seen from Table 1, compared with structure 2, structure 1 has a significantly higher degree of improvement in thermal conductivity at high temperatures, indicating that the heterostructures of the embodiments of the present invention can function in the range from room temperature to high temperature, and the effect is more obvious under high temperature conditions.

[0060] Table 1. AlAs thermal conductivity test data for structure 1 in Example 1 and structure 2 in Comparative Example 1

[0061] Example 2 An AlAs / GaAs heterostructure, denoted as Structure 3, includes a GaAs substrate, an AlAs layer, and a GaAs layer stacked together, used to improve the thermal conductivity of the GaAs substrate and the AlAs layer. Its structural schematic diagram is shown below. Figure 4 As shown in (A) above, the specific preparation method is as follows: First, in the molecular beam epitaxy system, a 2 μm AlAs layer is grown on a GaAs(001) substrate via molecular beam epitaxy, followed by an in-situ growth of a 10 nm GaAs layer to stabilize the AlAs surface. Second, in the magnetron sputtering deposition system, an 80-100 nm metal layer, specifically an aluminum film, is deposited as a metal transducer for thermal characterization using a time-domain thermal reflection system.

[0062] Comparative Example 2 A GaAs structure, denoted as structure 4, includes a GaAs substrate, and its schematic diagram is shown below. Figure 4 As shown in (B) above, the specific preparation method is as follows: In a magnetron sputtering deposition system, an 80-100 nm metal layer, specifically an aluminum film, is directly deposited on a GaAs(001) substrate to serve as a metal transducer for thermal characterization using a time-domain thermal reflection system. This structure serves as a sample for testing the intrinsic thermal conductivity of GaAs.

[0063] Using time-domain thermal reflectometry, the AlAs layer and GaAs substrate in structure 3, as well as the GaAs substrate in structure 4, were tested at room temperature. The test area was 0-7 μm deep from the AlAs layer / GaAs substrate interface.

[0064] Figure 5 The thermal conductivity test results are for the AlAs layer and GaAs substrate of structure 3 in Example 2. From... Figure 5 It can be seen that the thermal conductivity of the AlAs layer in structure 3 is 106 W·m at room temperature. -1 ·K -1 This is consistent with the thermal conductivity performance of AlAs under three-phonon scattering conditions. With increasing thermal penetration depth, within 2 μm of the AlAs / GaAs substrate interface, the thermal conductivity of the GaAs substrate is 53 W·m⁻¹. -1 ·K -1 The thermal conductivity of GaAs under three-phonon scattering is consistent with that of GaAs, while the thermal conductivity of the GaAs substrate gradually decreases with distance from the AlAs / GaAs interface to an intrinsic thermal conductivity value of 43 W·m. -1 ·K -1 That is, the thermal conductivity under three-phonon + four-phonon scattering.

[0065] Figure 6 The thermal conductivity test results are for the GaAs substrate with structure 4 in Comparative Example 2. From... Figure 6It can be seen that the intrinsic thermal conductivity of GaAs in structure 4 is 43 W·m. -1 ·K -1 It satisfies the thermal conductivity under three-phonon + four-phonon scattering.

[0066] The results show that the effect of using coherent heterostructures to improve the intrinsic thermal conductivity of materials can be applied to both ends of the material forming the interface.

[0067] Example 3 An AlGaAs / AlAs heterostructure, denoted as Structure 5, comprises a GaAs substrate, an AlGaAs layer (modification layer), an AlAs layer (semiconductor material), and a GaAs layer (modification layer) stacked together, used to improve the thermal conductivity of AlAs. Its structural schematic diagram is shown below. Figure 7 As shown, the specific preparation method is as follows: First, in the molecular beam epitaxy system, a 100 nm AlGaAs layer is grown on a GaAs(001) substrate via molecular beam epitaxy, followed by the growth of 2 μm AlAs, and then an in-situ growth of a 10 nm GaAs layer to stabilize the AlAs surface. Second, in the magnetron sputtering deposition system, an 80-100 nm metal layer, specifically an aluminum film, is deposited as a metal transducer for thermal characterization using a time-domain thermal reflection system.

[0068] The AlAs layer in structure 5 was tested at room temperature using time-domain thermal reflectometry. The test area was 1-2 μm deep from the AlAs / GaAs interface, where the upper and lower interfaces interacted.

[0069] Figure 8 The results show the thermal conductivity test results of the AlAs layer for structure 5 in Example 3 and structure 3 in Example 2; the test depth for structure 5 is 1.37 μm from the AlAs / GaAs interface and 0.63 μm from the AlAs / AlGaAs interface; the test depth for structure 3 is 1.37 μm from the upper AlAs / GaAs interface. Figure 8 As can be seen, in structure 5, the thermal conductivity of AlAs is 103 W·m at room temperature. -1 ·K -1 The thermal conductivity is consistent with that of AlAs in structure 3, which is in line with the thermal conductivity of AlAs under three-phonon scattering only.

[0070] The results show that the material forming the coherent heterogeneous interface can be either a crystalline layer or an alloy layer.

[0071] Example 4 An InGaAs / InP heterostructure, denoted as Structure 6, includes a stacked InP substrate (semiconductor material) and an InGaAs layer (modification layer) to improve the thermal conductivity of InP. A schematic diagram of its structure is shown below. Figure 9 As shown in (A) above, the specific preparation method is as follows: First, in the molecular beam epitaxy system, a 28 nm InGaAs layer is grown on an InP(001) substrate using molecular beam epitaxy. Second, in the magnetron sputtering deposition system, an 80-100 nm metal layer, specifically an aluminum film, is deposited as a metal transducer for thermal characterization using a time-domain thermal reflection system.

[0072] Comparative Example 3 An InP structure, denoted as structure 7, includes an InP substrate (semiconductor material), and its schematic diagram is shown below. Figure 9 As shown in (B) above, the specific preparation method is as follows: In a magnetron sputtering deposition system, an 80-100 nm metal layer, specifically an aluminum film, is directly deposited on the same InP(001) substrate to serve as a metal transducer for thermal characterization using a time-domain thermal reflection system. This structure serves as a sample for testing the intrinsic thermal conductivity of InP.

[0073] The InP in structure 6 of Example 4 and structure 7 of Comparative Example 3 were tested at room temperature using time-domain thermal reflectometry. The test area for structure 6 was 1-6 μm deep from the InGaAs / InP interface, and the test area for structure 7 was 1-6 μm deep from the metal / InP interface.

[0074] Figure 10 The results are the thermal conductivity test results of the InP layer of structure 6 in Example 4. Figure 11 The thermal conductivity test results for the InP layer in structure 7 of Comparative Example 3 are shown. From... Figure 11 It can be seen that the intrinsic thermal conductivity of InP in structure 7 is 67 W·m at room temperature. -1 ·K -1 This conforms to the thermal conductivity performance under triphonic + tetraphonic heat dissipation. And according to... Figure 10 In structure 6, the thermal conductivity of InP at room temperature is 102 W·m⁻² near the coherent InGaAs / InP interface (1-2 μm). -1 ·K -1 The eigenvalues ​​of InP are improved by 52%, and this almost matches the thermal conductivity of InP under three-phonon scattering conditions. Furthermore, the thermal conductivity of InP gradually decreases with increasing distance from the coherent InGaAs / InP interface.

[0075] The results show that the method of the present invention can be applied to a variety of semiconductor materials and has wide applicability.

[0076] Comparative Example 4 An InGaAs / InP heterostructure, denoted as Structure 8, includes a stacked InP substrate (semiconductor material) and an InGaAs layer (modification layer). As a comparative sample to Structure 6, its structural schematic diagram is shown below. Figure 12 As shown, the specific preparation method is as follows: First, an additional 10-30 nm InGaAs layer is grown on the InP(001) substrate via molecular beam epitaxy. However, the InGaAs / InP interface remains defective, exhibiting non-atomic flatness and not fully forming a coherent interface. Second, an 80-100 nm metal layer, specifically an aluminum film, is deposited in a magnetron sputtering deposition system to serve as a metal transducer for thermal characterization using a time-domain thermal reflection system.

[0077] The InP in structure 8 was tested at room temperature using time-domain thermal reflectometry, with the test area being 1-6 μm deep from the InGaAs / InP interface.

[0078] Figure 13 The results show the thermal conductivity of the InP layer in structure 8 of Comparative Example 4. Figure 13 It is evident that at room temperature, the thermal conductivity of InP in structure 8 is consistent with that of the intrinsic InP substrate in structure 7, and it conforms to the thermal conductivity performance under three-phonon + four-phonon heat dissipation. This indicates that if there are defects at the interface or in an incoherent interface, the defects will disrupt the non-equilibrium transport of phonons at the interface, thereby causing the disappearance of the breakthrough effect on the thermal conductivity limit of the material and failing to improve the intrinsic thermal conductivity of the material.

[0079] In summary, this invention proposes a semiconductor heterostructure based on coherent heterointerface engineering, whose thermal conductivity exceeds the intrinsic limit of semiconductor materials. By constructing a semiconductor heterostructure with a coherent heterointerface, phonon transport near the interface is placed in a non-equilibrium state, thereby modulating the phonon-phonon scattering process, reducing the thermal resistance caused by higher-order phonon scattering, prolonging the phonon relaxation time, and improving the intrinsic thermal conductivity of the material. This invention only requires interface engineering and does not require the introduction of new materials. The fabrication process of the semiconductor heterostructure is compatible with existing chip fabrication processes, making it highly feasible.

Claims

1. A semiconductor heterostructure, characterized in that, It includes a semiconductor material and a modified layer stacked together; the interface between the semiconductor material and the modified layer is a coherent heterojunction interface; the semiconductor material and the modified layer are acoustically phonon matched but optically phonon mismatched; the semiconductor material and the modified layer each independently include a III-V group semiconductor material.

2. The semiconductor heterostructure according to claim 1, characterized in that, The interface between the semiconductor material and the modified layer is an atomically flat interface; the depth of the interface diffusion layer of the atomically flat interface is ≤3nm; And / or, the lattice mismatch rate between the semiconductor material and the modified layer is ≤5%.

3. The semiconductor heterostructure according to claim 1, characterized in that, The semiconductor material includes at least one of AlAs, GaAs, InP, AlGaAs, or InGaAs; And / or, the modified layer includes at least one of AlAs, GaAs, InP, AlGaAs, or InGaAs.

4. The semiconductor heterostructure according to claim 3, characterized in that, The semiconductor material and the modified layer include at least one of the following combinations: the semiconductor material is AlAs and the modified layer is GaAs; the semiconductor material is GaAs and the modified layer is AlAs; the semiconductor material is AlAs and the modified layer is AlGaAs; the semiconductor material is InP and the modified layer is InGaAs.

5. The semiconductor heterostructure according to claim 1, characterized in that, The thickness of the modified layer is ≥8nm.

6. The semiconductor heterostructure according to claim 1, characterized in that, The semiconductor material has a region whose thermal conductivity exceeds its intrinsic thermal conductivity limit, and the thickness of the region is ≤3μm; or, the thickness of the semiconductor material is ≤the phonon mean free path of the semiconductor material.

7. A method for improving the intrinsic thermal conductivity of a semiconductor, characterized in that, The method includes the following steps: depositing a modification layer on the surface of a semiconductor material to improve the intrinsic thermal conductivity of the semiconductor material, thereby obtaining a semiconductor heterostructure as described in any one of claims 1 to 6.

8. The method according to claim 7, characterized in that, The application environment temperature of the semiconductor heterostructure is ≥290K.

9. A chip, characterized in that, The chip comprises a semiconductor heterostructure as described in any one of claims 1 to 6.

10. An electronic device, characterized in that, The electronic device includes a semiconductor heterostructure according to any one of claims 1 to 6, or a chip according to claim 9.

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