LED chip current equalization structure and method based on optimized copper film thickness

Abstract

The application discloses a kind of LED chip current sharing structure and method based on optimization copper film thickness, this scheme aims at the problem of " current rob " and luminous brightness inconsistency caused by uneven line resistance in multi-chip LED product, innovative structure improvement is proposed.The core is that the copper film thickness of the conductive line carrying and connecting multiple LED chips is increased from the conventional thin layer specification to thicker half ounce specification.This thickening design significantly reduces the resistance value and its difference of line itself, so that the current in each parallel chip branch can automatically realize balanced distribution, thereby fundamentally eliminating the phenomenon of uneven brightness.The method does not need to rely on complex active current sharing circuit or additional discrete components, by optimizing the inherent structure parameters of substrate line, the optical uniformity of product can be improved, the current carrying and heat dissipation capacity of line can be enhanced, and it is fully compatible with existing production process, with the outstanding advantages of simple structure, low cost and high reliability.

Description

Technical Field

[0001] This invention relates to the field of light-emitting diode (LED) packaging technology, specifically to an LED chip current sharing structure and method based on optimized copper film thickness. Background Technology

[0002] In multi-chip LED products (such as COB light sources and LED modules), multiple LED chips are typically electrically interconnected via internal metal circuits to operate in parallel or mixed configurations. A long-standing technical challenge in practical applications is the "current competition" phenomenon: due to slight differences in the volt-ampere characteristics of each LED chip, and the inherent resistance of the metal circuits connecting the chips (which varies due to manufacturing tolerances such as path length and width), current tends to concentrate along the path of lowest impedance under the same voltage. This results in uneven current flow through the parallel-connected chips, directly manifesting as inconsistent luminous brightness, producing noticeable bright and dark patches, and severely impacting the product's optical quality, appearance consistency, and user experience.

[0003] To alleviate the problem of uneven brightness, existing technologies typically employ the following approaches: First, adding a complex active current sharing control circuit to the driver circuit, which significantly increases system cost and design complexity; second, connecting precision current sharing resistors in series on the branches of each chip, but this introduces additional power consumption, heat generation, and increases material and soldering costs; third, performing extremely rigorous grading and matching of LED chips, which significantly increases the requirements and production costs of the upstream chip supply chain. None of these solutions fundamentally solve the "current competition" problem caused by the uneven resistance of the circuit itself, or they come at the cost of sacrificing cost, efficiency, or process feasibility.

[0004] Therefore, the industry urgently needs a solution that is simple in structure, low in cost, and seamlessly compatible with existing production processes to improve the uniformity of current distribution from a physical structure perspective. Summary of the Invention

[0005] To address the shortcomings of the existing technology, the purpose of this invention is to provide an LED chip current sharing structure and method based on optimized copper film thickness, so as to solve the problems mentioned in the background art.

[0006] To achieve the above objectives, a specific embodiment of the present invention provides an LED chip current sharing structure based on optimized copper film thickness, comprising: a substrate; conductive lines disposed on the substrate for conducting current; and a plurality of LED chips electrically connected to the conductive lines; wherein the conductive lines include a copper film, and the thickness of the copper film is 17.5 micrometers.

[0007] In addition, the LED chip current sharing structure and method based on optimized copper film thickness proposed in this application may also have the following additional technical features: In one embodiment of this application, the thickness of the copper film is the standard thickness corresponding to 1 / 2 ounce copper foil.

[0008] In one embodiment of this application, the plurality of LED chips are electrically connected in parallel on the conductive line.

[0009] In one embodiment of this application, the substrate is one of a metal substrate, a ceramic substrate, and a printed circuit board.

[0010] In one embodiment of this application, the plurality of LED chips are arranged in an array on the substrate.

[0011] A current sharing method for LED chips based on optimized copper film thickness includes the following steps: S1: Provides a substrate; S2: A conductive line is formed on the substrate; S3: Electrically connect multiple LED chips to the conductive line; Specifically, by setting the thickness of the copper film contained in the conductive circuit to 17.5 micrometers, the resistance of the conductive circuit is reduced, thereby making the current flowing through the multiple LED chips more evenly distributed.

[0012] In one embodiment of this application, in step S2, the thickness of the copper film is achieved by using 1 / 2 ounce of copper foil material.

[0013] In one embodiment of this application, in step S2, the thickness of the copper film is increased from the conventionally used 12.5 micrometers to 17.5 micrometers.

[0014] In one embodiment of this application, a design step is included before step S1: S0: Determine the arrangement and electrical connection method of the plurality of LED chips; Based on simulation or calculation, the influence of line resistance on current distribution is analyzed under standard thin copper film conditions. Based on the analysis results, the target copper film thickness of the conductive circuit is designed to be 17.5 micrometers.

[0015] The advantages of this invention compared to existing technologies are: (1) By increasing the thickness of the copper film of the conductive lines from the conventional 12.5 micrometers (1 / 3 ounce) to 17.5 micrometers (1 / 2 ounce), the DC resistance of the lines is significantly reduced. This makes the small differences in line impedance caused by manufacturing tolerances extremely small relative to the impedance of the chip itself and the impedance of the thickened lines, thereby effectively eliminating the physical basis for uneven current distribution, making the current of each parallel chip naturally balanced, and achieving excellent light emission consistency.

[0016] (2) The thicker copper film provides higher current carrying capacity and better thermal conductivity. This structure can support product designs with higher power and more chips, expanding application scenarios. At the same time, the reduced heat generation of the circuit helps to lower the overall operating temperature, delay material light decay and aging, thereby improving the long-term reliability and service life of the product.

[0017] (3) This invention optimizes only one parameter (copper film thickness) in the existing mature production process without adding any additional electronic components or complex packaging layers, and is fully compatible with existing printed circuit board (PCB) or metal substrate (MCPCB) manufacturing processes. While significantly improving the core optical performance of the product, it increases production costs almost without increasing production costs, thus possessing strong market competitiveness.

[0018] (4) The thickened copper film has higher mechanical strength, which can better resist thermal cycling stress, reduce the risk of microcracks in the circuit or fatigue of the solder joint caused by thermal expansion and contraction, reduce the probability of poor contact and open circuit failure, and further improve the overall quality and durability of the product.

[0019] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 This is a schematic diagram of the connection relationship of an LED chip current sharing structure based on optimized copper film thickness in one embodiment of the present invention; Figure 2 This is a schematic diagram of the electrical connection relationship of an LED chip current sharing structure based on optimized copper film thickness in one embodiment of the present invention; Figure 3This is a schematic diagram of an LED chip current sharing method based on optimized copper film thickness in one embodiment of the present invention; Figure 4 This is a schematic diagram of an LED chip current sharing structure based on optimized copper film thickness in one embodiment of the present invention.

[0022] Explanation of reference numerals in the attached figures: 1. Substrate; 2. Conductive circuit; 3. LED chip. Detailed Implementation

[0023] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0024] like Figures 1 to 4 As shown in the figure, an embodiment of the present invention provides an LED chip current sharing structure and method based on optimized copper film thickness. The structure mainly includes a substrate 1, conductive lines 2 formed on the substrate 1, and a plurality of LED chips 3 fixed and electrically connected to the conductive lines 2.

[0025] In one embodiment of this application, the substrate 1 serves as the mechanical support and heat dissipation carrier for the entire structure, and its material can be selected according to the product power and heat dissipation requirements. In this embodiment, the substrate 1 can be, but is not limited to: a metal substrate (such as an aluminum substrate, which typically includes a metal substrate, an insulating layer, and a copper foil circuit layer), a ceramic substrate with high thermal conductivity (such as an alumina or aluminum nitride substrate), or a common glass fiber printed circuit board. The selection of the substrate 1 is a conventional choice for those skilled in the art and does not affect the implementation of the core improvement of this invention.

[0026] In one embodiment of this application, the conductive line 2 is the core improved component for achieving the current sharing function of the present invention. The conductive line 2 is formed on the surface of the substrate 1 through conventional processes such as printing, bonding, etching, or electroplating. The core constituent material of the conductive line 2 is metallic copper, that is, its main body is a continuous copper film. The present invention does not impose special restrictions on the graphic design of the conductive line 2 (such as line width, line spacing, and routing path), and any known circuit layout suitable for multi-chip LED connections can be adopted. The key feature of the present invention, which distinguishes it from the prior art, is that the physical thickness of the copper film constituting the conductive line 2 is specifically set to 17.5 micrometers. This thickness value corresponds to the nominal thickness of the standard "1 / 2 ounce" copper foil in the electronics industry. This means that when manufacturing the substrate 1 or making the conductive line 2, it is necessary to select copper foil nominally labeled as 1 / 2 ounce as raw material, or to ensure that the final copper film thickness of the circuit reaches approximately 17.5 micrometers through methods such as electroplating thickening.

[0027] In one embodiment of this application, the plurality of LED chips 3 are die-bonded and attached to predetermined pads or die-bearing positions on the conductive line 2 using conductive adhesive (such as silver paste) or solder. The electrical connection relationship between the plurality of LED chips 3 is determined by the pattern of the conductive line 2. In a preferred embodiment of the present invention, the plurality of LED chips 3 are electrically connected in parallel. That is, the positive terminals of all LED chips 3 are connected to a common positive input terminal through a branch network of the conductive line 2, and the negative terminals of all LED chips 3 are connected to a common negative input terminal through another branch network of the conductive line 2. This parallel connection method makes the "current grabbing" phenomenon most significant, and therefore the current sharing effect of the present invention is particularly evident in this type of structure. In addition, the spatial arrangement of the plurality of LED chips 3 on the substrate 1 can be a regular array arrangement (such as a matrix) or other irregular arrangement adapted to the product optical design. The arrangement method does not affect the implementation of the current sharing principle of the present invention.

[0028] Working principle and workflow Combination Figure 3 The flowchart below details the specific implementation steps and internal logic of the flow equalization method of the present invention.

[0029] Step S0 (Design Step): Before physical fabrication, electrical and structural design is performed first. Designers determine the number, specific model (nominal voltage Vf), and physical arrangement and electrical connection method (usually parallel) of the LED chips 3 to be integrated, based on the optical output requirements (e.g., luminous flux, color temperature), size constraints, and driving conditions (e.g., operating current, voltage) of the target LED product. Subsequently, based on the preliminary circuit layout pattern, an electrical model is established using circuit simulation software (e.g., SPICE) or through theoretical calculations. In this model, the resistance of the conductive lines 2 connecting each LED chip 3 is modeled as a distributed resistance based on the parameters of a standard thin copper film (e.g., 1 / 3 ounce, approximately 12.5 micrometers thick). Through simulation analysis, it is possible to identify in advance which parallel branches will have relatively high or low impedances due to differences in line path length under standard thin copper film conditions, thereby predicting the areas where "current snatching" may occur and the degree of current non-uniformity. This analysis step provides crucial design basis. Based on the analysis, the designers made a key decision: to increase the target copper film thickness of conductive line 2 from the conventional 12.5 micrometers to 17.5 micrometers (i.e., using 1 / 2 ounce copper foil). This decision is based on the following physical principle: for a conductor with a fixed cross-section, its resistance R is directly proportional to the resistivity ρ and the length L, and inversely proportional to the cross-sectional area A (R = ρL / A). Increasing the copper film thickness is equivalent to increasing the vertical dimension of the conductor, thereby increasing the cross-sectional area A. According to the formula, with the length L and material (ρ) remaining constant, increasing the cross-sectional area A will directly lead to a decrease in resistance R. Therefore, step S0 is the key logical link connecting "problem identification" and "solution formulation".

[0030] Step S1 (Providing the substrate): Based on the design completed in Step S0, procure or fabricate a substrate 1 that meets the requirements. If substrate 1 is a purchased standard substrate (such as a copper-clad laminate), ensure that the nominal thickness of the copper foil attached to it is 1 / 2 ounce (approximately 17.5 micrometers). If substrate 1 is custom-made or requires electroplating to form circuitry, the process specifications must explicitly require the final conductive layer thickness to reach 17.5 micrometers.

[0031] Step S2 (Forming Conductive Circuits): On the prepared substrate 1, the conductive circuit pattern 2 designed in step S0 is fabricated. If the substrate 1 is a copper-clad substrate, conventional printed circuit board manufacturing processes are used: First, photoresist is coated on the surface of a 1 / 2 ounce thick copper foil. The circuit pattern is transferred onto the photoresist through exposure and development. Then, the copper not protected by the photoresist is etched away using chemical etching. Finally, the photoresist is removed, thereby obtaining conductive circuits 2 with precise patterns and a copper film thickness of approximately 17.5 micrometers. This step is the key physical manufacturing step for achieving the core feature of this invention, "17.5-micrometer thick copper film".

[0032] Step S3 (Connecting LED Chips): Multiple LED chips 3 are mounted and electrically connected to the conductive line 2 created in step S2 using die bonding and bonding processes. Specifically, using an adhesive material with good thermal and electrical conductivity (such as silver paste), the back side (usually the cathode) of each LED chip 3 is fixed to the corresponding die holder (pad) on the conductive line 2. Subsequently, using a wire bonder, the positive electrode of each LED chip 3 is bonded to the corresponding positive electrode pad on the conductive line 2 using metal bonding wire (such as gold wire), completing all electrical connections. At this point, a complete physical fabrication of an LED chip current sharing structure based on optimized copper film thickness is completed.

[0033] Workflow and flow equalization principle: When an external driving power supply applies a working voltage to the common input terminal of the structure, current flows from the positive terminal into the conductive line 2, and is distributed to each parallel LED chip 3 through the branch network of the conductive line 2. After flowing through the chip, the current is then collected in the negative terminal line and returns to the power supply.

[0034] In existing technologies using thin copper films (e.g., 12.5 micrometers), the resistance of the conductive line 2 itself is relatively large. Due to manufacturing tolerances, there are slight differences (ΔR_line) in the resistance of the specific circuit paths connecting different LED chips 3. This difference in line resistance (ΔR_line) is superimposed on the dynamic resistance (R_chip) of each LED chip 3, affecting the total impedance of each branch. According to the current division principle of parallel circuits, the current will tend to flow to the path with the lowest total impedance, resulting in a severe imbalance of current (I_chip) among the chips, i.e., "current snatching".

[0035] In this invention, because the copper film thickness of conductive line 2 is increased to 17.5 micrometers, the basic resistance value (R_line) of each path is significantly reduced according to the aforementioned resistance formula. More importantly, the absolute difference in line resistance (ΔR_line) is also greatly reduced. At this point, the value of ΔR_line becomes negligible compared to R_chip and the thickened R_line. Therefore, the total impedance of each parallel branch is mainly determined by the relatively uniform dynamic resistance R_chip of the LED chip 3 itself, while the influence of the slight non-uniformity of line impedance caused by manufacturing tolerances on current distribution is greatly suppressed. As a result, the current flowing through each parallel LED chip 3 automatically tends to be equal (I_chip1 ≈ I_chip2 ≈ ... ≈ I_chipN), thereby achieving uniform current distribution, ultimately resulting in highly consistent luminous brightness of all LED chips 3. The entire process requires no external active control and is achieved entirely through optimization of passive structural parameters.

[0036] The technical solution described in the above-described embodiments of this application effectively reduces line resistance and its inconsistencies by optimizing the copper film thickness of the conductive line 2 from the conventional 12.5 micrometers (1 / 3 ounce) to 17.5 micrometers (1 / 2 ounce), thereby fundamentally suppressing the "current grabbing" phenomenon when multiple chips are connected in parallel. This method can achieve automatic current sharing among the three LED chips without adding additional components or complex circuits, ultimately resulting in LED products with uniform light emission, improved performance, and controllable costs.

[0037] Obviously, the above-described embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention also intends to include these modifications and variations.

Claims

1. A current sharing structure for LED chips based on optimized copper film thickness, characterized in that, include: substrate(1); Conductive lines (2) are disposed on the substrate (1) for conducting current; Multiple LED chips (3) are electrically connected to the conductive line (2); The conductive line (2) includes a copper film with a thickness of 17.5 micrometers.

2. The LED chip current sharing structure based on optimized copper film thickness according to claim 1, characterized in that, The thickness of the copper film is the standard thickness corresponding to 1 / 2 ounce copper foil.

3. The LED chip current sharing structure based on optimized copper film thickness according to claim 1, characterized in that, The plurality of LED chips (3) are electrically connected in parallel to the conductive line (2).

4. The LED chip current sharing structure based on optimized copper film thickness according to claim 1, characterized in that, The substrate (1) is one of a metal substrate, a ceramic substrate, and a printed circuit board.

5. The LED chip current sharing structure based on optimized copper film thickness according to claim 1, characterized in that, The plurality of LED chips (3) are arranged in an array on the substrate (1).

6. A current sharing method for LED chips based on optimized copper film thickness, characterized in that, Includes the following steps: S1: Provide substrate (1); S2: A conductive line (2) is formed on the substrate (1); S3: Electrically connect multiple LED chips (3) to the conductive line (2); In this process, by setting the thickness of the copper film contained in the conductive line (2) to 17.5 micrometers, the resistance of the conductive line (2) is reduced, thereby making the current flowing through the multiple LED chips (3) more evenly distributed.

7. The LED chip current sharing method according to claim 6, characterized in that, In step S2, the thickness of the copper film is achieved by using 1 / 2 ounce of copper foil material.

8. The LED chip current sharing method according to claim 6, characterized in that, In step S2, the thickness of the copper film is increased from the conventional 12.5 micrometers to 17.5 micrometers.

9. The LED chip current sharing method according to claim 6, characterized in that, Before step S1, a design step is also included: S0: Determine the arrangement and electrical connection of the plurality of LED chips (3); Based on simulation or calculation, the influence of line resistance on current distribution is analyzed under standard thin copper film conditions. Based on the analysis results, the target copper film thickness of the conductive line (2) is designed to be 17.5 micrometers.

Images