A method for in-situ etching of a semiconductor device

Abstract

The application discloses a method for in-situ etching of a semiconductor device, and the method comprises the following steps: once deposition; in-situ etching, wherein the in-situ etching step comprises the following steps: etching temperature is 600-1000 DEG C, etching gas and silicon source gas are introduced into a chamber to etch a wafer in the chamber, the flow ratio of the silicon source gas to the etching gas is (0.05-0.85):1, and when the etching temperature fluctuation range is within ±10 DEG C, the change rate of the etching rate is less than 5%. In a specific etching temperature range, the application effectively reduces the sensitivity of the etching rate to the temperature in the etching step by adding a specific amount of silicon source gas into the etching gas, thereby significantly improving the stability of the etching rate.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method for in-situ etching of semiconductor devices. Background Technology

[0002] In semiconductor manufacturing, core processes such as thin film deposition and etching are typically performed on wafers within the chambers of epitaxial equipment. These chambers are formed by connecting upper and lower domes. Since chemical vapor deposition (CVD) reactions are primarily influenced by the chamber's temperature and flow fields, optimizing the chamber structure and improving hardware precision allows for precise control of the flow field and pressure, laying the foundation for stable CVD reactions.

[0003] However, precise control of the cavity temperature field in chemical vapor deposition (CVD) is extremely difficult. During wafer thin film deposition, film layers are also deposited on the inner surfaces (cavity walls) of the upper and lower domes, affecting the uniformity of light transmission through these layers. When thermal radiation passes through the unevenly transmitted upper and lower domes, it leads to uneven temperature distribution on the wafer. This is especially true for mid-to-low temperature processes, which are highly sensitive to temperature control due to chemical reactions; instability in the cavity temperature field can affect process stability.

[0004] Currently, existing technologies typically employ a cyclic cleaning method, where the chamber is cleaned after each thin-film deposition process to remove the film layer on the inner wall of the chamber, thereby restoring a stable temperature field. However, this cyclic cleaning method is not applicable in the Dep-Etch-Dep process. This process requires that after the first deposition step, the wafer is not moved out of the chamber before the second etching step. At this time, the film layer formed on the inner wall of the chamber during the first deposition step has not been removed, which will seriously interfere with the chamber temperature during the second etching step, leading to significant temperature fluctuations. The etching rate is extremely sensitive to temperature; significant changes in chamber temperature will result in a highly unstable etching rate, not only reducing etching accuracy but also causing poor etching consistency between wafers, seriously affecting product quality and process stability.

[0005] The statements herein provide only background information in relation to this invention and do not necessarily constitute prior art. Summary of the Invention

[0006] The purpose of this invention is to provide a method for in-situ etching of semiconductor devices. Within a specific etching temperature range, by adding a specific amount of silicon source gas to the etching gas, the sensitivity of the etching rate to temperature during the etching step is effectively reduced, thereby significantly improving the stability of the etching rate.

[0007] To achieve the above objectives, the present invention provides a method for in-situ etching of semiconductor devices. The method includes: a single deposition; and in-situ etching. The in-situ etching step includes: an etching temperature of 600℃~1000℃, introducing an etching gas and a silicon source gas into a cavity to etch the wafer in the cavity, wherein the flow rate ratio of the silicon source gas to the etching gas is (0.05~0.85):1, the etching temperature fluctuation range is within ±10℃, and the etching rate variation rate is less than 5%.

[0008] Optionally, the flow rate ratio of the silicon source gas to the etching gas is (0.2~0.5):1.

[0009] Optionally, the flow rate of the etching gas is 1 slm to 3 slm, and the flow rate of the silicon source gas is 0.05 slm to 2.5 slm.

[0010] Optionally, the silicon source gas is at least one of dichlorosilane and silane gas.

[0011] Optionally, the etching gas is at least one of HCl and Cl2.

[0012] Optionally, when the etching gas is HCl, the etching temperature is 800℃~1000℃; when the etching gas is Cl2, the etching temperature is 600℃~1000℃.

[0013] Optionally, the in-situ etching step further includes: introducing hydrogen gas as a carrier gas, with a hydrogen flow rate of 10 slm to 30 slm.

[0014] Optionally, the process pressure inside the chamber is 30 torr to 200 torr.

[0015] Optionally, after the in-situ etching step is completed, a second in-situ deposition is performed.

[0016] Compared with the prior art, the technical solution of the present invention has at least the following beneficial effects: In in-situ deposition-etching-deposition processes within the same chamber, deposition is first performed on the wafer surface, followed by etching, and finally deposition again. Because the film deposited on the chamber wall during the first deposition step causes significant temperature changes, and the etching gas is extremely sensitive to temperature, the etching rate during the second etching step becomes highly unstable. Therefore, this invention innovatively adds an appropriate amount of silicon source gas to the etching gas. Within the etching temperature range of 600℃ to 1000℃, both the etching rate of the etching gas and the reaction rate of the silicon source gas are positively correlated with temperature. Through the synergistic effect of the etching gas and the silicon source gas, and by controlling the flow ratio of silicon source gas to etching gas to be (0.05~0.85):1, the presence of silicon source gas can suppress significant changes in the etching rate due to large temperature variations (when the etching temperature fluctuation range is within ±10℃, the rate of change in etching rate is less than 5%), thereby effectively reducing the temperature sensitivity of the etching rate and significantly improving the stability of the etching rate. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the structure of an existing epitaxial device.

[0018] Figure 2 The graph shows the etching rate as a function of temperature when different flow ratios of dichlorosilane and HCl are used in this invention.

[0019] Figure 3 The graph shows the temperature changes of the platform when the dichlorosilane and HCl are used in different flow ratios according to the present invention.

[0020] Attached image labels: Epitaxial device 100, upper dome 110, lower dome 120, chamber 130, wafer 200, first heating component 300, second heating component 400. Detailed Implementation

[0021] The following detailed description, in conjunction with the accompanying drawings and specific embodiments, provides a further detailed explanation of the in-situ etching method for semiconductor devices proposed in this invention. The advantages and features of this invention will become clearer from the following description. It should be noted that the drawings are in a very simplified form and use non-precise proportions, used only to facilitate and clearly illustrate the embodiments of this invention. Please refer to the drawings to make the objectives, features, and advantages of this invention more apparent and understandable. It should be understood that the structures, proportions, sizes, etc., depicted in the accompanying drawings are only for illustrative purposes to aid those skilled in the art and are not intended to limit the implementation conditions of this invention. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments to the size, without affecting the effects and objectives achieved by this invention, should still fall within the scope of the technical content disclosed in this invention.

[0022] In the semiconductor manufacturing field, epitaxial equipment is crucial for growing semiconductor materials. The epitaxial process demands extremely high temperature uniformity to ensure consistent deposition quality on the wafer surface. Existing epitaxial equipment, such as... Figure 1 As shown, the structure includes a dome, a chamber, and heating components. The dome comprises an upper dome 110 and a lower dome 120, which are fixed to the sidewalls by upper and lower flanges to form a sealed chamber 130 for accommodating the wafer 200. The heating components include a first heating component 300 and a second heating component 400, both located outside the chamber 130. The first heating component 300 is located above the upper dome 110, and the second heating component 400 is located below the lower dome 120. The first heating component 300 and the second heating component 400 provide heat energy to the chamber 130 through the upper dome 110 and lower dome 120 respectively via thermal radiation.

[0023] This invention improves the in-situ deposition-etching-deposition process in the epitaxial device 100. When filling semiconductor devices with high aspect ratio vias, the deposited material after the first deposition may cause premature sealing at the via opening. Therefore, an in-situ etching process is required to open the seal. The in-situ etching is chemical etching. After the in-situ etching is completed, the next in-situ deposition is performed, and this cycle is repeated until the via is completely filled. The in-situ etching process described in this application uses a non-plasma process. In the first deposition process, since the deposition gas completes the deposition reaction under heating conditions, while radiating and heating the wafer 200 in the chamber 130, the deposition gas also forms a film on the inner surfaces of the upper dome 110 and the lower dome 120 (i.e., the inner wall of the chamber 130). This film will seriously affect the heating efficiency of the heating components in heating the chamber 130 and the light transmission uniformity of the upper dome 110 and the lower dome 120. After the first deposition process is completed, wafer 200 is not allowed to exit chamber 130 and directly undergoes the second in-situ etching process. At this time, the film layers deposited on the inner surfaces of the upper dome 110 and lower dome 120 are still present, resulting in uneven light transmission in the upper dome 110 and lower dome 120. When the first heating component 300 and the second heating component 400 radiate heat into chamber 130 through the unevenly transmitted upper dome 110 and lower dome 120, respectively, it causes a significant temperature change within chamber 130. Since the etching gas in the in-situ etching process is greatly affected by temperature, the etching rate is highly sensitive to temperature. Significant temperature changes within chamber 130 lead to extremely unstable etching rates, reducing etching accuracy and affecting product quality and process stability.

[0024] To improve the stability of the etching rate in in-situ etching processes, this invention innovatively adds an appropriate amount of silicon source gas to the etching gas. Within the etching temperature range of 600℃ to 1000℃, by controlling the flow rate ratio of silicon source gas to etching gas to be (0.05~0.85):1, the presence of silicon source gas can suppress significant changes in the etching rate due to large temperature variations, thereby effectively reducing the temperature sensitivity of the etching rate and significantly improving the stability of the etching rate. This is described in detail below.

[0025] This invention provides a method for in-situ etching of semiconductor devices. The method includes: a primary deposition, followed by in-situ etching after the primary deposition. The in-situ etching step includes: an etching temperature of 600℃~1000℃, introducing etching gas and silicon source gas into a cavity 130 to etch a wafer 200, controlling the flow rate ratio of silicon source gas to etching gas to be (0.05~0.85):1, and performing a secondary in-situ deposition after the in-situ etching, and repeating this cycle.

[0026] In some embodiments, the pressure within chamber 130 is controlled at 30 torr to 200 torr. The silicon source gas is at least one of dichlorosilane and silane, i.e., it can be dichlorosilane, silane, or a mixture of dichlorosilane and silane, and the flow rate of the silicon source gas is 0.05 slm to 2.5 slm. The etching gas is at least one of HCl and Cl2, i.e., it can be HCl, Cl2, or a mixture of HCl and Cl2, and the flow rate of the etching gas is 1 slm to 3 slm. Hydrogen is also introduced as a carrier gas simultaneously with the silicon source gas and the etching gas, and the flow rate of the hydrogen is 10 slm to 30 slm. Since the etching rate of the etching gas is positively correlated with temperature, by mixing the etching gas with the silicon source gas and controlling the flow rate of the silicon source gas to be less than that of the etching gas, etching becomes dominant. At the same time, the presence of the silicon source gas can suppress the significant change in the etching rate of the etching gas due to large temperature changes. When the etching temperature (the actual temperature inside the chamber 130) fluctuates within ±10℃, the rate of change of the etching rate is less than 5%, and the etching rate has good stability to resist temperature fluctuations.

[0027] In this embodiment, when the etching gas is HCl, the etching temperature is 800℃~1000℃; when the etching gas is Cl2, the etching temperature is 600℃~1000℃. Because the activation energy of Cl2 is lower than that of HCl, the etching temperature required for Cl2 is lower than that required for HCl.

[0028] In some embodiments, the flow rate ratio of silicon source gas to etching gas is (0.2~0.5):1. Within this flow rate ratio range, the etching rate is high and maintains good stability. As an example, this invention studied the etching rate versus temperature curves when dichlorosilane is used as the silicon source gas and HCl is used as the etching gas, with different flow rate ratios of dichlorosilane and HCl. The results are as follows: Figure 2 As shown. From Figure 2 As can be seen, when the flow ratio of dichlorosilane to HCl is ≤0.05:1, the etching rate increases with increasing temperature. When the flow ratio of dichlorosilane to HCl is (0.2~0.5):1 (specifically 0.24, 0.39, and 0.42), the etching rate first increases and then stabilizes with increasing temperature. Furthermore, the smaller the flow ratio of dichlorosilane to HCl, i.e., the less dichlorosilane is introduced, the less impact it has on HCl etching, and the higher the etching rate; conversely, the larger the flow ratio of dichlorosilane to HCl, i.e., the more dichlorosilane is introduced, the greater the impact on HCl etching, and the lower the etching rate. When the flow ratio of dichlorosilane to HCl is 0.84 (close to 0.85), i.e., the dichlorosilane flow rate is relatively large, the etching rate first increases and then stabilizes with increasing temperature, but the etching rate is very low, severely affecting the etching process. Therefore, in order to maintain a stable etching rate, the present invention controls the flow rate ratio of silicon source gas to etching gas to be (0.05~0.85):1. Furthermore, in order to maintain a stable and high etching rate, controlling the flow rate ratio of silicon source gas to etching gas to be (0.2~0.5):1 is even more effective.

[0029] Understandably, as the temperature gradually increases, the etching rate first rises and then tends to stabilize, indicating that the etching rate reaches a peak and then remains essentially constant. The temperature corresponding to this peak etching rate is the plateau temperature. Near the plateau temperature, the etching rate has extremely low sensitivity to temperature and a small rate of change, maintaining good stability. Taking HCl as the etching gas and dichlorosilane as the silicon source gas as an example... Figure 3 The changes in platform temperature are shown when dichlorosilane and HCl are used in different flow rates. From Figure 3As can be seen, when the flow ratio of dichlorosilane to HCl is 0.22, the plateau temperature is 980℃; when the flow ratio is 0.4, the plateau temperature is 955℃; when the flow ratio is 0.41, the plateau temperature is 945℃; and when the flow ratio is 0.82, the plateau temperature is 920℃. The plateau temperature decreases as the flow ratio of dichlorosilane to HCl increases. This indicates that when the flow ratio of dichlorosilane to HCl is relatively low, a relatively high etching temperature can be set in the in-situ etching process to maintain a stable etching rate; conversely, when the flow ratio is relatively high, a relatively low etching temperature can be set in the in-situ etching process to maintain a stable etching rate.

[0030] The process method of the present invention will be described in detail below with reference to embodiments. Taking HCl as the etching gas and dichlorosilane as the silicon source gas as an example.

[0031] Example 1 In the in-situ etching step: the etching temperature was 963℃, the process pressure was 30 torr, and HCl with a flow rate of 1slm~3slm, dichlorosilane with a flow rate of 0.05slm~2.5slm (the flow rate ratio of dichlorosilane to HCl was 0.24), and hydrogen with a flow rate of 10slm were introduced into the chamber to etch the wafer in the chamber. The process results were as follows: when the etching temperature was 963℃, the etching rate was 301nm / min; when the etching temperature was 953℃, the etching rate was 287nm / min; and when the etching temperature was 980℃, the etching rate was 284nm / min.

[0032] Example 2 In the in-situ etching step: the etching temperature was 953℃, the process pressure was 30 torr, and HCl with a flow rate of 1slm~3slm, dichlorosilane with a flow rate of 0.05slm~2.5slm (the flow rate ratio of dichlorosilane to HCl was 0.39), and hydrogen with a flow rate of 10slm were introduced into the chamber to etch the wafer in the chamber. The process results were as follows: when the etching temperature was 953℃, the etching rate was 219nm / min; when the etching temperature was 943℃, the etching rate was 216nm / min; and when the etching temperature was 963℃, the etching rate was 221nm / min.

[0033] Example 3 In the in-situ etching step: the etching temperature was 953℃, the process pressure was 30 torr, and HCl with a flow rate of 1slm~3slm, dichlorosilane with a flow rate of 0.05slm~2.5slm (the flow rate ratio of dichlorosilane to HCl was 0.42), and hydrogen with a flow rate of 10slm were introduced into the chamber to etch the wafer in the chamber. The process results were as follows: when the etching temperature was 953℃, the etching rate was 161nm / min; when the etching temperature was 943℃, the etching rate was 172nm / min; and when the etching temperature was 963℃, the etching rate was 142nm / min.

[0034] Example 4 In the in-situ etching step: the etching temperature was 953℃, the process pressure was 30 torr, and HCl with a flow rate of 1slm~3slm, dichlorosilane with a flow rate of 0.05slm~2.5slm (the flow rate ratio of dichlorosilane to HCl was 0.84), and hydrogen with a flow rate of 10slm were introduced into the chamber to etch the wafer in the chamber. The process results were: when the etching temperature was 953℃, the etching rate was 19nm / min; when the etching temperature was 943℃, the etching rate was 36nm / min.

[0035] The etching rate variation rate was calculated based on the etching rates tested in Examples 1-4, and the results are shown in Table 1. Table 1 shows that in Examples 1 and 2 (with flow ratios of dichlorosilane to HCl of 0.24 and 0.39, respectively), the etching rate was relatively high, and the variation rate was less than 5% when the etching temperature fluctuation range was within ±10℃. In Example 3 (with a flow ratio of dichlorosilane to HCl of 0.42), the etching rate was relatively low, and the variation rate was approximately 10% when the etching temperature fluctuation range was within ±10℃. In Example 4 (with a flow ratio of dichlorosilane to HCl of 0.84), the etching rate was extremely low, and the variation rate was much greater than 10% when the etching temperature fluctuation range was within ±10℃. These data indicate that when the flow ratio of dichlorosilane to HCl is (0.2~0.5):1, the etching rate is relatively high and the variation rate is small, maintaining good stability.

[0036] Table 1 Comparison of etching rate change data in Examples 1-4 In summary, this invention innovatively incorporates an appropriate amount of silicon source gas into the etching gas. Within the etching temperature range of 600℃ to 1000℃, by controlling the flow rate ratio of silicon source gas to etching gas to be (0.05~0.85):1, the presence of silicon source gas can suppress significant changes in the etching rate due to large temperature variations, thereby effectively reducing the temperature sensitivity of the etching rate and significantly improving the stability of the etching rate.

[0037] Those skilled in the art will understand that, in the above embodiments, HCl is used as the etching gas, dichlorosilane is used as the silicon source gas, the process temperature is between 800℃ and 1000℃, and the process pressure is 30 torr. Without departing from the principle of this invention, the etching gas can be Cl2 or a mixture of Cl2 and HCl, the silane gas can be silane or a mixture of dichlorosilane and silane, the process temperature can be adjusted between 600℃ and 1000℃, the process pressure can be adjusted between 30 torr and 200 torr, and the carrier gas flow rate can be adjusted between 10 slm and 30 slm.

[0038] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0039] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0040] Although the present invention has been described in detail through the preferred embodiments above, it should be understood that the above description should not be considered as a limitation of the present invention. Various modifications and substitutions to the present invention will be apparent to those skilled in the art after reading the above description. Therefore, the scope of protection of the present invention should be defined by the appended claims.

Claims

1. A method for in-situ etching of semiconductor devices, characterized in that, The method includes: First deposition; In-situ etching, the in-situ etching steps include: etching temperature of 600℃~1000℃, introducing etching gas and silicon source gas into the cavity to etch the wafer in the cavity, the flow rate ratio of silicon source gas to etching gas is (0.05~0.85):1, the etching temperature fluctuation range is within ±10℃, and the etching rate change rate is less than 5%.

2. The method as described in claim 1, characterized in that, The flow rate ratio of the silicon source gas to the etching gas is (0.2~0.5):

1.

3. The method as described in claim 1, characterized in that, The flow rate of the etching gas is 1 slm to 3 slm, and the flow rate of the silicon source gas is 0.05 slm to 2.5 slm.

4. The method as described in claim 1, characterized in that, The silicon source gas is at least one of dichlorosilane and silane gas.

5. The method as described in claim 1, characterized in that, The etching gas is at least one of HCl and Cl2.

6. The method as described in claim 5, characterized in that, When the etching gas is HCl, the etching temperature is 800℃~1000℃; when the etching gas is Cl2, the etching temperature is 600℃~1000℃.

7. The method as described in claim 1, characterized in that, The in-situ etching step further includes: introducing hydrogen gas as a carrier gas, with a hydrogen flow rate of 10 slm to 30 slm.

8. The method as described in claim 1, characterized in that, The process pressure inside the chamber is 30 torr to 200 torr.

9. The method as described in claim 1, characterized in that, After the in-situ etching step is completed, a second in-situ deposition is performed.

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