Method for realizing steep and high-uniform dielectric etching based on high-purity octafluorocyclobutane and application thereof

Abstract

The present application relates to the technical field of semiconductor integrated circuits, and particularly relates to a method for realizing steep and high-uniformity dielectric etching based on high-purity octafluorocyclobutane and application thereof. The method for dielectric etching of the present application prepares a patterned mask on the surface of a dielectric layer material to be etched through an electron beam lithography process; etches the dielectric layer material covered with the patterned mask using plasma formed from an etching gas to realize a vertical etching groove with a width of 20 nm to 150 nm; and the etching gas comprises high-purity octafluorocyclobutane gas with a purity of more than 99.99999%. The method for dielectric etching of the present application takes advantage of the high purity of high-purity octafluorocyclobutane gas, reduces the damage of etching gases such as oxygen and high-fluorocarbon ratio gas to the sidewall etching protection layer, thereby improving the steepness of the sidewall of nanoscale silicon oxide via etching, and simultaneously making the etching process relatively stable under different etching sizes.

Description

Technical Field

[0001] This invention relates to the field of semiconductor integrated circuit technology, and in particular to a method for achieving steep and highly uniform dielectric etching based on high-purity octafluorocyclobutane and its application. Background Technology

[0002] With the rapid development of integrated circuit technology, chip integration is becoming increasingly sophisticated, placing higher demands on the performance and precision of transistor devices. Dielectric etching is one of the key processes in integrated circuit manufacturing. It utilizes physical, chemical, or a combination of both methods to pattern or remove dielectric materials. Commonly used dielectric etching methods include dry etching and wet etching. Compared to wet etching, dry etching offers advantages such as high etching precision, anisotropy, and good etching uniformity, meeting the needs of advanced process node device fabrication. However, with the continuous miniaturization of semiconductor feature sizes, higher requirements are placed on the tilt angle of the dielectric etching sidewalls. A near-vertical etching sidewall is crucial for achieving high-density via etching. Furthermore, as chip manufacturing technology has advanced to the nanometer scale, impurities in the etching gas directly affect the uniformity and stability of the high-density etching process, thereby impacting chip yield and reliability. This necessitates even higher purity requirements for the etching gas. Summary of the Invention

[0003] This invention provides a method and application for achieving steep and highly uniform dielectric etching based on high-purity octafluorocyclobutane, in order to solve the problems of non-sharp etching sidewalls and poor etching uniformity in traditional dielectric etching methods, especially the problem of achieving steep etching sidewalls at the nanoscale.

[0004] According to a first aspect of the present invention, the present invention provides a method for achieving steep and highly uniform dielectric etching based on high-purity octafluorocyclobutane, comprising the following steps: Patterned masks are prepared on the surface of the dielectric layer material to be etched using electron beam lithography. A dielectric layer material covered with a patterned mask is etched using plasma formed by an etching gas to achieve a vertical etching trench width of 20 nm to 150 nm; wherein the etching gas includes high-purity octafluorocyclobutane gas with a purity of 99.99999% or higher.

[0005] This invention provides a dielectric etching method based on high-purity octafluorocyclobutane, which can achieve steep etching sidewalls and highly uniform etching results. By using high-purity octafluorocyclobutane gas (purity above 99.99999%), the influence of impurities in the etching gas on the etching process can be effectively reduced, thereby improving the precision and stability of nanoscale etching, enhancing the steepness of the etching sidewalls and the uniformity of etching, and making it suitable for the high-precision etching requirements of advanced process technologies.

[0006] Furthermore, the electron beam lithography process can better control the exposure accuracy by precisely controlling the spin coating parameters, exposure current, and development parameters. At the same time, it can make reasonable use of the overexposure characteristics of the electron beam lithography process to achieve the definition of the etching trench width at the sub-hundred nanometer scale.

[0007] Furthermore, the width of the etching trench is 30 nm to 105 nm. Experiments have shown that the method of the present invention can achieve an etching trench width definition below 105 nm.

[0008] Furthermore, the flow rate of the high-purity octafluorocyclobutane gas is 10-30 sccm. By precisely controlling the flow rate of the octafluorocyclobutane gas, the etching rate and etching uniformity can be better adjusted, ensuring the stability and repeatability of the etching process, thereby achieving more precise etching control and further optimizing the etching effect.

[0009] Furthermore, the flow rate of the high-purity octafluorocyclobutane gas is 15-25 sccm. In some specific embodiments, the flow rate of the high-purity octafluorocyclobutane gas is 20 sccm.

[0010] Furthermore, the etching gas also includes an inert gas; preferably, the inert gas is Ar or He. Introducing an inert gas (such as Ar or He) into the etching gas can improve the plasma characteristics during the etching process, enhance the anisotropy of the etching, and further strengthen the steepness of the etched sidewalls. Simultaneously, the addition of the inert gas helps stabilize the plasma, reduce plasma fluctuations, thereby improving the uniformity and stability of the etching process and reducing damage during etching.

[0011] Furthermore, the flow rate of the inert gas is 70-90 sccm. By precisely controlling the flow rate of the inert gas, the density and energy distribution of the plasma can be better regulated, optimizing the balance of physical and chemical reactions during the etching process. This helps to achieve steeper etching sidewalls while maintaining the uniformity and stability of the etching rate, further improving the etching quality.

[0012] Furthermore, the flow rate of the inert gas is 75-85 sccm. In some specific embodiments, the flow rate of the inert gas is 80 sccm.

[0013] Furthermore, the dielectric layer material includes silicon oxide or silicon nitride. Silicon oxide and silicon nitride are commonly used dielectric materials in semiconductor manufacturing. This method can achieve high-quality etching of these materials, meeting the dielectric etching requirements of different semiconductor device manufacturing processes, and improving the versatility and practicality of the etching method. In some specific embodiments, the dielectric layer material is silicon dioxide.

[0014] Furthermore, the antenna RF power is set to 250~750 W and the bias RF power to 100~300 W during the etching process; the etching process chamber pressure is 0.3~0.7 Pa and the gas delivery pressure is 500~800 Pa. By setting the antenna RF power to 250~750 W and the bias RF power to 100~300 W during the etching process, the excitation and maintenance conditions of the plasma can be precisely controlled, thereby achieving effective control over the etching rate, etching uniformity, and etching sidewall morphology. Simultaneously, specifying the etching pressure helps to further optimize the etching process, ensuring the stability and consistency of the etching effect and meeting the etching requirements under different process conditions. In some specific implementations, the selected etching process chamber pressure is 0.4 Pa and the gas delivery pressure is 600 Pa.

[0015] Furthermore, the sidewall tilt angle of the etched dielectric layer material is >85°. The sidewall tilt angle directly reflects the steepness of the etched sidewalls and is a crucial parameter for measuring etching quality. Achieving such a steep sidewall tilt angle effectively improves the integration and performance of semiconductor devices, reduces mutual interference between devices, and provides better conditions for subsequent process steps (such as metal interconnects), thereby enhancing the overall semiconductor manufacturing process.

[0016] Preferably, the sidewall tilt angle of the etched dielectric layer material is >85° and <90°. In some specific embodiments, the sidewall tilt angle of the etched dielectric layer material is 87.5°-88.7°.

[0017] Furthermore, the fabrication of a patterned mask on the surface of the dielectric layer material to be etched involves defining the mask pattern using electron beam photoresist combined with electron beam lithography, and then fabricating the hard mask using electron beam evaporation. Preferably, the hard mask is a metal hard mask or a diamond-like carbon (DLC) film. This method enables high-precision pattern transfer, ensuring the accuracy and quality of the mask pattern. The use of a hard mask (such as a metal hard mask or a DLC film) can improve the selectivity and stability during the etching process, protect non-etched areas from etching damage, thereby achieving more precise etching patterns and further improving the accuracy and reliability of the etching process.

[0018] In some specific embodiments, the hard mask includes an adhesive layer and a barrier layer, wherein the metal of the adhesive layer is Cr and the metal of the barrier layer is Pd.

[0019] Further, the electron beam photoresist is PMMA photoresist, Zep photoresist, or HSQ photoresist; in some specific embodiments, the electron beam photoresist is a polymethyl methacrylate photoresist with a molecular weight of 950K.

[0020] The electron beam lithography process uses a rotation speed of 4000~6000 rpm, a development time of 1.5~2.5 minutes, an exposure current of 1~10 nA, and an exposure dose of 5~8 mJ / cm². 2 To achieve the definition of metal mask pattern spacing from 20 nm to 150 nm.

[0021] In some specific embodiments, the process of fabricating a patterned mask on the surface of the dielectric layer material to be etched includes the following steps: Hard mask pattern definition: Electron beam photoresist, made of polymethyl methacrylate, is spin-coated onto the surface of the dielectric layer material. The thickness of the electron beam photoresist is 50-150 nm. The hard mask pattern is defined using electron beam lithography, with a spacing of 20 nm to 150 nm and an exposure dose of 5-8 mJ / cm². 2 After exposure, the dielectric layer material is developed using a developer to obtain a hard mask pattern. The developer is prepared by mixing MIBK and IPA in a volume ratio of 1:(2-4), with a rotation speed of 4000~6000 rpm, a development time of 1.5~3.5 min, and an exposure process current of 1~10 nA. Metal hard mask deposition: The hard mask metal is deposited using an electron beam lithography device; the hard mask metal is stripped using acetone to obtain a hard mask metal array; preferably, the metal of the deposited adhesion layer is Cr, the deposition thickness is 3-8 nm, and the deposition rate is 0.5-1.5 Å / s; the metal of the deposited etch barrier layer is Pd, the deposition thickness is 25-45 nm, and the deposition rate is 0.5-1.5 Å / s.

[0022] The aforementioned scheme provides a complete process flow capable of achieving high-quality, high-precision etching by specifically defining parameters such as the type of hard mask (metallic hard mask), the composition of the etching gas (high-purity octafluorocyclobutane gas and inert gas Ar), the dielectric layer material (silicon dioxide), gas flow rate, RF power, etching pressure, and etching rate. This comprehensively optimized process scheme ensures stable and reliable etching results in actual production, is suitable for large-scale semiconductor manufacturing processes, and improves production efficiency and product quality.

[0023] According to a second aspect of the present invention, the present invention also provides the application of the above-described method for achieving steep and highly uniform dielectric etching based on high-purity octafluorocyclobutane in the manufacture of semiconductors.

[0024] Applying the etching method based on high-purity octafluorocyclobutane to the semiconductor manufacturing field can meet the high precision and stability requirements of dielectric etching in semiconductor manufacturing processes, helping to improve the performance and reliability of semiconductor devices and promoting the development of semiconductor manufacturing technology. By applying this method in semiconductor manufacturing, smaller, more integrated semiconductor devices can be manufactured, providing technical support for the advancement of the semiconductor industry.

[0025] This invention provides a dielectric etching method based on high-purity octafluorocyclobutane. High-purity octafluorocyclobutane gas is used as both the etching gas and the protective gas in the dielectric etching process, with an inert gas assisting in the removal of etching residues. The high purity of octafluorocyclobutane gas reduces the damage to the sidewall etching protective layer caused by etching gases such as oxygen and high fluorocarbon ratio gases, thereby improving the sidewall steepness of nanoscale silicon oxide via etching and making the etching process more stable. This etching method is expected to be applied to via or contact hole etching processes in advanced manufacturing processes, improving device uniformity and yield. Attached Figure Description

[0026] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0027] Figure 1 This is a schematic diagram of the hard mask etching structure of the sample to be etched used in Embodiment 1 of the present invention.

[0028] Figure 2 This is a cross-sectional schematic diagram of the etching effect of a medium etching method based on high-purity octafluorocyclobutane to achieve steep and highly uniform etching, as proposed in Embodiment 1 of the present invention.

[0029] Figure 3 This is a statistical chart showing the etching depth of silicon dioxide medium under different etching trench widths in Embodiment 1 and Comparative Example 1 of the present invention.

[0030] Figure 4 This is a SEM characterization result of the sidewall of the etched sample, based on a high-purity octafluorocyclobutane-based method for achieving steep and highly uniform dielectric etching, as proposed in Example 1 of this invention.

[0031] Figure 5 This is a SEM characterization result of the sidewall of the etched sample of Comparative Example 1 of the present invention, which was etched using conventional octafluorocyclobutane gas.

[0032] Reference numerals: 101: silicon substrate; 102: silicon dioxide dielectric layer; 103: adhesion layer; 104: etching barrier layer. Detailed Implementation

[0033] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0034] Example 1 A method for achieving steep and highly uniform dielectric etching based on high-purity octafluorocyclobutane includes the following steps: (1) Hard mask pattern definition: Polymethyl methacrylate electron beam photoresist is spin-coated onto the substrate surface. The thickness of the spin-coated photoresist is 60±10nm. The hard mask pattern is defined by electron beam lithography. The hard mask pattern spacing is defined as 20~150nm, and the exposure dose is 6±0.5mJ / cm. 2 After exposure, the sample was developed using a developer solution with a MIBK:IPA ratio of 1:3 for 2 ± 0.5 min, at a rotation speed of 5000 rpm, and with an exposure process current of 6.2 nA. After fixing with IPA, a hard mask pattern was obtained.

[0035] (2) Metal hard mask deposition: The hard mask metal was deposited using an electron beam lithography device. The metal of the deposited adhesion layer was Cr, the deposition thickness was 5 nm, and the deposition rate was 1 Å / s. The metal of the deposited etch barrier layer was Pd, the deposition thickness was 35 nm, and the deposition rate was 1 Å / s. The metal was stripped using acetone to obtain the hard mask metal array.

[0036] (3) Etching: Argon gas with flow rates of 80 sccm and 20 sccm and high-purity octafluorocyclobutane gas (purity of 99.99999%) were used as etching gases. After plasma was formed based on a coupled plasma device, dry etching was performed on the silicon oxide substrate covered with a patterned hard mask. The etching times were 10 s, 20 s, 30 s, and 40 s. During the etching process, the antenna RF power was set to 500 W, the bias RF power was set to 200 W, the etching process chamber pressure was 0.4 Pa, and the gas delivery pressure was 600 Pa.

[0037] In the above process, a schematic diagram of the sample after (2) hard mask metal deposition is shown below. Figure 1As shown, the substrate includes a silicon substrate 101 and a silicon dioxide dielectric layer 102. An adhesion layer 103 and an etch barrier layer 104 are deposited on the silicon dioxide dielectric layer 102. A schematic diagram of the sample after completing the etching process (3) is shown below. Figure 2 As shown.

[0038] Comparative Example 1 This comparative example provides a dielectric etching method, which differs from Example 1 only in that the octafluorocyclobutane gas used in this comparative example has a purity of 99.999%.

[0039] Test case The etching depth and etching sidewall tilt angle at different etching times in Example 1 and Comparative Example 1 were statistically analyzed, and the specific method is as follows: The sample was cleaved along the direction perpendicular to the hard mold, and then platinum was sputtered using a gold sputtering device with a platinum thickness of 3.5±0.5nm. The sample was then attached to the electron beam developing microscope sample stage to observe the sidewall condition and to record the etching depth and sidewall etching condition.

[0040] See etching depth statistics Figure 3 , Figure 3 In the diagram, 5N represents a purity of 99.999% for octafluorocyclobutane gas, and 7N represents a purity of 99.99999% for octafluorocyclobutane gas.

[0041] The etching sidewall situation in Example 1 is as follows Figure 4 As shown, the etching sidewalls of Comparative Example 1 are as follows: Figure 5 As shown.

[0042] in conclusion: like Figure 3 As shown, in Example 1 (7N), the etching sidewall angle is closer to 90° within the 30 nm to 105 nm etching trench width; in Comparative Example 1 (5N), the etching sidewall tilt angle ranges from 85° to 99° within the 30 nm to 105 nm etching trench width. Compared to Comparative Example 1, the etching sidewall tilt angle in Example 1 fluctuates less with the etching trench width, resulting in better etching uniformity. In contrast, Comparative Example 1 shows significant fluctuations, with a clear correlation between the etching sidewall tilt angle and the etching trench width. This indicates that using high-purity octafluorocyclobutane etching achieves a more stable etching process, which is beneficial for improving etching uniformity in large-scale integrated circuit etching processes. Furthermore, the resulting trench sidewalls are steeper.

[0043] like Figure 4 and Figure 5As shown, the sidewall tilt angle α1 after etching in Example 1 is 87.9°, and the sidewall tilt angle α2 after etching in Comparative Example 1 is 85.2°. This indicates that Example 1 can achieve a steeper test tilt angle compared to Comparative Example 1, demonstrating that the etching method produces a better through-hole perpendicularity. Table 1 shows the statistical results of the etching sidewall tilt angles obtained from repeated experiments with different etching trench widths using the etching methods of Example 1 and Comparative Example 1.

[0044] Table 1 The experimental data in Table 1 show that when using high-purity (99.99999%) octafluorocyclobutane gas for etching, the sidewall tilt angle remains at a high level of 87.4°~88.7° for different etching trench widths, with minimal fluctuations, demonstrating good etching uniformity and stability. In contrast, when using octafluorocyclobutane gas with slightly lower purity (99.999%), the sidewall tilt angle ranges from 85.2° to 86.7°, with a lower average value and greater fluctuations, indicating poorer etching uniformity. This suggests that high-purity octafluorocyclobutane gas can significantly improve the steepness of the etching sidewalls and the stability of etching, making it more suitable for high-precision semiconductor etching processes.

[0045] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for steep and high-uniformity dielectric etching based on high-purity octafluorocyclobutane, characterized in that, Includes the following steps: Patterned masks are prepared on the surface of the dielectric layer material to be etched using electron beam lithography. A patterned mask-covered dielectric layer material is etched using plasma formed by an etching gas to achieve vertical etching trenches with a width of 20 nm to 150 nm; wherein the etching gas includes high-purity octafluorocyclobutane gas with a purity of 99.99999% or higher.

2. The method according to claim 1, wherein the steep and high-uniformity dielectric etching is achieved using high-purity octafluorocyclobutane. The width of the etched trench is 30 nm to 105 nm.

3. The method for achieving steep and highly uniform dielectric etching based on high-purity octafluorocyclobutane according to claim 1 or 2, characterized in that, The flow rate of the high-purity octafluorocyclobutane gas is 10-30 sccm.

4. The method for achieving steep and highly uniform dielectric etching based on high-purity octafluorocyclobutane according to any one of claims 1-3, characterized in that, The etching gas also includes an inert gas; preferably, the inert gas is Ar or He, and the gas flow rate is 70-90 sccm.

5. The method for achieving steep and highly uniform dielectric etching based on high-purity octafluorocyclobutane according to any one of claims 1-4, characterized in that, The dielectric layer material includes silicon oxide or silicon nitride.

6. The method for achieving steep and highly uniform dielectric etching based on high-purity octafluorocyclobutane according to any one of claims 1-5, characterized in that, The antenna RF power set during the etching process is 250~750 W, the bias RF power is 100~300 W, the etching process chamber pressure is 0.3~0.7 Pa, and the gas delivery pressure is 500~800 Pa.

7. The method for achieving steep and highly uniform dielectric etching based on high-purity octafluorocyclobutane according to any one of claims 1-6, characterized in that, The sidewall tilt angle of the etched dielectric layer material is >85°, preferably >85° and <90°.

8. The method for achieving steep and highly uniform dielectric etching based on high-purity octafluorocyclobutane according to any one of claims 1-7, characterized in that, The preparation of a patterned mask on the surface of the dielectric layer material to be etched involves defining the mask pattern using electron beam photoresist combined with electron beam lithography, and then using electron beam evaporation to prepare the hard mask; preferably, the hard mask is a metal hard mask or a diamond-like thin film.

9. The method for achieving steep and highly uniform dielectric etching based on high-purity octafluorocyclobutane according to claim 8, characterized in that, The electron beam photoresist is PMMA photoresist, Zep photoresist, or HSQ photoresist. The rotation speed of the electron beam lithography process is 4000-6000 revolutions per minute, the developing time is 1.5-2.5 minutes, the exposure process current is 1-10 nA, and the exposure dose is 5-8 mJ / cm 2 to achieve a metal mask pattern pitch definition of 20-150 nm.

10. The application of the dielectric etching method based on high-purity octafluorocyclobutane to achieve steep and highly uniform etching as described in any one of claims 1-9 in the manufacture of semiconductors.

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