Data processing apparatus and data driven apparatus

Abstract

An embodiment discloses a data processing apparatus, comprising: a first data conversion section that converts image data and control data; and a transmission section that transmits the converted image data and control data, the first data conversion section including: a first packetizer that converts the image data into first data packets; a second packetizer that converts the control data into second data packets; a first encoder that encodes the first data packets in a first rule; and a second encoder that encodes the second data packets in a second rule different from the first rule.

Description

Technical Field

[0001] This embodiment relates to a technology for driving a display device. Background Technology

[0002] The display panel consists of a plurality of pixels arranged in a matrix. Each pixel can have a hue such as R (red), G (green), and B (blue), and displays the image on the display panel while emitting light at a grayscale corresponding to the image data.

[0003] Image data is sent from a data processing device, such as a timing controller, to a data driving device, such as a source driver. The image data is sent as digital values, and the data driving device converts the image data into analog voltages to drive the individual pixels.

[0004] Since image data indicates the grayscale value of each pixel individually or independently, the amount of image data increases as the number of pixels configured on the display panel increases. Furthermore, as the frame rate increases, the amount of image data that must be transmitted per unit time also increases.

[0005] With the recent increase in the resolution of display panels, the number of pixels and the frame rate on display panels are both increasing. In order to handle the increased amount of image data due to the resolution, data communication in display devices is becoming faster. Summary of the Invention

[0006] The problem the invention aims to solve

[0007] One embodiment may provide a data processing apparatus and a data driving apparatus that encode and decode setting data, control data, and image data in different ways.

[0008] One embodiment may provide a data processing apparatus and a data driving apparatus for encoding image data to keep the maximum run length constant.

[0009] One embodiment may provide a data processing apparatus and a data driving apparatus for encoding to ensure the quality of transmission signals for control data.

[0010] The problems of this invention are not limited to those mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the following description.

[0011] means for solving problems

[0012] A data processing apparatus according to an embodiment of the present invention includes: a first data conversion unit for converting image data and control data; and a transmission unit for transmitting the converted image data and control data. The first data conversion unit includes: a first packetizer for converting the image data into a first data packet; a second packetizer for converting the control data into a second data packet; a first encoder for encoding the first data packet according to a first rule; and a second encoder for encoding the second data packet according to a second rule different from the first rule.

[0013] The number of bits in the second data packet can be less than the number of bits in the first data packet.

[0014] The number of bits in the encoded second data packet can be the same as the number of bits in the encoded first data packet.

[0015] The control data may include first control data and second control data. The first control data may include control values ​​applied in row units or pixel units of the display panel, and the second control data may include control values ​​applied in frame units.

[0016] The data driving device can divide each frame time into an effective interval and a blanking interval, and send the image data and the first control data in the effective interval, and send the second control data in the blanking interval.

[0017] The data processing apparatus may include a second data conversion unit, which includes: a third packetizer for converting set data into a third data packet; and a third encoder for encoding the third data packet using a third rule different from the first rule and the second rule.

[0018] The transmission circuit can transmit the converted image data, the control data, and the setting data in a predetermined order.

[0019] The first encoder may include: a data comparison unit that compares the most significant bit (MSB) of an adjacent first data packet (1-1) with the least significant bit (LSB) of a first data packet (1-2); a code conversion unit that, when the most significant bit of the first data packet and the least significant bit of the first data packet (1-1) have the same value, inverts the least significant bit of the first data packet (1-2); and a bit generation unit that generates an indicator packet that stores conversion information of the least significant bit of the first data packet (1-2).

[0020] It may also include a data group generation unit that inserts the instruction packet into a plurality of the first data packets to generate a plurality of data groups.

[0021] Each of the plurality of data groups has the same number of packets, and the number of bits in the indicator packet may be the same as the number of data packets in the data group.

[0022] The second encoder can map each unit bit constituting the control data to a plurality of redundant bits having the same value as the unit bit and a transition bit having a different value than the unit bit.

[0023] A data driving device according to an embodiment of the present invention includes: a receiving circuit for receiving a first data packet to a third data packet; a third data conversion unit for converting the first data packet and the second data packet; and a fourth data conversion unit for converting the third data packet. The third data conversion unit includes: a first decoder for decoding the first data packet according to a first rule; a second decoder for decoding the second data packet according to a second rule different from the first rule; a first unpacker for converting the first data packet into image data; and a second unpacker for converting the second data packet into control data. The fourth data conversion unit includes: a third decoder for decoding the third data packet according to a third rule different from the first rule and the second rule; and a third unpacker for converting the third data packet into set data.

[0024] The effects of the invention

[0025] According to the embodiments, it is possible to support control data transmission based on video timing such as horizontal lines or vertical blanking zones.

[0026] According to the embodiments, two or more data encoding techniques employing clock embedding can be utilized. Control data ensures the quality of transmitted signals and has the advantage of eliminating the need for data checkers such as CRC and checksums. Image data ensures a regular run-length and has the advantage of easy clock embedding.

[0027] According to an embodiment, EMI can be reduced by scrambling image data.

[0028] The effects of the present invention are not limited to those mentioned above, and other effects not mentioned will be clearly understood by those skilled in the art from the description in the claims. Attached Figure Description

[0029] Figure 1 This is a structural diagram of a display device according to an embodiment of the present invention.

[0030] Figure 2 This diagram illustrates the main communication and auxiliary communication between a data processing device and a data driving device according to an embodiment of the present invention.

[0031] Figure 3This is a structural diagram of a data processing device according to an embodiment of the present invention.

[0032] Figure 4 This is a structural diagram of a scrambler according to an embodiment of the present invention.

[0033] Figure 5 This is a structural diagram of the first encoder according to an embodiment of the present invention.

[0034] Figure 6 This is a structural diagram of the second encoder according to an embodiment of the present invention.

[0035] Figure 7 This is a structural diagram of a data processing apparatus according to another embodiment of the present invention.

[0036] Figure 8 This is a diagram illustrating a sequence of transmission signals according to an embodiment of the present invention.

[0037] Figure 9 This is a structural diagram of the hidden data and row data according to an embodiment of the present invention.

[0038] Figure 10 This is a diagram illustrating the bits of a plurality of packets according to an embodiment of the present invention.

[0039] Figure 11 This is a structural diagram of a data packet in the first horizontal row according to an embodiment of the present invention.

[0040] Figure 12 This is a diagram illustrating a data packet including virtual data according to an embodiment of the present invention.

[0041] Figure 13 This is a diagram illustrating the image data structure of an embodiment of the present invention.

[0042] Figure 14 This is a flowchart illustrating the image data encoding steps of an embodiment of the present invention.

[0043] Figure 15 This is a diagram illustrating an image data encoding method according to an embodiment of the present invention.

[0044] Figure 16 This is a diagram illustrating the decoding process of an embodiment of the present invention.

[0045] Figure 17 This is a diagram illustrating the process of encoding control data according to an embodiment of the present invention.

[0046] Figure 18 This is a diagram illustrating the process of encoding control data according to another embodiment of the present invention. Detailed Implementation

[0047] The advantages and features of the present invention, as well as the methods of implementing them, will become clear with reference to the accompanying drawings and detailed embodiments described below. The present invention is not limited to the embodiments disclosed below, but will be implemented in various forms that differ from each other. These embodiments are provided only to make the disclosure of the invention more complete and to fully inform those skilled in the art of the scope of the invention. The invention is defined only by the scope of the claims.

[0048] The shapes, sizes, proportions, angles, numbers, etc., disclosed in the accompanying drawings for the purpose of illustrating embodiments of the present invention are illustrative, and therefore the present invention is not limited to the items shown in the drawings. Throughout the specification, the same reference numerals substantially refer to the same constituent elements. Furthermore, in describing the present invention, detailed descriptions of related prior art will be omitted where it is determined that such detailed descriptions might unnecessarily obscure the essence of the invention.

[0049] The following embodiments can be combined or integrated with each other, either partially or entirely, and can be technically linked and driven in various ways. The embodiments can be implemented independently or together in a related manner.

[0050] Hereinafter, various embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0051] Figure 1 This is a structural diagram of a display device according to an embodiment.

[0052] Reference Figure 1 The display device 100 may include a data processing device 110, a data driving device 120, a display panel 130, and a gate driving device 140, etc.

[0053] The data processing device 110 can receive image data from other devices. These other devices, which generate the image data, can be a host computer.

[0054] The data processing device 110 can process image data received from other devices into a format suitable for the data driving device 120, and then send the processed image data to the data driving device 120. The data processing device 110 can perform digital gamma correction processing on the grayscale values ​​of each pixel included in the image data, and can also perform compensation processing to conform to the characteristics of each pixel.

[0055] The data driving device 120 can receive image data from the data processing device 110, generate a data voltage VD based on the grayscale values ​​of the pixels included in the image data, and supply the data voltage VD to the pixel P.

[0056] The display panel 130 may be configured with a plurality of pixels P. Each pixel P can be connected to the data driving device 120 via a data line DL, and can be connected to the gate driving device 140 via a gate line GL.

[0057] The display panel 130 can be a panel of a flat panel display device such as a liquid crystal display (LCD), a field emission display (FED), a plasma display panel (PDP), an organic light-emitting display (OLED), or a non-organic light-emitting display.

[0058] Each pixel P can be equipped with a transistor, whose gate terminal can be connected to the gate line GL, and whose source terminal can be connected to the data line DL. When the gate driving device 140 supplies a scan signal SCN to the gate line GL, the transistor is turned on, and the data line DL is connected to the pixel P. After the data line DL is connected to the pixel P, the data voltage VD supplied by the data driving device 120 is transmitted to the pixel P.

[0059] In order to align the timing of the gate drive device 140 and the data drive device 120, the data processing device 110 can send timing control signals to the gate drive device 140 and the data drive device 120.

[0060] The data processing device 110 can send a gate control signal to the gate driving device 140. The gate control signal may include the timing control signal described above. The gate driving device 140 can generate a scan signal SCN according to the gate control signal and supply the scan signal SCN to the pixel P through the gate line GL.

[0061] At least two communication lines, CLM and CLA, can be configured between the data processing device 110 and the data driving device 120. The data processing device 110 can send a first communication signal MDT through the first communication line CLM and send or receive a second communication signal LCK through the second communication line CLA.

[0062] For ease of explanation, the first communication line CLM can be defined as the main communication line, and the second communication line CLA as the auxiliary communication line. Furthermore, the first communication signal MDT can be defined as the main communication signal, and the second communication signal LCK as the auxiliary communication signal.

[0063] The data processing device 110 can send image data and timing control signals to the data driving device 120 through the main communication signal MDT, and the data driving device 120 can send status information to the data processing device 110 through the auxiliary communication signal LCK.

[0064] Figure 2 This is a diagram illustrating the main communication and auxiliary communication between a data processing apparatus and a data driving apparatus according to an embodiment.

[0065] Reference Figure 2 The data driving device 120 can be composed of a plurality of data driving integrated circuits 120a, 120b, 120c, and 120d.

[0066] The data processing device 110 can communicate with a plurality of data driver integrated circuits 120a, 120b, 120c, and 120d via the main communication line CLM. The data processing device 110 can be connected one-to-one with each of the data driver integrated circuits 120a, 120b, 120c, and 120d. For example, the data processing device 110 can be connected one-to-one with the first data driver integrated circuit 120a and one-to-one with the second data driver integrated circuit 120b.

[0067] Each main communication line (CLM) can consist of m electrically isolated lines (m being a natural number). Furthermore, the m lines can be paired, allowing each pair to perform LVDS (Low Voltage Differential Signaling) communication.

[0068] Such a communication connection structure and the main communication signals transmitted and received between the data processing device 110 and a plurality of data driver integrated circuits 120a, 120b, 120c, 120d (see reference) Figure 1 The MDT is defined as the main communication.

[0069] In addition to sending and receiving information via main communication, the data processing device 110 and the plurality of data driving integrated circuits 120a, 120b, 120c, and 120d can also send and receive information via auxiliary communication.

[0070] Auxiliary communication between a plurality of data driver integrated circuits 120a, 120b, 120c, and 120d can be connected in a cascaded configuration. For example, the first data driver integrated circuit 120a, configured at the beginning of the cascade, can send a first auxiliary communication signal LKa to the second data driver integrated circuit 120b via a first auxiliary communication line CLAa.

[0071] The second data driver integrated circuit 120b can combine the internally generated status signal with the first auxiliary communication signal LKa to generate a second auxiliary communication signal LCKb, and send the second auxiliary communication signal LCKb to the fourth data driver integrated circuit 120c through the second auxiliary communication line CLAb.

[0072] The fourth data driver integrated circuit 120c can combine the internally generated status signal with the second auxiliary communication signal LCKb to generate a fourth auxiliary communication signal LCKc, and send the fourth auxiliary communication signal LCKc to the fourth data driver integrated circuit 120d through the fourth data driver integrated circuit 120c.

[0073] The fourth data driver integrated circuit 120d, configured at the end of the cascade, can combine an internally generated status signal with a fourth auxiliary communication signal LCKc to generate a fourth auxiliary communication signal LCKd, and then send the fourth auxiliary communication signal LCKd to the data processing device 110 via the fourth auxiliary communication line CLAd. Here, the fourth data driver integrated circuit 120d, configured at the end of the cascade, sends auxiliary communication signals to the data processing device 110 via auxiliary communication.

[0074] The data processing device 110 can confirm the status of the data driver integrated circuits 120a, 120b, 120c, and 120d based on auxiliary communication signals received from the fourth data driver integrated circuit 120d configured at the end of the cascade.

[0075] The data processing device 110 can send an auxiliary communication feedback signal for the auxiliary communication signal to the first data driver integrated circuit 120a configured at the beginning of the cascade via the auxiliary communication feedback line CLAF. For example, the data processing device 110 can generate the auxiliary communication feedback signal in the same form as the auxiliary communication signal received from the fourth data driver integrated circuit 120d and send it to the first data driver integrated circuit 120a. However, embodiments of the present invention are not limited thereto. For example, the auxiliary communication feedback line CLAF can be omitted, and a drive voltage VCC and a pull-up resistor can be connected to the receiving section of the first data driver integrated circuit 120a. For example, a plurality of data driver integrated circuits 120a, 120b, 120c, and 120d can also be connected to the data processing device 110 in a multi-drop manner.

[0076] Figure 3 This is a structural diagram of a data processing apparatus and a data driving apparatus according to one embodiment. Figure 4 This is a structural diagram of a scrambler according to an embodiment of the present invention.

[0077] Reference Figure 3The data processing device 110 may include a first main communication circuit 410 and a first auxiliary communication circuit 420, and the data driving device 120 may include a second main communication circuit 610 and a second auxiliary communication circuit 620. The first main communication circuit 410 can communicate with the second main communication circuit 610, and the first auxiliary communication circuit 420 can communicate with the second auxiliary communication circuit 620.

[0078] The first main communication circuit 410 can send the main communication signal MDT to the data driving device 120 via the main communication line CLM. The first main communication circuit 410 can send image data and first control data in the active range and send second control data in the blanking range via the main communication line CLM.

[0079] The data driving device 120 can drive the pixels of the display panel according to image data. The first control data may include control values ​​applied in row units or pixel units of the display panel, and the second control data may include control values ​​applied with a period longer than row units or pixel units, or control values ​​applied in frame units.

[0080] The first main communication circuit 410 can transmit setting data at a first data rate via the main communication line CLM. Subsequently, the first main communication circuit 410 can transmit image data, first control data, and second control data at a second data rate higher than the first data rate via the main communication line CLM. The mode of communication at the first data rate can be defined as a low-speed communication mode, and the mode of communication at the second data rate can be defined as a high-speed communication mode.

[0081] The first main communication circuit 410 can receive image data, control data, and setting data, and convert and output the received image data, control data, and setting data according to their different rules. The first main communication circuit 410 may include a first data conversion unit 411 for converting image data and control data, and a second data conversion unit 412 for converting setting data. The first data conversion unit 411 and the second data conversion unit 412 may also be defined as a first data conversion circuit and a second data conversion circuit, respectively.

[0082] The first data conversion unit 411 can receive image data and control data, and convert the received image data and control data according to their different rules and output them. The first data conversion unit 411 may include a first packetizer 413A, a second packetizer 413B, a scrambler 414, a first encoder 415A, and a second encoder 415B.

[0083] The first packetizer 413A can receive image data from the data processing circuit 10. The data processing circuit can be an external host or an application processor (AP), but embodiments of the present invention are not limited thereto. For example, the data processing circuit can also be part of a data processing device 110 that receives data from a host.

[0084] The first packetizer 413A and the second packetizer 413B can be connected to the data processing circuit 10 via separate lines to receive data independently. The data processing circuit 10 can transmit data to the first packetizer 413A and / or the second packetizer 413B according to a predetermined timeline. However, embodiments of the present invention are not limited thereto. The first packetizer 413A and the second packetizer 413B can be connected to the data processing circuit 10 via a single line and receive data according to a predetermined timeline.

[0085] The first packetizer 413A can receive image data in the form of a continuous bit stream from the data processing circuit 10 and generate an image packet with a preset number of bits. The second packetizer 413B can receive first control data and / or second control data from the data processing circuit 10 and generate a control packet with a preset number of bits. The image packet can be referred to as a first data packet, image data packet, image packet data, etc., and the control packet can be referred to as a second data packet, control data packet, control packet data, etc.

[0086] The number of bits in an image packet packed by the first packer 413A and a control packet packed by the second packer 413B can differ. For example, an image packet may be packed with 12 bits, while a control packet may be packed with 3 or 4 bits. However, embodiments of the invention are not limited to this. For example, the image packet and the control packet may be packed with the same number of bits.

[0087] The scrambler 414 can scramble the data of the image packet. Scrambling is the process of changing the bits of the transmitted data, which can prevent the same bit from being configured K times (K is a natural number greater than 2) more than once in the data transmission stream. Scrambling is performed according to a pre-agreed rule, and according to the pre-agreed rule, the data driving device 120 can restore the scrambled data stream to its original state.

[0088] Reference Figure 4 The scrambler 414 may include G(x) = X 12 +X 6 +X 4 +X 1The system consists of a 12-bit Linear Feedback Shift Register (LFSR) constructed from a polynomial of +1, logic circuit 414B, and arithmetic circuit 414C. Upon power-on, the initial seed value of the linear feedback shift register 414A is 12'hFFF, and the LFSR of the scrambler 414 and descrambler 614 can be initialized to the seed value via SCR_RST. Subsequently, when SCR_EN is input to logic circuit 414B with "H", the linear feedback shift register 414A operates. The arithmetic circuit 414C performs an XOR operation between the value of the linear feedback shift register 414A and the image data, thereby outputting the scrambled data. Control signals such as SCR_RST and SCR_EN can be set in the control data of the display mode.

[0089] Scrambler 414 can scramble only the image data without applying scrambling to the first or second control data. However, embodiments of the invention are not limited to this. For example, scrambler 414 can also scramble the blanking data to more effectively reduce EMI.

[0090] Figure 5 This is a structural diagram of the first encoder according to an embodiment of the present invention. Figure 6 This is a structural diagram of the second encoder according to an embodiment of the present invention. Figure 7 This is a structural diagram of a data processing apparatus according to another embodiment of the present invention.

[0091] Reference Figure 5 The first encoder 415A may include a data comparison unit 521, a bit generation unit 522, a code conversion unit 523, and a data group generation unit 524.

[0092] The data comparison unit 521 can compare the most significant bit (MSB) of an adjacent first image packet with the least significant bit (LSB) of a second image packet. The first image packet may be the preceding image data packet immediately transmitted to the encoder, and the second image packet may be the current image data packet, but embodiments of the present invention are not limited thereto. For example, the data comparison unit 521 can simultaneously input multiple image data packets stored in the frame memory to compare the bits at packet boundaries. The first image packet may be referred to as packet 1-1, and the second image packet may be referred to as packet 1-2.

[0093] The data comparison unit 521 can output an inverted signal when the most significant bit of an adjacent first image packet is the same as the least significant bit of a second image packet, and output a non-inverted signal when the most significant bit of the first image packet is different from the least significant bit of the second image packet. "Same bits" can mean that the bit values ​​are either 0 or 1 and have the same value. "Different bits" can mean that the bit values ​​are either 0 or 1 and have different values.

[0094] The data comparison unit 521 can perform an XOR operation. When the most significant bit of the first image packet and the least significant bit of the second image packet are both 0 or both are 1, the data comparison unit 521 can output an inverted signal 0.

[0095] When the most significant bit of the first image packet is 1 and the least significant bit of the second image packet is 0, or when the most significant bit of the first image packet is 0 and the least significant bit of the second image packet is 1, the data comparison unit 521 can output a non-inverted signal 1.

[0096] The bit generation unit 522 can generate an indication packet and receive an inverted or non-inverted signal output from the data comparison unit 521, thereby mapping the conversion information of the bit to the indication packet. The conversion information can be an inverted or non-inverted signal output from the data comparison unit 521. For example, if the conversion information is input as 1, the decoder may not invert the bit; if the conversion information is input as 0, the decoder may invert the bit.

[0097] The code conversion unit 523 can invert or not invert the least significant bit of an image packet based on either an inverted signal or a non-inverted signal. However, embodiments of the present invention are not limited to this. For example, the most significant bit of a first image packet can be compared with the least significant bit of a second image packet, and the most significant bit of the first image packet can be inverted if the bits are the same. According to an embodiment, two adjacent image packets can be compared, and if adjacent bits at the packet boundary have the same value, one of the adjacent bits can be inverted in order to generate a clock edge.

[0098] According to an embodiment, the least significant bit of an image packet can have a different value than the most significant bit of an adjacent image packet. Since the bits located at the boundaries of each image packet have different values, clock edges can be generated at the packet boundaries. Therefore, the set maximum run length can be ensured.

[0099] For example, when the maximum run length is set to 3UI, if the bits of the first image packet are

[0100] and the bits of the second image packet are

[0000] , then 0 appears 6 times consecutively in the two image packets, which may exceed the maximum run length of 3UI. However, according to an embodiment, the least significant bit of the second image packet is inverted from 0 to 1, so the bits of the second image packet can be encoded as

[1000] . Therefore, since the bits change at the boundary between the first and second image packets, a clock edge is generated, thus satisfying the maximum run length requirement.

[0100] The data group generation unit 524 can generate a data group with N packets by inserting one indicator packet into N-1 (N is a natural number) image packets. According to the embodiment, one data group has N packets, and each packet can have N bits. That is, the number of packets and the number of bits in one data group can be the same. Therefore, effective clock recovery can be achieved in the receiver 200.

[0101] Reference Figure 6 The second encoder 415B may include: a first bit generation unit 531, which generates a plurality of redundant bits identical to the unit bit for each unit bit of the input control packet; and a second bit generation unit 532, which generates the inverted bit of the unit bit. The first bit generation unit 531 can generate a plurality of redundant data having the same value as the unit bit.

[0102] For example, when the value of a unit bit is 1, the first bit generation unit 531 can generate three redundant bits with a value of 1. For example, when the value of a unit bit is 0, the first bit generation unit 531 can generate three bits with a value of 0. In the encoded redundant bits, the middle bit can be a valid bit containing information. However, the number of bits generated by the first bit generation unit 531 is not limited to this. For example, the first bit generation unit 531 can also generate two redundant bits.

[0103] The second bit generation unit 532 can insert a unit bit and an inverted transition bit. For example, when the unit bit is 1, the second bit generation unit 532 can generate a transition bit with a value of 0. For example, when the unit bit has a value of 0, the second bit generation unit 532 can generate a transition bit with a value of 1.

[0104] Therefore, when the bits of the control packet consist of 3 unit bits

[110] , the bits encoded by the second encoder 415B can be [111011100001], and when the bits of the control packet are

[1101] , the encoded bits can be [110110001110]. Bit errors may occur when the data drive device samples each bit for data and clock recovery, but according to the embodiment, sampling margin can be ensured through redundant bits, thus reducing bit errors. Therefore, error detection components such as CRC and checksums used for error verification can be omitted.

[0105] The second encoding technique can be defined as TC (Transition code) encoding, but it is not limited to this and can also be defined by other names.

[0106] Re-reference Figure 3 The second data conversion unit 412 may include a third packetizer 413C and a third encoder 415C. The third packetizer 413C can receive setting data from the data processing circuit 10 and generate a setting packet according to a predetermined number of bits. The setting packet may be referred to as a third data packet, a setting data packet, setting packet data, etc.

[0107] The setup data is data transmitted at low speed and may include settings of the data drive device 120 required before high-speed communication. For example, the setup data may include settings of the circuitry in the data drive device 120 that performs high-speed communication.

[0108] The third encoder 415C can encode the configuration package packed by the third packer 413C in a predetermined manner. The third encoder 415C can encode the configuration package using DC balanced code. For example, the third encoder 415C can encode the configuration package using Manchester code or 8B10B code, but embodiments of the present invention are not limited thereto.

[0109] The first data output circuit 416 can receive data packets from the first encoder 415A, the second encoder 415B, and the third encoder 415C respectively, and transmit the data that conforms to the pattern to the serializer 417. For example, in setting mode, the first data output circuit 416 can transmit setting data to the serializer 417, and in display mode, it can transmit image data and control data to the serializer 417.

[0110] Data transmitted in parallel from the first data output circuit 416 can be serially converted by the serializer 417. The serializer 417 can send the serially converted data to the data drive device 120. At this time, the serially transmitted series of data can form a transmission stream, which can be in the form of the main communication signal MDT. The first data output circuit 416 and the serializer 417 can constitute a transmission unit. The transmission unit can be called a transmission circuit or transmission logic, etc.

[0111] According to the embodiment, the setting data for low-speed transmission can also be transmitted using the high-speed serializer 417. Therefore, a separate low-speed serializer can be omitted. In this case, the transmitted data can also be modified so that it can be transmitted substantially at a low speed even under the high-speed drive of the serializer 417. For example, when transmitting bit

[10] , by extending the bit to [11111111110000000000] for transmission, although transmission is at a high speed, the actual data transmission speed can be adjusted to be driven at a low speed.

[0112] However, embodiments of the present invention are not limited thereto. For example, the first data output circuit 416 can synchronize the setting data transmitted from the third encoder 415C to a high frequency or image packet frequency based on the second data rate and transmit it to the serializer 417. The serializer 417 can serialize the received setting data and transmit it at the second data rate.

[0113] For example, it can be assumed that the set data output by the third encoder 415C is 12 bits, the output of the first data output circuit 416 is 12 bits, and the second data rate is 12 times faster than the first data rate. In this case, the first data output circuit 416 can transmit one clock cycle of the set data output by the third encoder 415C to the serializer 417 at a high-speed packet clock over a period of 12 clock cycles. Here, the data in one clock cycle, which is the high-speed packet clock, is the data where one bit of the set data output by the third encoder 415C is expanded to the same 12 bits and transmitted, with one bit output per clock cycle. Based on this configuration, high-speed transmission can be achieved without the need for a separate low-speed serializer in the transmitter, and the transmission rate in the first communication line CLM can be transmitted at the second data rate.

[0114] For example, the setting data encoded by the second data conversion unit 412 can also be transmitted to the main communication line CLM via a separately configured low-speed serializer.

[0115] The main communication line CLM can consist of m electrically isolated lines (m being a natural number). Furthermore, the m lines can be paired, allowing each pair to perform LVDS (Low Voltage Differential Signaling) communication. When the main communication line CLM comprises two or more pairs, the serializer 417 can distribute the data to be transmitted across each pair.

[0116] The transmitted data consists of bits, and a plurality of bits can form a symbol. A symbol can also consist of 6 bits, 8 bits, or 10 bits. Furthermore, a plurality of symbols can form image data. The image data can sequentially include information corresponding to sub-pixels such as R (red), G (green), and B (blue). The data driving device 120 can arrange the data received serially in bit units into byte units or into pixel units.

[0117] The main communication signal can be an embedded clock signal. Because the main communication signal has an embedded clock, the data drive device 120 may need clock training in the initial communication interval.

[0118] The data processing device 110 includes a first auxiliary communication circuit 420, which may include a first auxiliary control circuit 421 and a first auxiliary signal processing circuit 422.

[0119] The first auxiliary signal processing circuit 422 can receive auxiliary communication signal LCK from the auxiliary communication line CLA or send auxiliary communication signal LCK to the auxiliary communication line CLA.

[0120] The first auxiliary control circuit 421 can confirm the auxiliary communication signal LCK received from the auxiliary communication line CLA. When the auxiliary communication signal LCK indicates an abnormality in the data drive device 120, it can send an auxiliary communication feedback signal with the same form as the auxiliary communication signal LCK to the auxiliary communication line CLA.

[0121] The data driving device 120 may include a second main communication circuit 610 and a second auxiliary communication circuit 620.

[0122] The second main communication circuit 610 can receive the main communication signal MDT via the main communication line CLM. The second main communication circuit 610 can receive image data and first control data in the active region and second control data in the blanking region via the main communication line CLM. The data driving circuit 20 can drive the pixels of the display panel according to the image data and control data.

[0123] The second main communication circuit 610 can receive setting data at a first data rate via the main communication line CLM. Furthermore, the second main communication circuit 610 can receive image data, first control data, and second control data at a second data rate higher than the first data rate via the main communication line CLM.

[0124] The second main communication circuit 610 may include a deserializer 617, a second data output circuit 616, a third data conversion unit 611, and a fourth data conversion unit 612. The deserializer 617 and the second data output circuit 616 may constitute a receiving unit or a receiving circuit.

[0125] The deserializer 617 can parallelize the main communication signal MDT received serially through the main communication line CLM in byte or symbol units.

[0126] The second data output circuit 616 can transmit the parallel data converted by the deserializer 617 to the third data conversion unit 611 and the fourth data conversion unit 612 according to the mode. For example, in the setting mode, the setting data can be transmitted to the third decoder 615C; in the display mode, the image data can be transmitted to the first decoder 615A or the control data can be transmitted to the second decoder 615B.

[0127] The third data conversion unit 611 may include a first decoder 615A, a second decoder 615B, a descrambler 614, a first unpacker 613A, and a second unpacker 613B.

[0128] The first decoder 615A can decode image data, and the second decoder 615B can decode control data. The first decoder 615A can perform decoding in reverse order of encoding the image data by the first encoder 415A. The second decoder 615B can perform decoding in reverse order of encoding the control data by the second encoder 415B. For example, the second decoder 615B can extract only the second bit from every four bits in each control packet and delete the remaining bits. For example, when the bits of the control packet are [111011100001], only the second bit can be extracted from every four bits and decoded as

[110] .

[0129] The descrambler 614 can restore the scrambled data to its original state according to pre-agreed rules. The descrambler 614 can be synchronized with the scrambler 414 to restore the scrambled data.

[0130] The first unpacker 613A can arrange image data by pixel and transmit the image data of each pixel to the data driving circuit 20. The second unpacker 613B can restore the control data to its original form and transmit it to the data driving circuit 20.

[0131] The fourth data conversion unit 612 may include a third decoder 615C and a third unpacker 613C. The third decoder 615C can recover setting data encoded in Manchester code. The third unpacker 613C can receive the setting data and transmit the setting values ​​included in the setting data to the data drive circuit.

[0132] The second auxiliary communication circuit 620 may include a second auxiliary control circuit 621 and a second auxiliary signal processing circuit 622.

[0133] The second auxiliary control circuit 621 can confirm the abnormal state of the main communication signal MDT, the abnormal state of the main communication circuit and / or other abnormal states, and generate a status signal.

[0134] The second auxiliary signal processing circuit 622 can generate an auxiliary communication signal LCK using a status signal or a feedback signal, and send the auxiliary communication signal LCK to the auxiliary communication line CLA.

[0135] The data driving device 120 according to an embodiment may include a main control circuit 430. The main control circuit 430 can receive control signals from the data processing circuit 10 to control the first data conversion unit 411, the second data conversion unit 412, the first data output circuit 416, etc. However, the embodiments of the present invention are not limited thereto. For example, such as... Figure 7 As shown, the data drive device 120 can also be configured such that, without a separate main control circuit and operating in block units, it transmits signals to the block to perform the next function according to logic to enable it to perform that function. In the absence of an interface for a low-speed drive setting mode, the second data conversion unit 412 can also be omitted from the data drive device 120.

[0136] Figure 8 This is a diagram illustrating the sequence of main signals in one embodiment. Figure 9 This is a structural diagram of the hidden data and row data according to an embodiment of the present invention. Figure 10 This is a diagram illustrating the bits of a plurality of packets according to an embodiment of the present invention.

[0137] Reference Figures 8 to 10 The driving voltage VCC initially has a low voltage level, and its waveform can change to a high voltage level at a certain point in time. The point at which the driving voltage VCC changes to a high voltage level can be the driving time point of the display driving device.

[0138] After the driving time point, the data processing device 110 and the data driving device 120 can operate in the setting mode (CFGmode) T101. After the operation in the setting mode T101 is completed, the data processing device 110 and the data driving device 120 can operate in the display mode T102.

[0139] In setting mode T101, the data processing device 110 can continuously send preamble packet P710 and setting packet P720 via the main communication signal MDT.

[0140] The data processing device 110 can change the voltage of the auxiliary communication feedback signal from low to high level while transmitting the preamble packet P710. Through this voltage change, the data processing device 110 can inform the data driving device 120 that the preamble packet P710 is being transmitted.

[0141] The data driver 120 can use a preamble packet P710 composed of a clock training mode to train a low-speed communication clock for receiving a setting packet P720. The data driver 120 can then train the clock after training is complete. CFG_LOCK Phase locking of the preamble mode is performed within a specified time.

[0142] The data processing device 110 can transmit the preamble packet P710 and the setup packet P720 at a relatively low first data rate. The low-speed communication clock will become the first data rate, and the data driving device 120 can use the preamble packet P710 to train the low-speed communication clock.

[0143] When the low-speed communication clock training is complete, the data driving device 120 can inform the data processing device 110 of the clock training status via an auxiliary communication signal. For example, when the low-speed communication clock training is complete, the data driving device 120 can change the voltage of the auxiliary communication signal from a low level to a high level. After confirming via the auxiliary communication signal that the data driving device 120 has trained the low-speed communication clock, the data processing device 110 can send a setting packet P720.

[0144] The configuration packet P720 can consist of a start bit (CFGS) P721, a header P722, body data P723, and an end bit (CFGE) P724. Checksum data may also be included as needed.

[0145] The header P722 may include parameter values ​​such as data type, mode, receiver identification number (ID), data length, and receiver configuration register address. The main data P723 may include configuration information for message transmission and reception.

[0146] The start bit P721 and the stop bit P724 can be composed of different data bits. For example, if the start bit P721 is a data bit equivalent to the binary number "0", then the stop bit P724 can be composed of a data bit equivalent to the binary number "1".

[0147] After the data driving device 120 identifies the end bit P724 through the first communication signal MDT, it can determine that the setting mode T101 has ended and enter the display mode T102 when the first communication signal MDT is maintained at a voltage level that can be recognized as a binary number "0" or "1". However, embodiments of the present invention are not limited to this. Even when the voltage level is not recognized as a binary number "0" or "1" but is a high level or a low level, it can still be determined that the setting mode has ended.

[0148] After setting mode T101 ends, data processing device 110 and data driving device 120 can enter display mode T102. Display mode T102 can be composed of clock training interval T103 and frame interval T104. If the high-speed communication clock P730 is trained in clock training interval T103, the subsequent frame interval T104 will appear repeatedly.

[0149] During the clock training interval T103, the data processing device 110 can send a clock training mode P730 to the data driving device 120 at a second data rate. The data driving device 120 can train a high-speed communication clock equivalent to the second data rate under the clock training mode P730. Here, the second data rate can have a higher frequency than the first data rate.

[0150] If the data driving device 120 fails to train the high-speed communication clock during the clock training interval T103, the data driving device 120 can send a clock training failure signal through an auxiliary communication signal. For example, the data driving device 120 can reduce the voltage of the auxiliary communication signal from a high level to a low level and inform the data processing device 110 of the clock training failure.

[0151] When clock training for the high-speed communication clock fails, the data processing device 110 can either add a clock training mode or return to the setting mode T101.

[0152] When the clock training for the high-speed communication clock is completed, the data processing device 110 and the data driving device 120 can enter the frame interval T104.

[0153] Frame interval T104 may include a valid interval T106 and a blanking interval T105. The valid interval T106 may be an interval in which image data and control data are transmitted in line units, while the blanking interval T105 may be an interval in which no line units of image data are transmitted. The blanking interval T105 can be divided into a horizontal blanking interval and a vertical blanking interval; for ease of explanation, the blanking interval T105 will be described as the vertical blanking interval below.

[0154] During the blanking interval T105, the data processing device 110 can send frame control packets P740 in line units. The frame control packet P740 may include a control start packet (CS) P741, a frame start packet (FPS) P742, and a frame data packet (FC data) P743.

[0155] The control start packet P741 indicates the start of control packets. The frame start packet P742 indicates the start of frame data transmission. Therefore, it is possible to distinguish whether the data transmitted after the control start signal is frame data or line data.

[0156] Reference Figure 10 The bits of the start of control packet P741 can be [110011110000] in the direction from MSB to LSB, and the bits of the start of frame packet P742 can be [001111001100], but are not limited to these; various other modes are also possible. Sometimes TC encoding or scrambling is not applied to the start of control packet P741 and the start of frame packet P742.

[0157] The frame data packet P743 may include setting values ​​that change in frame units or remain unchanged. The frame clock training mode may include a pattern signal capable of training a clock for high-speed communication. According to an embodiment, the frame control packet P740 and the frame clock training mode may not be scrambled. However, embodiments of the present invention are not limited thereto. For example, the frame control packet P740 may not be scrambled, while the frame clock training mode P744, as blanking data, may be scrambled to reduce EMI.

[0158] In the blanking interval T105, the data processing device 110 can send blanking data packets to all rows before entering the valid interval T106. According to an embodiment, the blanking data may include information about dummy data included in the image data. For example, by adding a virtual control signal capable of identifying dummy rows, the data processing device 110 can distinguish whether the pixel data is valid pixel data or dummy data generated to satisfy the 12-bit requirement. That is, in the vertical blanking interval, frame control packets P740, dummy control packets, and clock training can be combined and transmitted.

[0159] Within the effective interval T106, the data processing device 110 can send line control packets P750, image packets P760, and line clock training mode P754 on a per-line basis.

[0160] The line control packet P750 can consist of a control start packet P751, a line start packet P752, and a line data packet P753. The control start packet P751 indicates the start of the line control packet P750, and the line start packet P752 indicates the start of line data transmission. For example, the bits of the start packet can be [110011110000], and the bits of the line start packet P752 can be [110000111100], but it is not limited to these; various other modes are also possible. Sometimes scrambling is not applied to the control start packet P751 and the line start packet P752.

[0161] The line data packet P753 may include setting values ​​that can be changed on a line-by-line basis or at any time. For example, the line data packet P753 may include polarity values ​​representing the polarity of each pixel, values ​​indicating whether the scrambler 414 has been reset, and control information regarding whether the image data is valid or dummy data.

[0162] The image packet P760 may include grayscale values ​​of pixels arranged in a row. The row clock training mode P754 may include a pattern signal capable of training a clock for high-speed communication.

[0163] In the valid interval T106, the data processing device 110 can re-enter the blanking interval T105 after sending the line control packet P750 to all lines.

[0164] Figure 11 This is a structural diagram of a data packet in the first horizontal row according to an embodiment of the present invention. Figure 12 This is a diagram illustrating a data packet including virtual data according to an embodiment of the present invention.

[0165] Reference Figure 11 The data packets of the first horizontal row may include a row control packet P750, multiple data groups including grayscale values ​​of pixels configured in a row, and a clock training mode.

[0166] A data set can include one instruction packet and N-1 image packets (Packet 1 to Packet (n-1)), totaling N packets. Figure 11 The example illustrates a data group consisting of 12 packets. Image packets, as RGB image data, can be defined as effective data, but embodiments of the invention are not limited to this. Figure 12 As shown, when there is insufficient RGB data in the last data group of a 1-line, virtual bits can also be mapped to generate a packet. As mentioned above, information about whether the image data in that line is valid image data or virtual data can be stored in the blanking data or line data.

[0167] Figure 13 This is a diagram illustrating the image data structure of an embodiment of the present invention. Figure 14 This is a flowchart illustrating the image data encoding steps of an embodiment of the present invention. Figure 15 This is a diagram illustrating an image data encoding method according to an embodiment of the present invention.

[0168] Reference Figure 13 The indicator packet IDP can have N bits (HD1, I1 to I(n-1), and HD2). The least significant bit (LSB) and most significant bit (MSB) of the indicator packet IDP can be clock bits (CK) or dummy bits. Transition information (BI) of each image packet can be mapped between the LSB and MSB of the indicator packet. In an embodiment, the least significant bit can be the bit closest to the previous packet within each packet, and the most significant bit can be the bit closest to the next packet within each data packet; however, embodiments of the present invention are not limited to this.

[0169] The least significant bit (LSB) of an indicator packet can be mapped to a value different from the most significant bit (B(n-1)) of the previous image packet. For example, if the last bit (B(n-1)) of the previous data group is 0, a 1 can be written to the LSB of the indicator packet. Conversely, if the last bit (B(n-1)) of the previous data group is 1, a 0 can be written to the LSB of the indicator packet. Therefore, a clock edge can be generated at the boundary between the previous and current data groups.

[0170] The most significant bit (MSB) of the indicator packet can be matched by inverting the value of the least significant bit (B0) of the first image packet (Packet 1) within the current data group. For example, if the least significant bit (B0) of the first image packet within the current data group is 1, the most significant bit (MSB) of the indicator packet can be mapped to 0. Similarly, if the least significant bit (B0) of the first image packet (Packet 1) within the current data group is 0, the most significant bit (MSB) of the indicator packet can be mapped to 1. Therefore, a clock edge occurs at the boundary between the indicator packet and the adjacent first image packet (Packet 1), thus satisfying the maximum run length requirement.

[0171] Reference Figure 5 , Figure 14 as well as Figure 15 The comparison step can be performed by performing an XOR operation on the most significant bit (MSB) of the first image packet and the least significant bit (LSB) of the second image packet.

[0172] When the most significant bit (MSB) of the first image packet and the least significant bit (LSB) of the current image packet are both 0 or 1, the data comparison unit 521 can output an inversion signal 0.

[0173] When the data comparison unit 521 has different bit values ​​for the most significant bit (MSB) of the first image packet and the least significant bit (LSB) of the second image packet, it can output a non-inverted signal 1.

[0174] For example, when the most significant bit (MSB) of the first image packet (Packet 1) is 1 and the least significant bit (LSB) of the second image packet is 1, since the bit values ​​are the same, the data comparison unit 521 can output an inversion signal 0 that inverts the least significant bit (LSB) of the second image packet.

[0175] Since the inverted signal 0 is output, the code conversion unit 523 can invert the least significant bit (LSB) of the second image packet and convert the LSB of the second image packet to 0 (~B0). The bit generation unit 522 can map the conversion information 0 to the I1 position of the indicator packet.

[0176] Subsequently, the data comparison unit 521 compares the most significant bit (MSB) of the second image packet with the least significant bit (LSB) of the third image packet. If the bit values ​​are the same, it can output an inverted signal. For example, when the most significant bit (MSB) of the second image packet (Packet 2) is 1 and the least significant bit (LSB) of the third image packet (Packet 2) is 0, the data comparison unit 521 can output a non-inverted signal 1 because the bit values ​​are different. The third image packet can be referred to as the first to third data packets.

[0177] The code conversion unit 523 can maintain the original state (B0) of the least significant bit (LSB) of the third image packet (Packet 3) without inverting it based on the non-inverted signal 1. The bit generation unit 522 can map the conversion information 1 to the I2 position of the indicator packet.

[0178] Similarly, the data comparison unit 521 can sequentially compare the most significant bit (MSB) of the previous image packet with the least significant bit (LSB) of the current image packet, thereby outputting an inverted signal or a non-inverted signal.

[0179] The code conversion unit 523 can invert or not invert the bit value of the least significant bit (LSB) of the current image packet according to the inverted or non-inverted signal. The bit generation unit 522 can sequentially map the conversion information BI to the corresponding bit positions.

[0180] The least significant bit (LSB) of the indicator packet IDP can be reversed from 0 and mapped to 1, and the least significant bit (MSB) of the first image packet (Packet 1) of the current data group can be reversed from 1 and mapped to 0.

[0181] The least significant bit (LSB) and most significant bit (MSB) of the indicator packet IDP can be sequentially mapped between the least significant bit (LSB) and most significant bit (MSB) of the second to eleventh image packets (Packet 2 to Packet 11).

[0182] According to the embodiment, since the most significant bit (MSB) of the indicator packet is mapped to a value different from the least significant bit (LSB) of the first image packet (Packet 1), the least significant bit (LSB) of the first image packet (Packet 1), which is closest to the indicator packet configuration, may not be encoded. The least significant bits (LSBs) of the remaining 10 image packets (excluding the first image packet (Packet 1)) within the data group can be inverted or preserved using an XOR operation.

[0183] For example, a data group can consist of a total of 12 packets, including one indicator packet and 11 image packets. Each indicator packet and image packet can consist of 12 bits. Therefore, the total number of bits in the data group can be 144 bits. However, the specification of this invention is not limited to this. For example, the data group can also consist of 8 packets, including one indicator packet and 7 image packets. With each packet consisting of 8 bits, the total number of bits in the data group can also be 64 bits. According to embodiments, since the number of packets is the same as the number of bits in the packets, the maximum run length can be maintained consistently.

[0184] Figure 16 This is a diagram illustrating the decoding process of an embodiment of the present invention.

[0185] Reference Figure 16 The decoder can separate the indicator packet and the image packet from the data group and store them separately. The decoder can invert or not invert the least significant bit of the image packet based on the conversion information BI of the indicator packet. The conversion information BI can be an indicator bit mapped to a bit position.

[0186] Since the bit information at position I1 in the conversion information BI is 0, the decoder can invert the least significant bit (LSB) of the second image packet (Packet 2) to 1.

[0187] Since the bit information at position I2 in the conversion information BI is 1, the decoder can keep the least significant bit (LSB) of the third image packet (Packet 3) 0 without inverting it.

[0188] Since the bit information at position I3 in the conversion information BI is 0, the decoder can invert the least significant bit (LSB) of the fourth image packet (Packet 4) to 0.

[0189] Since the bit information at position I10 in the conversion information BI is 1, the decoder can keep the least significant bit (LSB) of the eleventh image packet (Packet 11) 0 without inverting it.

[0190] The recovered data can be restored to be identical to the original data. According to an embodiment, since decoding is performed using the conversion information stored in the instruction packet, it has the advantage of eliminating the need for a separate memory for decoding.

[0191] Figure 17 This is a diagram illustrating the process of encoding control data according to an embodiment of the present invention. Figure 18 This is a diagram illustrating the process of encoding control data according to another embodiment of the present invention.

[0192] Reference Figure 17 The control packet can consist of 3 bits. The second encoder can map each bit of the input control packet to 4 bits. For example, when a control packet consists of a total of 3 unit bits such as D0, D1, and D2, the second encoder can map the 3 bits identical to the first unit bit D0 to redundant bits B0, B1, and B2, and map the bit that is reversed from D0 (~D0) to a transition bit B3. Similarly, the second unit bit D1 and the third unit bit D2 can also be mapped to 3 redundant bits B4, B5, B6, B8, B9, and B10 and 1 reversed transition bit B7 and B11.

[0193] For example, when the control packet has

[101] bits, the encoded bits can be [111000011110]. When packaged by the second packer, the control packet has fewer bits than the image packet, but after encoding, each packet can have the same 12 bits. Therefore, a control packet consisting of 3 bits can be mapped to 12 bits by the second encoder, thus satisfying the 12-bit format. Therefore, all data sent from the data drive device can satisfy the 12-bit format.

[0194] In the encoded bits, the middle bits B1, B5, and B9 of the three redundant bits are likely to be valid bits containing information. Bit errors may occur when sampling each bit, but according to the embodiment, sampling margin can be ensured through redundant bits, thus reducing bit errors. Therefore, error detection components such as CRC and checksums used for error verification can be omitted.

[0195] Reference Figure 18The control packet can also consist of 4 unit bits. The second encoder can map each bit of the input control packet to 3 bits. For example, when the control packet consists of a total of 4 bits such as D0, D1, D2, and D3, the second encoder can map the 2 bits that are the same as the first bit D0 to redundant bits B0 and B1, and map the inverted bit to a transition bit B2. Similarly, the second bit D1, the third bit D2, and the fourth bit D3 can also be mapped to 2 non-inverted redundant bits and 1 inverted transition bit.

[0196] For example, when the bits of the control packet are

[1010] , the encoded bits can be [110001110001]. Therefore, a control packet consisting of 4 bits can be mapped to 12 bits by the second encoder to meet the 12-bit format.

[0197] As the contents of the specification describing the problem to be solved, the means to solve the problem, and the effect are not used to limit the essential features of the claims, the scope of the claims is not limited by the matters described in the specification.

[0198] The embodiments have been described in more detail above with reference to the accompanying drawings. However, the present invention is not necessarily limited to these embodiments, and various modifications can be made without departing from the technical spirit of the invention. Therefore, the embodiments disclosed in this invention are not intended to limit the technical spirit of the invention but are intended to illustrate it, and the scope of the technical spirit of the invention is not limited by these embodiments. Therefore, it should be understood that the embodiments described above are illustrative and not limiting in all respects.

Claims

1. A data processing apparatus, wherein, include: The first data conversion unit converts image data and control data; as well as The transmission unit transmits the converted image data and the control data. The first data conversion unit includes: A first packetizer converts the image data into a first data packet; The second packetizer converts the control data into a second data packet; A first encoder encodes the first data packet according to a first rule; and The second encoder encodes the second data packet using a second rule that differs from the first rule.

2. The data processing apparatus according to claim 1, wherein, The second data packet has fewer bits than the first data packet.

3. The data processing apparatus according to claim 2, wherein, The number of bits in the encoded second data packet is the same as the number of bits in the encoded first data packet.

4. The data processing apparatus according to claim 1, wherein, The control data includes first control data and second control data. The first control data includes control values ​​applied in row units or pixel units of the display panel, and the second control data includes control values ​​applied in frame units.

5. The data processing apparatus according to claim 4, wherein, The transmission unit divides each frame time into an effective interval and a blanking interval, transmits the image data and the first control data in the effective interval, and transmits the second control data in the blanking interval.

6. The data processing apparatus according to claim 1, wherein, Including the second data conversion unit, The second data conversion unit includes: The third packetizer converts the configured data into a third data packet; and A third encoder encodes the third data packet using a third rule that differs from the first and second rules.

7. The data processing apparatus according to claim 6, wherein, The transmission unit transmits the converted image data, the control data, and the setting data in a predetermined order.

8. The data processing apparatus according to claim 1, wherein, The first encoder includes: The data comparison unit compares the most significant bit of an adjacent first data packet (1-1) with the least significant bit of an adjacent first data packet (1-2). The code conversion unit, when the most significant bit of the first-1 data packet and the least significant bit of the first-2 data packet have the same value, reverses the least significant bit of the first-2 data packet; and The bit generation unit generates an instruction packet, which stores the conversion information of the least significant bit of the first-second data packet.

9. The data processing apparatus according to claim 8, wherein, It also includes a data group generation unit, which inserts the instruction packet into a plurality of the first data packets to generate a plurality of data groups.

10. The data processing apparatus according to claim 9, wherein, Each of the plurality of said data groups has the same number of packets. The number of bits in the instruction packet is the same as the number of data packets in the data group.

11. The data processing apparatus according to claim 1, wherein, The second encoder maps each unit bit constituting the control data to a plurality of redundant bits having the same value as the unit bit and a transition bit having a different value than the unit bit.

12. A data-driven device, wherein, include: The receiving circuit receives data packets from the first to the third. The third data conversion unit converts the first data packet and the second data packet; as well as The fourth data conversion unit converts the third data packet; The third data conversion unit includes: A first decoder decodes the first data packet according to a first rule; The second decoder decodes the second data packet using a second rule that is different from the first rule; A first unpacker converts the first data packet into image data; and The second unpacker converts the second data packet into control data; The fourth data conversion unit includes: A third decoder decodes the third data packet using a third rule different from the first and second rules; and The third unpacker converts the third data packet into the set data.

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