Imaging apparatus and imaging method

Abstract

[Problem] To provide an imaging device and an imaging method capable of suppressing a change in electric potential according to the elapse of time from initialization of a pixel. [Solution] The present disclosure provides an imaging device including: a pixel array unit in which a plurality of first pixels each outputting a luminance signal corresponding to an amount of light are arranged in a matrix; a detection circuit unit that outputs a detection signal indicating occurrence of an address event when the luminance signal of each of the plurality of first pixels exceeds a predetermined threshold value; and a drive unit having a first driver for resetting accumulated charges of the first pixels in a partial region within the plurality of first pixels.

Description

Technical Field

[0001] This disclosure relates to an imaging device and an imaging method. Background Technology

[0002] In an imaging element that includes a pixel array section, only pixels that detect predetermined brightness changes are selected, and the signals of these brightness changes are read. In the pixel array section, pixels, including a photoelectric conversion unit that performs photoelectric conversion of incident light, are arranged in a two-dimensional matrix. These brightness changes are caused by the movement of a target object. By selecting and reading only the pixels that detect the brightness changes, moving objects can be detected at a high frame rate. This type of imaging element is called an event-based vision sensor (EVS).

[0003] Reference List

[0004] Patent documents

[0005] Patent Document 1: Japanese Patent Application Publication No. 2021-048554 Summary of the Invention

[0006] The problem to be solved by the present invention

[0007] On the other hand, there is a situation where only pixels that detect changes in brightness are initialized, and there is a possibility that the potential corresponding to the accumulated charge of the pixel may fluctuate as time passes from initialization.

[0008] Therefore, this disclosure provides an imaging device and imaging method capable of suppressing potential fluctuations of pixels as time passes from initialization.

[0009] Solution to the problem

[0010] To address the aforementioned problems, according to this disclosure, an imaging device is provided, comprising: The pixel array section has a plurality of first pixels arranged in a matrix to output a brightness signal corresponding to the amount of light. The detection circuit section outputs a detection signal indicating the occurrence of an address event when the brightness signal of each of the plurality of first pixels exceeds a predetermined threshold; and The driving unit includes a first drive that resets the accumulated charge in a portion of a plurality of first pixels.

[0011] The first driver can be executed for each line.

[0012] The first drive can be executed for each of multiple rows.

[0013] It may further include a signal processing unit, which determines the range of execution of the first drive based on the number of times a signal is detected within a predetermined time.

[0014] The drive unit can execute the first drive based on the determination of the signal processing unit.

[0015] The pixel array can perform imaging on a frame-by-frame basis, and

[0016] The signal processing unit can determine the scope of the first drive based on the number of times the detection signal appears in a single frame.

[0017] The pixel array can perform imaging on a frame-by-frame basis, and

[0018] The signal processing unit can determine the scope of the first drive based on the number of times the detection signal appears in multiple frames.

[0019] The driving unit can output the brightness signal corresponding to the light amount from the first pixel of the output detection signal in rows.

[0020] It may further include an arbitrator unit that arbitrates the detection signal and outputs a brightness signal corresponding to the light amount from the first pixel to the driver unit.

[0021] It may further include an output unit that generates a data type signal, which includes information indicating that the first pixel has been driven.

[0022] The output unit can generate a signal that includes information indicating the first pixel in at least one of the line header and embedded data of the data packet.

[0023] The driving unit may further include a second driver that resets all of the plurality of first pixels.

[0024] The driver can execute the first driver for each randomly selected row.

[0025] The pixel array section may further include a plurality of second pixels for grayscale arranged in a matrix, and

[0026] It can generate grayscale images based on the output signals of multiple second pixels.

[0027] The driving unit can perform the first drive based on the control signal when controlling the second pixel.

[0028] The driving unit can perform the first drive based on the control signals when initializing or reading the second pixel.

[0029] The driving unit can perform a first drive on the row in which the second pixel is initialized or on the row in which the reading is executed.

[0030] The driving unit can perform a first drive on a first pixel in at least one of the rows in which the second pixel is initialized and the rows in which reading is performed, as well as on a first pixel in another row that is different from the rows in which the second pixel is initialized and the rows in which reading is performed.

[0031] It may further include a second driving unit that drives a plurality of second pixels, and

[0032] The accumulated charge can be read from multiple second pixels for each row.

[0033] It may further include a second driving unit that drives a plurality of second pixels, and

[0034] The accumulated charge can be read from multiple second pixels for all rows.

[0035] To address the aforementioned problems, according to this disclosure, an imaging method is provided, comprising: The detection step involves outputting a detection signal indicating the occurrence of an address event when the luminance signal of each of the plurality of first pixels that outputs a luminance signal corresponding to the light intensity exceeds a predetermined threshold; and The driving circuit step performs a first drive to reset the accumulated charge of the first pixel in a portion of the plurality of first pixels. Attached Figure Description

[0036] Figure 1 This is a block diagram illustrating an example of the configuration of an imaging system to which the technology of this disclosure is applied.

[0037] Figure 2 This is a block diagram illustrating a configuration example of a scanning imaging device.

[0038] Figure 3 This is a block diagram illustrating an example of the configuration of a pixel array section.

[0039] Figure 4 This is a block diagram showing an example of the configuration of the column processing unit.

[0040] Figure 5 This is a circuit diagram showing an example of the circuit configuration of a pixel.

[0041] Figure 6 This is a block diagram showing a configuration example of the address event detection unit.

[0042] Figure 7 This is a diagram showing voltage fluctuations based on the charge accumulated in the photoreceiving element.

[0043] Figure 8 This is a diagram showing an example of a row with a low frequency of becoming an effective pixel.

[0044] Figure 9 This is a diagram showing an example of a circuit configuration.

[0045] Figure 10 This is a diagram illustrating a first control example according to this embodiment.

[0046] Figure 11 This is a diagram illustrating a second control example according to this embodiment.

[0047] Figure 12 This is a diagram illustrating a third control example according to this embodiment.

[0048] Figure 13 This is a diagram illustrating a fourth control example according to this embodiment.

[0049] Figure 14 This is a diagram illustrating an example of a data structure according to this embodiment.

[0050] Figure 15 It is shown in Figure 14 A diagram showing a row of data in an example of the data format shown.

[0051] Figure 16 This is a schematic diagram illustrating an example of processing in an image processing apparatus in a subsequent stage.

[0052] Figure 17 This is a diagram illustrating a configuration example of an imaging device according to the second embodiment.

[0053] Figure 18 This is a diagram illustrating a control example according to the second embodiment.

[0054] Figure 19 This is a block diagram illustrating a configuration example of an imaging device according to a third embodiment.

[0055] Figure 20 It is a diagram that schematically shows the configuration of pixel blocks.

[0056] Figure 21 It is a schematic diagram showing the signal flow between the first access control circuit, the second access control circuit, and the second signal processing unit.

[0057] Figure 22 This is a diagram illustrating a fifth control example according to the third embodiment.

[0058] Figure 23 This is a diagram illustrating a sixth control example according to the third embodiment.

[0059] Figure 24 This is a diagram illustrating a seventh control example according to the third embodiment.

[0060] Figure 25 This is a diagram illustrating an eighth control example according to the third embodiment.

[0061] Figure 26 This is a diagram illustrating a ninth control example according to the third embodiment. Detailed Implementation

[0062] In the following description, embodiments of the imaging apparatus and imaging method will be described with reference to the accompanying drawings. Although the main components of the imaging apparatus will be described primarily below, the imaging apparatus may have components and functions not shown or described. The following description is not intended to exclude components or functions not shown or described.

[0063] (First Implementation)

[0064] Figure 1 This is a block diagram illustrating an example of a system configuration for an imaging system to which the technology of this disclosure is applied.

[0065] like Figure 1 As shown, the imaging system 10 applying the technology of this disclosure includes an imaging lens 11, an imaging device 20, a recording unit 12, and a control unit 13. The imaging system 10 is an example of the electronic device of this disclosure, and examples of the electronic device include camera systems mounted on industrial robots, vehicle-mounted camera systems, etc.

[0066] In the imaging system 10 with the above configuration, the imaging lens 11 captures incident light from the object and forms an image on the imaging surface of the imaging device 20. The imaging device 20 photoelectrically converts the incident light captured by the imaging lens 11 in pixels to obtain imaging data. The imaging device 20 is an imaging device of the present disclosure described later.

[0067] Imaging device 20 performs predetermined signal processing (such as image recognition processing) on ​​the captured image data and outputs data indicating the processing result and a detection signal of an address event (hereinafter simply referred to as the "detection signal"), described later, to recording unit 12. The method for generating the address event detection signal will be described later. Recording unit 12 stores data provided from imaging device 20 via signal line 14. Control unit 13 includes, for example, a microcomputer and controls the imaging operation in imaging device 20.

[0068] [Imaging device (scanning type) according to the first configuration example]

[0069] The imaging device according to the first configuration example is an imaging device that applies a synchronous readout method. The imaging device is a scanning type imaging device, the same as a regular imaging device that performs imaging at a specified frame rate.

[0070] Figure 2A block diagram illustrating an example of the configuration of an imaging device (i.e., a scanning imaging device) according to a first configuration example, which is used as an imaging device 20 in an imaging system 10 applying the technology according to this disclosure.

[0071] like Figure 2 As shown, the imaging device 20, which is a first configuration example of the imaging device of this disclosure, includes a pixel array unit 21, a driving unit 22, a column processing unit 24, a signal processing unit 25, and a readout area selection unit 27.

[0072] The pixel array unit 21 includes a plurality of pixels 30. The plurality of pixels 30 output an output signal in response to a selection signal from the readout region selection unit 27. For example, each of the plurality of pixels 30 may have, for example, Figure 3 The quantizer is shown in the pixel diagram. Multiple pixels 30 output output signals corresponding to changes in light intensity. Multiple pixels 30 can be configured as follows: Figure 2 The matrix shown is arranged in a two-dimensional form.

[0073] [Configuration example of pixel array section]

[0074] Figure 3 This is a block diagram showing an example of the configuration of the pixel array section 21.

[0075] In the pixel array section 21 in which a plurality of pixels 30 are arranged in a matrix in a two-dimensional manner, each of the plurality of pixels 30 includes a light receiving section 31, a pixel signal generating section 32 and an address event detection section 33.

[0076] In the pixel 30 with the above configuration, the light receiving unit 31 photoelectrically converts the incident light to generate a photocurrent. Then, under the control of the driving unit 22, the light receiving unit 31 supplies the photocurrent generated by the photoelectric conversion to the pixel signal generation unit 32 or the address event detection unit 33 (see...). Figure 2 ).

[0077] The pixel signal generation unit 32 generates a signal corresponding to the voltage of the photocurrent supplied from the light receiving unit 31 as a pixel signal SIG, and supplies the generated pixel signal SIG to the column processing unit 24 (see reference) via the vertical signal line VSL. Figure 2 ).

[0078] The address event detection unit 33 detects the presence or absence of an address event based on whether the change in photocurrent from each optical receiving unit 31 exceeds a predetermined threshold. Address events include, for example, an on-time event indicating that the change in photocurrent exceeds an upper threshold and an off-time event indicating that the change in photocurrent falls below a lower threshold. Furthermore, the address event detection unit 33 according to this embodiment can generate a 1-bit on-time detection signal indicating whether an on-time event has occurred, a 1-bit off-time detection signal indicating whether an off-time event has occurred, and a 1-bit detection signal indicating whether either an on-time event or an off-time event has occurred. For example, the on-time detection signal, the off-time detection signal, and the detection signal indicate a true value (e.g., 1) or a false value (e.g., 0). For example, the on-time detection signal indicates a true value when an on-time event occurs and a false value when no on-time event occurs. Similarly, the off-time detection signal indicates a true value when an off-time event occurs and a false value when no off-time event occurs. Similarly, the detection signal indicates a true value when at least one of an on-time event or an off-time event occurs, and a false value when neither an on-time event nor an off-time event occurs.

[0079] When an address event occurs, the address event detection unit 33 supplies a detection signal for the address event to the driving unit 22 and the signal processing unit 25. Note that, according to this embodiment, the address event detection unit 33 corresponds to the detection circuit unit. Furthermore, multiple address event detection units 33 may have a single circuit configuration outside the pixel 30.

[0080] Again Figure 2 As shown, the drive unit 22 responds to the control signal from the control unit 13 (see reference). Figure 1 The driving unit 22 drives the pixel array unit 21 for each frame. The driving unit 22 causes the column processing unit 24 to output the pixel signal generated in the pixel 30 for each row selected by the read area selection unit 27, which will be described later. At this time, the driving unit 22 causes the column processing unit 24 to output the pixel signal generated by the pixel 30 according to the detection signal output from the address event detection unit 33, in units of the selected rows.

[0081] Furthermore, the driving unit 22 executes a first drive to reset the accumulated charge in a portion of the plurality of pixels 30 based on the determination of the signal processing unit 25. Additionally, the driving unit 22 can execute a second drive to reset the accumulated charge in the entire region of the plurality of pixels 30 at a predetermined period.

[0082] [Configuration Example of Column Processing Department]

[0083] Figure 4 This is a block diagram illustrating a configuration example of the column processing unit 24 of the imaging device 20 according to a first configuration example. (See diagram below.) Figure 4As shown, the column processing unit 24 according to this example includes a plurality of analog-to-digital converters (ADCs) 241 arranged for each pixel column of the pixel array unit 21.

[0084] It should be noted that, here, an example of a configuration in which the analog-to-digital converter 241 is arranged in a one-to-one correspondence with the pixel columns of the pixel array 21 has been described, but the present invention is not limited to this configuration example. For example, the analog-to-digital converter 241 may be arranged in units of multiple pixel columns, and the analog-to-digital converter 241 may be configured to perform processing in a time-division manner between multiple pixel columns.

[0085] The analog-to-digital converter 241 converts the analog pixel signal SIG supplied via the vertical signal line VSL into a digital signal with a larger bit depth than the detection signal of the address event described above. For example, when the detection signal of the address event is 2 bits, the pixel signal is converted into a 3-bit or more (16-bit, etc.) digital signal. The analog-to-digital converter 241 provides the digital signal generated by the analog-to-digital conversion to the signal processing unit 25. It should be noted that the column processing unit 24 may include, for example, a column selection circuit that arbitrates signals entering the column processing unit 24. Furthermore, the column processing unit 24 may be configured to output not only information about valid pixels that have detected events, but also information about invalid pixels that have not detected events. It should be noted that the column processing unit 24 according to this embodiment corresponds to the detection unit.

[0086] Again Figure 2 As shown, the signal processing unit 25 performs predetermined signal processing on the digital signal provided by the column processing unit 24, such as correlated double sampling (CDS) processing or image recognition processing. Then, the signal processing unit 25 provides a signal including data representing the processing result and information about the detection signal provided by the address event detection unit 33 (described later) to the recording unit 12 (see reference 14) via signal line 14. Figure 1 ).

[0087] Furthermore, the signal processing unit 25 determines the scope of executing the first drive based on the number of occurrences of the detection signal provided from the address event detection unit 33 within a predetermined time period. In this case, for example, the signal processing unit 25 causes the drive unit 22 to execute the first drive for each row. Alternatively, for example, the signal processing unit 25 causes the drive unit 22 to execute the first drive for each multiple rows.

[0088] The signal processing unit 25 can be configured to output not only information about valid pixels where events have been detected, but also information about invalid pixels where no events were detected. Furthermore, address information and timestamp information (e.g., (X, Y, T)) of valid pixels where events have been detected are output from the signal processing unit 25 via output line 14. However, the data output from the column processing unit 24 can be not only address information and timestamp information, but also information in frame format (e.g., (0, 0, 1, 0, ...)). It should be noted that details of the signal processing unit 25 will be described later.

[0089] The reading region selection unit 27 selects some of the plurality of pixels 30 included in the pixel array unit 21. For example, the reading region selection unit 27 selects any one or more rows from the rows included in the structure corresponding to the two-dimensional matrix of the pixel array unit 21. The reading region selection unit 27 selects one or more rows sequentially according to a preset period. Furthermore, the reading region selection unit 27 can determine the selected region based on the request from each pixel 30 of the pixel array unit 21.

[0090] [Circuit Configuration Example for Pixels]

[0091] Figure 5 This is a circuit diagram showing an example of the circuit configuration of pixel 30. As described above, each of the plurality of pixels 30 includes a light receiving unit 31, a pixel signal generating unit 32, and an address event detection unit 33.

[0092] In the pixel 30 with the above configuration, the light receiving unit 31 includes a light receiving element (photoelectric conversion element) 311, a transistor 312, and a transistor 313. For example, N-type metal-oxide-semiconductor (MOS) transistors are used as transistors 312 and 313. Transistors 312 and 313 are connected in series with each other.

[0093] The light receiving element 311 is connected between the connection node N1 shared by transistors 312 and 313 and ground, and photoelectrically converts the incident light to generate a charge corresponding to the amount of incident light.

[0094] Transmit signal TRG from Figure 2 The driving unit 22 shown provides the gate electrode to the transistor 312. In response to the transmission signal TRG, the transistor 312 provides the charge converted by the light receiving element 311 to the pixel signal generating unit 32.

[0095] A control signal OFG is provided from the driving unit 22 to the gate electrode of the transistor 313. In response to the control signal OFG, the transistor 313 provides an electrical signal generated by the photoreceiving element 311 to the address event detection unit 33. The electrical signal provided to the address event detection unit 33 is a photocurrent including charge.

[0096] The pixel signal generation unit 32 includes a reset transistor 321, an amplification transistor 322, a selection transistor 323, and a floating diffusion layer 324. For example, an N-type MOS transistor can be used as the reset transistor 321, the amplification transistor 322, and the selection transistor 323.

[0097] The charge converted by the receiving element 311 is supplied from the light receiving unit 31 to the pixel signal generating unit 32 via the transistor 312. The charge supplied from the light receiving unit 31 is accumulated in the floating diffusion layer 324. The floating diffusion layer 324 generates a voltage signal having a voltage value corresponding to the amount of accumulated charge. That is, the floating diffusion layer 324 converts charge into voltage.

[0098] The reset transistor 321 is connected between the power supply line of the power supply voltage VDD and the floating diffusion layer 324. In response to the reset signal RST, the reset transistor 321 initializes (resets) the amount of charge in the floating diffusion layer 324.

[0099] Furthermore, the drive unit 22 provides a reset signal RST to the pixels 30 in a specific area according to the control signal of the signal processing unit 25. As a result, the pixel array unit 21 includes a first drive for providing the reset signal RST to the pixels 30 in the specific area and a second drive for periodically performing initialization (reset) of all pixels 30 under the control of the signal processing unit 25.

[0100] Amplifying transistor 322 and selecting transistor 323 are connected in series between the power supply line VDD and the vertical signal line VSL. Amplifying transistor 322 amplifies the voltage signal that has undergone charge-to-voltage conversion by the floating diffusion layer 324.

[0101] The selection signal SEL is provided from the driving unit 22 to the gate electrode of the selection transistor 323. In response to the selection signal SEL, the selection transistor 323 outputs the voltage signal amplified by the amplifying transistor 322 as a pixel signal SIG to the column processing unit 24 (see reference 24) via the vertical signal line VSL. Figure 2 ).

[0102] The driving unit 22 provides a reset signal RST to the pixel signal generation unit 32, which has been supplied with the selection signal SEL, after a predetermined time. As a result, by setting pixel 30 to its initial state, continuous selection of pixel 30, which has already been selected once, is suppressed.

[0103] In the imaging device 20, which includes a pixel array section 21 (in which pixels 30 having the above-described configuration are arranged in two dimensions), when passing through Figure 1When the control unit 13 shown in the figure gives the instruction to start detecting address events, the drive unit 22 provides the control signal OFG to the transistor 313 of the light receiving unit 31, thereby driving the transistor 313 to provide photocurrent to the address event detection unit 33.

[0104] Furthermore, when an address event is detected in a specific pixel 30, the driving unit 22 disconnects the transistor 313 of the pixel 30 and stops supplying photocurrent to the address event detection unit 33. Next, the driving unit 22 drives the transistor 312 by providing the transmission signal TRG to the transistor 312, and transfers the charge converted by the photoelectric receiving element 311 to the floating diffusion layer 324.

[0105] In this way, the imaging device 20, which includes a pixel array section 21 in which pixels 30 arranged in two dimensions with the above configuration, outputs only the pixel signals of the pixels 30 in which address events are detected to the column processing section 24. As a result, compared with the case of outputting the pixel signals of all pixels, the power consumption and image processing workload of the imaging device 20 can be reduced regardless of the presence or absence of address events.

[0106] Note that the configuration of pixel 30 shown here is an example and is not limited to this configuration example. For example, a pixel configuration without a pixel signal generation unit 32 is also possible. In the case of this pixel configuration, transistor 313 can be omitted in light receiving unit 31, and transistor 312 can have the function of transistor 313.

[0107] [Configuration Example of Address Event Detection Department]

[0108] Figure 6 This is a block diagram showing a configuration example of the address event detection unit 33. For example... Figure 6 As shown, the address event detection unit 33 according to this configuration example includes a current-to-voltage conversion unit 331, a buffer 332, a subtractor 333, a quantizer 334, an arithmetic circuit 335, a signal holding circuit 336, a transfer unit 337, and a control circuit 338.

[0109] The current-to-voltage converter 331 converts the photocurrent from the light receiving unit 31 of the pixel 30 into a logarithmic voltage signal. The current-to-voltage converter 331 provides the converted voltage signal to the buffer 332. The buffer 332 buffers the voltage signal supplied from the current-to-voltage converter 331 and supplies the buffered voltage signal to the subtractor 333.

[0110] A row drive signal is provided from the driver unit 22 to the subtractor 333. The subtractor 333 reduces the level of the voltage signal supplied from the buffer 332 according to the row drive signal. Then, the subtractor 333 provides the reduced voltage signal to the quantizer 334. The quantizer 334 quantizes the voltage signal provided from the subtractor 333 into a digital signal and outputs this digital signal as an address event detection signal to the arithmetic circuit 335. For example, the quantizer 334 sequentially supplies an on detection signal and an off detection signal to the arithmetic circuit 335.

[0111] The arithmetic circuit 335 performs logical operations based on the on and off detection signals sequentially supplied from the quantizer 334 and generates detection signals. For example, the arithmetic circuit 335 provides the value of the first signal provided among the on and off detection signals to the signal holding circuit 336. Then, when either the value of the next signal provided among the on and off detection signals or the value of the first provided signal held by the signal holding circuit 336 is true, the arithmetic circuit 335 provides a signal indicating the true value to the signal holding circuit 336; and when both are false, the arithmetic circuit 335 provides a signal indicating the false value to the signal holding circuit 336. As described above, when at least one of the on and off detection signals is true, the arithmetic circuit 335 outputs a detection signal indicating the true value, and when both are false, the arithmetic circuit 335 outputs a detection signal indicating the false value.

[0112] A signal holding circuit 336 is disposed between the arithmetic circuit 335 and the transfer unit 337, and accumulates the arithmetic result of the arithmetic circuit 335 based on the sampled signal supplied from the control circuit 338. The signal holding circuit 336 can be a sampling circuit such as a switch, plastic, or capacitor, or a digital memory circuit such as a latch or flip-flop. According to this embodiment, the signal holding circuit 336 has a so-called single latch configuration, wherein one signal holding circuit 336 is configured to both enable and disable the detection signal. Therefore, compared to a so-called dual latch configuration where a signal holding circuit 336 is configured for each of the enable and disable detection signals, the area of ​​the signal holding circuit 336 can be further reduced.

[0113] The transfer unit 337 transfers the address event detection signal provided by the quantizer 334 to the arbitrator unit 23, etc. When an address event is detected, the transfer unit 337 provides a request to the arbitrator unit 23 to request the transmission of the address event detection signal. Then, when a response to the request is received from the arbitrator unit 23, the transfer unit 337 provides the address event detection signal to the driver unit 22 and the signal processing unit 25.

[0114] Control circuit 338 will set a predetermined threshold voltage V th The inverting (-) input of comparator 3341 is provided. The threshold voltage V supplied to comparator 3341 from control circuit 338 is... th Different voltage values ​​are applied in a time-division manner. For example, control circuit 338 provides a threshold voltage V at different timings corresponding to the turn-on event indicating that the change in photocurrent exceeds an upper limit threshold. th1 The sum and the threshold voltage V corresponding to the disconnection event where the change amount is lower than the lower threshold are represented. th2 As a result, a comparator 3341 can generate an on detection signal and an off detection signal.

[0115] Figure 7 This is a diagram showing voltage fluctuations based on the accumulated charge in the photoreceiving element 311. The horizontal axis represents time, and the vertical axis represents voltage. Line L12 represents the lower threshold of the address event detection unit 33, while line L14 represents the voltage change based on the accumulated charge after reset. Line L16 represents the automatic zero potential of the ADC 241 when the accumulated charge remains constant. Line L18 represents the upper threshold of the address event detection unit 33.

[0116] like Figure 7 As shown, the charge accumulated in the light-receiving element 311 after reset decreases over time. Therefore, the difference between the upper threshold L16 and the potential L14 after reset increases from d10 to d12 over time. As a result, there is a variation in the amount of light received by the light-receiving element 311, and even if the upper threshold is initially exceeded, the amount of light does not exceed the upper threshold. Alternatively, even if a charge exceeding the lower threshold accumulates in the light-receiving element 311, there is a possibility that the charge will not exceed the lower threshold.

[0117] Figure 8 This is a diagram illustrating an example of a row with a low frequency of becoming a valid pixel. Even if such a row is selected, the accumulated charge is not read if a second drive as a full pixel reset is not performed during a period of several frames.

[0118] Figure 9 This is a diagram showing an example of a circuit configuration according to this embodiment. The OR circuit O22 is disposed between the driving unit 22 and the signal processing unit 25. As described above, the signal processing unit 25 counts detection signals for each pixel 30 and can determine the existence of rows of pixels 30 that have not output detection signals. Therefore, in this embodiment, in addition to the control signal from the control unit 13 (see...),... Figure 1 In addition, the accumulated charge of the light receiving element 311 is reset by the control signal from the signal processing unit 25.

[0119] Figure 10This is a diagram illustrating a first control example according to this embodiment. The horizontal axis represents time. The EVS synchronization signal S10 on the other vertical axis is a control signal from the control unit 13 (see reference). Figure 1 And it is the start signal for each frame. The EVS control status indicator indicates the control status based on the control signal from the control unit 13 (see reference). Figure 1 The access row indicates the access status of pixel 30. "All rows" means all pixels 30, and "part" means some pixels out of all pixels 30.

[0120] The detection period S12 is the period during which the light receiving element 311 accumulates data. During this period, pixels 30 in all rows are accumulated. The reset period S14 is for the floating diffusion layer 324 (see...). Figure 5 The period during which the charge of pixels 30 in all rows is initialized. During this period, pixel 30 in all rows is accumulated.

[0121] The data reading period S16 is the period during which the brightness signal is read from the pixel 30 that has already output the detection signal. Line RD is the start period for reading each row. As described above, the brightness signal of each row is read at the timing indicated by line RD, the brightness signal of the pixel 30 that outputs the detection signal is read, and the pixel 30 is initialized.

[0122] On the other hand, the reset period S18 is a period determined by the signal processing unit 25 during which rows of pixels 30 with low output frequencies where detection signals exist are reset. The reset period S18 can be for a single row or multiple rows.

[0123] The signal processing unit 25 counts the output frequency of the detection signal for each frame and initializes the rows at a low detection frequency during the reset period S18. As described above, by initializing the rows at a low detection frequency during the reset period S18, the occurrence of pixels 30 with reduced accumulated charge can be suppressed.

[0124] Figure 11 This is a diagram illustrating a second control example according to this embodiment. The horizontal axis represents time. The EVS synchronization signal S10 on the other vertical axis is a control signal from the control unit 13 (see reference). Figure 1 And it is the start signal for each frame. The EVS control status indicator indicates the control status based on the control signal from the control unit 13 (see reference). Figure 1 The access row indicates the access status of pixel 30. "All rows" means all pixels 30, and "part" means some pixels out of all pixels 30.

[0125] Figure 11The second control instance differs from the first control instance in that it periodically repeats the time period S14 in which all pixels 30 are reset. As described above, by cyclically repeating the time period S14 in which all pixels 30 are reset, the occurrence of pixels 30 with reduced accumulated charge can be further suppressed.

[0126] Figure 12 This is a diagram illustrating a third control example according to this embodiment. The horizontal axis represents time. The EVS synchronization signal S10 on the other vertical axis is a control signal from the control unit 13 (see reference). Figure 1 And it is the start signal for each frame. The EVS control status indicator indicates the control status based on the control signal from the control unit 13 (see reference). Figure 1 The access row indicates the access status of pixel 30. "All rows" means all pixels 30, and "part" means some pixels among all pixels 30. The data reading period S16 is not shown.

[0127] exist Figure 12 In the third control instance, the reset period S20 differs from that in the first control instance in that the rows to be reset change sequentially in each frame. The reset period S20 can be used for a single row or multiple rows.

[0128] As described above, by using the set time period S20 cycle for resetting pixel 30 and changing the reset row sequentially, the occurrence of pixel 30 with reduced accumulated charge can be uniformly suppressed.

[0129] Figure 13 This is a diagram illustrating a fourth control example according to this embodiment. The horizontal axis represents time. The EVS synchronization signal S10 on the other vertical axis is a control signal from the control unit 13 (see reference). Figure 1 And it is the start signal for each frame. The EVS control status indicator indicates the control status based on the control signal from the control unit 13 (see reference). Figure 1 The access row indicates the access status of pixel 30. "All rows" means all pixels 30, and "part" means some pixels among all pixels 30. The data reading period S16 is not shown.

[0130] exist Figure 13 In the fourth control example, the reset period S22 differs from the third control example in that the order of the rows to be reset is randomly changed in each frame. The reset period S22 can be used for a single row or multiple rows. As described above, by using the set period S22 cycle for resetting pixels 30, the reset rows are randomly changed, which can uniformly suppress the occurrence of pixels 30 with reduced accumulated charge and suppress the periodicity of the reset stripes in each row.

[0131] Figure 14 This is a diagram illustrating an example of a data structure according to this embodiment. For example... Figure 14As shown, the signal processing unit 25 (see...) Figure 2 This diagram illustrates an example of a frame configuration for sending event data of a frame to the recording unit 12. As described above, the event data of a frame is stored in multiple long data packets arranged in a row between the start of frame (FS) and the end of frame (FE). The start of frame (FS) is a short data packet indicating the start of the frame, and the end of frame (FE) is a short data packet indicating the end of the frame. Furthermore, in Figure 14 In the example shown, a long data packet storing embedded data is placed in the header of a long data packet that stores event data.

[0132] It should be noted that, according to this embodiment, the signal processing unit 25 corresponds to the output unit.

[0133] Long data packets have a header (PH) and a trailer (PF). The header (PH) contains a data type (DT) indicating the type of data stored in the long data packet, and the data type (DT) can distinguish which of the following is stored: embedded data (EBD), preliminary data (LH), or pixel data (DATA). Note that in addition to being placed in the header (PH), the data type (DT) can also be placed in the header of the area used to store data within the long data packet. Figure 14 As shown, the data indicating the position of the reset row is stored in the embedded data EBD.

[0134] Figure 15 It is shown Figure 14 The image shows a row of data in an example of the data format. For example... Figure 15 As shown, the data indicating the position of the reset row can be stored in the initial data LH.

[0135] Figure 16 These are schematic diagrams illustrating an example of processing in an image processing apparatus in a subsequent stage. Figure (a) schematically illustrates a row where data is lost during initialization. As mentioned above, there are cases where the information captured in the image is reduced compared to other rows during initialization. Figure (b) illustrates an example of performing interpolation processing using a data signal for the reset row included in a data structure. As shown in Figure (b), the data structure can determine whether the loss of information in the reset row is due to initialization or whether no information was present from the beginning. As a result, the data structure determines whether information is lost due to initialization, and interpolation becomes possible.

[0136] As described above, according to this embodiment, in addition to the second drive that periodically initializes all light receiving units 31 by the drive unit 22, a first drive is also included for resetting the accumulated charge in a portion of all light receiving units 31. As a result, it is possible to suppress the decrease in potential based on the accumulated charge from the moment the second drive is reset.

[0137] (Second Implementation)

[0138] The imaging device 20 according to the first embodiment is a scanning type, while the imaging device 20 according to the second embodiment is an arbitrator type. The differences between the imaging device 20 and the imaging device 20 according to the first embodiment will be described below.

[0139] Figure 17 This is a diagram illustrating a configuration example of the imaging device 20 according to the second embodiment. For example... Figure 17 As shown, the imaging device 20, which is a second configuration example of the imaging device of this disclosure, is an asynchronous imaging device called EVS, and includes a pixel array unit 21, a driving unit 22, an arbitrator unit (arbitration unit) 23, a column processing unit 24, and a signal processing unit 25.

[0140] In the imaging device 20 with the above configuration, a plurality of pixels 30 are arranged in a matrix (array) in a two-dimensional manner in the pixel array section 21. For each pixel column of the matrix-arranged pixel array, a vertical signal line VSL (vertical signal 1in) is wired.

[0141] Each of the plurality of pixels 30 generates an analog signal corresponding to the voltage of the photocurrent as a pixel signal. Furthermore, each of the plurality of pixels 30 detects the presence or absence of an address event based on whether the change in photocurrent exceeds a predetermined threshold. Then, when an address event occurs, pixel 30 outputs a request to arbitrator unit 23.

[0142] The driving unit 22 drives each of the plurality of pixels 30 to output the pixel signal generated in each pixel 30 to the column processing unit 24.

[0143] Arbitrator unit 23 arbitrates requests from each of the plurality of pixels 30 and transmits a response based on the arbitration result to the corresponding pixel 30. Pixel 30 that has received a response from arbitrator unit 23 provides a detection signal (an address event detection signal) indicating the detection result to driver unit 22 and signal processing unit 25. Reading the detection signal from pixel 30 can be performed by reading multiple rows.

[0144] The column processing unit 24 includes, for example, an analog-to-digital converter, and performs processing for each pixel column of the pixel array unit 21 to convert the analog pixel signal output from the pixel 30 of that column into a digital signal. Then, the column processing unit 24 provides the digital signal after analog-to-digital conversion to the signal processing unit 25.

[0145] The signal processing unit 25 performs predetermined signal processing on the digital signal provided by the slave processing unit 24, such as correlated double sampling (CDS) processing or image recognition processing. Then, the signal processing unit 25 provides data representing the processing result and the detection signal provided from the arbitrator unit 23 to the recording unit 12 (see signal line 14) via the signal line 14. Figure 1 ).

[0146] The signal processing unit 25 counts the detection signals of each pixel 30 and outputs a control signal to the driving unit 22 to reset pixels 30 that have a small number of detection signals. As a result, the driving unit 22 resets pixels 30 that have a small number of detection signals.

[0147] Figure 18 This is a diagram illustrating a control example according to the second embodiment. The horizontal axis represents time, and the EVS reset synchronization signal tr on the other vertical axis is a synchronization control signal from the control unit 13 (see reference). Figure 1 Based on the EVS reset synchronization signal tr, the signal processing unit 25 outputs a reset control signal sr to the driving unit 22. The reset control signal sr includes a reset address, which is the address of the pixel 30 to be reset. As a result, the driving unit 22 can perform a first drive to reset pixels 30 in which the number of detected signal outputs is small.

[0148] Data reading is performed during the period when optical pixel signals are read through arbitration by the arbitrator unit 23, separate from the reset via the reset control signal sr. Note that the second drive, which resets all pixels 30, is executed at the start of the drive.

[0149] As described above, according to this embodiment, in addition to the second drive that periodically initializes all light receiving units 31 by the driving unit 22, a first drive for resetting the pixels 30 with a small amount of detection signal output is also included. As a result, the decrease in potential based on accumulated charge from the moment the second drive is reset can be suppressed.

[0150] (Third implementation method)

[0151] The imaging device 20 according to the third embodiment differs from the imaging device 20 according to the first embodiment in that the pixel block 30a includes a plurality of grayscale pixels (gradation pixels) 308a and EVS pixels 308b. The differences from the imaging device 20 according to the first embodiment will be described below.

[0152] Figure 19 This is a block diagram illustrating a configuration example of the imaging device 20 according to the third embodiment. (As shown) Figure 19As shown, the imaging device 20 according to this disclosure is a device capable of performing asynchronous imaging, known as EVS, and synchronous imaging for grayscale images in parallel. The imaging device 20 includes a pixel array unit 21, a first access control circuit 211a, a second access control circuit 211b, an AD converter 212a, an EVS readout circuit 212b, a first signal processing unit 213, a second signal processing unit 214, a timestamp generation circuit 215, a timing control circuit 216, and output interfaces 217 and 218.

[0153] For example, grayscale pixels 308a all include Figure 5 The pixel 30 shown includes a light-receiving element (photoelectric conversion element) 311 and a pixel signal generation unit 32. For example, the light-receiving element (photoelectric conversion element) 311 is directly connected to the floating diffusion layer 324. For example, the EVS pixel 308b has a light-receiving element (photoelectric conversion element) 311 and a pixel signal generation unit 32. Figure 5 The configuration of pixel 30 shown is quite similar.

[0154] Here, refer to Figure 20 This describes the configuration of pixel block 30a. Figure 20 This is a schematic diagram illustrating the configuration of pixel block 30a. For example... Figure 20 As shown, pixel block 30a includes a plurality of grayscale pixels 308a, EVS pixels 308b, and an EVS analog front-end (AFE) 314. In pixel block 30a, the plurality of grayscale pixels 308a and EVS pixels 308b are arranged in a matrix. For this pixel array, a first vertical signal line is routed for each pixel column of the grayscale pixels 308a. Furthermore, a second vertical signal line, independent of the first vertical signal line, is routed for each pixel column of the EVS pixels 308b. Each of the plurality of grayscale pixels 308a generates an analog signal corresponding to a voltage of photocurrent as a grayscale brightness signal and outputs this signal to an AD converter 212a (see...). Figure 19 ).

[0155] On the other hand, the EVS pixel 308b outputs an analog signal of the voltage corresponding to the photocurrent to the EVS AFE 314. Furthermore, the EVS pixel 308b generates an analog signal of the voltage corresponding to the photocurrent as the EVS brightness signal, and outputs this signal to the EVS readout circuit 212b (see reference) in the event of an address event. Figure 19 ).

[0156] The EVS analog front-end (AFE) 314 generates a detection signal from the voltage signal output based on the EVS pixel 308b, and outputs the detection signal to the second signal processing unit 214 (see reference). Figure 19More specifically, the EVS AFE 314 detects the presence or absence of an address event based on whether the change in photocurrent in the EVS pixel 308b exceeds a predetermined threshold. Then, the EVS AFE 314 outputs the detection signal to the second signal processing unit 214. For example, the EVS AFE 314 outputs the address information (X, Y), timestamp information T, address event information VCH, and VCL of the detected valid pixel as event information (X, Y, T, VCH, VCL) to the second signal processing unit 214. Multiple grayscale pixels 308a, EVS pixels 308b, and the EVS AFE 314 can operate in parallel through an independent control system.

[0157] Return again Figure 19 The first access control circuit 211a controls multiple grayscale pixels 308a. Specifically, the first access control circuit 211a controls the generation and output of grayscale brightness signals corresponding to the accumulated amount of photoelectric conversion current. For example, the first access control circuit 211a causes the AD converter 212a to sequentially output the photoelectric conversion current accumulated in each of the multiple grayscale pixels 308a as the grayscale brightness signal for each row.

[0158] The second access control circuit 211b controls a plurality of EVS AFEs 314. According to this embodiment, the second access control circuit 211b causes the plurality of EVS AFEs 314 to sequentially detect address events in each row, and sequentially outputs the detection signals to the second signal processing unit 214 for each row. Furthermore, the second access control circuit 211b sequentially outputs the brightness signals of the EVS pixels 308b in which address events have been detected to the EVS readout circuit 212b for each row. Additionally, the second access control circuit 211b executes either a first drive to refresh a portion of all EVS pixels 308b or a second drive to refresh all EVS pixels 308b according to the second signal processing unit 214. Note that the second access control circuit 211b according to this embodiment corresponds to the drive unit.

[0159] The AD converter 212a includes an ADC for each of the pixel blocks 30a and 30b arranged for each column of grayscale pixels 308a. The ADC converts the analog grayscale brightness signal provided via a first vertical signal line into a digital signal. The ADC of the AD converter 212a provides the generated digital signal to the first signal processing unit 213.

[0160] EVS readout circuit 212b includes an ADC for each column of EVS pixels 308b arranged for each of pixel blocks 30a and 30b. The ADC converts the analog EVS luminance signal provided via vertical signal line VSL2 into a digital signal. The ADC of EVS readout circuit 212b provides the generated digital signal to second signal processing unit 214.

[0161] Again Figure 19 As shown, the first signal processing unit 213 performs predetermined signal processing on the digital signal from the AD converter 212a, such as correlated double sampling (CDS) processing and image recognition processing. The signal processing unit 212 provides data representing the processing result and a detection signal to the recording unit 12 (see reference 209) via signal line 209. Figure 1 ).

[0162] The second signal processing unit 214 performs predetermined signal processing on the detection signals from the plurality of EVS AFEs 314. The second signal processing unit 214 generates an EVS image using the detection signals, for example, arranged in a two-dimensional grid pattern as pixel signals. In addition, the second signal processing unit 214 causes the second access control circuit 211b to initialize (refresh) the predetermined EVS pixel 308b synchronously with the control signals of the first access control circuit 211a.

[0163] The timestamp generation circuit 215 generates timestamp information T and provides the timestamp information T to each configuration of the solid-state imaging element 200. For example, the timestamp generation circuit 215 provides the timestamp information T to multiple EVS AFEs 314s.

[0164] Timing control circuit 216 controls the timing of each configuration of solid-state imaging element 200. For example, timing control circuit 216 controls the timing of first access control circuit 211a and second access control circuit 211b.

[0165] Output interface 217 outputs image data, etc., provided by the first signal processing unit 213 to the recording unit 12. Similarly, output interface 218 outputs image data, etc., provided by the second signal processing unit 214 to the recording unit 12.

[0166] Figure 21 This is a schematic diagram illustrating the signal flow between the first access control circuit 211a, the second access control circuit 211b, and the second signal processing unit 214. The OR circuit O22 is connected between the second signal processing unit 214 and the second access control circuit 211b. As a result, the second access control circuit 211b executes a second drive to refresh all EVS pixels 308b based on control signals from the control unit 13, and executes a first drive to refresh a portion of all EVS pixels 308b based on control signals from the second signal processing unit 214.

[0167] The row selection signal SEL_SH / RD is used to select grayscale pixels 308a for each row, the transmission signal TRG_SH / RD is used to transmit light from the light receiving unit of grayscale pixel 308a to the floating diffusion layer, and the reset signal RST_SH / RD is used to reset the floating diffusion layer of grayscale pixel 308a. Each signal includes row information or address information of grayscale pixel 308a.

[0168] The second signal processing unit 214 references the row selection signal SEL_SH / RD, the transmission signal TRG_SH / RD, and the reset signal RST_SH / RD, and outputs a control signal including information about the row of the EVS pixel 308b to be reset to the second access control circuit 211b. As a result, as described above, the second access control circuit 211b performs a first drive to refresh a portion of all EVS pixels 308b.

[0169] Figure 22 This is a diagram illustrating a fifth control example according to the third embodiment. The horizontal axis represents time, and the EVS frame synchronization signal S10 on the other vertical axis comes from the control unit 13 (see...). Figure 1 The control signal is also the start signal for each frame in EVS pixel 308b. The EVS control status indicator indicates the control status based on the control signal from the control unit 13 (see reference). Figure 1 The grayscale frame synchronization signal S30 is a control signal from the control unit 13 (see reference). Figure 1 ), and is the start signal for each frame in grayscale pixel 308a. The access row address indicates the row of pixel array section 21.

[0170] The detection period S12 is the period during which EVS pixels 308b are accumulated. During this period, the accumulation of EVS pixels 308b in all rows is performed. The reset period S14 is the period during which the charge of EVS pixels 308b is initialized. During this period, the EVS pixels 308b in each row of the pixel array 21 are initialized sequentially.

[0171] During data reading, S16 is the period in which the luminance signal is read from the pixel 30 of the output detection signal. Line RD is the start time of reading each line. As described above, the luminance signal of each line is read at the timing indicated by line RD, the luminance signal of the pixel 30 of the output detection signal is read, and the pixel 30 is initialized.

[0172] The SH line indicates the timing of initializing grayscale pixel 308a, while the RD line indicates the timing of reading the light detection signal from grayscale pixel 308a. That is, grayscale pixel 308a is initialized for each row, and the light detection signal is read.

[0173] As described above, the signal processing unit 25 initializes the EVS pixels 308b in each row S26 of the pixel array unit 21 in time with the timing of the line SH. As described above, by initializing the EVS pixels 308b in each row S26 of the pixel array unit 21 in time with the timing of the line SH, the generation of EVS pixels 308b that have decreased due to accumulated charge can be suppressed.

[0174] Figure 23 This is a diagram illustrating a sixth control example according to the third embodiment. The horizontal axis represents time, and the EVS frame synchronization signal S10 on the other vertical axis comes from the control unit 13 (see...). Figure 1 The grayscale frame synchronization signal S34 is a control signal from the control unit 13 (see reference 13). It is also the start signal for each frame in the EVS pixel 308b. Figure 1 ), and is the start signal for each frame in grayscale pixel 308a. The access row address indicates the row of pixel array section 21 (see reference ). Figure 19 ).

[0175] The signal processing unit 25 initializes the EVS pixels 308b in each row S26 of the pixel array unit 21 according to the timing of the lines SH and RD. As described above, by initializing the EVS pixels 308b in each row S26 of the pixel array unit 21 in sync with the timing of the lines SH and RD, the generation of EVS pixels 308b with reduced accumulated charge can be further suppressed.

[0176] Figure 24 This is a diagram illustrating a seventh control example according to the third embodiment. The horizontal axis represents time, and the EVS frame synchronization signal S10 on the vertical axis comes from the control unit 13 (see reference 13). Figure 1 The grayscale frame synchronization signal S34 is a control signal from the control unit 13 (see reference 13). It is also the start signal for each frame in the EVS pixel 308b. Figure 1 ), and is the start signal for each frame in grayscale pixel 308a. The access row address indicates the row of pixel array section 21 (see reference ). Figure 19 ).

[0177] The signal processing unit 25 initializes the EVS pixels 308b in each row S26 of the pixel array unit 21 according to the timing of the line RD. As described above, by initializing the EVS pixels 308b in each row S26 of the pixel array unit 21 in sync with the timing of the line RD, the generation of EVS pixels 308b that have decreased due to accumulated charge can be suppressed.

[0178] Figure 25 This is a diagram illustrating the eighth control example according to the third embodiment. The horizontal axis represents time, and the EVS frame synchronization signal S10 on the other vertical axis comes from the control unit 13 (see...). Figure 1The control signal is also the start signal for each frame in EVS pixel 308b. The EVS control state indicates the control state based on the control signal from the control unit 13 (see reference). Figure 1 Grayscale pixel 308a is controlled by a so-called global shutter method. That is, the eighth control instance differs from the seventh control instance according to the third embodiment in that the luminance signals of all pixels are transmitted via line transmission, and the luminance signals of all pixels are reset via line SH.

[0179] As described above, in the global shutter method, by initializing the EVS pixels 308b in each row S26 of the pixel array section 21 in time synchronization with the line RD, the generation of EVS pixels 308b with reduced accumulated charge can be suppressed.

[0180] Figure 26 This is a diagram illustrating the ninth control example according to the third embodiment. The horizontal axis represents time, and the EVS frame synchronization signal S10 on the other vertical axis comes from the control unit 13 (see reference). Figure 1 The control signal is also the start signal for each frame in EVS pixel 308b. The EVS control state indicates the control state based on the control signal from the control unit 13 (see reference). Figure 1 As described above, the EVS pixels 308b in each row S36 of the pixel array section 21 are initialized synchronously with the timing of lines SH and RD. Furthermore, the EVS pixels 308b in multiple rows are initialized sequentially for each frame. During the time period S38, the EVS pixels 308b of all pixels are initialized. As a result, the generation of EVS pixels 308b with reduced accumulated charge can be further suppressed.

[0181] It should be noted that this technology can have the following configurations.

[0182] (1) An imaging device, comprising: The pixel array section has a plurality of first pixels arranged in a matrix to output a brightness signal corresponding to the amount of light. The detection circuit section outputs a detection signal indicating the occurrence of an address event when the brightness signal of each of the plurality of first pixels exceeds a predetermined threshold; and The driving unit includes a first drive that resets the accumulated charge in a portion of a plurality of first pixels.

[0183] (2) According to the imaging device of (1), wherein the first drive is performed for each row.

[0184] (3) The imaging device according to (1), wherein the first drive is performed for each plurality of rows.

[0185] (4) The imaging device according to (1) further includes a signal processing unit, which determines the range of execution of the first drive based on the number of times the detected signal occurs within a predetermined time, wherein

[0186] The drive unit executes the first drive based on the determination made by the signal processing unit.

[0187] (5) The imaging device according to (4), wherein the pixel array performs imaging in units of different frames, and

[0188] The signal processing unit determines the scope of the first drive based on the number of times the detection signal appears in a single frame.

[0189] (6) The imaging device according to (4), wherein the pixel array performs imaging in units of different frames, and

[0190] The signal processing unit determines the scope of the first drive based on the number of times the detection signal appears in multiple frames.

[0191] (7) The imaging device according to (1), wherein the driving unit outputs the brightness signal corresponding to the light amount from the first pixel of the output detection signal in rows.

[0192] (8) The imaging device according to (1), wherein the device further includes an arbitration unit that arbitrates the detection signal and outputs a brightness signal corresponding to the light amount from the first pixel to the driving unit.

[0193] (9) The imaging device according to (1) further includes: The output section generates a data type signal, which includes information indicating that the first pixel has been driven.

[0194] (10) The imaging device according to (9), wherein the output unit generates a signal, the signal including information indicating the first pixel in at least one of the line header of the data packet and the embedded data.

[0195] (11) The imaging device according to (1), wherein the driving unit further includes a second drive that resets all of the plurality of first pixels.

[0196] (12) The imaging device according to (2), wherein the driving unit performs a first drive for each randomly selected row.

[0197] (13) The imaging device according to (1), wherein the pixel array further includes a plurality of second pixels for grayscale arranged in a matrix, and

[0198] It can generate grayscale images based on the output signals of multiple second pixels.

[0199] (14) The imaging device according to (13), wherein the driving unit performs a first drive based on a control signal when performing control on the second pixel.

[0200] (15) The imaging device according to (13), wherein the driving unit performs a first drive based on a control signal when initializing or reading the second pixel.

[0201] (16) The imaging device according to (13), wherein the driving unit performs a first drive on the first pixel in the row in which the second pixel is initialized or in the row in which reading is performed.

[0202] (17) The imaging device according to (13) wherein the driving unit performs a first drive on a first pixel in at least one of a row in which a second pixel is initialized and a row in which reading is performed, and on a first pixel in another row that is different from the row in which a second pixel is initialized and the row in which reading is performed.

[0203] (18) The imaging device according to (17) further includes a second driving unit for driving a plurality of second pixels, wherein

[0204] For each row, the accumulated charge is read from multiple second pixels.

[0205] (19) The imaging device according to (17) further includes a second driving unit that drives a plurality of second pixels, wherein

[0206] Accumulated charge is read from multiple second pixels for all rows.

[0207] (20) An imaging method, comprising: The detection step involves outputting a detection signal indicating the occurrence of an address event when the luminance signal of each of the plurality of first pixels that outputs a luminance signal corresponding to the light intensity exceeds a predetermined threshold; and The driving circuit step performs a first drive to reset the accumulated charge of the first pixel in a portion of the plurality of first pixels.

[0208] This disclosure is not limited to the various embodiments described above, but includes various modifications that can be conceived by those skilled in the art, and the effects of this disclosure are not limited to the above-described contents. In other words, various additions, modifications, and partial deletions can be made without departing from the conceptual idea and spirit of this disclosure as defined in the claims and their equivalents.

[0209] Reference Symbol List

[0210] 20 Imaging devices

[0211] 21-pixel array

[0212] 22 Drive Unit

[0213] 23 Arbitration Department

[0214] 24-unit processing unit

[0215] 25. Signal Processing Department

[0216] 33 Address Event Detection Department

[0217] 311 Optical receiving element

[0218] 211a First Access Control Circuit

[0219] 211b Second Access Control Circuit

[0220] 214 Second Signal Processing Unit.

Claims

1. An imaging device, comprising: A pixel array section, wherein a plurality of first pixels are arranged in a matrix to output a brightness signal corresponding to the amount of light; The detection circuit outputs a detection signal indicating the occurrence of an address event when the brightness signal of each of the plurality of first pixels exceeds a predetermined threshold. as well as The driving unit includes a first drive that resets the accumulated charge in a portion of the first pixels among a plurality of first pixels.

2. The imaging device according to claim 1, wherein, Execute the first driver for each line.

3. The imaging device according to claim 1, wherein, The first driver is executed for each set of multiple rows.

4. The imaging device according to claim 1, further comprising: The signal processing unit determines the range for executing the first drive based on the number of occurrences of the detection signal within a predetermined time period, wherein... The driving unit executes the first drive according to the determination of the signal processing unit.

5. The imaging device according to claim 4, wherein, The pixel array performs imaging in units of different frames, and The signal processing unit determines the scope of executing the first drive based on the number of times the detection signal appears in a single frame.

6. The imaging device according to claim 4, wherein, The pixel array performs imaging in units of different frames, and The signal processing unit determines the scope of executing the first drive based on the number of times the detection signal appears in multiple frames.

7. The imaging device according to claim 1, wherein, The driving unit outputs the brightness signal corresponding to the light amount from the first pixel of the output detection signal in rows.

8. The imaging device according to claim 1, further comprising: The arbitration unit arbitrates the detection signal and outputs a brightness signal corresponding to the light amount from the first pixel to the driving unit.

9. The imaging device according to claim 1, further comprising: The output unit generates a data type signal, which includes information indicating that the first pixel has been driven by the first driver.

10. The imaging device according to claim 9, wherein, The output unit generates a signal that includes information indicating the first pixel in at least one of the line header and embedded data of the data packet.

11. The imaging device according to claim 1, wherein, The driving unit further includes a second driver that resets all of the plurality of first pixels.

12. The imaging device according to claim 2, wherein, The driving unit executes the first driving for each randomly selected row.

13. The imaging device according to claim 1, wherein, The pixel array further includes a plurality of second pixels for grayscale arranged in a matrix, and It can generate grayscale images based on the output signals of multiple second pixels.

14. The imaging device according to claim 13, wherein, The driving unit executes the first driving based on the control signal when controlling the second pixel.

15. The imaging device according to claim 13, wherein, The driving unit executes the first driving based on the control signal when initializing or reading the second pixel.

16. The imaging device according to claim 13, wherein, The driving unit executes the first driving on the first pixel in the row where the second pixel is initialized or in the row where reading is performed.

17. The imaging device according to claim 13, wherein, The driving unit performs the first driving on a first pixel in at least one of the rows in which the second pixel is initialized and the rows in which reading is performed, and on a first pixel in another row that is different from the rows in which the second pixel is initialized and the rows in which reading is performed.

18. The imaging apparatus according to claim 17, further comprising: The second driving unit drives a plurality of the second pixels, wherein... For each row, the accumulated charge is read from multiple second pixels.

19. The imaging apparatus according to claim 17, further comprising: The second driving unit drives the plurality of second pixels, wherein... Accumulated charge is read from the plurality of second pixels for all rows.

20. An imaging method, comprising: The detection step involves outputting a detection signal indicating the occurrence of an address event when the brightness signal of each of the plurality of first pixels that outputs a brightness signal corresponding to the light amount exceeds a predetermined threshold. as well as The driving circuit step involves performing a first drive to reset the accumulated charge of the first pixel in a portion of the plurality of first pixels.

Images