Display panel and display device

Abstract

A display panel comprises a display area and a non-display area located around the display area, the non-display area comprises a lead-out area located at one side of the display area; the display panel comprises: a substrate; a power line located on the substrate, the power line comprises a first sub-line located in the lead-out area; the first sub-line comprises a first conductive pattern and a second conductive pattern which are sequentially stacked in a direction away from the substrate; the orthographic projection of the second conductive pattern on the substrate at least partially overlaps with the orthographic projection of the first conductive pattern on the substrate, and the first conductive pattern is electrically connected with the second conductive pattern; a first protective layer located on the side of the first sub-line away from the substrate; the first protective layer covers at least part of the side surface of the second conductive pattern of the first sub-line.

Description

Display panel and display device TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, and in particular, to a display panel and a display device. BACKGROUND

[0002] Organic Light Emitting Diode (OLED) display technology is a technology that uses light-emitting materials to emit light under the drive of current to realize display. OLED display has the advantages of ultra-light, ultra-thin, high brightness, large viewing angle, low voltage, low power consumption, fast response, high definition, shock resistance, bendable, low cost, simple process, less use of raw materials, high luminous efficiency, and wide temperature range.

[0003] SUMMARY

[0004] In one aspect, a display panel is provided. The display panel comprises: a substrate; a power line on the substrate, the power line comprising a first sub-line in the lead-out area; the first sub-line comprising a first conductive pattern and a second conductive pattern stacked in sequence in a direction away from the substrate; a projection of the second conductive pattern on the substrate at least partially overlaps with a projection of the first conductive pattern on the substrate, and the first conductive pattern and the second conductive pattern are electrically connected; a first protective layer on a side of the first sub-line away from the substrate; the first protective layer covers at least part of a side surface of the second conductive pattern of the first sub-line.

[0005] In some embodiments, the display panel further comprises: a first source-drain metal layer and a second source-drain metal layer stacked in sequence in a direction away from the substrate; the first conductive pattern is located in the first source-drain metal layer, and the second conductive pattern is located in the second source-drain metal layer.

[0006] In some embodiments, the display panel further comprises: a blocking dam located in the non-display area and surrounding the display area; part of the first sub-line is covered by the blocking dam; a side surface of a part of the second conductive pattern of the first sub-line that is not covered by the blocking dam is covered by the first protective layer.

[0007] In some embodiments, the material of the first protective layer comprises an inorganic material.

[0008] In some embodiments, the display panel further comprises: a first passivation layer on a side of the second source-drain metal layer away from the substrate; the first protective layer is located in the first passivation layer.

[0009] In some embodiments, the blocking dam comprises a first blocking layer; the first protective layer and the first blocking layer are of the same material and are arranged in the same layer.

[0010] In some embodiments, the display panel further comprises: a first planar layer between the first source-drain metal layer and the second source-drain metal layer; a second planar layer on a side of the second source-drain metal layer away from the substrate; the first protective layer and the first barrier layer of the barrier dam are on the second planar layer.

[0011] In some embodiments, the second planar layer has a thickness smaller than that of the first planar layer.

[0012] In some embodiments, the first conductive pattern is in direct contact with and electrically connected to the second conductive pattern.

[0013] In some embodiments, an edge portion of the second conductive pattern covers a side surface of the first conductive pattern.

[0014] In some embodiments, the display panel further comprises: a second protective layer between the first conductive pattern and the second conductive pattern, the second protective layer covering a side surface of a portion of the first conductive pattern not covered by the barrier dam.

[0015] In some embodiments, the display panel further comprises: a second passivation layer between the first source-drain metal layer and the second source-drain metal layer; the second protective layer is on the second passivation layer.

[0016] In some embodiments, the second protective layer is provided with at least one first through hole, and the second conductive pattern is electrically connected to the first conductive pattern through the at least one first through hole.

[0017] In some embodiments, the second protective layer has a groove exposing a surface of the first conductive pattern away from the substrate.

[0018] In some embodiments, a region of the second conductive pattern covered by the barrier dam is provided with at least one second through hole.

[0019] In some embodiments, the power supply line is a VSS line; the first sub-line comprises a first sub-portion and a second sub-portion connected to each other, the first sub-portion extends in a first direction, and the second sub-portion extends in a second direction; the first direction is the arrangement direction of the display area and the lead-out area, and the first direction and the second direction intersect; the second sub-portion is closer to the display area than the first sub-portion, and a portion of the second sub-portion is covered by the barrier dam; the first protective layer covers side surfaces of opposite sides of the first sub-portion in the second direction and side surfaces of a portion of the second sub-portion not covered by the barrier dam.

[0020] In some embodiments, an area of at least one of the first conductive pattern and the second conductive pattern is greater than or equal to 4x10 6 μm 2 .

[0021] In some embodiments, the power line is a VDD line; the first sub-line includes a third sub-portion and a fourth sub-portion connected in series, the third sub-portion extends in a first direction, and the fourth sub-portion extends in a second direction; the first direction is a direction in which the display area and the lead-out area are arranged, and the first direction and the second direction intersect; the fourth sub-portion is closer to the display area than the third sub-portion, and part of the third sub-portion is covered by the barrier dam; the first protective layer covers side surfaces of the fourth sub-portion on opposite sides in the first direction and side surfaces of the third sub-portion that are not covered by the barrier dam.

[0022] In some embodiments, an area of at least one of the first conductive pattern and the second conductive pattern is greater than or equal to 8x10 6 μm 2 .

[0023] In another aspect, a display device is provided, including: the display panel described in the above embodiments; and a circuit board electrically connected to the display panel. BRIEF DESCRIPTION OF DRAWINGS

[0024] In order to more clearly illustrate the technical solutions in the present disclosure, the following will briefly introduce the drawings needed to be used in some embodiments of the present disclosure. Obviously, the drawings described in the following description are only some drawings of some embodiments of the present disclosure, and other drawings can also be obtained by those skilled in the art according to these drawings. In addition, the drawings described in the following description can be regarded as schematic diagrams, and are not limited to the actual size, actual process, etc. of the products involved in the embodiments of the present disclosure.

[0025] FIG. 1 is a structural diagram of a display device according to some embodiments;

[0026] FIG. 2 is a structural diagram of a display panel according to some embodiments;

[0027] FIG. 3 is a structural diagram of another display panel according to some embodiments;

[0028] FIG. 4 is an equivalent circuit diagram of a pixel driving circuit according to some embodiments;

[0029] FIG. 5 is a structural diagram of a power line according to some embodiments;

[0030] FIG. 6 is a partial structural diagram of a display panel according to some embodiments;

[0031] FIG. 7 is a partial film layer stack diagram of a display panel according to some embodiments;

[0032] FIG. 8 is a partial film layer stack diagram of another display panel according to some embodiments;

[0033] FIG. 9 is a cross-sectional view along B-B of FIG. 8;

[0034] FIG. 10 is a partial view of a film layer of a first source-drain metal layer according to some embodiments;

[0035] FIG. 11 is a partial view of a film layer of a second source-drain metal layer according to some embodiments;

[0036] FIG. 12 is a partial structure diagram of another display panel according to some embodiments;

[0037] FIG. 13 is a partial film layer stack diagram of yet another display panel according to some embodiments;

[0038] FIG. 14 is a partial film layer stack diagram of a VSS line according to some embodiments;

[0039] FIG. 15 is a partial film layer stack diagram of yet another display panel according to some embodiments;

[0040] FIG. 16 is a partial film layer stack diagram of a VDD line according to some embodiments. DETAILED DESCRIPTION

[0041] The technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the drawings. It should be apparent that the described embodiments are only a part of the embodiments of the present disclosure, and not all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by those of ordinary skill in the art belong to the scope of protection of the present disclosure.

[0042] Unless the context clearly requires otherwise, throughout the description and the claims, the term "comprise," and variations thereof (e.g., "comprises" and "comprising"), will be construed to be inclusive in a manner consistent with the term's plain meaning, namely, "including but not limited to." In describing the description, the terms "one embodiment," "some embodiments," "exemplary embodiments," "example," "specific example" or "some examples," and the like, mean that a particular feature, structure, material, or characteristic is included in at least one embodiment or example of the disclosure, but that it can not be included in other embodiments or examples. The illustrative appearance of the foregoing terms in various places in the description are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics can be combined in any suitable manner in one or more embodiments or examples.

[0043] Hereinafter, the terms "first", "second", etc. are used only for the purpose of description and should not be construed as indicating or implying relative importance or implying the number of the technical features indicated. Therefore, the features defined with "first", "second" can explicitly or implicitly include one or more of the features. In the description of the embodiments of the disclosure, the meaning of "a plurality of" is two or more, unless otherwise specified.

[0044] In describing some embodiments, "coupled" and "connected," and variations thereof, can be used. The term "connected" should be interpreted broadly, for example, "connected" can be fixedly connected, or detachably connected, or integrated; can be directly connected, or indirectly connected through an intermediate medium. The term "coupled" indicates, for example, that two or more components have direct physical contact or electrical contact. The term "coupled" or "communicatively coupled" can also mean that two or more components do not have direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content herein.

[0045] "A, B, and C at least one of" has the same meaning as "at least one of A, B, or C", and includes the following combinations of A, B, and C: only A, only B, only C, a combination of A and B, a combination of A and C, a combination of B and C, and a combination of A, B, and C.

[0046] "A and / or B" includes the following three combinations: only A, only B, and a combination of A and B.

[0047] Additionally, the use of "based on" means open and inclusive, as "based on" one or more stated conditions or values can in practice be based on additional conditions or values beyond those stated.

[0048] It will be understood that when a layer or element is referred to as being "on" another layer or substrate, it can be directly on the other layer or substrate, or intervening layers can also be present.

[0049] Exemplary embodiments are described herein with reference to cross-sectional and / or plan view illustrations that are idealized examples. In the interest of clarity, not all of the scale of the layers and regions can be shown in the drawings, and the dimensions of the layers and regions can be exaggerated relative to each other. Accordingly, the exemplary embodiments are not to be limited to the precise shapes and configurations shown in the drawings, but rather are to cover any and all modifications and variations that can be made to the shapes and configurations shown in the drawings. For example, etched regions shown as rectangular in shape will typically have a curved character. Therefore, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the precise shape of a region of a device and are not intended to limit the scope of the exemplary embodiments.

[0050] Some embodiments of the disclosure provide a display device that can be any display device that displays images whether in motion (e.g., video) or stationary (e.g., a still image) and whether textual or pictorial. More specifically, it is contemplated that the display devices of the described embodiments can be implemented in or in association with a variety of electronic devices such as, but not limited to, mobile telephones, wireless devices, personal data assistants (PDAs), hand-held or pocket computers, GPS receivers / navigators, cameras, MP4 video players, camcorders, game consoles, watches, clocks, calculators, television monitors, flat panel displays, computer monitors, auto displays (e.g., odometer display, etc.), cockpit controls and / or displays, camera view displays (e.g., display of a rear view camera in a vehicle), electronic photographs, electronic billboards or signs, projections, architectural structures, packaging, and aesthetic structures (e.g., display of images on a piece of jewelry) and the like.

[0051] FIG. 1 is a structural diagram of a display device according to some embodiments. As shown in FIG. 1, the display device 1000 includes a frame 100, a cover plate 200, a display panel 300, a circuit board 400, and other electronic components including a camera.

[0052] The longitudinal section of the frame 100 is in a U shape, the display panel 300, the circuit board 400, and other electronic components including a camera are arranged in the frame 100, the circuit board 400 is located between the display panel 300 and the frame 100, and the cover plate 200 is located on the light-emitting side of the display panel 300. The side of the display panel 300 for displaying images is the light-emitting side of the display panel 300, and the side away from the light-emitting side of the display panel 300 is the back light side of the display panel 300.

[0053] For example, the circuit board 400 is located on the back light side of the display panel 300, and the circuit board 400 is electrically connected to the display panel 300. The circuit board 400 is used to provide driving signals for the display panel 300, thereby ensuring the normal display of the display panel 300.

[0054] For example, the display panel 300 can be an organic light-emitting diode (OLED) display panel, a quantum dot light-emitting diode (QLED) display panel, a micro light-emitting diode (Micro LED) display panel, or a mini light-emitting diode (Mini LED) display panel, and the present disclosure does not make specific limitations. The following describes some embodiments of the present disclosure by taking the display panel 300 as an OLED display panel.

[0055] In some examples, as shown in FIG. 2, the display panel 300 includes a display area AA and a non-display area BB located around the display area AA. For example, the non-display area BB is adjacent to the display area AA, and the non-display area BB is arranged around the display area AA.

[0056] For example, as shown in FIG. 2, the non-display area BB includes a lead-out area B10 located on one side of the display area AA.

[0057] In addition, as shown in FIG. 2, the non-display area BB can also include a binding area B20 located on a side of the lead-out area B10 away from the display area AA.

[0058] In some examples, as shown in FIG. 2 and FIG. 3, the display panel 300 includes a substrate 10.

[0059] The type of the substrate 10 includes a variety of types, which can be selected and arranged according to actual needs.

[0060] Exemplarily, the substrate 10 can be a rigid substrate. The rigid substrate can be a glass substrate, a Polymethyl methacrylate (PMMA) substrate, or the like.

[0061] Exemplarily, the substrate 10 can be a flexible substrate. The flexible substrate can be a Polyethylene terephthalate (PET) substrate, a Polyethylene naphthalate two formic acid glycol ester (PEN) substrate, a Polyimide (PI) substrate, or the like. In this case, the display panel 300 can implement flexible display, for example.

[0062] Optionally, the substrate 10 can be formed as a single layer, a double layer, or a multi-layer. Embodiments of the present disclosure do not limit this.

[0063] Exemplarily, as shown in FIG. 3, the display panel 300 further includes a sub-pixel P located on the substrate 10. The sub-pixel P is located in the display area AA, and a plurality of sub-pixels P can be arranged in an array in the display area AA.

[0064] In some examples, as shown in FIG. 3, each sub-pixel P includes a driving circuit layer 20 and a light emitting device layer 30 arranged in sequence. The driving circuit layer 20 is located on the substrate 10, and the light emitting device layer 30 is located on a side of the driving circuit layer 20 away from the substrate 10.

[0065] It can be understood that the driving circuit layer 20 refers to a film layer in which a plurality of pixel driving circuits are located, and specifically includes a plurality of patterned conductive layers and insulating layers. Exemplarily, the driving circuit layer 20 includes a plurality of pixel driving circuits 210 and a plurality of signal lines, and the like. The light emitting device layer 30 includes a plurality of light emitting devices 31.

[0066] Exemplarily, the pixel driving circuit 210 is generally composed of electronic devices such as a Thin film transistor (TFT), a capacitor, and the like. For example, the pixel driving circuit 210 can be of a structure of “2T1C”, “6T1C”, “7T1C”, “6T2C”, or “7T2C”, and the like. Here, “T” represents a transistor, for example, a thin film transistor. The number before “T” represents the number of transistors. “C” represents a capacitor, and the number before “C” represents the number of capacitors. In some embodiments of the present disclosure, only one thin film transistor 211 is taken as an example for illustration, as shown in FIG. 3. For example, the thin film transistor 211 can be a driving transistor.

[0067] In some examples, the pixel driving circuit 210 is of a 7T1C structure. That is, the pixel driving circuit 210 is composed of 7 thin film transistors and 1 capacitor.

[0068] Specifically, as shown in FIG. 4, the pixel driving circuit 210 includes a switch transistor T1, a driving transistor T2, a compensation transistor T3, a first light-emitting control transistor T4, a second light-emitting control transistor T5, a first reset transistor T6, a second reset transistor T7, and a storage capacitor Cst.

[0069] In the case where the level of the reset signal transmitted by the reset signal terminal RST is an effective level, the first reset transistor T6 and the second reset transistor T7 can be turned on under the control of the reset signal, receive the initial signal transmitted by the initial signal terminal Vinit, the first reset transistor T6 can transmit the initial signal to one end of the storage capacitor Cst to reset it, and the second reset transistor T7 can transmit the initial signal to the second electrode of the second reset transistor T7 to reset it. Here, the driving transistor T2 can be turned on under the control of the initial signal.

[0070] In the case where the level of the scan signal transmitted by the scan signal terminal Gate is an effective level, the switch transistor T1 and the compensation transistor T3 can be turned on under the control of the scan signal, and the data signal transmitted by the data signal terminal Data can be transmitted to the control electrode of the driving transistor T2 through the switch transistor T1, the driving transistor T2, and the compensation transistor T3 in sequence to charge the control electrode of the driving transistor T2 until the driving transistor T2 is turned off. At this time, the threshold voltage of the driving transistor T2 is compensated.

[0071] In the case where the level of the enable signal transmitted by the enable signal terminal EM is an effective level, the first light-emitting control transistor T4 and the second light-emitting control transistor T5 can be turned on under the control of the enable signal, receive the first voltage signal VDD from the first voltage signal terminal VDD, and the driving transistor T2 can generate a driving signal according to the data signal and the first voltage signal VDD and transmit the driving signal to the second electrode of the second reset transistor T7.

[0072] In some examples, the light-emitting device 31 described above can be an OLED light-emitting device.

[0073] For example, as shown in FIG. 3, the light-emitting device 31 includes a first electrode 311, a light-emitting part 312, and a second electrode 313 which are sequentially stacked in a direction away from the substrate 10.

[0074] For example, the first electrode 311 is an anode, and the second electrode 313 is a cathode. Alternatively, the first electrode 311 is a cathode, and the second electrode 313 is an anode. In the embodiments of the present disclosure, the first electrode 311 is an anode, and the second electrode 313 is a cathode.

[0075] For example, the light emitting part 312 of the light emitting device 31 can include an electroluminescent (EL) layer. In other examples, the light emitting part 312 can include one or more of an election transporting layer (ETL), an election injection layer (EIL), a hole transporting layer (HTL), and a hole injection layer (HIL) in addition to the EL layer. In the case where the display panel 300 is an organic electroluminescent display panel, the light emitting layer is an organic light emitting layer. In the case where the display panel 300 is a quantum dot electroluminescent display panel, the light emitting layer is a quantum dot light emitting layer.

[0076] For example, the first electrode 311 of the light emitting device 31 and the drain of the thin film transistor 211 used as a driving transistor in the pixel driving circuit 210 are electrically connected. The pixel driving circuit 210 can generate a driving signal (for example, a driving current) and transmit the driving signal to the first electrode 311 of the light emitting device 31. The driving signal can cooperate with a second voltage signal VSS provided by the second voltage signal end VSS coupled to the second electrode 313 of the light emitting device 31, so as to drive the light emitting device 31 to emit light normally.

[0077] For example, the electrical connection relationship between the light emitting device 31 and the pixel driving circuit 210 includes various types, which can be selected and arranged according to actual needs, and the present disclosure does not limit this.

[0078] For example, the plurality of pixel driving circuits 210 and the plurality of light emitting devices 31 can be coupled one by one. For example, in the present disclosure, one pixel driving circuit 210 can be coupled to a plurality of light emitting devices 31, or a plurality of pixel driving circuits 210 can be coupled to one light emitting device 31. The embodiments of the present disclosure do not limit this.

[0079] In the following, the structure of the display panel 300 is schematically described by taking one pixel driving circuit 210 coupled to one light emitting device 31 as an example.

[0080] Exemplarily, in the display panel 300, the pixel driving circuit 210 can generate a driving signal and transmit the driving signal to the corresponding light emitting device 31 to control the light emitting state of the light emitting device 31. The light emitting state includes, for example, whether the light emitting device 31 emits light or the luminance of the light emitting device 31. The light emitting states of the plurality of light emitting devices 31 are collectively controlled by the plurality of pixel driving circuits 210, and the light emitted by the plurality of light emitting devices 31 cooperates with each other, so that the display panel 300 realizes image display.

[0081] In some examples, as shown in FIG. 3, the display panel 300 further includes an encapsulation layer 40 located on the side of the light emitting device layer 30 away from the substrate 10.

[0082] Exemplarily, the encapsulation layer 40 can be a thin film encapsulation (TFE) or an encapsulation substrate. The encapsulation layer 40 is configured to encapsulate the pixel driving circuit 210 and the plurality of light emitting devices 31 on the substrate 10 to block water and oxygen, so as to avoid the erosion of the water and oxygen to the light emitting device 31, thereby affecting the light emitting efficiency and service life of the light emitting device 31.

[0083] For example, as shown in FIG. 3, the encapsulation layer 40 can include a first inorganic layer 41, an organic layer 42 and a second inorganic layer 43 which are sequentially stacked in the direction away from the substrate 10. Of course, the encapsulation layer 40 can further include more inorganic layers and organic layers. The first inorganic layer 41 and / or the second inorganic layer 43 can be made of inorganic insulating material and prepared by deposition process; the organic layer 42 can be made of organic insulating material and prepared by inkjet printing process.

[0084] In some examples, as shown in FIG. 2, the display panel 300 further includes a power line 50. The power line 50 is located on the substrate 10.

[0085] Exemplarily, the power line 50 can be a laminated structure of metal material. The metal material can be pure metal material or metal compound. The metal material includes titanium (Ti), aluminum (Al), molybdenum (Mo) or metal, etc.

[0086] Exemplarily, the power line 50 can be a laminated structure of Ti / AL / Ti.

[0087] For example, as shown in FIGS. 5 and 6, the power line 50 includes two layers of first metal layers 501 which are stacked, and one layer of second metal layer 502 located between the two layers of first metal layers 501. The material of the first metal layer 501 includes Ti, and the material of the second metal layer 502 includes Al. Of course, the power line 50 can also be a two-layer structure or a four-layer structure, and can also be a more-layer structure, which is not limited here.

[0088] For example, the plurality of power lines 50 can be used to transmit different electrical signals.

[0089] For example, as shown in FIG. 2, the plurality of power lines 50 can include at least one VSS line and at least one VDD line.

[0090] The VDD line is used to transmit the first voltage signal VDD, and the VSS line is used to transmit the second voltage signal VSS.

[0091] Specifically, one end of the VSS line can be connected to the driving chip, and the other end of the VSS line can be connected to the second electrode 313 of the light emitting device 31, so that the VSS line can provide the second voltage signal VSS for the second electrode 313 of the light emitting device 31; one end of the VDD line can be connected to the driving chip, and the other end of the VDD line can be electrically connected to the first voltage signal end VDD of the pixel driving circuit 210, so that the VDD line can provide the first voltage signal VDD for the pixel driving circuit 210.

[0092] For example, the power line 50 is at least partially located in the lead-out area B10, and the portion of the power line 50 located in the lead-out area B10 extends to the bonding area B20 along the arrangement direction of the lead-out area B10 and the bonding area B20. In addition, the bonding area B20 is provided with a bonding pin, and the power line 50 is connected to the bonding pin after extending to the bonding area B20 along the arrangement direction of the lead-out area B10 and the bonding area B20.

[0093] In some implementations, in order to realize the narrow frame design of the display panel 300, the size of the lead-out area B10 is designed to be small, which causes the portion of the power line 50 located in the lead-out area B10 to be compressed, the area of the portion of the power line 50 located in the lead-out area B10 to be reduced, and thus the signal transmission load on the portion of the power line 50 located in the lead-out area B10 to be increased, the stability of the signal transmitted on the portion of the power line 50 located in the lead-out area B10 to be reduced, and the display panel 300 to be prone to display quality problems.

[0094] In addition, in some implementations, as shown in FIG. 7, the portion of the power line 50 located in the lead-out area B10 is a single-layer trace. The power line 50 occupies a relatively large space, and the voltage loss is relatively obvious.

[0095] In some examples, as shown in FIGS. 2 and 7, the display panel 300 further includes a blocking dam 60. The blocking dam 60 is located on the substrate 10, and the blocking dam 60 is located in the non-display area BB and surrounds the display area AA.

[0096] The barrier dam 60 is used to block the organic layer 42 in the encapsulation layer 40 to ensure good encapsulation effect.

[0097] For example, the number of barrier dams 60 can be one or multiple. Embodiments of the present disclosure do not limit this.

[0098] For example, as shown in combination with FIG. 2 and FIG. 7, the number of barrier dams 60 is two, and the two barrier dams 60 are respectively a first barrier dam 61 and a second barrier dam 62, which are sequentially and spaced apart in a direction away from the display area AA.

[0099] For example, the structure of the barrier dam 60 can be a single-layer structure or a multi-layer structure. Embodiments of the present disclosure do not limit this.

[0100] For example, as shown in combination with FIG. 2, in the case where the display panel 300 further includes the barrier dam 60, part of each power line 50 is located within the area surrounded by the barrier dam 60, and another part of the power line 50 is located outside the area surrounded by the barrier dam 60. That is, each power line 50 passes through the barrier dam 60 into the area surrounded by the barrier dam 60.

[0101] For example, the barrier dam 60 is formed by using an organic insulating layer. In the process of preparing the display panel 300, in order to form the barrier dam 60, the organic insulating layer near the barrier dam 60 needs to be removed. For example, the organic insulating layer on the power line 50 near the barrier dam 60 needs to be removed. Moreover, since the organic material is easy to absorb water and oxygen, in order to avoid the water and oxygen entering the inside of the display panel 300 along the organic insulating layer and affecting the display effect of the display panel 300, usually the organic insulating layer on the remaining part of the part of the power line 50 located in the non-display area AA, except for the part covered by the barrier dam 60, also needs to be removed. That is, the remaining part of the part of the power line 50 located in the non-display area AA, except for the part covered by the barrier dam 60, is not covered by the organic insulating layer. That is, the side of the part of the power line 50 located in the non-display area AA, which is not covered by the barrier dam 60, is in a bare state.

[0102] The inventors of the present disclosure have found that, in the process of forming a subsequent film layer (for example, the first electrode 311 of the light-emitting device 31, or other film layers located on the side of the power line 50 away from the substrate 10), when the film layer is patterned by an etching process, the etchant used will come into contact with the side of the power line 50 in the bare state, thereby causing over-etching to the side of the power line 50 in the bare state. Since the wet etching rates of Ti and Al in the power line 50 are different, the side of the part of the power line 50 located in the non-display area AA, which is not covered by the barrier dam 60, is prone to form an undercut structure (as shown in position A in FIG. 5).

[0103] In the case that the undercut structure exists on the side surface of the power line 50, it is easy to cause the encapsulation failure at the position where the undercut structure exists on the side surface of the power line 50 when the encapsulation layer 40 is subsequently formed, such as the position B shown in FIG. 6. For example, the encapsulation layer 40 has poor film uniformity at the position where the undercut structure exists on the side surface of the power line 50, and the encapsulation ability is weak, and the encapsulation layer 40 may be broken or separated after a period of time, thereby causing the encapsulation failure of the display panel 300. The moisture or oxygen in the air may enter through the crack and enter the inside of the display panel 300 along the side surface of the power line 50, so that the growing black spots (GDS) phenomenon occurs on the display panel 300. For example, the growing black spots may occur at the junction of the display area AA along the wire direction of the power line 50 (such as the position C shown in FIG. 2), which seriously affects the yield and quality of the display panel 300.

[0104] Based on this, in the embodiments of the present disclosure, a display panel 300 is provided.

[0105] As shown in FIGS. 8 and 9, the power line 50 includes a first sub-line 51 located in the lead-out area B10. The first sub-line 51 includes a first conductive pattern 511 and a second conductive pattern 512 which are sequentially stacked in a direction away from the substrate 10. The second conductive pattern 512 has a projection on the substrate 10 which at least partially overlaps with a projection of the first conductive pattern 511 on the substrate 10, and the first conductive pattern 511 is electrically connected to the second conductive pattern 512.

[0106] In some examples, the projection of the second conductive pattern 512 on the substrate 10 completely overlaps with the projection of the first conductive pattern 511 on the substrate 10. In other examples, the projection of the second conductive pattern 512 on the substrate 10 partially overlaps with the projection of the first conductive pattern 511 on the substrate 10. The embodiments of the present disclosure do not make any limitation in this regard.

[0107] In some examples, as shown in FIG. 9, the display panel 300 further includes a first protective layer 70. The first protective layer 70 is located on a side of the first sub-line 51 away from the substrate 10, and the first protective layer 70 covers at least part of the side surface of the second conductive pattern 512 of the first sub-line 51.

[0108] For example, the material of the first protective layer 70 can be an organic material or an inorganic material. The embodiments of the present disclosure do not make any limitation in this regard.

[0109] In some examples, the first protective layer 70 covers part of the side surface of the second conductive pattern 512 of the first sub-wire 51. In other examples, the first protective layer 70 covers the entire side surface of the second conductive pattern 512 of the first sub-wire 51. Embodiments of the present disclosure do not limit this.

[0110] In addition, in some examples, the first protective layer 70 can also cover at least part of the side surface of the first conductive pattern 511 of the first sub-wire 51.

[0111] In this embodiment, the first sub-wire 51 in the power supply line 50 located in the lead-out area B10 includes a first conductive pattern 511 and a second conductive pattern 512 which are stacked and electrically connected, that is, the double-layered parallel connection of the first sub-wire 51 is realized, thereby increasing the area of the first sub-wire 51, reducing the signal transmission loading on the first sub-wire 51, improving the stability of the signal transmitted on the first sub-wire 51, ensuring the display yield of the display panel 300; it can also save the wiring space, reduce the height of the lead-out area B10, reduce the frame size of the display panel 300, and be beneficial to realize the narrow frame design of the display panel 300. Moreover, by setting the first protective layer 70 to cover at least part of the side surface of the second conductive pattern 512 of the first sub-wire 51, the probability of corrosion of the side surface of the second conductive pattern 512 of the first sub-wire 51 caused by the development and etching process in the subsequent film layer forming process can be reduced, the probability of the side surface of the second conductive pattern 512 of the first sub-wire 51 generating an undercut structure can be reduced, thereby reducing the probability of the encapsulation layer 40 breaking, improving the encapsulation reliability of the display panel 300, reducing the probability of water vapor or oxygen invading the inside of the display panel 300, reducing the probability of the display panel 300 appearing GDS defects, and thereby improving the display uniformity of the display panel 300.

[0112] In some embodiments, as shown in FIG. 3, the display panel 300 further includes a first source-drain metal layer 21 and a second source-drain metal layer 22 which are sequentially stacked in the direction away from the substrate 10.

[0113] As shown in FIGS. 8, 10 and 11, the first conductive pattern 511 of the first sub-wire 51 is located in the first source-drain metal layer 21, and the second conductive pattern 512 of the first sub-wire 51 is located in the second source-drain metal layer 22.

[0114] For example, the first source-drain metal layer 21 can include the source and drain of a plurality of thin film transistors 211. The first conductive pattern 511 is located in the first source-drain metal layer 21, that is, the first conductive pattern 511 is located in the same layer and has the same material as the source and drain of the plurality of thin film transistors 211.

[0115] For example, the second source-drain metal layer 22 can include a plurality of signal lines. The second conductive pattern 512 is located in the second source-drain metal layer 22, i.e., the second conductive pattern 512 is located in the same layer and is made of the same material as the signal lines in the second source-drain metal layer 22.

[0116] It should be noted that "in the same layer" means that the layer structure is formed by using the same film forming process to form a film layer for forming a specific pattern, and then using the same mask plate to form the layer structure by one patterning process. According to different specific patterns, the one patterning process can include multiple exposure, development or etching processes, and the specific patterns in the formed layer structure can be continuous or discontinuous, and these specific patterns can also be at different heights or have different thicknesses. In this way, the first conductive pattern 511 and the source and drain electrodes of the plurality of thin film transistors 211 can be formed in the same patterning process; and the second conductive pattern 512 and the signal lines in the second source-drain metal layer 22 can be formed in the same patterning process.

[0117] In addition, in the present disclosure, the patterning process can refer to a process including photolithography, or a process including photolithography and etching steps, and can also include printing, inkjet and other processes for forming predetermined patterns; the photolithography process refers to a process for forming patterns using photoresist, mask plate, exposure machine and the like, including film forming, exposure, development and the like. The corresponding patterning process can be selected according to the structure formed in the present disclosure.

[0118] It can be understood that, in the case that the first conductive pattern 511 is located in the first source-drain metal layer 21, in the manufacturing process of the display panel 300, a new mask plate does not need to be added, and only the mask plate originally used to form the first source-drain metal layer 21 needs to be improved, so that the first conductive pattern 511 and the source and drain electrodes of the plurality of thin film transistors 211 can be formed in the same patterning process.

[0119] In the case that the second conductive pattern 512 is located in the second source-drain metal layer 22, in the manufacturing process of the display panel 300, a new mask plate does not need to be added, and only the mask plate originally used to form the second source-drain metal layer 22 needs to be improved, so that the second conductive pattern 512 and the plurality of signal lines included in the second source-drain metal layer 22 can be formed in the same patterning process.

[0120] With the above arrangement, the first conductive pattern 511 and the source and drain electrodes of the plurality of thin film transistors 211 in the first source-drain metal layer 21 can be formed by the same film forming process and then patterned by the same mask plate in one patterning process; the second conductive pattern 512 and the plurality of signal lines included in the second source-drain metal layer 22 can be formed by the same film forming process and then patterned by the same mask plate in one patterning process, thereby forming the first sub-line 51 with a double-layer design without adding extra processes, increasing the area of the first sub-line 51, reducing the signal transmission load on the first sub-line 51, improving the stability of the signals transmitted on the first sub-line 51, and ensuring the display yield of the display panel 300. Moreover, the display panel 300 has a simple patterning process, thereby reducing the difficulty of manufacturing the display panel 300 and the manufacturing cost of the display panel 300.

[0121] In some embodiments, as shown in FIG. 8, part of the first sub-line 51 is covered by the blocking dam 60. The side surface of the part of the second conductive pattern 512 of the first sub-line 51 that is not covered by the blocking dam 60 is covered by the first protective layer 70.

[0122] It should be noted that the above-mentioned "the side surface of the part of the second conductive pattern 512 of the first sub-line 51 that is not covered by the blocking dam 60 is covered by the first protective layer 70" means that the side surface of the part of the second conductive pattern 512 of the first sub-line 51 that is not covered by the blocking dam 60 is wrapped by the first protective layer 70.

[0123] As can be seen from the above, the side surface of the part of the first sub-line 51 that is not covered by the blocking dam 60 is in an exposed state.

[0124] In this embodiment, the first protective layer 70 covers the side surface of the part of the second conductive pattern 512 of the first sub-line 51 that is not covered by the blocking dam 60, thereby avoiding the side surface of the part of the second conductive pattern 512 of the first sub-line 51 that is not covered by the blocking dam 60 from being corroded by the development and etching processes in the process of forming subsequent film layers, reducing the probability of the side surface of the part of the second conductive pattern 512 of the first sub-line 51 that is not covered by the blocking dam 60 from forming an undercut structure, thereby reducing the probability of the encapsulation layer 40 from being broken, improving the encapsulation reliability of the display panel 300, reducing the probability of water vapor or oxygen invading the inside of the display panel 300, reducing the probability of the display panel 300 from having GDS defects, and improving the display effect of the display panel 300.

[0125] In some embodiments, the material of the first protective layer 70 includes an inorganic material.

[0126] For example, the inorganic material can be silicon nitride (SiNx), silicon oxynitride (SiON), or silicon oxide (SiOx), etc.

[0127] With the above arrangement, the first protective layer 70 formed of inorganic material can protect the first sub-wire 51, avoid the side of the part of the second conductive pattern 512 of the first sub-wire 51 not covered by the blocking dam 60 from being corroded by the development and etching process in the process of forming the subsequent film layer, reduce the probability of the side of the part of the second conductive pattern 512 of the first sub-wire 51 not covered by the blocking dam 60 from generating an undercut structure, thereby reducing the probability of the encapsulation layer 40 from being broken, improving the encapsulation reliability of the display panel 300, reducing the probability of water vapor or oxygen and the like from invading the inside of the display panel 300, reducing the probability of the display panel 300 from generating GDS defects, and improving the display effect of the display panel 300.

[0128] In some embodiments, as shown in FIG. 3, the display panel 300 further includes a first passivation layer 23 located on the side of the second source-drain metal layer 22 away from the substrate 10. The first protective layer 70 is located on the first passivation layer 23.

[0129] Here, the material of the first passivation layer 23 is not limited. For example, the material of the first passivation layer 23 can be any one of silicon dioxide (SiO2) and silicon nitride (SiNx).

[0130] In this embodiment, the first protective layer 70 is located on the first passivation layer 23, so that the first protective layer 70 can be formed without adding an additional process, the protection of the first sub-wire 51 is realized, the probability of the side of the part of the second conductive pattern 512 of the first sub-wire 51 not covered by the blocking dam 60 from generating an undercut structure is reduced, thereby reducing the probability of the encapsulation layer 40 from being broken, improving the encapsulation reliability of the display panel 300, reducing the probability of water vapor or oxygen and the like from invading the inside of the display panel 300, reducing the probability of the display panel 300 from generating GDS defects, and improving the display effect of the display panel 300; and moreover, the display panel 300 has simple patterning process steps, thereby reducing the preparation difficulty of the display panel 300 and reducing the manufacturing cost of the display panel 300.

[0131] In some embodiments, the blocking dam 60 includes a first blocking layer; and the first protective layer 70 is the same material as and is arranged in the same layer as the first blocking layer.

[0132] For example, the material of the first blocking layer can be an organic material. The organic material can be, for example, PI (Polyimide), BCB (benzocyclobutene), or acrylic acid, etc.

[0133] For example, the blocking dam 60 can further include a second blocking layer, a third blocking layer, etc. The embodiments of the present disclosure do not limit this.

[0134] It can be understood that, in the case that the first protective layer 70 is the same as and is disposed in the same layer as the first barrier layer material of the barrier dam 60, in the manufacturing process of forming the display panel 300, a new mask is not needed to be added, and the mask originally used to form the first barrier layer only needs to be improved, so as to simultaneously form the first protective layer 70 and the first barrier layer of the barrier dam 60.

[0135] With the above arrangement, the first protective layer 70 and the first barrier layer of the barrier dam 60 can be simultaneously formed, that is, the first protective layer 70 can be formed without adding an additional process, the protection of the second conductive pattern 512 of the first sub-wire 51 is realized, the probability of the undercut structure occurring in the side surface of the part of the second conductive pattern 512 not covered by the barrier dam 60 is reduced, the probability of the encapsulation layer 40 being broken is reduced, the encapsulation reliability of the display panel 300 is improved, the probability of water vapor or oxygen and the like invading the inside of the display panel 300 is reduced, the probability of the display panel 300 having GDS defects is reduced, and the display effect of the display panel 300 is improved; moreover, the patterning process steps of the display panel 300 are simple, so that the preparation difficulty of the display panel 300 is reduced, and the manufacturing cost of the display panel 300 is reduced.

[0136] In some embodiments, as shown in FIG. 3, the display panel 300 further includes: a first planar layer 24 located between the first source-drain metal layer 21 and the second source-drain metal layer 22; and a second planar layer 25 located on the side of the second source-drain metal layer 22 away from the substrate 10. The first protective layer 70 and the first barrier layer of the barrier dam 60 are located on the second planar layer 25.

[0137] For example, the materials of the first planar layer 24 and the second planar layer 25 can be the same or different. Embodiments of the present disclosure do not limit this. For example, the materials of the first planar layer 24 and the second planar layer 25 are the same.

[0138] Specifically, the materials of the first planar layer 24 and the second planar layer 25 can include an organic insulating material. For example, the organic insulating material includes general-purpose polymers such as polymethyl methacrylate (PMMA) and polystyrene (PS), polymer derivatives having phenol groups, acryl-based polymers, imide-based polymers, aryl ether-based polymers, amide-based polymers, fluorine-based polymers, p-xylene-based polymers, vinyl alcohol-based polymers, or mixtures thereof. For example, the materials of the first planar layer 24 and the second planar layer 25 both include polyimide.

[0139] Exemplarily, the thickness of the first protective layer 70 and the first barrier layer of the barrier dam 60 can be same as or different from the thickness of the second planar layer 25. For example, the thickness of the first protective layer 70 and the first barrier layer of the barrier dam 60 is same as the thickness of the second planar layer 25, thereby reducing the complexity of the patterning process of the display panel 300, reducing the difficulty of manufacturing the display panel 300, and reducing the manufacturing cost of the display panel 300.

[0140] With the above arrangement, the first protective layer 70 and the first barrier layer of the barrier dam 60 are located on the second planar layer 25, thereby forming the first protective layer 70 and the first barrier layer of the barrier dam 60 without increasing the number of masks, thereby simplifying the manufacturing process of the display panel 300, reducing the difficulty of manufacturing the display panel 300, and reducing the manufacturing cost of the display panel 300.

[0141] In some embodiments, the thickness of the second planar layer 25 is less than the thickness of the first planar layer 24.

[0142] For example, the thickness of the first planar layer 24 is 2 μm, and the thickness of the second planar layer 25 is 1.5 μm. For another example, the thickness of the first planar layer 24 is 1.5 μm, and the thickness of the second planar layer 25 is 1.0 μm.

[0143] As described above, the first protective layer 70 is located on the second planar layer 25, and the thickness of the first protective layer 70 can be same as the thickness of the second planar layer 25.

[0144] Exemplarily, the first protective layer 70 is in a stepped shape and extends along the side surface of the first sub-line 51. In this way, the step between the side surface of the first sub-line 51 and the substrate 10 can be reduced, thereby improving the problem that, when the encapsulation layer 40 is subsequently formed, the step between the edge of the first sub-line 51 and the substrate 10 is large, which leads to poor film uniformity of the encapsulation layer 40, and thus the encapsulation layer 40 and the substrate 10 are easily peeled off and bubbles are generated.

[0145] In some embodiments, as shown in FIG. 9, the first conductive pattern 511 directly contacts and is electrically connected to the second conductive pattern 512. That is, there is no other film layer between the first conductive pattern 511 and the second conductive pattern 512.

[0146] With the above arrangement, the electrical connection between the first conductive pattern 511 and the second conductive pattern 512 can be ensured to be effective, thereby realizing the double-layer parallel design of the part (i.e., the first sub-line 51) of the power line 50 located in the lead-out area B10, increasing the area of the first sub-line 51, reducing the signal transmission load on the first sub-line 51, improving the stability of the signal transmitted on the first sub-line 51, and ensuring the display yield of the display panel 300.

[0147] In some embodiments, as shown in FIG. 9, the edge portion of the second conductive pattern 512 covers the side surface of the first conductive pattern 511.

[0148] For example, the portion of the second conductive pattern 512 covering the first conductive pattern 511 is in a stepped shape. In this way, the film layer step difference of the edge of the first sub-wire 51 can be reduced, thereby improving the problem that, in the case of forming the encapsulation layer 40 subsequently, the encapsulation layer 40 has poor film forming uniformity due to the large step difference between the edge of the first sub-wire 51 and the substrate 10, and thus the encapsulation layer 40 and the substrate 10 are prone to peeling and bubbles, thereby further improving the encapsulation yield of the display panel 300, improving the encapsulation reliability of the display panel 300, reducing the probability of water vapor or oxygen invading the inside of the display panel 300, reducing the probability of GDS failure of the display panel 300, and thus improving the display effect of the display panel 300.

[0149] In some embodiments, as shown in FIG. 12, the display panel 300 further includes a second protective layer 80 located between the first conductive pattern 511 and the second conductive pattern 512. The second protective layer 80 covers the side surface of the portion of the first conductive pattern 511 that is not covered by the blocking dam 60.

[0150] For example, the material of the second protective layer 80 can be an organic material or an inorganic material. Embodiments of the present disclosure do not make any limitation in this regard.

[0151] With the above arrangement, by arranging the second protective layer 80 to cover the side surface of the portion of the first conductive pattern 511 of the first sub-wire 51 that is not covered by the blocking dam 60, the probability of the side surface of the first conductive pattern 511 of the first sub-wire 51 being corroded by the development and etching process in the subsequent film layer forming process can be reduced, and the probability of the side surface of the first conductive pattern 511 of the first sub-wire 51 having an undercut structure can be reduced, thereby reducing the probability of the encapsulation layer 40 being broken, improving the encapsulation reliability of the display panel 300, reducing the probability of water vapor or oxygen invading the inside of the display panel 300, reducing the probability of GDS failure of the display panel 300, and thus improving the display effect of the display panel 300.

[0152] In addition, in the case where the display panel 300 includes both the first protective layer 70 and the second protective layer 80, the first conductive pattern 511 and the second conductive pattern 512 can be protected at the same time, the probability of the side surface of the first conductive pattern 511 and the second conductive pattern 512 having an undercut structure can be reduced, thereby reducing the probability of the encapsulation layer 40 being broken, improving the encapsulation reliability of the display panel 300, and thus meeting the high reliability requirement of the display panel 300.

[0153] In some embodiments, as shown in FIG. 3, the display panel 300 further comprises: a second passivation layer 26 located between the first source-drain metal layer 21 and the second source-drain metal layer 22; and a second protective layer 80 located on the second passivation layer 26.

[0154] Here, the material of the second passivation layer 26 is not limited. For example, the material of the second passivation layer 26 can be any one of silicon dioxide (SiO2) and silicon nitride (SiNx).

[0155] In this embodiment, the second protective layer 80 is located on the second passivation layer 26, so that the second protective layer 80 can be formed without adding an additional process, the portion of the first conductive pattern 511 not covered by the blocking dam 60 is protected, the probability of the undercut structure occurring on the side of the portion of the first conductive pattern 511 not covered by the blocking dam 60 is reduced, the probability of the encapsulation layer 40 being broken is reduced, the encapsulation reliability of the display panel 300 is improved, the probability of water vapor or oxygen invading the inside of the display panel 300 is reduced, the probability of the display panel 300 having GDS defects is reduced, and the display effect of the display panel 300 is improved; moreover, the patterning process steps of the display panel 300 are simple, so that the preparation difficulty of the display panel 300 is reduced, and the manufacturing cost of the display panel 300 is reduced.

[0156] In some embodiments, as shown in FIG. 12, the second protective layer 80 is provided with at least one first via hole 81, and the second conductive pattern 512 is electrically connected to the first conductive pattern 511 through the at least one first via hole 81.

[0157] For example, the number of the first via hole 81 can be one, two or more, and the embodiments of the present disclosure do not limit this.

[0158] In addition, the first via hole 81 can be arranged on the second protective layer close to the binding area.

[0159] With the above arrangement, the electrical connection between the second conductive pattern 512 and the first conductive pattern 511 is realized, so that the double-layer parallel design of the first sub-wire 51 is realized, the area of the first sub-wire 51 is increased, the signal transmission load on the first sub-wire 51 is reduced, the stability of the signal transmitted on the first sub-wire 51 is improved, and the display yield of the display panel 300 is ensured.

[0160] In some embodiments, the second protective layer 80 has a groove, and the groove exposes the surface of the first conductive pattern 511 away from the substrate 10.

[0161] For example, the boundary of the groove coincides with the boundary of the surface of the first conductive pattern 511 away from the substrate 10.

[0162] With the above arrangement, the first conductive pattern 511 is exposed by the groove away from the surface of the substrate 10, and the second conductive pattern 512 is in contact with the first conductive pattern 511 away from the surface of the substrate 10, thereby realizing the electrical connection between the second conductive pattern 512 and the first conductive pattern 511, ensuring the effectiveness of the electrical connection between the second conductive pattern 512 and the first conductive pattern 511, thereby realizing the double-layer parallel design of the portion of the power supply line 50 located in the lead-out area B10 (i.e., the first sub-line 51), thereby increasing the area of the portion of the power supply line 50 located in the lead-out area B10 (i.e., the first sub-line 51), reducing the signal transmission load on the first sub-line 51, improving the stability of the signal transmitted on the first sub-line 51, and ensuring the display yield of the display panel 300.

[0163] In some embodiments, as shown in FIG. 13, the area of the second conductive pattern 512 covered by the blocking dam 60 is provided with at least one second through hole 5121.

[0164] For example, the number of the second through holes 5121 provided in the area of the second conductive pattern 512 covered by the blocking dam 60 is multiple, and the multiple second through holes 5121 are uniformly arranged.

[0165] For example, in the manufacturing process of the display panel 300, after the first planar layer 24 is formed, the substrate 10 and the pixel driving circuit 210 on the substrate 10 and the first planar layer 24 need to be cleaned to remove foreign matter on the first planar layer 24; and after cleaning, drying is performed to prevent water remaining during cleaning from affecting the thin film transistor in the pixel driving circuit 210, further prevent the characteristics of the thin film transistor from changing adversely, and further prevent display abnormalities of the display panel 300.

[0166] It can be understood that, in the process of cleaning and drying the first planar layer 24, residual gas may exist in the first planar layer 24, which may cause the subsequent formed film layer to peel off or generate bubbles.

[0167] In the embodiments of the present disclosure, the second conductive pattern 512 on the first planar layer 24 is provided with at least one second through hole 5121, and the residual gas existing in the first planar layer 24 can be discharged through the at least one second through hole 5121, thereby reducing the probability of the subsequent formed film layer peeling off or generating bubbles due to the residual gas existing in the first planar layer 24.

[0168] In some embodiments, as shown in FIGS. 8, 10 and 11, the power supply line is a VSS line.

[0169] In combination with FIGS. 8, 10, 11, and 14, in the case where the power supply line is a VSS line, the first sub-line 51 includes a first sub-portion 52 and a second sub-portion 53 connected in series, the first sub-portion 52 extending along the first direction X, and the second sub-portion 53 extending along the second direction Y.

[0170] The first direction X is the arrangement direction of the display area AA and the lead-out area B10, and the first direction X and the second direction Y intersect. Here, the included angle between the first direction X and the second direction Y can be selected according to actual needs. For example, the included angle between the first direction X and the second direction Y is 85°, 88°, or 90°, and the like.

[0171] For example, the second sub-portion 53 is closer to the display area AA than the first sub-portion 52, and part of the second sub-portion 53 is covered by the blocking dam 60; and the first protective layer 70 covers the side surfaces of the first sub-portion 52 on opposite sides in the second direction Y, and the side surface of the second sub-portion 53 that is not covered by the blocking dam 60.

[0172] For example, the orthographic projection of the first sub-portion 52 on the substrate 10 is arranged offset from the orthographic projection of the blocking dam 60 on the substrate 10, and the orthographic projection of the second sub-portion 53 on the substrate 10 partially overlaps the orthographic projection of the blocking dam 60 on the substrate 10.

[0173] In this embodiment, the side surface of the part of the first sub-line 51 of the VSS line that is not covered by the blocking dam 60 is covered by the first protective layer 70, so that the probability of corrosion of the side surface of the first sub-line 51 of the VSS line caused by the development and etching processes in the subsequent film layer formation process can be reduced, the probability of the side surface of the first sub-line 51 of the VSS line generating an undercut structure can be reduced, the probability of the encapsulation layer 40 breaking can be reduced, the encapsulation reliability of the display panel 300 is improved, the probability of water vapor or oxygen and the like invading the inside of the display panel 300 is reduced, the probability of the display panel 300 generating GDS defects is reduced, and thus the display effect of the display panel 300 is improved.

[0174] In some embodiments, in the case where the power supply line 50 is a VSS line, the area of at least one of the first conductive pattern 511 and the second conductive pattern 512 is greater than or equal to 4×106μm2. For example, in the case where the power supply line 50 is a VSS line, the area of at least one of the first conductive pattern 511 and the second conductive pattern 512 can be 4×106μm2, 5×106μm2, 6×106μm2, 7×106μm2, 8×106μm2, and the like. Embodiments of the present disclosure do not make any limitation in this regard.

[0175] In some examples, the area of the first conductive pattern 511 is greater than or equal to 4x106μm2when the power line 50 is a VSS line. In other examples, the area of the second conductive pattern 512 is greater than or equal to 4x106μm2when the power line 50 is a VSS line. In yet other examples, the area of both the first conductive pattern 511 and the second conductive pattern 512 is greater than or equal to 4x106μm2when the power line 50 is a VSS line.

[0176] In some implementations, the VSS line is located in the first source-drain metal layer 21.

[0177] In embodiments of the present disclosure, the VSS line, except for the second conductive pattern 512 of the first sub-line 51, can be located in the first source-drain metal layer 21. That is, compared with the related art, in embodiments of the present disclosure, the second conductive pattern 512 is newly added in the lead-out area B10 to realize double-layer wiring of the VSS line in the lead-out area B10. The area of the second conductive pattern 512, that is, the newly added area of the first sub-line 51 of the VSS line, is also increased compared with the related art.

[0178] With the above arrangement, the area of the part of the VSS line located in the lead-out area B10 (that is, the first sub-line 51) is increased, the signal transmission load on the first sub-line 51 is reduced, the stability of the signal transmitted on the first sub-line 51 is improved, and the display yield of the display panel 300 is ensured. The height of the lead-out area B10 can also be reduced, the frame size of the display panel 300 is reduced, and the narrow-frame design of the display panel 300 is facilitated.

[0179] In some embodiments, the power line is a VDD line.

[0180] In some examples, as shown in FIGS. 15 and 16, when the power line is a VDD line, the first sub-line 51 includes a third sub-portion 54 and a fourth sub-portion 55 connected to each other, the third sub-portion 54 extends along the first direction X, and the fourth sub-portion 55 extends along the second direction Y.

[0181] The fourth sub-portion 55 is closer to the display area AA than the third sub-portion 54, and part of the third sub-portion 54 is covered by the blocking dam 60. The first protective layer 70 covers the side surfaces of the fourth sub-portion 55 on opposite sides in the first direction X, and the side surfaces of the part of the third sub-portion 54 that is not covered by the blocking dam 60.

[0182] In some examples, the fourth sub-portion 55 is arranged to be offset from the orthogonal projection of the blocking dam 60 on the substrate 10, and the orthogonal projection of the third sub-portion 54 on the substrate 10 partially overlaps the orthogonal projection of the blocking dam 60 on the substrate 10.

[0183] In the embodiment, the side surface of the portion of the first sub-line 51 of the VDD line which is not covered by the blocking dam 60 is covered by the first protective layer 70, so that the probability of corrosion of the side surface of the first sub-line 51 of the VDD line caused by the development and etching process in the subsequent film layer forming process is reduced, the probability of the undercut structure of the side surface of the first sub-line 51 of the VDD line is reduced, the probability of the rupture of the encapsulation layer 40 is reduced, the encapsulation reliability of the display panel 300 is improved, the probability of the invasion of water vapor or oxygen and the like into the inside of the display panel 300 is reduced, the probability of the GDS defect of the display panel 300 is reduced, and thus the display effect of the display panel 300 is improved.

[0184] In some embodiments, in the case where the power line 50 is a VDD line, the area of at least one of the first conductive pattern 511 and the second conductive pattern 512 is greater than or equal to 8x106μm2. For example, in the case where the power line 50 is a VDD line, the area of at least one of the first conductive pattern 511 and the second conductive pattern 512 can be 8x106μm2.

[0185] In some examples, in the case where the power line 50 is a VDD line, the area of the first conductive pattern 511 is greater than or equal to 8x106μm2. In other examples, in the case where the power line 50 is a VDD line, the area of the second conductive pattern 512 is greater than or equal to 8x106μm2. In yet other examples, in the case where the power line 50 is a VDD line, the areas of the first conductive pattern 511 and the second conductive pattern 512 are both greater than or equal to 8x106μm2.

[0186] In some examples, in some implementations, the VDD line is located in the second source-drain metal layer 22.

[0187] For example, in the embodiments of the present disclosure, the remaining part of the VDD line except the first conductive pattern 511 of the first sub-line 51 can be located in the second source-drain metal layer 22. That is, compared with the related art, in the embodiments of the present disclosure, the first conductive pattern 511 is newly added in the lead-out area B10 to realize the double-layer wiring of the VDD line in the lead-out area B10. The area of the first conductive pattern 511, that is, the newly added area of the first sub-line 51 of the VDD line, is also increased compared with the related art.

[0188] With the above arrangement, the area of the part of the VDD line located in the lead-out area B10 (that is, the first sub-line 51) is increased, the signal transmission load on the first sub-line 51 is reduced, the stability of the signal transmitted on the first sub-line 51 is improved, the display yield of the display panel 300 is ensured, the height of the lead-out area B10 is also reduced, the frame size of the display panel 300 is reduced, and the narrow frame design of the display panel 300 is facilitated.

[0189] The above merely provides the specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto, any person skilled in the art can think of the changes or replacements within the technical range disclosed by the present disclosure, which should be covered in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A display panel, comprising a display area and a non-display area located around the display area, the non-display area comprising a lead-out area located at one side of the display area; the display panel comprising: a substrate; a power supply line located on the substrate, the power supply line comprising a first sub-line located in the lead-out area; the first sub-line comprising a first conductive pattern and a second conductive pattern which are sequentially and laminatedly arranged in a direction away from the substrate; a projection of the second conductive pattern on the substrate at least partially overlaps with a projection of the first conductive pattern on the substrate, and the first conductive pattern is electrically connected with the second conductive pattern; a first protective layer located at a side of the first sub-line away from the substrate; the first protective layer covering at least part of a side surface of the second conductive pattern of the first sub-line. 2.The display panel of claim 1, further comprising: a first source-drain metal layer and a second source-drain metal layer which are sequentially and laminatedly arranged in a direction away from the substrate; the first conductive pattern is located on the first source-drain metal layer, and the second conductive pattern is located on the second source-drain metal layer. 3.The display panel of claim 2, further comprising: a blocking dam located in the non-display area and arranged around the display area; part of the first sub-line is covered by the blocking dam; a side surface of a part of the second conductive pattern of the first sub-line which is not covered by the blocking dam is covered by the first protective layer. The material of the first protective layer comprises an inorganic material. 5.The display panel of claim 4, further comprising: a first passivation layer located at a side of the second source-drain metal layer away from the substrate; the first protective layer is located on the first passivation layer. The blocking dam comprises a first blocking layer; The first protective layer is the same material as the first blocking layer and is arranged in the same layer. 7.The display panel of claim 6, further comprising: a first planarization layer located between the first source-drain metal layer and the second source-drain metal layer; a second planarization layer located at a side of the second source-drain metal layer away from the substrate; the first protective layer and the first blocking layer of the blocking dam are located on the second planarization layer. 8.The display panel of claim 7, wherein a thickness of the second planarization layer is less than a thickness of the first planarization layer. The first conductive pattern is in direct contact with and electrically connected with the second conductive pattern. An edge part of the second conductive pattern covers a side surface of the first conductive pattern.

4. The display panel of claim 3, wherein, 11.The display panel of any one of claims 3-8, further comprising: a second protective layer located between the first conductive pattern and the second conductive pattern, the second protective layer covering a side surface of a part of the first conductive pattern which is not covered by the blocking dam. 12.The display panel of claim 11, further comprising: a second passivation layer located between the first source-drain metal layer and the second source-drain metal layer; the second protective layer is located on the second passivation layer. At least one first through hole is arranged on the second protective layer, and the second conductive pattern is electrically connected with the first conductive pattern through the at least one first through hole. ​ 6. The display panel of claim 3, wherein, ​ ​ ​ ​ ​ ​ ​ 9. The display panel according to any one of claims 3 to 8, wherein, ​ 10. The display panel of claim 9, wherein, ​ ​ ​ ​ ​ ​ 13. The display panel of claim 11 or 12, wherein, ​ 14. The display panel of claim 11 or 12, wherein, The second protective layer has a groove exposing a surface of the first conductive pattern away from the substrate.

15. The display panel according to any one of claims 3 to 14, wherein, The second conductive pattern has at least one second via hole in the area covered by the barrier dam.

16. The display panel according to any one of claims 1 to 15, wherein, The power line is a VSS line. The first sub-line includes a first sub-portion and a second sub-portion connected to each other, the first sub-portion extends in a first direction, and the second sub-portion extends in a second direction; the first direction is the arrangement direction of the display area and the lead-out area, and the first direction and the second direction intersect each other. The second sub-portion is closer to the display area than the first sub-portion, and part of the second sub-portion is covered by the barrier dam; the first protective layer covers the side surfaces of the first sub-portion on two opposite sides in the second direction, and the side surfaces of the part of the second sub-portion which is not covered by the barrier dam.

17. The display panel of claim 16, wherein, an area of at least one of the first conductive pattern and the second conductive pattern is equal to 4 x 10 6 μm 2 .

18. The display panel according to any one of claims 1 to 15, wherein, The power line is a VDD line. The first sub-line includes a third sub-portion and a fourth sub-portion connected to each other, the third sub-portion extends in a first direction, and the fourth sub-portion extends in a second direction; the first direction is the arrangement direction of the display area and the lead-out area, and the first direction and the second direction intersect each other. The fourth sub-portion is closer to the display area than the third sub-portion, and part of the third sub-portion is covered by the barrier dam; the first protective layer covers the side surfaces of the fourth sub-portion on two opposite sides in the first direction, and the side surfaces of the part of the third sub-portion which is not covered by the barrier dam.

19. The display panel of claim 18, wherein, An area of at least one of the first conductive pattern and the second conductive pattern is greater than or equal to 8 x 10 6 μm 2 .

20. A display device, comprising: The display panel according to any one of claims 1-19; A circuit board electrically connected to the display panel.

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