Display substrate and display device

Abstract

A display substrate and a display device, the display substrate comprising a substrate and a plurality of pixel units (P) and at least one type of initial signal line (Vinit) disposed on one side of the substrate; in at least part of the type of initial signal line (Vinit), the same type of initial signal line (Vinit) comprises at least two types of initial signal lines; in at least part of the pixel units (P), the same pixel unit P comprises at least two types of sub-pixels (Pxij); in the same type of initial signal line Vinit, each type of initial signal line (Vinit) is connected with at least one type of sub-pixel (Pxij) in the pixel unit (P), and different types of initial signal lines (Vinit) are connected with different types of sub-pixels (Pxij) in the pixel unit (P).

Description

Display substrate and display device TECHNICAL FIELD

[0001] The present disclosure relates to, but is not limited to, the technical field of display, and in particular, to a display substrate and a display device. BACKGROUND

[0002] Organic light emitting diode (OLED) and quantum dot light emitting diode (QLED) are active light emitting display devices, which have the advantages of self-emission, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, flexibility, and low cost. With the continuous development of display technology, flexible display devices using OLED or QLED as light emitting devices and controlled by thin film transistors (TFT) have become the mainstream products in the current display field.

[0003] SUMMARY

[0004] The subject matter of the present text is outlined in this summary. This summary is not intended to limit the scope of protection of the claims.

[0005] In a first aspect, the embodiments of the present disclosure provide a display substrate, comprising: a substrate, and a plurality of pixel units and at least one type of initial signal line arranged on one side of the substrate; in at least part of the type of initial signal line, the same type of initial signal line comprises at least two types of initial signal lines; in at least part of the pixel units, the same pixel unit comprises at least two types of sub-pixels.

[0006] In the same type of initial signal line, each type of initial signal line is connected to at least one type of sub-pixel in the pixel unit, and different types of initial signal lines are connected to different types of sub-pixels in the pixel unit.

[0007] In an exemplary embodiment, in at least part of the pixel units, the types of sub-pixels in the same pixel unit at least include a first sub-pixel, a second sub-pixel, and a third sub-pixel.

[0008] In at least part of the type of initial signal line, the same type of initial signal line at least includes a first type of initial signal line and a second type of initial signal line; the first type of initial signal line is connected to at least one of the first sub-pixel and the second sub-pixel, and is arranged to provide an initial signal to at least one of the first sub-pixel and the second sub-pixel; the second type of initial signal line is connected to the third sub-pixel, and is arranged to provide an initial signal to the third sub-pixel.

[0009] In an exemplary embodiment, in the at least partially type of initial signal lines, the same type of initial signal lines further includes a third type of initial signal line, the first type of initial signal line is connected with one of the first sub-pixel and the second sub-pixel; the third type of initial signal line is connected with the other of the first sub-pixel and the second sub-pixel.

[0010] In an exemplary embodiment, at least part of the sub-pixels includes a pixel driving circuit, and at least part of the pixel driving circuit includes a plurality of transistors and at least one capacitor;

[0011] In a direction perpendicular to a plane on which the substrate is located, the capacitor includes a first plate located on a side of the substrate, and a second plate located on a side of the first plate away from the substrate; the transistor includes an active layer located on a side of the second plate away from the substrate, a control electrode located on a side of the active layer away from the substrate, a first electrode and a second electrode located on a side of the control electrode away from the substrate.

[0012] In an exemplary embodiment, the type of the initial signal line at least includes a second initial signal line, at least part of the sub-pixels includes an anode, and in a direction perpendicular to a plane on which the substrate is located, the anode is located on a side of the first electrode and the second electrode away from the substrate; the plurality of transistors includes a seventh transistor as a reset transistor, a first electrode of the seventh transistor is connected with the second initial signal line of the corresponding type, and a second electrode of the seventh transistor is connected with the anode;

[0013] The plurality of pixel units form a plurality of rows, the second initial signal line is connected with the first electrode of the seventh transistor of at least part of the sub-pixels in one of the rows of pixel units, and is configured to provide the second initial signal to the corresponding anode under the control of at least part of the seventh transistors in the row of pixel units;

[0014] The second initial signal line is arranged in the same layer as one of the first plate and the second plate, or is arranged in the same layer as the first electrode and the second electrode.

[0015] In an exemplary embodiment, the type of the second initial signal line at least includes a first type of second initial signal line and a second type of second initial signal line;

[0016] The first type of second initial signal line is connected with at least one of the first electrode of the seventh transistor of the first sub-pixel and the first electrode of the seventh transistor of the second sub-pixel in one of the rows of pixel units, and is configured to provide the initial signal to the corresponding anode under the control of at least one of the seventh transistor of the first sub-pixel and the seventh transistor of the second sub-pixel in the row of pixel units;

[0017] The second second initial signal line of the second kind is connected with the first electrode of the seventh transistor of the third sub-pixel in one row of pixel units, and is configured to provide an initial signal to the anode of the third sub-pixel in the row of pixel units under the control of the seventh transistor of the third sub-pixel in the row of pixel units.

[0018] The second second initial signal line of the second kind is arranged in the same layer as one of the first electrode plate and the second electrode plate, or arranged in the same layer as the first electrode and the second electrode.

[0019] In an exemplary embodiment, in the structure in which the second second initial signal line of the second kind is arranged in the same layer as one of the first electrode plate and the second electrode plate, the first second initial signal line of the first kind is arranged in the same layer as the first electrode and the second electrode.

[0020] In the structure in which the second second initial signal line of the second kind is arranged in the same layer as the first electrode and the second electrode, the first second initial signal line of the first kind is arranged in the same layer as the first electrode and the second electrode, or arranged in the same layer as one of the first electrode plate and the second electrode.

[0021] In an exemplary embodiment, in the structure in which the first second initial signal line of the first kind and the second second initial signal line of the second kind are arranged in different layers, the orthographic projection of the first second initial signal line of the first kind and the second second initial signal line of the second kind on the substrate at least partially overlaps.

[0022] In an exemplary embodiment, the display substrate can further include at least one first second initial signal connection line and at least one second second initial signal connection line, and the first second initial signal connection line and the second second initial signal connection line are located on the side of the first electrode and the second electrode away from the substrate and on the side of the anode close to the substrate in the direction perpendicular to the plane in which the substrate is located.

[0023] The first second initial signal connection line is connected with at least one first second initial signal line, and the second second initial signal connection line is connected with at least one second second initial signal line.

[0024] In an exemplary embodiment, the kind of the second initial signal line further includes a third second initial signal line.

[0025] The first second initial signal line is connected with the first electrode of the seventh transistor of the first sub-pixel in one of the rows of pixel units, and is configured to provide an initial signal to the anode of the first sub-pixel in the row of pixel units under the control of the seventh transistor of the first sub-pixel in the row of pixel units; and the third second initial signal line is connected with the first electrode of the seventh transistor of the second sub-pixel in one of the rows of pixel units, and is configured to provide an initial signal to the anode of the third sub-pixel in the row of pixel units under the control of the seventh transistor of the second sub-pixel in the row of pixel units.

[0026] In the structure in which the second second initial signal line is arranged in the same layer as the first electrode and the second electrode, one of the first second initial signal line and the third second initial signal line is arranged in the same layer as one of the first electrode plate and the second electrode plate, and the other is arranged in the same layer as the first electrode and the second electrode or the other of the first electrode plate and the second electrode plate.

[0027] In the structure in which the second second initial signal line is arranged in the same layer as one of the first electrode plate and the second electrode plate, the first second initial signal line and the third second initial signal line are arranged in the same layer as the first electrode and the second electrode, or one of the first second initial signal line and the third second initial signal line is arranged in the same layer as the first electrode and the second electrode, and the other is arranged in the same layer as the other of the first electrode plate and the second electrode plate.

[0028] In an exemplary embodiment, the display substrate can further include a third second initial signal connection line, which is located on the side of the first electrode and the second electrode away from the substrate and on the side of the anode close to the substrate in the direction perpendicular to the plane in which the substrate is located.

[0029] The third second initial signal connection line is connected with at least one third second initial signal line.

[0030] In an exemplary embodiment, the types of the initial signal lines include at least a first initial signal line.

[0031] The plurality of transistors include a driving transistor and a first transistor as a reset transistor, the first electrode of the first transistor is connected with the first initial signal line, and the second electrode of the first transistor is connected with the control electrode of the driving transistor.

[0032] The plurality of pixel units form a plurality of rows, and the first initial signal line is connected to the first electrode of the first transistor of at least some of the sub-pixels in one row of the pixel units, and is configured to provide an initial signal to the control electrode of the corresponding driving transistor under the control of at least some of the first transistors in the row of pixel units.

[0033] The first initial signal line is arranged in the same layer as the first electrode and the second electrode, or is arranged in the same layer as the control electrode.

[0034] In an exemplary embodiment, the first initial signal line includes a first first initial signal line and a second first initial signal line.

[0035] The first first initial signal line is connected to at least one of the first electrode of the first transistor of the first sub-pixel and the first electrode of the first transistor of the second sub-pixel in one row of the pixel units, and is configured to provide an initial signal to the control electrode of the corresponding driving transistor under the control of at least one of the first transistor of the first sub-pixel and the first transistor of the second sub-pixel in the row of pixel units.

[0036] The second first initial signal line is connected to the first electrode of the first transistor of the third sub-pixel in one row of the pixel units, and is configured to provide an initial signal to the control electrode of the driving transistor of the third sub-pixel in the row of pixel units under the control of the first transistor of the third sub-pixel.

[0037] One of the first first initial signal line and the second first initial signal line is arranged in the same layer as the control electrode, and the other is arranged in the same layer as the first electrode and the second electrode.

[0038] In an exemplary embodiment, the display substrate can further include at least one first first initial signal connection line and at least one second first initial signal connection line, and the first first initial signal connection line and the second first initial signal connection line are located on the side of the anode close to the substrate and on the side of the first electrode and the second electrode away from the substrate in a direction perpendicular to the plane in which the substrate is located.

[0039] The first first initial signal connection line is connected to at least one first first initial signal line, and the second first initial signal connection line is connected to at least one second first initial signal line.

[0040] In an exemplary embodiment, the first initial signal line further includes a third first initial signal line.

[0041] The first initial signal line of the first kind is connected to the first electrode of the first transistor of the first sub-pixel in one of the rows of pixel units, and is configured to provide an initial signal to the control electrode of the drive transistor of the first sub-pixel in the row of pixel units under the control of the first transistor of the first sub-pixel in the row of pixel units; and the first initial signal line of the third kind is connected to the first electrode of the first transistor of the second sub-pixel in one of the rows of pixel units, and is configured to provide an initial signal to the control electrode of the drive transistor of the second sub-pixel in the row of pixel units under the control of the first transistor of the second sub-pixel in the row of pixel units.

[0042] The first initial signal line of the third kind is arranged in the same layer as the control electrode, or arranged in the same layer as the first electrode and the second electrode.

[0043] In an exemplary embodiment, the display substrate further comprises at least one third kind of first initial signal connection line, which is located on the side of the first electrode and the second electrode away from the substrate in the direction perpendicular to the plane on which the substrate is located.

[0044] The third kind of first initial signal connection line is connected to at least one first initial signal line of the third kind.

[0045] In an exemplary embodiment, the plurality of transistors further comprises a second transistor as a reset transistor, and the at least one capacitor comprises a first capacitor and a second capacitor.

[0046] The first electrode of the second transistor is connected to the first initial signal line, the second electrode of the second transistor is connected to the first electrode plate of the first capacitor and the first electrode plate of the second capacitor, the second electrode plate of the first capacitor is connected to the second electrode of the first transistor and the control electrode of the drive transistor, and the second electrode plate of the second capacitor is connected to the second electrode of the drive transistor.

[0047] The first initial signal line is further connected to the first electrode of the second transistor of at least part of the sub-pixels in one of the rows of pixel units, and is configured to provide an initial signal to the first electrode plate of the first capacitor and the first electrode plate of the second capacitor in the corresponding sub-pixel under the control of at least part of the second transistors in the row of pixel units.

[0048] In an exemplary embodiment, in the same pixel unit, the first electrode of the first transistor and the first electrode of the second transistor are connected to the same kind of first initial signal line.

[0049] In an exemplary embodiment, the display substrate further comprises a plurality of first power supply connection lines and a plurality of first power supply lines, and the plurality of transistors comprises a fifth transistor as a light-emitting control transistor and a drive transistor.

[0050] The first power connection line is arranged in the same layer as the first electrode and the second electrode, and the first power line is located on the side of the first power connection line away from the substrate in the direction perpendicular to the plane on which the substrate lies, the first power connection line is connected with the first electrode of the fifth transistor, and is arranged to provide a first power signal to the fifth transistor; the at least partial first power line and the at least partial first power connection line are connected to form a grid structure through a via.

[0051] The first electrode of the fifth transistor is connected with the first power connection line, and the second electrode of the fifth transistor is connected with the first electrode of the driving transistor.

[0052] In an exemplary embodiment, the display substrate further comprises a plurality of second power connection lines and a plurality of second power lines.

[0053] The second power connection line is arranged in the same layer as the first electrode and the second electrode, and the second power line is located on the side of the second power connection line away from the substrate and on the side of the anode close to the substrate in the direction perpendicular to the plane on which the substrate lies, and the at least partial second power line and the at least partial second power connection line are connected to form a grid structure through a via.

[0054] In an exemplary embodiment, the first sub-pixel is a light-emitting unit emitting red light, the second sub-pixel is a light-emitting unit emitting green light, and the third sub-pixel is a light-emitting unit emitting blue light.

[0055] In an exemplary embodiment, the plurality of transistors are oxide transistors.

[0056] In a second aspect, the embodiments of the present disclosure further provide a display device comprising the display substrate described in any of the above embodiments.

[0057] Other aspects can become apparent from a review of the drawings and detailed description. BRIEF DESCRIPTION OF DRAWINGS

[0058] The accompanying drawings are included to provide a further understanding of the technical solutions of the present disclosure, and constitute a part of the specification, and are used to explain the technical solutions of the present disclosure together with the embodiments of the present disclosure, and do not constitute a limitation on the technical solutions of the present disclosure. The shape and size of each component in the drawings do not reflect the true proportion, and the purpose is only to schematically illustrate the present disclosure.

[0059] FIG. 1 is a structural schematic diagram of a display device;

[0060] FIG. 2 is a structural schematic diagram of a display substrate;

[0061] FIG. 3 is a schematic diagram of the cross-sectional structure of a display substrate;

[0062] Fig. 4 is a schematic diagram of an equivalent circuit of a pixel driving circuit;

[0063] Fig. 5a is a schematic diagram of a structure of a display substrate according to an embodiment of the present disclosure;

[0064] Fig. 5b is a schematic diagram of a structure of a display substrate according to an embodiment of the present disclosure;

[0065] Fig. 5c is a schematic diagram of a planar structure of a display substrate according to an exemplary embodiment of the present disclosure;

[0066] Fig. 5d is a schematic diagram of a planar structure of a fifth conductive layer in a display substrate according to an exemplary embodiment of the present disclosure;

[0067] Fig. 6a is a schematic diagram of an equivalent circuit of a pixel driving circuit according to an exemplary embodiment of the present disclosure;

[0068] Fig. 6b is a schematic diagram of an equivalent circuit of a pixel driving circuit according to an exemplary embodiment of the present disclosure;

[0069] Fig. 6c is a schematic diagram of an equivalent circuit of a pixel driving circuit according to an exemplary embodiment of the present disclosure;

[0070] Fig. 6d is a schematic diagram of an equivalent circuit of a pixel driving circuit according to an exemplary embodiment of the present disclosure;

[0071] Fig. 6e is a schematic diagram of an equivalent circuit of a pixel driving circuit according to an exemplary embodiment of the present disclosure;

[0072] Fig. 6f is a schematic diagram of an equivalent circuit of a pixel driving circuit according to an exemplary embodiment of the present disclosure;

[0073] Fig. 6g is a schematic diagram of an equivalent circuit of a pixel driving circuit in a pixel unit according to an exemplary embodiment of the present disclosure;

[0074] Fig. 6h is a schematic diagram of an equivalent circuit of a pixel driving circuit in a pixel unit according to an exemplary embodiment of the present disclosure;

[0075] Fig. 7 is a schematic diagram of a display substrate after a first conductive layer pattern is formed according to an exemplary embodiment of the present disclosure;

[0076] Fig. 8a is a schematic diagram of a display substrate after a second conductive layer pattern is formed according to an exemplary embodiment of the present disclosure;

[0077] Fig. 8b is a schematic diagram of a second conductive layer in a display substrate according to an exemplary embodiment of the present disclosure;

[0078] FIG. 9a shows a schematic diagram of a display substrate after forming a semiconductor layer pattern according to an exemplary embodiment of the present disclosure;

[0079] FIG. 9b shows a schematic diagram of a semiconductor layer in a display substrate according to an exemplary embodiment of the present disclosure;

[0080] FIG. 10a shows a schematic diagram of a display substrate after forming a third conductive layer pattern according to an exemplary embodiment of the present disclosure;

[0081] FIG. 10b shows a schematic diagram of a third conductive layer in a display substrate according to an exemplary embodiment of the present disclosure;

[0082] FIG. 11 shows a schematic diagram of a display substrate after forming a fourth insulating layer pattern according to an exemplary embodiment of the present disclosure;

[0083] FIG. 12a shows a schematic diagram of a display substrate after forming a fourth conductive layer pattern according to an exemplary embodiment of the present disclosure;

[0084] FIG. 12b shows a schematic diagram of a fourth conductive layer in a display substrate according to an exemplary embodiment of the present disclosure;

[0085] FIG. 13 shows a schematic diagram of a display substrate after forming a first planarization layer pattern according to an exemplary embodiment of the present disclosure;

[0086] FIG. 14a shows a schematic diagram of a display substrate after forming a fifth conductive layer pattern according to an exemplary embodiment of the present disclosure;

[0087] FIG. 14b shows a schematic diagram of a fifth conductive layer in a display substrate according to an exemplary embodiment of the present disclosure;

[0088] FIG. 15 shows a schematic diagram of a display substrate after forming a second planarization layer pattern according to an exemplary embodiment of the present disclosure;

[0089] FIG. 16a shows a schematic diagram of a display substrate after forming an anode conductive layer pattern according to an exemplary embodiment of the present disclosure;

[0090] FIG. 16b shows a schematic diagram of an anode conductive layer in a display substrate according to an exemplary embodiment of the present disclosure;

[0091] FIG. 17a shows a schematic diagram of a display substrate after forming a pixel definition layer pattern according to an exemplary embodiment of the present disclosure;

[0092] FIG. 17b shows a schematic diagram of a pixel definition layer pattern in a display substrate according to an exemplary embodiment of the present disclosure;

[0093] FIG. 18 shows a schematic diagram of a display substrate after forming a first conductive layer pattern according to an exemplary embodiment of the present disclosure;

[0094] FIG. 19a is a schematic view of a display substrate after forming a semiconductor layer pattern according to an exemplary embodiment of the present disclosure;

[0095] FIG. 19b is a schematic view of a semiconductor layer in a display substrate according to an exemplary embodiment of the present disclosure;

[0096] FIG. 20 is a schematic view of a display substrate after forming a fourth insulating layer pattern according to an exemplary embodiment of the present disclosure;

[0097] FIG. 21a is a schematic view of a display substrate after forming a fourth conductive layer pattern according to an exemplary embodiment of the present disclosure;

[0098] FIG. 21b is a schematic view of a fourth conductive layer in a display substrate according to an exemplary embodiment of the present disclosure;

[0099] FIG. 22 is a schematic view of forming a first planarization layer pattern according to an exemplary embodiment of the present disclosure;

[0100] FIG. 23a is a schematic view of a display substrate after forming a fifth conductive layer pattern according to an exemplary embodiment of the present disclosure;

[0101] FIG. 23b is a schematic view of a fifth conductive layer in a display substrate according to an exemplary embodiment of the present disclosure;

[0102] FIG. 23c is a schematic view of a display substrate after forming an anode conductive layer pattern according to an exemplary embodiment of the present disclosure;

[0103] FIG. 24a is a schematic view of a display substrate after forming a semiconductor layer pattern according to an exemplary embodiment of the present disclosure;

[0104] FIG. 24b is a schematic view of a semiconductor layer in a display substrate according to an exemplary embodiment of the present disclosure;

[0105] FIG. 25 is a schematic view of a display substrate after forming a fourth insulating layer pattern according to an exemplary embodiment of the present disclosure;

[0106] FIG. 26a is a schematic view of a display substrate after forming a fourth conductive layer pattern according to an exemplary embodiment of the present disclosure;

[0107] FIG. 26b is a schematic view of a fourth conductive layer in a display substrate according to an exemplary embodiment of the present disclosure;

[0108] FIG. 27 is a schematic view of forming a first planarization layer pattern according to an exemplary embodiment of the present disclosure;

[0109] FIG. 28a is a schematic view of a display substrate after forming a fifth conductive layer pattern according to an example embodiment of the present disclosure;

[0110] FIG. 28b is a schematic view of a fifth conductive layer in a display substrate according to an example embodiment of the present disclosure;

[0111] FIG. 28c is a schematic view of a display substrate after forming an anode conductive layer pattern according to an example embodiment of the present disclosure;

[0112] FIG. 29 is a schematic view of a display device according to an example embodiment of the present disclosure. DETAILED DESCRIPTION

[0113] Embodiments of the present disclosure will be described in detail below with reference to the drawings. The embodiments can be implemented in various forms. It will be readily understood by those skilled in the art that the modes and contents can be changed into various forms without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure should not be construed as being limited to the contents described in the following embodiments. The embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other without conflict unless otherwise specified. In order to keep the following description of the embodiments of the present disclosure clear and concise, detailed description of some known functions and known components will be omitted. The drawings of the embodiments of the present disclosure only involve structures related to the embodiments of the present disclosure, and other structures can be referred to the generally designed structures

[0114] The scale of the drawings in the present disclosure can be used as a reference in the actual process, but is not limited thereto. For example, the thickness and interval of each film layer, the width and interval of each signal line, can be adjusted according to the actual situation. The drawings described in the present disclosure are only schematic views, and one mode of the present disclosure is not limited to the shapes or values shown in the drawings.

[0115] In the present specification, ordinal numbers such as "first", "second", "third", and the like are provided to avoid confusion of the components, and are not intended to be limiting in terms of quantity.

[0116] In the present specification, in order to facilitate the description, words indicating the orientation or positional relationship such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like are used to describe the positional relationship of the components with reference to the drawings, and are only for the convenience of the description of the present specification and simplification of the description, and are not intended to indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present disclosure. The positional relationship of the components is appropriately changed according to the direction of describing each component. Therefore, it is not limited to the words described in the specification, and can be appropriately changed according to the situation.

[0117] In this specification, unless otherwise explicitly specified and limited, the terms "mount", "connected", and "linked" are to be interpreted broadly. For example, it can be a fixed connection, or a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection via an intermediate element, or a communication inside two elements. The specific meaning of the above terms in the present disclosure can be understood according to the context.

[0118] In this specification, a transistor refers to an element including at least a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (a drain electrode terminal, a drain region, or a drain electrode) and a source electrode (a source electrode terminal, a source region, or a source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to a region where current flows mainly.

[0119] In this specification, the first electrode can be a drain electrode and the second electrode can be a source electrode, or the first electrode can be a source electrode and the second electrode can be a drain electrode. In the case of using a transistor with opposite polarity or in the case where the direction of current flow is changed in the operation of a circuit, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged with each other. Therefore, in this specification, the "source electrode" and the "drain electrode" can be interchanged with each other, and the "source terminal" and the "drain terminal" can be interchanged with each other. In this embodiment of the disclosure, a gate electrode can be referred to as a control electrode.

[0120] In this specification, "electrically connected" includes the case where elements are connected through an element having a certain electrical action. The element having a certain electrical action is not particularly limited as long as it can transmit or receive an electrical signal between elements to be connected. Examples of the element having a certain electrical action include not only an electrode and a wiring but also a switching element such as a transistor, a resistor, an inductor, a capacitor, and another element having a variety of functions.

[0121] In this specification, "parallel" refers to a state where an angle formed between two straight lines is greater than or equal to -10° and less than or equal to 10°, and thus a state where the angle is greater than or equal to -5° and less than or equal to 5° is also included. In addition, "perpendicular" refers to a state where an angle formed between two straight lines is greater than or equal to 80° and less than or equal to 100°, and thus a state where the angle is greater than or equal to 85° and less than or equal to 95° is also included.

[0122] In this specification, "film" and "layer" can be interchanged with each other. For example, "a conductive layer" can be replaced with "a conductive film". Similarly, "an insulating film" can be replaced with "an insulating layer".

[0123] In the specification, the triangle, rectangle, trapezoid, pentagon or hexagon, etc. are not strictly, and can be approximately triangle, rectangle, trapezoid, pentagon or hexagon, etc. There can be some small deformation caused by tolerance, there can be an angle, an arc edge and deformation, etc.

[0124] In the embodiments of the present disclosure, "about" means not strictly limited to the limit, and allows the value within the range of process and measurement error.

[0125] FIG. 1 shows a structural schematic diagram of a display device, a display substrate can include a timing controller, a data signal driving circuit, a scan signal driving circuit, a light emission signal driving circuit, and a pixel array, the timing controller is connected with the data signal driving circuit, the scan signal driving circuit, and the light emission signal driving circuit respectively, the data signal driving circuit is connected with a plurality of data signal lines (D1 to Dn) respectively, the scan signal driving circuit is connected with a plurality of scan signal lines (G1 to Gm) respectively, and the light emission signal driving circuit is connected with a plurality of light emission signal lines (E1 to Eo) respectively. The pixel array can include a plurality of sub-pixels Pxij, i and j can be natural numbers, at least one sub-pixel Pxij can include a circuit unit and a light emitting device connected with the circuit unit, the circuit unit can include a pixel driving circuit, and the pixel driving circuit can be connected with a scan signal line, a light emission signal line, and a data signal line (which can be referred to as a data line) respectively. In an exemplary embodiment, the timing controller can provide a gray value and a control signal suitable for the specification of the data signal driving circuit to the data signal driving circuit, can provide a clock signal, a scan start signal, and the like suitable for the specification of the scan signal driving circuit to the scan signal driving circuit, and can provide a clock signal, an emission stop signal, and the like suitable for the specification of the light emission signal driving circuit to the light emission signal driving circuit. The data signal driving circuit can generate a data voltage to be provided to the data signal lines D1, D2, D3, …, and Dn using the gray value and the control signal received from the timing controller. For example, the data signal driving circuit can sample the gray value using the clock signal, and apply a data voltage corresponding to the gray value to the data signal lines D1 to Dn in units of a pixel row. n can be a natural number. The scan signal driving circuit can generate a scan signal to be provided to the scan signal lines G1, G2, G3, …, and Gm by receiving the clock signal, the scan start signal, and the like from the timing controller. For example, the scan signal driving circuit can sequentially provide the scan signal having an on-level pulse to the scan signal lines G1 to Gm. For example, the scan signal driving circuit can be configured in the form of a shift register, and can generate the scan signal in a manner of sequentially transferring the scan start signal provided in the form of an on-level pulse to a next stage circuit under the control of the clock signal. m can be a natural number. The light emission signal driving circuit can generate an emission signal to be provided to the light emission signal lines E1, E2, E3, …, and Eo by receiving the clock signal, the emission stop signal, and the like from the timing controller. For example, the light emission signal driving circuit can sequentially provide the emission signal having an off-level pulse to the light emission signal lines E1 to Eo. For example, the light emission driver can be configured in the form of a shift register, and can generate the emission signal in a manner of sequentially transferring the emission stop signal provided in the form of an off-level pulse to a next stage circuit under the control of the clock signal. o can be a natural number.

[0126] FIG. 2 is a schematic diagram of a planar structure of a display substrate. As shown in FIG. 2, the display substrate can include a plurality of pixel units P arranged in a matrix manner, at least one of the plurality of pixel units P including a first sub-pixel P1 emitting first color light, a second sub-pixel P2 emitting second color light, and a third sub-pixel P3 emitting third color light, the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 each including a pixel driving circuit and a light emitting device. The pixel driving circuit in the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 is respectively connected with a scan signal line, a data signal line, and a light emitting signal line, and is configured to receive a data voltage transmitted by the data signal line under the control of the scan signal line and the light emitting signal line, and output a corresponding current to the light emitting device. The light emitting device in the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 is respectively connected with the pixel driving circuit in the sub-pixel where the light emitting device is located, and is configured to emit light with a corresponding brightness in response to the current output by the pixel driving circuit in the sub-pixel where the light emitting device is located.

[0127] In an example embodiment, the pixel unit P can include a red (R) sub-pixel, a green (G) sub-pixel, and a blue (B) sub-pixel. In an example embodiment, the shape of the sub-pixels in the pixel unit can be rectangular, diamond, pentagonal, or hexagonal, and the three sub-pixels can be arranged in a horizontal parallel, vertical parallel, or triangular manner, which is not limited in the present disclosure.

[0128] FIG. 3 is a schematic diagram of a cross-sectional structure of a display substrate, illustrating the structure of three sub-pixels of an OLED display substrate. As shown in FIG. 3, in a plane perpendicular to the display substrate, the display substrate can include a driving circuit layer 102 disposed on a substrate 101, a light emitting structure layer 103 disposed on a side of the driving circuit layer 102 away from the substrate 101, and an encapsulation layer 104 disposed on a side of the light emitting structure layer 103 away from the substrate 101. In some possible implementations, the display substrate can include other film layers, such as a spacer, which is not limited in the present disclosure.

[0129] In the example embodiment, the substrate 101 can be a flexible substrate, or can be a rigid substrate. The driving circuit layer 102 of each sub-pixel can include a plurality of transistors and a storage capacitor constituting a pixel driving circuit. The light-emitting structure layer 103 can include an anode 301 connected to the drain electrode of the driving transistor 210 through a via, an organic light-emitting layer 302 connected to the anode 301, and a cathode 303 connected to the organic light-emitting layer 302, the organic light-emitting layer 302 emitting light of a corresponding color under the driving of the anode 301 and the cathode 303. The encapsulation layer 104 can include a first encapsulation layer 401, a second encapsulation layer 402, and a third encapsulation layer 403 stacked together, the first encapsulation layer 401 and the third encapsulation layer 403 can be made of inorganic material, the second encapsulation layer 402 can be made of organic material, and the second encapsulation layer 402 is arranged between the first encapsulation layer 401 and the third encapsulation layer 403, so as to prevent external water vapor from entering the light-emitting structure layer 103.

[0130] In the example embodiment, the organic light-emitting layer 302 can include a hole injection layer (HIL), a hole transport layer (HTL), an electron block layer (EBL), an emitting layer (EML), a hole block layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL) stacked together. In the example embodiment, the hole injection layer of all sub-pixels can be a common layer connected together, the electron injection layer of all sub-pixels can be a common layer connected together, the hole transport layer of all sub-pixels can be a common layer connected together, the electron transport layer of all sub-pixels can be a common layer connected together, the hole block layer of all sub-pixels can be a common layer connected together, the emitting layer of adjacent sub-pixels can have a small amount of overlap, or can be isolated, and the electron block layer of adjacent sub-pixels can have a small amount of overlap, or can be isolated.

[0131] In an exemplary embodiment, the pixel driving circuit can be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, 8T1C or 7T2C structure. FIG. 4 is a schematic diagram of an equivalent circuit of a pixel driving circuit. As shown in FIG. 4, the pixel driving circuit can include 7 transistors (first transistor T1 to seventh transistor T7) and 2 capacitors C (first capacitor C1 and second capacitor C2), and can be connected with 11 signal lines (data signal line D, scan signal line Gate, first reset control line Reset1, second reset control line Reset2, third reset control line Reset3, first emission control line EM1, second emission control line EM2, first initial signal line Vinit1, second initial signal line Vinit2, first power supply line VDD and second power supply line VSS).

[0132] In an exemplary embodiment, the pixel driving circuit can include a first node N1, a second node N2, a third node N3, a fourth node N4 and a fifth node N5. The first node N1 is connected with the control electrode of the third transistor T3, the second electrode of the fourth transistor T4, the second end of the second capacitor C2 and the second electrode of the first transistor T1 respectively. The second node N2 is connected with the first electrode of the third transistor T3 and the second electrode of the fifth transistor T5 respectively. The third node N3 is connected with the second end of the first capacitor C1, the second electrode of the third transistor T3 and the first electrode of the sixth transistor T6 respectively. The fourth node N4 is connected with the first end of the first capacitor C1, the first end of the second capacitor C2 and the second electrode of the second transistor T2 respectively. The fifth node N5 is connected with the second electrode of the sixth transistor T6, the second electrode of the seventh transistor T7 and the anode of the light emitting device EL respectively.

[0133] In an exemplary embodiment, the first end of the first capacitor C1 is connected with the fourth node N4, and the second end of the first capacitor C1 is connected with the third node N3. The first end of the second capacitor C2 is connected with the fourth node N4, and the second end of the second capacitor C2 is connected with the first node N1.

[0134] The control electrode of the first transistor T1 is connected with the first reset control line Reset1, the first electrode of the first transistor T1 is connected with the first initial signal line Vinit1, and the second electrode of the first transistor is connected with the first node N1. When the turn-on level reset signal is applied to the first reset control line Reset1, the first transistor T1 transmits the initialization voltage to the control electrode of the third transistor T3, so as to initialize the charge amount of the control electrode of the third transistor T3.

[0135] The control electrode of the second transistor T2 is connected with the second reset control line Reset2, the first electrode of the second transistor T2 is connected with the first initial signal line Vinit1, and the second electrode of the second transistor T2 is connected with the fourth node N4.

[0136] The control electrode of the third transistor T3 is connected to the first node N1, the first electrode of the third transistor T3 is connected to the second node N2, and the second electrode of the third transistor T3 is connected to the third node N3. The third transistor T3 can be referred to as a drive transistor, and the third transistor T3 determines the amount of drive current flowing between the first power supply line VDD and the second power supply line VSS according to a potential difference between the control electrode and the first electrode thereof.

[0137] The control electrode of the fourth transistor T4 is connected to the scan signal line Gate, the first electrode of the fourth transistor T4 is connected to the data signal line D, and the second electrode of the fourth transistor T4 is connected to the first node N1. The fourth transistor T4 can be referred to as a switch transistor, and the fourth transistor T4 inputs a data voltage of the data signal line D to the pixel drive circuit when an on-level scan signal is applied to the scan signal line Gate.

[0138] The control electrode of the fifth transistor T5 is connected to the first emission control line EM1, the first electrode of the fifth transistor T5 is connected to the first power supply line VDD, and the second electrode of the fifth transistor T5 is connected to the second node N2. The control electrode of the sixth transistor T6 is connected to the second emission control line EM2, the first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the first electrode of the light emitting device (also the fifth node N5). The fifth transistor T5 and the sixth transistor T6 can be referred to as emission transistors. When on-level emission signals are applied to the first emission control line EM1 and the second emission control line EM2, the fifth transistor T5 and the sixth transistor T6 are turned on, forming a drive current path between the first power supply line VDD and the second power supply line VSS to cause the light emitting device to emit light.

[0139] The control electrode of the seventh transistor T7 is connected to the third reset control line Reset3, the first electrode of the seventh transistor T7 is connected to the second initial signal line Vinit2, and the second electrode of the seventh transistor T7 is connected to the first electrode of the light emitting device (also the fifth node N5). When an on-level reset signal is applied to the third reset control line Reset3, the seventh transistor T7 transmits an initialization voltage to the first electrode of the light emitting device to initialize the amount of charge accumulated in the first electrode of the light emitting device or release the amount of charge accumulated in the first electrode of the light emitting device.

[0140] In an example embodiment, the second electrode of the light emitting device is connected to a second power line VSS, and the signal of the second power line VSS is a low level signal, and the signal of the first power line VDD is a high level signal continuously provided. In an example embodiment, the first transistor T1 to the seventh transistor T7 can be P-type transistors, or can be N-type transistors. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the yield of the product. In some possible implementations, the first transistor T1 to the seventh transistor T7 can include P-type transistors and N-type transistors.

[0141] In an example embodiment, the first transistor T1 to the seventh transistor T7 can be low temperature poly-silicon thin film transistors (which can be referred to as P-type transistors), or can be oxide thin film transistors (which can be referred to as N-type transistors), or can be low temperature poly-silicon thin film transistors and oxide thin film transistors. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the yield of the product. The active layer of the low temperature poly-silicon thin film transistor uses low temperature poly-silicon (LTPS), and the active layer of the oxide thin film transistor uses oxide semiconductor (Oxide). The low temperature poly-silicon thin film transistor has the advantages of high mobility and fast charging, and the oxide thin film transistor has the advantages of low leakage current, low frequency driving, and low power consumption. Integrating the low temperature poly-silicon thin film transistor and the oxide thin film transistor on one display substrate forms a low temperature poly-crystalline oxide (LTPO) display substrate, which can take advantage of both types of transistors, can achieve low frequency driving, can reduce power consumption, and can improve display quality.

[0142] In an example embodiment, the light emitting device EL can be an organic light emitting diode (OLED) including a first electrode (anode), an organic light emitting layer, and a second electrode (cathode) stacked.

[0143] The anode of the light emitting device EL in the pixel driving circuit of the sub-pixel is usually reset by a direct current signal. Due to the different light emitting efficiencies of the red light emitting sub-pixel R, the green light emitting sub-pixel G, and the blue light emitting sub-pixel B, screen flicker or uneven brightness problems may occur, especially at low gray scale, and the screen flicker or uneven brightness problems are more obvious. In addition, in an all-oxide pixel driving circuit (all the transistors in the pixel driving circuit are oxide transistors), for example, a display substrate using a 7T2C pixel driving circuit, the temperature or brightness at different positions is usually inconsistent, which leads to uneven screen brightness and affects the display effect of the display substrate.

[0144] The display substrate provided by the example embodiments of the present disclosure can include a substrate, and a plurality of pixel units and at least one type of initial signal line arranged on one side of the substrate; in at least part of the type of initial signal line, the same type of initial signal line includes at least two types of initial signal lines; in at least part of the pixel units, the same pixel unit includes at least two types of sub-pixels.

[0145] In the same type of initial signal line, each type of initial signal line is connected to at least one type of sub-pixel in the pixel unit, and different types of initial signal lines are connected to different types of sub-pixels in the pixel unit.

[0146] The display substrate provided by the example embodiments of the present disclosure includes a plurality of pixel units and at least one type of initial signal line, the same type of initial signal line includes at least two types of initial signal lines, the same pixel unit includes at least two types of sub-pixels, and different types of initial signal lines in the same type of initial signal line are connected to different types of sub-pixels in the pixel unit, which can to some extent avoid the defects of screen flicker or uneven brightness, thereby improving the display effect.

[0147] As shown in FIGS. 5a-5c, the display substrate provided by the example embodiments of the present disclosure can include a substrate, and a plurality of pixel units P and at least one type of initial signal line Vinit arranged on one side of the substrate; in at least part of the type of initial signal line Vinit, the same type of initial signal line Vinit includes at least two types of initial signal lines; in at least part of the pixel units P, the same pixel unit P includes at least two types of sub-pixels Pxij.

[0148] In the same type of initial signal line Vinit, each type of initial signal line Vinit is connected to at least one type of sub-pixel Pxij in the pixel unit P, and different types of initial signal lines Vinit are connected to different types of sub-pixels Pxij in the pixel unit P.

[0149] In the example embodiments, in the same type of initial signal line Vinit, different types of initial signal lines Vinit are connected to different types of sub-pixels Pxij in the pixel unit P, which can to some extent avoid the technical problems of screen flicker or uneven brightness caused by different luminous efficiencies of different types of sub-pixels.

[0150] In the example embodiments, in at least part of the pixel units P, the types of sub-pixels Pxij in the same pixel unit P include at least a first sub-pixel P1, a second sub-pixel P2, and a third sub-pixel P3.

[0151] In at least part of the initial signal lines Vinit, the same type of initial signal lines Vinit includes at least a first initial signal line and a second initial signal line; the first initial signal line is connected with at least one of the first sub-pixel P1 and the second sub-pixel P2, and is configured to provide an initial signal to at least one of the first sub-pixel P1 and the second sub-pixel P2; and the second initial signal line is connected with the third sub-pixel P3, and is configured to provide an initial signal to the third sub-pixel P3.

[0152] In the example embodiment, the third sub-pixel P3 is independently provided with an initial signal through the second initial signal line, which can avoid the phenomenon of screen flickering or uneven brightness of the display substrate caused by the inconsistent luminous efficiency of the third sub-pixel P3 with the first sub-pixel P1 and the second sub-pixel P2 to a certain extent, and can improve the picture quality (for example, the picture quality improvement for low gray scale is more obvious).

[0153] In the example embodiment, in at least part of the initial signal lines Vinit, the same type of initial signal lines Vinit can also include a third initial signal line, the first initial signal line is connected with one of the first sub-pixel P1 and the second sub-pixel P2; and the third initial signal line is connected with the other of the first sub-pixel P1 and the second sub-pixel P2. The first sub-pixel P1, the second sub-pixel P2 and the third sub-pixel P3 are independently provided with an initial signal through the three initial signal lines of the same type, which can avoid the phenomenon of screen flickering or uneven brightness of the display substrate caused by the inconsistent luminous efficiency of the first sub-pixel P1, the second sub-pixel P2 and the third sub-pixel P3 to a certain extent, and can improve the picture quality (for example, the picture quality improvement for low gray scale is more obvious).

[0154] In the example embodiment, in the same type of initial signal lines, a plurality of initial signal lines of the same type can form a grid structure with a plurality of initial signal connection lines of the same type, which can reduce the voltage drop of the initial signal lines of the same type, avoid the difference between the initial signals received by the sub-pixels at different positions caused by the excessive voltage drop on the initial signal lines of the same type, and thus avoid the difference in luminance (brightness) of the sub-pixels at different positions caused by the excessive difference between the initial signals received by the sub-pixels at different positions, which can improve the display uniformity of the display substrate to a certain extent.

[0155] In the example embodiment, at least part of the sub-pixels Pxij can include a pixel driving circuit, and at least part of the pixel driving circuit includes a plurality of transistors and at least one capacitor.

[0156] In the direction perpendicular to the plane where the substrate is located, the capacitor can include: a first plate located on one side of the substrate, a second plate located on the side of the first plate away from the substrate; the transistor can include: an active layer located on the side of the second plate away from the substrate, a control electrode located on the side of the active layer away from the substrate, a first electrode and a second electrode located on the side of the control electrode away from the substrate.

[0157] In the exemplary embodiment, the type of the initial signal line Vinit at least includes the second initial signal line Vinit2, at least part of the sub-pixel Pxij includes an anode AN, and in the direction perpendicular to the plane where the substrate is located, the anode AN is located on the side of the first electrode and the second electrode away from the substrate; the plurality of transistors can include a seventh transistor T7 as a reset transistor, the first electrode of the seventh transistor T7 is connected with the second initial signal line Vinit2 of the corresponding type, and the second electrode of the seventh transistor T7 is connected with the anode AN;

[0158] The plurality of pixel units P form a plurality of rows, and the second initial signal line Vinit2 is connected with the first electrode of the seventh transistor T7 of at least part of the sub-pixels in one row of pixel units P, and is configured to provide the second initial signal to the corresponding anode AN under the control of at least part of the seventh transistor T7 in the row of pixel units P;

[0159] The second initial signal line Vinit2 is arranged in the same layer as one of the first plate and the second plate, or is arranged in the same layer as the first electrode and the second electrode.

[0160] In the exemplary embodiment, the type of the second initial signal line Vinit2 at least includes the first second initial signal line Vinit2-1 and the second second initial signal line Vinit2-3;

[0161] The first second initial signal line Vinit2-1 is connected with at least one of the first electrode of the seventh transistor T7 of the first sub-pixel P1 and the first electrode of the seventh transistor T7 of the second sub-pixel P2 in one row of pixel units P, and is configured to provide the initial signal to the corresponding anode AN under the control of at least one of the seventh transistor T7 of the first sub-pixel P1 and the seventh transistor T7 of the second sub-pixel P2 in the row of pixel units P;

[0162] The second second initial signal line Vinit2-3 is connected with the first electrode of the seventh transistor T7 of the third sub-pixel P3 in one row of pixel units P, and is configured to provide the initial signal to the anode AN of the third sub-pixel P3 in the row of pixel units P under the control of the seventh transistor T7 of the third sub-pixel P3 in the row of pixel units P;

[0163] The second second initial signal line Vinit2-3 is arranged in the same layer as one of the first plate and the second plate, or is arranged in the same layer as the first electrode and the second electrode.

[0164] In the example embodiment, the anode AN of the third sub-pixel P3 is independently reset by the second second initial signal line Vinit2-3, which can avoid the technical problem of screen flicker or uneven brightness caused by the difference in luminous efficiency between the third sub-pixel P3 and the first sub-pixel P1 and the second sub-pixel P2, and can improve the image quality (for example, the improvement in image quality for low gray scale is more obvious).

[0165] In the example embodiment, in the structure in which the second second initial signal line Vinit2-3 is arranged in the same layer as one of the first plate and the second plate, the first second initial signal line Vinit2-1 is arranged in the same layer as the first electrode and the second electrode; as shown in FIG. 5a, the second second initial signal line Vinit2-3 is arranged in the same layer as the first plate, and the first second initial signal line Vinit2-1 is arranged in the same layer as the first electrode and the second electrode.

[0166] In the structure in which the second second initial signal line Vinit2-3 is arranged in the same layer as the first electrode and the second electrode, the first second initial signal line Vinit2-1 is arranged in the same layer as the first electrode and the second electrode, or arranged in the same layer as one of the first plate and the second plate; as shown in FIG. 5b and FIG. 5c, the second second initial signal line Vinit2-3 is arranged in the same layer as the first electrode and the second electrode, the first second initial signal line Vinit2-1 is arranged in the same layer as the first electrode and the second electrode in FIG. 5b, and the first second initial signal line Vinit2-1 is arranged in the same layer as the first plate in FIG. 5c.

[0167] In the example embodiment, as shown in FIG. 5a and FIG. 5c, in the structure in which the first second initial signal line Vinit2-1 and the second second initial signal line Vinit2-3 are arranged in different layers, the orthographic projection of the first second initial signal line Vinit2-1 and the second second initial signal line Vinit2-3 on the substrate at least partially overlaps, which can save space and improve the utilization rate of the display substrate space.

[0168] In the example embodiment, as shown in FIG. 5a and FIG. 5b, the display substrate can further include at least one first second initial signal connection line Vinit2-1L and at least one second second initial signal connection line Vinit2-3L, and in the direction perpendicular to the plane in which the substrate is located, the first second initial signal connection line Vinit2-1L and the second second initial signal connection line Vinit2-3L are located on the side of the first electrode and the second electrode away from the substrate, and on the side of the anode AN close to the substrate.

[0169] The first second initial signal connection line Vinit2-1L is connected with at least one first second initial signal line Vinit2-1, and the second second initial signal connection line Vinit2-3L is connected with at least one second second initial signal line Vinit2-3.

[0170] In the example embodiment, the plurality of first second initial signal connection lines Vinit2-1L are connected with the plurality of first second initial signal lines Vinit2-1 in the plurality of rows of pixel units P, forming a grid structure, which can reduce the voltage drop of the first second initial signal line Vinit2-1, avoid the too large difference of the initial signals received by the anodes AN of the same type of sub-pixels (the same type in the first sub-pixel P1 and the second sub-pixel P2) at different positions due to the too large voltage drop on the first second initial signal line Vinit2-1, and thus can avoid the different light emission (brightness) of the same type of sub-pixels at different positions due to the too large difference of the initial signals received by the anodes of the same type of sub-pixels (the same type in the first sub-pixel P1 and the second sub-pixel P2) at different positions, and to some extent, improve the display uniformity of the display substrate.

[0171] In the example embodiment, the plurality of second second initial signal connection lines Vinit2-3L are connected with the plurality of second second initial signal lines Vinit2-3 in the plurality of rows of pixel units P, forming a grid structure, which can reduce the voltage drop of the second second initial signal line Vinit2-3, avoid the too large difference of the initial signals received by the anodes AN in the third sub-pixel P3 at different positions due to the too large voltage drop on the second second initial signal line Vinit2-3, and thus can avoid the different light emission (brightness) of the third sub-pixel P3 at different positions due to the too large difference of the initial signals received by the anodes of the third sub-pixel P3 at different positions, and to some extent, improve the display uniformity of the display substrate.

[0172] In the example embodiment, as shown in FIG. 5c, the types of the second initial signal lines Vinit2 can further include a third second initial signal line Vinit2-2.

[0173] The first second initial signal line Vinit2-1 is connected with the first electrode of the seventh transistor T7 of the first sub-pixel P1 in one of the rows of pixel units P, and is configured to provide an initial signal to the anode AN of the first sub-pixel P1 in the row of pixel units P under the control of the seventh transistor T7 of the first sub-pixel P1 in the row of pixel units P; and the third second initial signal line Vinit2-2 is connected with the first electrode of the seventh transistor T7 of the second sub-pixel P2 in one of the rows of pixel units P, and is configured to provide an initial signal to the anode AN of the third sub-pixel P3 in the row of pixel units P under the control of the seventh transistor T7 of the second sub-pixel P2 in the row of pixel units P.

[0174] In the structure in which the second second initial signal line Vinit2-3 is arranged in the same layer as the first electrode and the second electrode, one of the first second initial signal line Vinit2-1 and the third second initial signal line Vinit2-2 is arranged in the same layer as one of the first electrode plate and the second electrode plate, and the other is arranged in the same layer as the first electrode and the second electrode or in the same layer as the other of the first electrode plate and the second electrode plate.

[0175] In the structure in which the second second initial signal line Vinit2-3 is arranged in the same layer as one of the first electrode plate and the second electrode plate, the first second initial signal line Vinit2-1 and the third second initial signal line Vinit2-2 are arranged in the same layer as the first electrode and the second electrode, or one of the first second initial signal line Vinit2-1 and the third second initial signal line Vinit2-2 is arranged in the same layer as the first electrode and the second electrode, and the other is arranged in the same layer as the other of the first electrode plate and the second electrode plate.

[0176] In the exemplary embodiment, the anode AN of the first sub-pixel P1, the anode AN of the second sub-pixel P2, and the anode AN of the third sub-pixel P3 are independently reset by the first second initial signal line Vinit2-1, the third second initial signal line Vinit2-2, and the second second initial signal line Vinit2-3, respectively, which can avoid the technical problem of screen flickering or uneven brightness caused by different luminous efficiencies of the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3, and can improve the picture quality (for example, the picture quality of low gray scale is improved more obviously).

[0177] In the exemplary embodiment, as shown in FIG. 5c, the display substrate can further include a third second initial signal connection line Vinit2-2L, which is located on the side of the first electrode and the second electrode away from the substrate and on the side of the anode AN close to the substrate in the direction perpendicular to the plane where the substrate is located.

[0178] The third second initial signal connection line Vinit2-2L is connected with at least one third second initial signal line Vinit2-2.

[0179] In the example embodiment, the plurality of third second initial signal connection lines Vinit2-2L are connected with the plurality of third second initial signal lines Vinit2-2 in the plurality of rows of pixel units P, forming a grid structure, which can reduce the voltage drop of the third second initial signal line Vinit2-2, avoid the too large difference of the initial signal received by the anode AN in the second sub-pixel P2 at different positions due to the too large voltage drop on the third second initial signal line Vinit2-3, and thus avoid the different luminance of the second sub-pixel P2 at different positions due to the too large difference of the initial signal received by the anode in the second sub-pixel P2 at different positions, and to some extent, improve the display uniformity of the display substrate.

[0180] In the example embodiment, as shown in FIG. 5d, which is a structural schematic diagram of three pixel units P in the Mth row, the first second initial signal connection line Vinit2-1L can be arranged in the N-1th and N+5th column sub-pixel driving circuits, the second second initial signal connection line Vinit2-3L can be arranged in the N+2th and N+7th column sub-pixel driving circuits, and the third second initial signal connection line Vinit2-2L can be arranged in the N+2th and N+7th column sub-pixel driving circuits. It can be understood that the interval between the adjacent two second initial signal connection lines of the same type is five column pixel driving circuits.

[0181] In the example embodiment, as shown in FIGS. 5a-5c and 6a-6g, the types of the initial signal lines include at least the first initial signal line Vinit1.

[0182] The plurality of transistors can include a driving transistor T3 and a first transistor T1 as a reset transistor, the first electrode of the first transistor T1 is connected with the first initial signal line Vinit1, and the second electrode of the first transistor T1 is connected with the control electrode of the driving transistor T3.

[0183] The plurality of pixel units P form a plurality of rows, the first initial signal line Vinit1 is connected with the first electrode of the first transistor T1 of at least part of the sub-pixels in one row of pixel units P, and is arranged to provide the initial signal to the control electrode of the corresponding driving transistor T3 under the control of at least part of the first transistors in the row of pixel units P.

[0184] The first initial signal line Vinit1 is arranged in the same layer as the first electrode and the second electrode, or is arranged in the same layer as the control electrode.

[0185] In the example embodiment, as shown in FIGS. 6d, 6f and 6g, the first initial signal lines Vinit1 can include a first first initial signal line Vinit1-1 and a second first initial signal line Vinit1-3;

[0186] The first first initial signal line Vinit1-1 is connected with at least one of the first electrode of the first transistor T1 of the first sub-pixel P1 and the first electrode of the first transistor T1 of the second sub-pixel P2 in one row of the pixel units P, and is configured to provide an initial signal to the control electrode of the driving transistor T3 under the control of at least one of the first transistor T1 of the first sub-pixel P1 and the first transistor T1 of the second sub-pixel P2 in the row of the pixel units P;

[0187] The second first initial signal line Vinit1-3 is connected with the first electrode of the first transistor T1 of the third sub-pixel P3 in one row of the pixel units P, and is configured to provide an initial signal to the control electrode of the driving transistor T3 of the third sub-pixel P3 in the row of the pixel units P under the control of the first transistor T1 of the third sub-pixel P3 in the row of the pixel units P;

[0188] Among the first first initial signal line Vinit1-1 and the second first initial signal line Vinit1-3, one is arranged in the same layer as the control electrode, and the other is arranged in the same layer as the first electrode and the second electrode.

[0189] In the example embodiment, the control electrode of the driving transistor T3 of the third sub-pixel P3 is independently reset through the second first initial signal line Vinit1-3, which can avoid the technical problems of screen flicker or uneven brightness caused by the difference in luminous efficiency of the third sub-pixel P3 and the luminous efficiency of the first sub-pixel P1 and the second sub-pixel P2, and can improve the picture quality (for example, the picture quality improvement for low gray scale is more obvious).

[0190] In the example embodiment, the display substrate can further include at least one first first initial signal connection line Vinit1-1L and at least one second first initial signal connection line Vinit1-3L, and in the direction perpendicular to the plane where the substrate is located, the first first initial signal connection line Vinit1-1L and the second first initial signal connection line Vinit1-3L are located on the side away from the substrate of the first electrode and the second electrode, and on the side close to the substrate of the anode AN;

[0191] The first first initial signal connection line Vinit1-1L is connected with the at least one first first initial signal line Vinit1-1, and the second first initial signal connection line Vinit1-3L is connected with the at least one second first initial signal line Vinit1-3.

[0192] In the example embodiment, the plurality of first first initial signal connection lines Vinit1-1L are connected with the plurality of first first initial signal lines Vinit1-1 in the plurality of rows of pixel units P, forming a grid structure, which can reduce the voltage drop of the first first initial signal lines Vinit1-1L, avoid the voltage drop of the first first initial signal lines Vinit1-1 being too large to cause the control electrodes of the driving transistors of the same type of sub-pixels (the same type in the first sub-pixel P1 and the second sub-pixel P2) at different positions to receive too large difference in initial signals, so as to avoid the different positions of the same type of sub-pixels (the same type in the first sub-pixel P1 and the second sub-pixel P2) to emit light (brightness) differently due to the control electrodes of the driving transistors receiving too large difference in initial signals, and to improve the display uniformity of the display substrate to a certain extent.

[0193] In the example embodiment, the second first initial signal connection line Vinit1-3L is connected with the plurality of second first initial signal lines Vinit1-3 in the plurality of rows of pixel units P, forming a grid structure, which can reduce the voltage drop of the second first initial signal lines Vinit1-3L, avoid the voltage drop of the second first initial signal lines Vinit1-3 being too large to cause the control electrodes of the driving transistors in the third sub-pixel P3 at different positions to receive too large difference in initial signals, so as to avoid the different positions of the third sub-pixel P3 to emit light (brightness) differently due to the anodes of the third sub-pixel P3 receiving too large difference in initial signals, and to improve the display uniformity of the display substrate to a certain extent.

[0194] In the example embodiment, as shown in FIGS. 6f and 6g, the types of the first initial signal lines Vinit1 can further include a third first initial signal line Vinit1-2.

[0195] The first first initial signal line Vinit1-1 is connected with the first electrode of the first transistor T1 of the first sub-pixel P1 in one row of pixel units P, and is configured to provide the control electrode of the driving transistor T3 of the first sub-pixel P1 in the row of pixel units P with an initial signal under the control of the first transistor T1 of the first sub-pixel P1 in the row of pixel units P; and the third first initial signal line Vinit1-2 is connected with the first electrode of the first transistor T1 of the second sub-pixel P2 in one row of pixel units P, and is configured to provide the control electrode of the driving transistor T3 of the second sub-pixel P2 in the row of pixel units P with an initial signal under the control of the first transistor T1 of the second sub-pixel P2 in the row of pixel units P.

[0196] The third first initial signal line Vinit1-2 is arranged in the same layer as the control electrode, or arranged in the same layer as the first electrode and the second electrode.

[0197] In the example embodiment, the control electrode of the driving transistor T3 of the first sub-pixel P1, the control electrode of the driving transistor T3 of the second sub-pixel P2, and the control electrode of the driving transistor T3 of the third sub-pixel P3 are independently reset by the first initial signal line Vinit1-1, the third initial signal line Vinit1-2, and the second initial signal line Vinit1-3, respectively, which can avoid the technical problem of screen flicker or uneven brightness caused by different luminous efficiencies of the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3, and can improve the picture quality (for example, the picture quality of low gray scale is improved more obviously).

[0198] In the example embodiment, the display substrate can further include at least one third initial signal connection line Vinit1-2L, which is located on the side of the first electrode and the second electrode away from the substrate and on the side of the anode AN close to the substrate in the direction perpendicular to the plane where the substrate is located.

[0199] The third initial signal connection line Vinit1-2L is connected with the at least one third initial signal line Vinit1-2.

[0200] In the example embodiment, the plurality of third initial signal connection lines Vinit1-2L are connected with the plurality of third initial signal lines Vinit1-2 located in the plurality of pixel units P, forming a grid structure, which can reduce the voltage drop of the third initial signal line Vinit1-2L and avoid the difference between the initial signals received by the anodes AN of the second sub-pixels P2 at different positions due to the excessive voltage drop on the third initial signal line Vinit1-2L, so that the difference between the initial signals received by the control electrodes of the driving transistors in the third sub-pixels P3 at different positions can be avoided, and the luminance of the second sub-pixels P2 at different positions is different, which improves the display uniformity of the display substrate to a certain extent.

[0201] In the example embodiment, as shown in FIGS. 5a to 6g, the plurality of transistors can further include a second transistor T2 as a reset transistor, and the at least one capacitor can include a first capacitor C1 and a second capacitor C2.

[0202] The first electrode of the second transistor T2 is connected with the first initial signal line Vinit1, the second electrode of the second transistor T2 is connected with the first plate C11 of the first capacitor C1 and the first plate C21 of the second capacitor C2, the second plate C12 of the first capacitor C1 is connected with the second electrode of the first transistor T1 and the control electrode of the driving transistor T3, and the second plate C22 of the second capacitor C2 is connected with the second electrode of the driving transistor T3.

[0203] The first initial signal line Vinit1 can also be connected to the first electrode of the second transistor T2 of at least part of the sub-pixels in one row of pixel units, and is configured to provide an initial signal to the first plate C11 of the first capacitor C1 and the first plate C21 of the second capacitor C2 in the corresponding sub-pixel under the control of at least part of the second transistor T2 in the row of pixel units P.

[0204] In the exemplary embodiments, in the same pixel unit P, the first electrode of the first transistor T1 and the first electrode of the second transistor T2 are connected to the same type of first initial signal line Vinit1. For example, in FIG. 6g, the first electrode of the second transistor T2 and the first electrode of the first transistor T1 in the first sub-pixel P1 are both connected to the first type of first initial signal line Vinit1-1, the first electrode of the second transistor T2 and the first electrode of the first transistor T1 in the second sub-pixel P2 are both connected to the third type of first initial signal line Vinit1-2, and the first electrode of the second transistor T2 and the first electrode of the first transistor T1 in the third sub-pixel P3 are both connected to the second type of first initial signal line Vinit1-3. In the exemplary embodiments, the first plate C11 of the first capacitor C1 and the first plate C21 of the second capacitor C2 of the first sub-pixel P1, the first plate C11 of the first capacitor C1 and the first plate C21 of the second capacitor C2 of the second sub-pixel P2, and the first plate C11 of the first capacitor C1 and the first plate C21 of the second capacitor C2 of the third sub-pixel P3 are independently reset by the first type of first initial signal line Vinit1-1, the third type of first initial signal line Vinit1-2, and the second type of first initial signal line Vinit1-3, respectively, which can avoid the technical problem of screen flickering or uneven brightness caused by different light-emitting efficiencies of the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3, and can improve the image quality (for example, the improvement in image quality for low gray scale is more obvious).

[0205] In the exemplary embodiments, the display substrate can further include a plurality of first power connection lines VDDL and a plurality of first power lines VDD, and the plurality of transistors include a fifth transistor T5 as a light-emitting control transistor and a driving transistor T3.

[0206] The first power connection line VDDL is disposed in the same layer as the first electrode and the second electrode, and in a direction perpendicular to the plane on which the substrate is located, the first power line VDD is located on the side of the first power connection line VDDL away from the substrate, the first power connection line VDDL is connected to the first electrode of the fifth transistor T5 and configured to provide a first power signal to the fifth transistor T5; at least part of the first power line VDD and at least part of the first power connection line VDDL are connected to form a grid-like structure through a via, which can reduce the voltage drop of the first power line VDD and improve the display uniformity of the display substrate.

[0207] The first electrode of the fifth transistor T5 is connected with the first power supply connection line VDDL, and the second electrode of the fifth transistor T5 is connected with the first electrode of the driving transistor T3.

[0208] In the example implementation, the at least partial first power supply line VDD and the at least partial first power supply connection line VDDL are connected through the via to form a grid structure, which can reduce the voltage drop of the first power supply line VDD, avoid that the first power supply signals received by the sub-pixels at different positions are too different due to the excessive voltage drop of the first power supply line VDD, and thus can avoid that the light emission (brightness) and heat emission (temperature) of the sub-pixels at different positions are different due to the excessive difference of the first power supply signals received by the sub-pixels at different positions, to a certain extent, improve the display uniformity of the display substrate.

[0209] In the example implementation, the display substrate can further include a plurality of second power supply connection lines VSSL, a plurality of second power supply lines VSS, and a cathode layer.

[0210] The second power supply connection line VSSL is arranged in the same layer as the first electrode and the second electrode, and in the direction perpendicular to the plane where the substrate is located, the second power supply line VSS is located on the side of the second power supply connection line VSSL away from the substrate and on the side of the anode AN close to the substrate, at least partial second power supply line VSS and at least partial second power supply connection line VSSL are connected through the via to form a grid structure, which can reduce the voltage drop of the second power supply line VSS, improve the display uniformity of the display substrate, avoid that the second power supply signals received by the sub-pixels at different positions are too different due to the excessive voltage drop of the second power supply line VSS, and thus can avoid that the light emission (brightness) and heat emission (temperature) of the sub-pixels at different positions are different due to the excessive difference of the second power supply signals received by the sub-pixels at different positions, to a certain extent, improve the display uniformity of the display substrate.

[0211] In the example implementation, the display substrate can further include a cathode layer, and in the direction perpendicular to the plane where the substrate is located, the cathode layer is located on the side of the anode AN away from the substrate, and the second power supply connection line VSSL can be connected with the cathode layer, to reduce the impedance and voltage drop of the cathode layer and the second power supply line VSS, and improve the display uniformity of the display substrate, for example, the second power supply connection line VSSL can be connected with the cathode layer through the via.

[0212] In the example implementation, the first sub-pixel P1 is a light-emitting unit emitting red light, the second sub-pixel P2 is a light-emitting unit emitting green light, and the third sub-pixel P3 is a light-emitting unit emitting blue light.

[0213] In the example implementation, the plurality of transistors in the pixel driving circuit can all be oxide transistors.

[0214] In an exemplary embodiment, as shown in FIGS. 5a-6g, the pixel driving circuit can include a first transistor T1 to a seventh transistor T3, wherein the third transistor T3 can serve as a driving transistor, the control electrode of the driving transistor T3 is connected with the first node N1, and the second electrode of the seventh transistor T7 is connected with the anode of the light emitting device EL (also the fifth node N5). The orthographic projection of the first capacitor C1 on the substrate at least partially overlaps with the orthographic projection of the third transistor T3 on the substrate, for example, the orthographic projection of the channel of the third transistor T3 on the substrate can be located within the range of the orthographic projection of the first capacitor C1 on the substrate, the first capacitor C2 can shield the channel of the third transistor T3, and the stability of the third transistor T3 is improved. In an exemplary embodiment, in the first direction X, the first transistor T1, the second transistor T2, and the fourth transistor T4 can be located on the same side of the first capacitor C1 and the second capacitor C2; in the second direction Y, the fourth transistor T4 and the second transistor T2 can be located on both sides of the first transistor T1, the second transistor T2, the sixth transistor T6, and the seventh transistor T7 are located on the same side of the first capacitor C1, the fourth transistor T4 and the fifth transistor T5 are located on the same side of the second capacitor C2, the seventh transistor T7 can be located on the side of the sixth transistor T6 away from the third transistor T3, and the second capacitor C2 and the first capacitor C1 can be arranged in sequence along the second direction Y. In an exemplary embodiment, two adjacent sub-pixels can be symmetrical with respect to a center line (which can be substantially symmetrical in structure), the center line can extend along the second direction Y, and is located between the two adjacent sub-pixels in the first direction X.

[0215] In an exemplary embodiment, the first direction X can be a row direction, and the second direction Y can be a column direction.

[0216] In the exemplary embodiments, as shown in FIGS. 6a-6f, equivalent circuit diagrams of the pixel driving circuit are shown. In the planar structure shown in FIGS. 5a and 5b, the equivalent circuit diagram of the pixel driving circuit can be as shown in FIGS. 6a and 6b, FIG. 6a is an equivalent circuit diagram of the pixel driving circuit in the first and second sub-pixels, and FIG. 6b is an equivalent circuit diagram of the pixel driving circuit in the third sub-pixel, in FIG. 6a, the first second initial signal line Vinit2-1 is configured to provide an initial signal to the first sub-pixel P1 and the second sub-pixel P2, and in FIG. 6b, the second second initial signal line Vinit2-3 is configured to provide an initial signal to the third sub-pixel P3; in the planar structure shown in FIG. 5c, the equivalent circuit diagram of the pixel driving circuit is as shown in FIGS. 6a-6c, FIG. 6a is an equivalent circuit diagram of the pixel driving circuit in the first sub-pixel, FIG. 6b is an equivalent circuit diagram of the pixel driving circuit in the third sub-pixel, and FIG. 6c is an equivalent circuit diagram of the pixel driving circuit in the second sub-pixel, in FIG. 6a, the first second initial signal line Vinit2-1 is configured to provide an initial signal to the first sub-pixel P1, in FIG. 6b, the second second initial signal line Vinit2-3 is configured to provide an initial signal to the third sub-pixel P3, and in FIG. 6c, the third second initial signal line Vinit2-3 is configured to provide an initial signal to the second sub-pixel P2.

[0217] In the example embodiment, as shown in FIGS. 6d-6f, which are equivalent circuit diagrams of several pixel driving circuits, the pixel driving circuit of the first sub-pixel P1 and the second sub-pixel P2 in the display substrate can adopt the pixel driving circuit shown in FIG. 6d, the third sub-pixel P3 can adopt the pixel driving circuit shown in FIG. 6f, the first initial signal line Vinit1-1 of the first kind is configured to provide an initial signal to the first sub-pixel P1 and the second sub-pixel P2, and the first initial signal line Vinit1-3 of the second kind is configured to provide an initial signal to the third sub-pixel P3; or, the first sub-pixel P1 adopts the pixel driving circuit shown in FIG. 6d, the second sub-pixel P2 can adopt the pixel driving circuit shown in FIG. 6f, and the third sub-pixel P3 can adopt the pixel driving circuit shown in FIG. 6e, the first initial signal line Vinit1-1 of the first kind is configured to provide an initial signal to the first sub-pixel P1, the first initial signal line Vinit1-3 of the second kind is configured to provide an initial signal to the third sub-pixel P3, and the first initial signal line Vinit1-2 of the third kind is configured to provide an initial signal to the second sub-pixel P2, as shown in FIGS. 6g and 6h, which are schematic diagrams of three pixel driving circuits of one pixel unit P in the pixel driving circuit of the Mth row, the plurality of first initial signal lines Vinit1-1 of the first kind in the plurality of pixel driving circuits can be connected to form a grid structure with the plurality of first initial signal connection lines Vinit1-1L, the plurality of second initial signal lines Vinit1-3 of the second kind in the plurality of pixel driving circuits can be connected to form a grid structure with the plurality of second initial signal connection lines Vinit1-3L, and the plurality of third initial signal lines Vinit1-2 of the third kind in the plurality of pixel driving circuits can be connected to form a grid structure with the plurality of third initial signal connection lines Vinit1-2L; in FIG. 6h, on the basis of the plurality of first initial signal lines Vinit1 of the same kind being connected to the plurality of first initial signal connection lines of the same kind to form a grid structure, the plurality of second initial signal lines Vinit2 of the same kind are connected to the plurality of second initial signal connection lines of the same kind to form a grid structure, that is, in FIG. 6h: the plurality of first second initial signal lines Vinit2-1 in the plurality of pixel driving circuits can be connected to form a grid structure with the plurality of first second initial signal connection lines Vinit2-1L, the plurality of second second initial signal lines Vinit2-3 in the plurality of pixel driving circuits can be connected to form a grid structure with the plurality of second second initial signal connection lines Vinit2-3L, and the plurality of third second initial signal lines Vinit2-2 in the plurality of pixel driving circuits can be connected to form a grid structure with the plurality of third second initial signal connection lines Vinit2-2L.

[0218] In the all-oxide pixel circuit (that is, all the transistors in the pixel driving circuit are oxide transistors), for example, the display substrate adopts a 7T2C pixel driving circuit, and the inconsistent temperature and brightness at different positions will cause the screen brightness to be uneven, affecting the display effect. The reasons for the inconsistent temperature and brightness at different positions of the display substrate mainly include two aspects:

[0219] Firstly, due to the voltage drop (such as IR drop) of the first power supply line VDD or the second power supply line VSS, the brightness and temperature at different positions of the display substrate are different. The embodiments of the present disclosure can reduce the voltage drop of the first power supply line VDD by connecting the plurality of first power supply connection lines VDDL and the plurality of first power supply lines VDD to form a grid-like structure, and reduce the voltage drop of the second power supply line VSS by connecting the plurality of second power supply connection lines VSSL and the plurality of second power supply lines VSS to form a grid-like structure, thereby solving the problem of inconsistent brightness and temperature at different positions of the display substrate caused by the voltage drop of the first power supply line VDD and the second power supply line VSS to a certain extent.

[0220] Secondly, the oxide (Oxide) transistor is used as a driving transistor, and the transfer and output characteristic curves of the driving transistor are obviously different from those of the low-temperature polysilicon (LTPS) transistor, which makes the oxide transistor used as a driving transistor more sensitive to the voltage fluctuation of the related nodes (such as the gate, source and drain) in the pixel driving circuit. That is, the brightness sensitivity or temperature sensitivity caused by the characteristics (such as the gate-source voltage difference △Vgs) of the oxide driving transistor in different areas will be poor, which causes the characteristics of the pixel driving circuits in different areas of the display area to be different (such as the parasitic coupling of the nodes in the circuit caused by process fluctuation), thereby causing the light-emitting devices EL in different positions of the display area to have different light-emitting (brightness) and heating (temperature). After research, it is found that the light-emitting efficiency of the first sub-pixel R emitting red light, the second sub-pixel G emitting green light and the third sub-pixel B emitting blue light are obviously different. The embodiments of the present disclosure can effectively improve the technical problem of poor brightness and temperature uniformity of the all-oxide pixel driving circuit by independently driving the reset node signal (such as Vinit1 / Vinit2) in the pixel driving circuit of the first sub-pixel R, the second sub-pixel G and the third sub-pixel B.

[0221] In theory, the transistor characteristics in the pixel driving circuit of the first sub-pixel R, the second sub-pixel G and the third sub-pixel B are consistent, and under the condition of ensuring good uniformity of transistor characteristics (for example, the uniformity of transistor characteristics can reach 100%), in this case, by adjusting the white balance of the first sub-pixel R, the second sub-pixel G and the third sub-pixel B, the problem of uneven brightness (mura, which can be referred to as uneven brightness) in the display area will not occur. However, the characteristics of transistors in different areas of the pixel driving circuit in the display substrate usually differ greatly, and the fluctuation of the characteristics of the transistors will cause the display substrate to have differences in brightness or flicker level (Flicker) of the display screen at the same frequency in different areas of the display area. Such differences in brightness or flicker level (Flicker) of the display screen at the same frequency (i.e., mura or Flicker difference) exist at high and low gray scales, and the lower the gray scale, the more obvious the mura or Flicker difference caused by the fluctuation of the transistor characteristics. Further, the mura or Flicker level difference of the first sub-pixel R, the second sub-pixel G and the third sub-pixel B caused by the slight fluctuation of the transistor characteristics is more obvious at low gray scales. The embodiments of the present disclosure can effectively improve the technical problem that the mura or Flicker level difference is more obvious at low gray scales by independently driving the reset node signals (such as Vinit1 / Vinit2) in the pixel driving circuit of the first sub-pixel R, the second sub-pixel G and the third sub-pixel B, for example, refreshing different nodes of different sub-pixels at different frequencies.

[0222] In the example embodiments, in the embodiments of the present disclosure, the first node N1 (also the control electrode of the driving transistor T3) of different sub-pixels is reset by different types of first initial signal lines Vinit1, and the fifth node N5 (also the anode in the sub-pixel) of different sub-pixels is reset by different types of second initial signal lines Vinit2, which is beneficial to reduce the difference (△gs difference) in the characteristics of the driving transistors in different areas of the display area, thereby effectively improving the technical problem of poor brightness and temperature uniformity of the all-oxide pixel driving circuit, and improving the display uniformity and display quality.

[0223] The preparation process of the display substrate is exemplarily described below. The "patterning process" in the present disclosure includes coating photoresist, mask exposure, development, etching, stripping photoresist and the like for metal material, inorganic material or transparent conductive material, and includes coating organic material, mask exposure and development and the like for organic material. The deposition can adopt any one or more of sputtering, evaporation, chemical vapor deposition, the coating can adopt any one or more of spraying, spin coating and inkjet printing, and the etching can adopt any one or more of dry etching and wet etching, which are not limited in the present disclosure. The "thin film" refers to a thin film of a certain material on a substrate (or substrate substrate) made by deposition, coating or other processes. If the "thin film" does not need a patterning process during the entire manufacturing process, the "thin film" can also be referred to as a "layer". If the "thin film" needs a patterning process during the entire manufacturing process, it is referred to as a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". The "A and B are arranged in the same layer" in the present disclosure means that A and B are formed at the same time by the same patterning process. The "thickness" of the film layer is the size of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of the present disclosure, "the orthographic projection of B is within the orthographic projection of A" or "the orthographic projection of A contains the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0224] In the exemplary embodiments, taking 3 sub-pixels (1 pixel driving circuit row of sub-pixels, 3 pixel driving circuit columns of sub-pixels) in the display area (AA) as an example, the preparation process of one kind of display substrate can include the following operations.

[0225] (101) A substrate is prepared on a glass carrier. In an exemplary embodiment, the substrate can be a flexible substrate, or can be a rigid substrate. The rigid substrate can include, but is not limited to, one or more of glass, quartz, and the flexible substrate can be, but is not limited to, one or more of polyethylene terephthalate, polyether ether ketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers. In an exemplary embodiment, the flexible substrate can include a first flexible material layer, a first inorganic material layer, a bonding layer, a second flexible material layer, and a second inorganic material layer stacked. The materials of the first and second flexible material layers can be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film, and the like, and the materials of the first and second inorganic material layers can be silicon nitride (SiNx) or silicon oxide (SiOx), and the like, for improving the water and oxygen resistance of the substrate, and the first and second inorganic material layers are also called barrier layers, and the material of the bonding layer can be amorphous silicon (a-si). In an exemplary embodiment, taking the stacked structure PI1 / Barrier1 / a-si / PI2 / Barrier2 as an example, the preparation process can include: first coating a layer of polyimide on the glass carrier, and after curing to form a film, a first flexible material (PI1) layer is formed; then depositing a barrier film on the first flexible layer to form a first barrier (Barrier1) layer covering the first flexible material layer; then depositing an amorphous silicon film on the first barrier layer to form an amorphous silicon (a-si) layer covering the first barrier layer; then coating a layer of polyimide on the amorphous silicon layer, and after curing to form a film, a second flexible material (PI2) layer is formed; then depositing a barrier film on the second flexible layer to form a second barrier (Barrier2) layer covering the second flexible layer, and the preparation of the substrate is completed.

[0226] (102) A first conductive layer pattern is formed. In an exemplary embodiment, forming the first conductive layer pattern can include: depositing a first conductive film on the substrate, patterning the first conductive film by a patterning process, and forming a first conductive layer pattern on the substrate, as shown in FIG. 7, which is a schematic diagram of the planar structure of three sub-pixels after the first conductive layer is formed. The first conductive layer can be referred to as a first gate metal (GATE1) layer.

[0227] In the example embodiment, the first conductive layer pattern can at least include: a second second initial signal line Vinit2-3, a first plate C11 of a first capacitor C1, a first plate C21 of a second capacitor C2; the main body part of the second second initial signal line Vinit2-3 can extend along the first direction X and be electrically connected to a plurality of third sub-pixels in one row of sub-pixels; in the same sub-pixel, the first plate C11 of the first capacitor C1 and the first plate C21 of the second capacitor C2 are connected to each other, for example, the first plate C11 of the first capacitor C1 and the first plate C21 of the second capacitor C2 are integrally formed, and the shapes of the first plate C11 of the first capacitor C1 and the first plate C21 of the second capacitor C2 can be rectangular.

[0228] In the example embodiment, in the second direction Y, the second second initial signal line Vinit2-3 can be located on one side of the first plate C11 of the first capacitor C1 and the first plate C21 of the second capacitor C2, and the first plate C11 of the first capacitor C1 is located on the side of the first plate C21 of the second capacitor C2 away from the second second initial signal line Vinit2-3. For example, in the same sub-pixel, in the second direction, the second second initial signal line Vinit2-3, the first plate C21 of the second capacitor C2, and the first plate C11 of the first capacitor C1 are arranged in sequence.

[0229] Taking the Mth row and Nth column sub-pixel as an example, in the second direction Y, the second second initial signal line Vinit2-3 in the Mth row can be located on the side of the first plate C21 of the second capacitor C2 in the sub-pixel close to the M+1th row sub-pixel; the first plate C11 of the first capacitor C1 can be located on the side of the first plate C21 of the second capacitor C2 in the sub-pixel close to the M-1th row sub-pixel.

[0230] In the example embodiment, the first conductive layer of the Nth column sub-pixel and the first conductive layer of the N+1th column sub-pixel can be mirror symmetrical relative to a first center line, the first conductive layer of the N+1th column sub-pixel and the first conductive layer of the N+2th column sub-pixel can be mirror symmetrical relative to a second center line, and the first conductive layer of the N+2th column sub-pixel and the first conductive layer of the N+3th column sub-pixel can be mirror symmetrical relative to a third center line. The first center line, the second center line, and the third center line can be straight lines extending along the second direction Y between adjacent columns of sub-pixels, for example, the first center line can be a straight line extending along the second direction Y between the Nth column and the N+1th column of sub-pixels, the second center line can be a straight line extending along the second direction Y between the N+1th column and the N+2th column of sub-pixels, and the third center line can be a straight line extending along the second direction Y between the N+2th column and the N+3th column of sub-pixels.

[0231] (103) forming a second conductive layer pattern. In an exemplary embodiment, forming the second conductive layer pattern can include: sequentially depositing a first insulating thin film and a second conductive thin film on the substrate on which the aforementioned pattern is formed, patterning the second conductive thin film by using a patterning process, forming a first insulating layer covering the first conductive layer, and a second conductive layer pattern disposed on the first insulating layer, as shown in FIGS. 8a and 8b, FIG. 8a is a planar structural diagram of three sub-pixels after the second conductive layer is formed, and FIG. 8b is a planar schematic diagram of the second conductive layer in FIG. 8a. In an exemplary embodiment, the second conductive layer can be referred to as a second gate metal (GATE2) layer.

[0232] In an exemplary embodiment, the second conductive layer pattern at least includes: a second plate C12 of the first capacitor C1, a second plate C22 of the second capacitor C2. In the second direction Y, the second plate C12 of the first capacitor C1 can be located on one side of the second plate C22 of the second capacitor C2 in the same sub-pixel, for example, in the same sub-pixel, the second plate C22 of the second capacitor C2 and the second plate C12 of the first capacitor C1 can be arranged in sequence along the second direction Y.

[0233] In an exemplary embodiment, the second plate C12 of the first capacitor C1 and the second plate C22 of the second capacitor C2 can have a rectangular profile, and the orthographic projection of the second plate C12 of the first capacitor C1 and the second plate C22 of the second capacitor C2 on the substrate can have an overlapping area with the orthographic projection of the first plate C11 of the first capacitor C1 and the first plate C21 of the second capacitor C2 on the substrate, for example, the orthographic projection of the second plate C12 of the first capacitor C1 and the second plate C22 of the second capacitor C2 on the substrate can be located within the range of the orthographic projection of the first plate C11 of the first capacitor C1 and the first plate C21 of the second capacitor C2 on the substrate. In an exemplary embodiment, the first plate C11 of the first capacitor C1 and the second plate C12 of the first capacitor C1 constitute the first capacitor C1, and the first plate C21 of the second capacitor C2 and the second plate C22 of the second capacitor C2 constitute the second capacitor C2.

[0234] In an exemplary embodiment, an opening K11 can be disposed on the second plate C22 of the second capacitor C2, and the opening K11 can be located at a middle portion or an edge position of the second plate C22 of the second capacitor C2 (for example, the opening K11 can be located at a corner of the second plate C22 of the second capacitor C2). The opening K11 can have a rectangular profile, the opening K11 exposes the first insulating layer covering the first plate C21 of the second capacitor C2, and the orthographic projection of the first plate C21 of the second capacitor C2 on the substrate contains the orthographic projection of the opening K11 on the substrate. In an exemplary embodiment, the opening K11 is configured to accommodate a ninth via to be formed subsequently, the ninth via is located in the opening K11 and exposes the first plate C21 of the second capacitor C2 (also the first plate C11 of the first capacitor C1), so that the second electrode of the second transistor T2 to be formed subsequently is connected with the first plate C21 of the second capacitor C2 (also the first plate C11 of the first capacitor C1).

[0235] In an exemplary embodiment, the second conductive layer of the Nth column of sub-pixels and the second conductive layer of the N+1th column of sub-pixels can be mirror-symmetrical relative to the first center line, the second conductive layer of the N+1th column of sub-pixels and the second conductive layer of the N+2th column of sub-pixels can be mirror-symmetrical relative to the second center line, and the second conductive layer of the N+2th column of sub-pixels and the second conductive layer of the N+3th column of sub-pixels can be mirror-symmetrical relative to the third center line.

[0236] (104) Forming a semiconductor layer pattern. In an exemplary embodiment, forming a semiconductor layer pattern can include: sequentially depositing a second insulating thin film and a semiconductor thin film on the substrate on which the aforementioned pattern is formed, patterning the semiconductor thin film by a patterning process, forming a second insulating layer covering the substrate, and a semiconductor layer pattern disposed on the second insulating layer, as shown in FIGS. 9a and 9b, FIG. 9a is a planar structure diagram of three sub-pixels after forming a semiconductor layer, and FIG. 9b is a planar schematic diagram of the semiconductor layer in FIG. 9a.

[0237] In an exemplary embodiment, the semiconductor layer pattern in at least part of the sub-pixels at least includes: an active layer AT1 of the first transistor T1 to an active layer AT7 of the seventh transistor T7.

[0238] In an example embodiment, in the same sub-pixel, the active layer AT1 of the first transistor T1, the active layer AT2 of the second transistor T2, and the active layer AT4 of the fourth transistor T4 are connected to each other, and the active layer AT3 of the third transistor T3, the active layer AT5 of the fifth transistor T5, and the active layer AT7 of the seventh transistor T7 are connected to each other, for example, the active layer AT1 of the first transistor T1, the active layer AT2 of the second transistor T2, and the active layer AT4 of the fourth transistor T4 can be an integrated structure connected to each other, and the active layer AT3 of the third transistor T3, the active layer AT5 of the fifth transistor T5, and the active layer AT7 of the seventh transistor T7 can be an integrated structure connected to each other.

[0239] In an example embodiment, in the same sub-pixel, in the first direction X, the active layer of the first transistor T1, the active layer AT2 of the second transistor T2, and the active layer AT4 of the fourth transistor T4 are located on the same side of the active layer AT3 of the third transistor T3, the active layer AT5 of the fifth transistor T5, and the active layer AT6 of the sixth transistor T6; in the second direction Y, the active layer AT4 of the fourth transistor T4 and the active layer AT2 of the second transistor T2 are located on both sides of the active layer AT1 of the first transistor T1, the active layer AT5 of the fifth transistor T5 and the active layer AT6 of the sixth transistor T6 are located on both sides of the active layer AT3 of the third transistor T3, and the active layer AT7 of the seventh transistor T7 is located on the side of the active layer AT6 of the sixth transistor T6 away from the active layer AT3 of the third transistor T3.

[0240] In an example embodiment, taking the sub-pixel of the Mth row and the Nth column as an example for description: in the first direction X, the active layer AT1 of the first transistor T1, the active layer AT2 of the second transistor T2, and the active layer AT4 of the fourth transistor T4 are located on the side of the active layer AT3 of the third transistor T3, the active layer AT5 of the fifth transistor T5, and the active layer AT6 of the sixth transistor T6 away from the sub-pixel of the N+1th column; in the second direction Y, the active layer AT4 of the fourth transistor T4 is located on the side of the active layer AT1 of the first transistor T1 away from the sub-pixel of the M+1th row, the active layer AT2 of the second transistor T2 is located on the side of the active layer AT1 of the first transistor T1 away from the sub-pixel of the M-1th row, the active layer AT7 of the seventh transistor T7 is located on the side of the active layer AT6 of the sixth transistor T6 close to the sub-pixel of the M+1th row, and the active layer AT5 of the fifth transistor T5 is located on the side of the active layer AT3 of the third transistor T3 away from the sub-pixel of the M+1th row.

[0241] In the example embodiment, the active layer AT1 of the first transistor T1, the active layer AT2 of the second transistor T2, the active layer AT3 of the third transistor T3, the active layer AT4 of the fourth transistor T4, the active layer AT5 of the fifth transistor T5 can have an "I" shape, the active layer AT6 of the sixth transistor T6 can have an "I" shape or a "mountain" shape, and the active layer AT7 of the seventh transistor T7 can have an "L" shape.

[0242] In the example embodiment, the active layer of at least some of the transistors can include a first region, a second region, and a channel region between the first region and the second region. In the example embodiment, the first region AT11 of the active layer AT1 of the first transistor T1 can serve as the first region AT21 of the active layer AT2 of the second transistor T2, the second region AT12 of the active layer AT1 of the first transistor T1 can serve as the second region AT42 of the active layer AT4 of the fourth transistor T4, the first region AT31 of the active layer AT3 of the third transistor T3 can serve as the second region AT52 of the active layer AT5 of the fifth transistor T5, the second region AT32 of the active layer AT3 of the third transistor T3 can serve as the first region AT61 of the active layer AT6 of the sixth transistor T6, the second region AT62 of the active layer AT6 of the sixth transistor T6 can serve as the second region AT72 of the active layer AT7 of the seventh transistor T7, and the first region AT41 of the active layer AT4 of the fourth transistor T4, the first region AT51 of the active layer AT5 of the fifth transistor T5, and the first region AT71 of the active layer AT7 of the seventh transistor T7 can be separately provided.

[0243] In an example embodiment, as shown in FIG. 9b, the first region AT51 of the active layer AT5 of the fifth transistor T5 in the Nth column is interconnected with the first region AT51 of the active layer AT5 of the fifth transistor T5 in the N+1th column, and the first region AT21 of the active layer AT2 of the second transistor T2 in the N+1th column (also the first region AT11 of the active layer AT1 of the first transistor T1) is interconnected with the first region AT21 of the active layer AT2 of the second transistor T2 in the N+2th column (also the first region AT11 of the active layer AT1 of the first transistor T1). In an example embodiment, since the first region of the active layer of the fifth transistor T5 in the sub-pixel is electrically connected with the first power supply line formed subsequently, by forming the first regions of the active layers of the fifth transistors T5 of the adjacent sub-pixels into an integrated structure interconnected with each other, the first electrode of the fifth transistor T5 in the adjacent sub-pixel can have substantially the same electric potential, which is conducive to improving the uniformity of the panel display, avoiding display defects of the display substrate, and ensuring the display effect of the display substrate.

[0244] In an example embodiment, the semiconductor layer in the Nth column and the semiconductor layer in the N+1th column can be mirror-symmetrical relative to the first center line, the semiconductor layer in the N+1th column and the semiconductor layer in the N+2th column can be mirror-symmetrical relative to the second center line, and the semiconductor layer in the N+2th column and the semiconductor layer in the N+3th column can be mirror-symmetrical relative to the third center line.

[0245] In an example embodiment, the conductor layer can employ an oxide, i.e., the first transistor T1 to the seventh transistor T7 are oxide thin film transistors. In an example embodiment, the oxide can be any one or more of the following: indium gallium zinc oxide (InGaZnO), indium gallium zinc nitride oxide (InGaZnON), zinc oxide (ZnO), zinc nitride oxide (ZnON), zinc tin oxide (ZnSnO), cadmium tin oxide (CdSnO), gallium tin oxide (GaSnO), titanium tin oxide (TiSnO), copper aluminum oxide (CuAlO), strontium copper oxide (SrCuO), lanthanum copper sulfur oxide (LaCuOS), gallium nitride (GaN), indium gallium nitride (InGaN), aluminum gallium nitride (AlGaN), and indium gallium aluminum nitride (InGaAlN). In some possible implementations, the semiconductor thin film can employ indium gallium zinc oxide (IGZO), which has a higher electron mobility than amorphous silicon. Since the leakage current of the IGZO TFT is relatively small, the N-type transistor can be employed to avoid the leakage of the first node N1 in the light emitting stage.

[0246] (105) Forming a third conductive layer pattern. In an example embodiment, forming the third conductive layer pattern can include: on the substrate on which the aforementioned patterns are formed, sequentially depositing a third insulating thin film and a third conductive thin film, patterning the third conductive thin film by a patterning process, forming a third insulating layer covering the semiconductor layer, and a third conductive layer pattern disposed on the third insulating layer, as shown in FIGS. 10a to 10b, FIG. 10a is a plan view of the three sub-pixels after the third conductive layer is formed, and FIG. 10b is a plan view of the third conductive layer in FIG. 10a. In an example embodiment, the third conductive layer can be referred to as a third gate metal (GATE3) layer.

[0247] In an example embodiment, the third conductive layer pattern at least includes: a first light emitting control line EM1, a second light emitting control line EM2, a control electrode T1g of the first transistor T1 to a control electrode T4g of the fourth transistor T4, and a control electrode T7g of the seventh transistor T7. The first light emitting control line EM1 and the second light emitting control line EM2 can be polyline or bar-shaped extending along the first direction X in the body portion. In the same sub-pixel row, the second light emitting control line EM2 and the first light emitting control line EM1 can be arranged at intervals along the second direction Y. In the same sub-pixel in the second direction Y, the control electrode T1g of the first transistor T1 to the control electrode T4g of the fourth transistor T4 are located between the first light emitting control line EM1 and the second light emitting control line EM2, and the control electrode T7g of the seventh transistor T7 is located on the side of the second light emitting control line EM2 away from the first light emitting control line EM1.

[0248] In the exemplary embodiments, the region where the first light-emitting control line EM1 overlaps with the active layer AT5 of the fifth transistor T5 can serve as the control electrode of the fifth transistor T5, and the region where the second light-emitting control line EM2 overlaps with the active layer AT6 of the sixth transistor T6 can serve as the control electrode of the sixth transistor T6.

[0249] In the exemplary embodiments, the orthogonal projection of the control electrode T1g of the first transistor T1 on the substrate at least partially overlaps with the orthogonal projection of the active layer AT1 of the first transistor T1 on the substrate; the orthogonal projection of the control electrode T2g of the second transistor T2 on the substrate at least partially overlaps with the orthogonal projection of the active layer AT2 of the second transistor T2 on the substrate; the orthogonal projection of the control electrode T3g of the third transistor T3 on the substrate at least partially overlaps with the orthogonal projection of the active layer AT3 of the third transistor T3 on the substrate; the orthogonal projection of the control electrode T4g of the fourth transistor T4 on the substrate at least partially overlaps with the orthogonal projection of the active layer AT4 of the fourth transistor T4 on the substrate; and the orthogonal projection of the control electrode T7g of the seventh transistor T7 on the substrate at least partially overlaps with the orthogonal projection of the active layer AT7 of the seventh transistor T7 on the substrate.

[0250] In the exemplary embodiments, the control electrode T1g of the first transistor T1, the control electrode T2g of the second transistor T2, the control electrode T4g of the fourth transistor T4, and the control electrode T7g of the seventh transistor T7 are substantially rectangular structures, and the control electrode T3g of the third transistor T3 is substantially an "L" shaped structure. In the same sub-pixel, in the second direction Y, the control electrode T1g of the first transistor T1, the control electrode T2g of the second transistor T2, the control electrode T3g of the third transistor T3, and the control electrode T4g of the fourth transistor T4 are located between the first light-emitting control line EM1 and the second light-emitting control line EM2, the control electrode T7g of the seventh transistor T7 is located on the side of the second light-emitting control line EM2 away from the first light-emitting control line EM1, and the control electrode T1g of the first transistor T1 is located between the control electrode T2g of the second transistor T2 and the control electrode T4g of the fourth transistor T4; in the first direction X, in the same sub-pixel, the control electrode T1g of the first transistor T1, the control electrode T2g of the second transistor T2, and the control electrode T4g of the fourth transistor T4 are located on the same side of the control electrode T3g of the third transistor T3.

[0251] In the example embodiment, the control electrode T1g of the first transistor T1 of the (N+1)th column of sub-pixels is connected to the control electrode T1g of the first transistor T1 of the (N+2)th column of sub-pixels, for example, the control electrode T1g of the first transistor T1 of the (N+1)th column of sub-pixels and the control electrode T1g of the first transistor T1 of the (N+2)th column of sub-pixels can be an integrated structure connected to each other. In the example embodiment, since the control electrode T1g of the first transistor T1 in the sub-pixel is connected to the first reset control line Reset1 formed subsequently, by forming the control electrode T1g of the first transistor T1 of adjacent sub-pixels into an integrated structure connected to each other, it can be ensured that the control electrode T1g of the first transistor T1 of adjacent sub-pixels has substantially the same potential, which is conducive to improving the uniformity of panel display, avoiding display defects of the display substrate, and ensuring the display effect of the display substrate

[0252] In the example embodiment, the third conductive layer of the Nth column and the third conductive layer of the (N+1)th column can be mirror symmetrical with respect to the first center line, the third conductive layer of the (N+1)th column and the third conductive layer of the (N+2)th column can be mirror symmetrical with respect to the second center line, and the third conductive layer of the (N+2)th column and the third conductive layer of the (N+3)th column can be mirror symmetrical with respect to the third center line.

[0253] In the example embodiment, after forming the third conductive layer pattern, the third conductive layer can be used as a shield to conduct the semiconductor layer. The semiconductor layer in the area shielded by the third conductive layer forms the channel region of the first transistor T1 to the seventh transistor T7, and the semiconductor layer in the area not shielded by the third conductive layer is conductive, that is, the first region and the second region of the active layer AT1 of the first transistor T1 to the active layer AT7 of the seventh transistor T7 are conductive.

[0254] (106) Forming a fourth insulating layer pattern. In the example embodiment, forming the fourth insulating layer pattern can include: depositing a fourth insulating film on the substrate on which the aforementioned patterns are formed, and patterning the fourth insulating film by a patterning process to form a fourth insulating layer covering the third conductive layer, the fourth insulating layer being provided with a plurality of vias, as shown in FIG. 11, which is a planar structure diagram of three sub-pixels after the fourth insulating layer is formed.

[0255] In the example embodiment, the plurality of vias in at least part of the sub-pixels at least include: a first via V1, a second via V2, a third via V3, a fourth via V4, a fifth via V5, a sixth via V6, a seventh via V7, an eighth via V8, a ninth via V9, a tenth via V10, an eleventh via V11, a twelfth via V12, a thirteenth via V13, a fourteenth via V14, a fifteenth via V15, a sixteenth via V16, a seventeenth via V17, and an eighteenth via V18.

[0256] In the example embodiment, the first via V1 is located within the range of the active layer AT1 of the first transistor T1 on the substrate, the fourth insulating layer and the third insulating layer within the first via V1 are etched away, exposing the surface of the first region AT11 of the active layer AT1 of the first transistor T1 (also the first region AT21 of the active layer AT2 of the second transistor T2). The first via V1 is configured to connect the first electrode of the first transistor T1 and the first electrode of the second transistor T2 to the active layer AT1 and AT2 of the first and second transistors T1 and T2 respectively through the via.

[0257] In the example embodiment, the second via V2 is located within the range of the active layer AT1 of the first transistor T1 on the substrate, the fourth insulating layer, the third insulating layer and the second region AT12 of the active layer AT1 of the first transistor T1 (also the second region AT42 of the active layer AT4 of the fourth transistor T4) within the second via V2 are etched away. The second via V2 is configured to connect the second electrode of the first transistor T1 and the second electrode of the fourth transistor T4 to the active layer AT1 and AT4 of the first and fourth transistors T1 and T4 respectively through the via.

[0258] In the example embodiment, the third via V3 is located within the range of the active layer AT2 of the second transistor T2 on the substrate, the fourth insulating layer and the third insulating layer within the third via V3 are etched away, exposing the surface of the second region AT22 of the active layer AT2 of the second transistor T2. The third via V3 is configured to connect the second electrode of the second transistor T2 to the active layer AT2 of the second transistor T2 through the via.

[0259] In the example embodiment, the fourth via V4 is located within the range of the active layer AT3 of the third transistor T3 on the substrate, the fourth insulating layer and the third insulating layer within the fourth via V4 are etched away, exposing the surface of the second region AT32 of the active layer AT3 of the third transistor T3 (also the first region AT61 of the active layer AT6 of the sixth transistor T6). The fourth via V4 is configured to connect the second electrode of the third transistor T3 and the first electrode of the sixth transistor T6 to the active layer AT3 and AT6 of the third and sixth transistors T3 and T6 respectively through the via.

[0260] In the exemplary embodiment, the fifth via V5 is located within the range of the active layer AT4 of the fourth transistor T4 on the substrate, the fourth insulating layer and the third insulating layer within the fifth via V5 are etched to expose the first region AT41 of the active layer AT4 of the fourth transistor T4. The fifth via V5 is configured to connect the first electrode of the fourth transistor T4 to the active layer AT4 of the fourth transistor T4 through the via.

[0261] In the exemplary embodiment, the sixth via V6 is located within the range of the active layer AT5 of the fifth transistor T5 on the substrate, the fourth insulating layer and the third insulating layer within the sixth via V6 are etched to expose the surface of the first region AT51 of the active layer AT5 of the fifth transistor T5. The sixth via V6 is configured to connect the first electrode of the fifth transistor T5 to the active layer AT5 of the fifth transistor T5 through the via.

[0262] In the exemplary embodiment, the seventh via V7 is located within the range of the active layer AT6 of the sixth transistor T6 on the substrate, the fourth insulating layer and the third insulating layer within the seventh via V7 are etched to expose the surface of the second region AT62 of the active layer AT6 of the sixth transistor T6 (also the first region AT71 of the active layer AT7 of the seventh transistor T7). The seventh via V7 is configured to connect the second electrode of the sixth transistor T6 to the active layer AT6 of the sixth transistor T6 through the via, and to connect the second electrode of the seventh transistor T7 to the active layer AT7 of the seventh transistor T7 through the via.

[0263] In the exemplary embodiment, the eighth via V8 is located within the range of the active layer AT7 of the seventh transistor T7 in the first sub-pixel and the second sub-pixel on the substrate, the fourth insulating layer and the third insulating layer within the eighth via V8 are etched to expose the surface of the first region AT71 of the active layer AT7 of the seventh transistor T7. The eighth via V8 is configured to connect the first electrode of the seventh transistor T7 to the active layer AT7 of the seventh transistor T7 through the via, and to connect the first second initial signal line Vinit2-1 to the active layer AT7 of the seventh transistor T7 through the via.

[0264] In the example embodiment, the normal projection of the ninth via V9 on the substrate is located within the range of the normal projection of the first plate C21 of the second capacitor C2 on the substrate (the normal projection of the ninth via V9 on the substrate can be located within the range of the normal projection of the opening K11 on the substrate), the fourth insulating layer, the third insulating layer, the second insulating layer, and the first insulating layer within the ninth via V9 are etched away, exposing the surface of the first plate C21 of the second capacitor C2 (also the first plate C11 of the first capacitor C1). The ninth via V9 is configured to enable the second electrode of the second transistor T2 formed subsequently to be connected to the first plate C21 of the second capacitor C2 (also the first plate C11 of the first capacitor C1) through the via.

[0265] In the example embodiment, the normal projection of the tenth via V10 on the substrate is located within the range of the normal projection of the second plate C12 of the first capacitor C1 on the substrate, the fourth insulating layer, the third insulating layer, and the second insulating layer within the tenth via V10 are etched away, exposing the surface of the second plate C12 of the first capacitor C1. The tenth via V10 is configured to enable the second electrode of the third transistor T3 formed subsequently (also the first electrode of the sixth transistor T6) to be connected to the second plate C12 of the first capacitor C1 through the via.

[0266] In the example embodiment, the normal projection of the eleventh via V11 on the substrate is located within the range of the normal projection of the second plate C22 of the second capacitor C2 on the substrate, the fourth insulating layer, the third insulating layer, and the second insulating layer within the eleventh via V11 are etched away, exposing the surface of the second plate C22 of the second capacitor C2. The eleventh via V11 is configured to enable the fourth connection electrode formed subsequently to be connected to the second plate C22 of the second capacitor C2 through the via.

[0267] In the example embodiment, the normal projection of the twelfth via V12 on the substrate is located within the range of the normal projection of the control electrode T1g of the first transistor T1 on the substrate, the fourth insulating layer within the twelfth via V12 is etched away, exposing the surface of the control electrode T1g of the first transistor T1. The twelfth via V12 is configured to enable the first reset control line Reset1 formed subsequently to be connected to the control electrode T1g of the first transistor T1 through the via.

[0268] In the example embodiment, the normal projection of the thirteenth via V13 on the substrate is located within the range of the normal projection of the control electrode T2g of the second transistor T2 on the substrate, the fourth insulating layer within the thirteenth via V13 is etched away, exposing the surface of the control electrode T2g of the second transistor T2. The thirteenth via V13 is configured to enable the second reset control line Reset2 formed subsequently to be connected to the control electrode T2g of the second transistor T2 through the via.

[0269] In the example embodiment, the fourteenth via V14 is located within the range of the orthogonal projection of the control electrode T3g of the third transistor T3 on the substrate, and the fourth insulating layer in the fourteenth via V14 is etched to expose the surface of the control electrode T3g of the third transistor T3. The fourteenth via V14 is configured to connect the second electrode of the first transistor T1 (also the second electrode of the fourth transistor T4) formed subsequently therewith the control electrode T3g of the third transistor T3.

[0270] In the example embodiment, the fifteenth via V15 is located within the range of the orthogonal projection of the control electrode T3g of the third transistor T3 on the substrate, and the fourth insulating layer in the fifteenth via V15 is etched to expose the surface of the control electrode T3g of the third transistor T3. The fifteenth via V15 is configured to connect the fourth connection electrode formed subsequently therewith the control electrode T3g of the third transistor T3.

[0271] In the example embodiment, the sixteenth via V16 is located within the range of the orthogonal projection of the control electrode T4g of the fourth transistor T4 on the substrate, and the fourth insulating layer in the sixteenth via V16 is etched to expose the surface of the control electrode T4g of the fourth transistor T4. The sixteenth via V16 is configured to connect the scan signal line Gate formed subsequently therewith the control electrode T4g of the fourth transistor T4.

[0272] In the example embodiment, the seventeenth via V17 is located within the range of the orthogonal projection of the control electrode T7g of the seventh transistor T7 on the substrate, and the fourth insulating layer in the seventeenth via V17 is etched to expose the surface of the control electrode T4g of the fourth transistor T4. The seventeenth via V17 is configured to connect the third reset control line Reset3 formed subsequently therewith the control electrode T7g of the seventh transistor T7.

[0273] In the example embodiment, the eighteenth via V18 is located within the range of the orthogonal projection of the second second initial signal line Vinit2-3 on the substrate, and the fourth insulating layer, the third insulating layer and the second insulating layer in the eighteenth via V18 are etched to expose the surface of the second second initial signal line Vinit2-3. The eighteenth via V18 is configured to connect the eighth connection electrode formed subsequently therewith the second second initial signal line Vinit2-3.

[0274] (107) A fourth conductive layer pattern is formed. In an exemplary embodiment, forming the fourth conductive layer can include: on the substrate on which the aforementioned patterns are formed, depositing a fourth conductive thin film, patterning the fourth conductive thin film using a patterning process, and forming the fourth conductive layer disposed on the fourth insulating layer, as shown in FIGS. 12a and 12b, FIG. 12a is a plan view of three sub-pixels after the fourth conductive layer is formed, and FIG. 12b is a plan view of the fourth conductive layer in FIG. 12a. In an exemplary embodiment, the fourth conductive layer can be referred to as a first source-drain metal (SD1) layer.

[0275] In an exemplary embodiment, the fourth conductive layer includes at least: a first power connection line VDDL, a second power connection line VSSL, a scan signal line Gate, a first reset control line Reset1, a first initial signal line Vinit1, a second reset control line Reset2, a first second initial signal line Vinit2-1, a third reset control line Reset3, a first connection electrode L1, a second connection electrode L2, a third connection electrode L3, a fourth connection electrode L4, a fifth connection electrode L5, a sixth connection electrode L6, and a seventh connection electrode L7.

[0276] In an exemplary embodiment, the main body part of the first power connection line VDDL, the second power connection line VSSL, the scan signal line Gate, the first reset control line Reset1, the first initial signal line Vinit1, the second reset control line Reset2, the first second initial signal line Vinit2-1, and the third reset control line Reset3 can be in a strip shape structure or a polyline shape structure extending along the first direction X, and the first power connection line VDDL, the second power connection line VSSL, the scan signal line Gate, the first reset control line Reset1, the first initial signal line Vinit1, the second reset control line Reset2, the first second initial signal line Vinit2-1, and the third reset control line Reset3 can be arranged in sequence along the opposite direction of the second direction Y.

[0277] In an exemplary embodiment, in the same sub-pixel, along the second direction Y, the first connection electrode L1 is located between the first power connection line VDDL and the second power connection line VSSL, the second connection electrode L2 and the third connection electrode L3 are located between the scan signal line Gate and the first reset control line Reset1, the third connection electrode L3 and the second connection electrode L2 are arranged in sequence along the second direction Y, the fourth connection electrode L4 is located between the first reset control line Reset1 and the first initial signal line Vinit1, the fifth connection electrode L5 is located between the first initial signal line Vinit1 and the main body part of the second reset control line Reset2, and the sixth connection electrode L6 is located between the second reset control line Reset2 and the first second initial signal line Vinit2-1.

[0278] In an example embodiment, the first power connection line VDDL can be connected to the first region AT51 of the active layer AT5 of the fifth transistor T5 in a row of sub-pixels through a sixth via V6 in the row of sub-pixels. In an example embodiment, the first power connection line VDDL can be configured as the first electrode of the fifth transistor T5 to provide the first power voltage to a plurality of fifth transistors T5 in the sub-pixel.

[0279] In an example embodiment, the scan signal line Gate can be connected to the control electrode T4g of the fourth transistor T4 in a row of sub-pixels through a sixteenth via V16 in the row of sub-pixels, and configured to provide a scan signal to a plurality of fourth transistors T4 in the row of sub-pixels.

[0280] In an example embodiment, the second power connection line VSSL can be connected to a plurality of second power lines formed subsequently, at least part of the second power connection line VSSL is electrically connected to the plurality of second power lines, at least part of the second power lines is electrically connected to the plurality of second power connection lines VSSL in a plurality of pixel driving circuits, at least part of the second power connection lines VSSL and at least part of the second power lines are connected to each other to form a grid-like structure, which can reduce the voltage drop of the second power lines and improve the display uniformity of the display substrate.

[0281] In an example embodiment, the first reset control line Reset1 can be connected to the control electrode T1g of the first transistor T1 in a row of sub-pixels through a twelfth via V12 in the row of sub-pixels, and configured to provide a first reset control signal to a plurality of first transistors T1 in the row of sub-pixels.

[0282] In an example embodiment, the first initial signal line Vinit1 can be connected to the first region AT11 of the active layer AT1 of the first transistor T1 (also the first region AT21 of the active layer AT2 of the second transistor T2) in a row of sub-pixels through a first via V1 in the row of sub-pixels, and configured to provide a first initial signal to the first transistor T1 and the second transistor T2 in the row of sub-pixels. In an example embodiment, the first initial signal line Vinit1 can be configured as the first electrode of the first transistor T1 and as the first electrode of the second transistor T2.

[0283] In an example embodiment, the second reset control line Reset2 can be connected to the control electrode T2g of the second transistor T2 in a row of sub-pixels through a thirteenth via V13 in the row of sub-pixels, and configured to provide a second reset control signal to a plurality of second transistors T2 in the row of sub-pixels.

[0284] In the example embodiment, the first second initial signal line Vinit2-1 can be connected with the first area AT71 of the active layer AT7 of the seventh transistor T7 in the first and second sub-pixels in the row of sub-pixels through the eighth via V8 in the row of sub-pixels, and configured to provide the second initial signal to the seventh transistor T7 in the first and second sub-pixels in the row of sub-pixels. In the example embodiment, the first second initial signal line Vinit2-1 can be configured as the first electrode of the seventh transistor T7 in the first and second sub-pixels.

[0285] In the example embodiment, the third reset control line Reset3 can be connected with the control electrode T7g of the seventh transistor T7 in the row of sub-pixels through the seventeenth via V17 in the row of sub-pixels, and configured to provide the third reset control signal to the plurality of seventh transistors T7 in the row of sub-pixels.

[0286] In the example embodiment, the first connection electrode L1 is connected with the first area AT41 of the active layer AT4 of the fourth transistor T4 through the fifth via V5. In the example embodiment, the first connection electrode L1 can be configured as the first electrode of the fourth transistor T4, and configured to be connected with the data signal line formed subsequently.

[0287] In the example embodiment, the main body portion of the second connection electrode L2 is along the first direction X, the first end is connected with the second area AT12 of the active layer AT1 of the first transistor T1 (also the second area AT42 of the active layer AT4 of the fourth transistor T4) through the second via V2, and the second end is connected with the control electrode T3g of the third transistor T3 through the fourteenth via V14. The second area AT12 of the active layer AT1 of the first transistor T1 (also the second area AT42 of the active layer AT4 of the fourth transistor T4) and the control electrode T3g of the third transistor T3 are electrically connected through the second connection electrode L2, so that the second electrode of the first transistor T1, the second electrode of the fourth transistor T4, and the control electrode T4g of the third transistor T3 have the same potential. In the example embodiment, the second connection electrode L2 can be configured as the second electrode of the first transistor T1 and the second electrode of the fourth transistor T4.

[0288] In the example embodiment, the main body portion of the third connection electrode L3 extends along the first direction X, one end thereof is connected to the second region AT32 of the active layer AT3 of the third transistor T3 (also the first region AT61 of the active layer AT6 of the sixth transistor T6) through the fourth via V4, and the other end thereof is connected to the second plate C12 of the first capacitor C1 through the tenth via V10. The second region AT32 of the active layer AT3 of the third transistor T3 (also the first region AT61 of the active layer AT6 of the sixth transistor T6) and the second plate C12 of the first capacitor C1 are connected through the third connection electrode L3. In the example embodiment, the third connection electrode L3 can serve as the second electrode of the third transistor T3 and the first electrode of the sixth transistor T6.

[0289] In the example embodiment, the main body portion of the fourth connection electrode L4 extends along the first direction X, one end thereof is connected to the second plate C22 of the second capacitor C2 through the eleventh via V11, and the other end thereof is connected to the control electrode T3g of the third transistor T3 through the fifteenth via V15. The second plate C22 of the second capacitor C2 and the control electrode T3g of the third transistor T3 are electrically connected through the third connection electrode L3, so that the third connection electrode L3 and the second plate C22 of the second capacitor C2 have the same potential.

[0290] In the example embodiment, the main body portion of the fifth connection electrode L5 extends along the first direction X, one end thereof is connected to the second region AT22 of the active layer AT2 of the second transistor T2 through the third via V3, and the other end thereof is connected to the first plate C21 of the second capacitor C2 (also the first plate C11 of the first capacitor C1) through the ninth via V9. The second region AT22 of the active layer AT2 of the second transistor T2 and the first plate C21 of the second capacitor C2 (also the first plate C11 of the first capacitor C1) are connected through the fifth connection electrode L5. In the example embodiment, the fifth connection electrode L5 can serve as the second electrode of the second transistor T2.

[0291] In the example embodiment, the sixth connection electrode L6 is connected to the second region AT62 of the active layer AT6 of the sixth transistor T6 (also the second region AT72 of the active layer AT7 of the seventh transistor T7) through the seventh via V7. In the example embodiment, the sixth connection electrode L6 can serve as the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7, and the sixth connection electrode L6 is configured to be connected to the anode connection electrode of the light emitting element formed subsequently.

[0292] In the example embodiment, one end of the seventh connection electrode L7 can be connected to the first region AT71 of the active layer AT7 of the seventh transistor T7 through the eighth via V8, and the other end can be connected to the second second initial signal line Vinit2-3 through the eighteenth via V18. In the example embodiment, the seventh connection electrode L7 can serve as the first electrode of the seventh transistor T7.

[0293] (108) Forming the fifth insulating layer and the first planar layer pattern. In the example embodiment, forming the fifth insulating layer and the first planar layer pattern can include: on the substrate on which the aforementioned patterns are formed, first depositing a fifth insulating thin film, then coating a first planar thin film, and patterning the first planar thin film and the fifth insulating thin film by using a patterning process, to form the fifth insulating layer covering the fourth conductive layer pattern and the first planar layer disposed on the fifth insulating layer, the fifth insulating layer and the first planar layer being provided with a plurality of vias, as shown in FIG. 13, which is a planar structure diagram of the three sub-pixels after the first planar layer is formed.

[0294] In the example embodiment, the plurality of vias in each sub-pixel can at least include: the nineteenth via V19, the twentieth via V20, the twenty-first via V21, the twenty-second via V22, the twenty-third via V23, the twenty-fourth via V24, and the twenty-fifth via V25.

[0295] In the example embodiment, the normal projection of the nineteenth via V19 on the substrate is within the range of the normal projection of the first initial signal line Vinit1 on the substrate, and the first planar layer and the fifth insulating layer in the nineteenth via V19 are etched away, exposing the surface of the first initial signal line Vinit1. The nineteenth via V19 is configured to allow the subsequently formed first initial signal connection line to be connected to the first initial signal line Vinit1 through the via.

[0296] In the example embodiment, the normal projection of the twentieth via V20 on the substrate is within the range of the normal projection of the sixth connection electrode L6 on the substrate, and the first planar layer and the fifth insulating layer in the twentieth via V20 are etched away, exposing the surface of the sixth connection electrode L6. The twentieth via V20 is configured to allow the subsequently formed anode connection electrode of the light-emitting element to be electrically connected to the sixth connection electrode L6 through the via.

[0297] In the example embodiment, the normal projection of the twenty-first via V21 on the substrate is within the range of the normal projection of the first power connection line VDDL on the substrate, and the first planar layer and the fifth insulating layer in the twenty-first via V21 are etched away, exposing the surface of the first power connection line VDDL. The twenty-first via V21 is configured to allow the subsequently formed first power line to be connected to the first power connection line VDDL through the via.

[0298] In an example embodiment, the orthogonal projection of the twenty-second via V22 on the substrate is within the range of the orthogonal projection of the first connection electrode L1 on the substrate, the first planar layer and the fifth insulating layer in the twenty-second via V22 are etched away, exposing the surface of the first connection electrode L1. The twenty-second via V22 is configured to allow the subsequently formed data signal line to pass through the via and be electrically connected to the first connection electrode L1.

[0299] In an example embodiment, the orthogonal projection of the twenty-third via V23 on the substrate is within the range of the orthogonal projection of the seventh connection electrode L7 on the substrate, the first planar layer and the fifth insulating layer of the twenty-third via V23 are etched away, exposing the surface of the seventh connection electrode L7. The twenty-third via V23 is configured to allow the subsequently formed second second initial signal connection line Vinit2-3L to pass through the via and be electrically connected to the seventh connection electrode L7.

[0300] In an example embodiment, the orthogonal projection of the twenty-fourth via V24 on the substrate is within the range of the orthogonal projection of the first second initial signal line Vinit2-1 on the substrate, the first planar layer and the fifth insulating layer of the twenty-fourth via V24 are etched away, exposing the surface of the first second initial signal line Vinit2-1. The twenty-fourth via V24 is configured to allow the subsequently formed first second initial signal connection line Vinit2-1L to pass through the via and be electrically connected to the first second initial signal line Vinit2-1.

[0301] In an example embodiment, the orthogonal projection of the twenty-fifth via V25 on the substrate is within the range of the orthogonal projection of the second power supply connection line VSSL on the substrate, the first planar layer and the fifth insulating layer in the twenty-fifth via V25 are etched away, exposing the surface of the second power supply connection line VSSL. The twenty-fifth via V25 is configured to allow the subsequently formed second power supply line to pass through the via and be connected to the second power supply connection line VSSL.

[0302] (109) Forming a fifth conductive layer pattern. In an example embodiment, forming the fifth conductive layer can include: on the substrate on which the aforementioned pattern is formed, depositing a fifth conductive thin film, patterning the fifth conductive thin film using a patterning process, forming a fifth conductive layer disposed on the first planar layer, as shown in FIGS. 14a and 14b, FIG. 14a is a plan view of three sub-pixels after the fifth conductive layer is formed, and FIG. 14b is a plan view of the fifth conductive layer in FIG. 14a. In an example embodiment, the fifth conductive layer can be referred to as a second source-drain metal (SD2) layer.

[0303] In the example embodiment, the fifth conductive layer at least includes: a data signal line D, a first power supply line VDD, a second power supply line VSS, a first initial signal connection line Vinit1L, an anode connection electrode ZL, a first second initial signal connection line Vinit2-1L, and a second second initial signal connection line Vinit2-3L.

[0304] In the example embodiment, the data signal line D is a polyline shape extending along the second direction Y, and the data signal line D is connected to the first connection electrode L1 through the twenty-second via V22. Since the first connection electrode L1 is connected to the first area AT41 of the active layer AT4 of the fourth transistor T4 through the via, the connection between the data signal line D and the first electrode of the fourth transistor T4 is realized, and the data signal is written into the fourth transistor T4.

[0305] In the example embodiment, the first power supply line VDD is a polyline shape extending along the second direction Y, and the first power supply line VDD is connected to the first power supply connection line VDDL through the twenty-first via V21. Since the first power supply connection line VDDL is connected to the first area AT51 of the active layer AT5 of the fifth transistor T5 through the via, the connection between the first power supply line VDD and the fifth transistor T5 is realized, and the power supply signal is written into the first electrode of the fifth transistor T5. In the example embodiment, at least part of the first power supply connection line VDDL is electrically connected to a plurality of first power supply lines VDD, at least part of the first power supply line VDD is electrically connected to a plurality of first power supply connection lines VDDL, and at least part of the first power supply line is connected to at least part of the first power supply connection line VDDL to form a grid-like structure, which can reduce the voltage drop of the first power supply line VDD, so that the first power supply signals received by a plurality of sub-pixels in the display substrate are substantially consistent, and the display uniformity of the display substrate is improved. For example, each first power supply connection line VDDL is electrically connected to a plurality of first power supply lines VDD in a plurality of pixel driving circuits, each first power supply line VDD is electrically connected to a plurality of first power supply connection lines VDDL, and a plurality of first power supply lines are connected to a plurality of first power supply connection lines VDDL to form a grid-like structure.

[0306] In the example embodiment, the anode connection electrode ZL in the first sub-pixel is in the shape of an "I" or an "L", the anode connection electrode ZL in the second and third sub-pixels is in the shape of an "I", and the anode connection electrode ZL is connected to the sixth connection electrode L6 through the twentieth via V20. Since the sixth connection electrode L6 is connected to the second area AT62 of the active layer AT6 of the sixth transistor T6 (also the second area AT72 of the active layer AT7 of the seventh transistor T7) through the via, the connection between the anode connection electrode ZL and the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7 is realized.

[0307] In the example embodiment, the first initial signal connection line Vinit1L is a polyline shape extending along the second direction Y, the first initial signal connection line Vinit1L is connected with the first initial signal connection line Vinit1 through the nineteenth via V19, and the plurality of first initial signal connection lines Vinit1L and the plurality of first initial signal lines Vinit1 form a grid structure, so that the first initial signals received by the first transistor T1 and the second transistor T2 in adjacent sub-pixels are basically consistent, which is beneficial to improve the uniformity of panel display, avoid display defects of the display substrate, and ensure the display effect of the display substrate.

[0308] In the example embodiment, the first initial signal connection line Vinit1L is a polyline shape extending along the second direction Y, the first initial signal connection line Vinit1L is connected with the first initial signal connection line Vinit1 through the nineteenth via V19, and the plurality of first initial signal connection lines Vinit1L and the plurality of first initial signal lines Vinit1 form a grid structure, so that the first initial signals received by the first transistor T1 and the second transistor T2 in adjacent sub-pixels are basically consistent, which is beneficial to improve the uniformity of panel display, avoid display defects of the display substrate, and ensure the display effect of the display substrate.

[0309] In the example embodiment, the second initial signal connection line Vinit2-3L is a polyline shape extending along the second direction Y, the second initial signal connection line Vinit2-3L is connected with the second initial signal line Vinit2-3 through the twenty-third via V23, and the plurality of second initial signal connection lines Vinit2-3L and the plurality of second initial signal lines Vinit2-3 form a grid structure, so that the second initial signals received by the second transistor T2 in adjacent third sub-pixels are basically consistent, which is beneficial to improve the uniformity of panel display, avoid display defects of the display substrate, and ensure the display effect of the display substrate.

[0310] In an example embodiment, the second power supply lines VSS are in a zigzag shape extending along the second direction, the second power supply lines VSS can be connected with the second power supply connection lines VSSL through the twenty-fifth via holes V25, at least part of the second power supply connection lines VSSL are electrically connected with the plurality of second power supply lines VSS, at least part of the second power supply lines VSS are electrically connected with the plurality of second power supply connection lines VSSL located in the plurality of pixel driving circuits, at least part of the second power supply connection lines VSSL and at least part of the second power supply lines VSS are connected to form a grid structure, which can reduce the voltage drop of the second power supply lines VSS and improve the display uniformity of the display substrate; for example, each second power supply connection line VSSL is electrically connected with the plurality of second power supply lines VSS, each second power supply line VSS is electrically connected with the plurality of second power supply connection lines VSSL located in the plurality of pixel driving circuits, and the plurality of second power supply connection lines VSSL and the plurality of second power supply lines VSS are connected to form a grid structure. In an example embodiment, the display substrate can include a display area and a frame area located at the periphery of the display area, the display area can be provided with a plurality of sub-pixels, and the frame area can be provided with a second power supply signal line, in the first direction X, the second power supply connection line VSSL can be electrically connected with the second power supply signal line located in the frame area on both sides of the display area; in the second direction Y, the second power supply line VSS can be electrically connected with the second power supply signal line located in the frame area on both sides of the display area. The second power supply line VSS can be electrically connected with the cathode formed subsequently in the display area, which can reduce the voltage drop of the cathode and improve the display effect.

[0311] In an example embodiment, in the same pixel unit, the first initial signal connection line Vinit1L, the second power supply line VSS, the first power supply line VDD, the second second initial signal connection line Vinit2-3L, and the first second initial signal connection line Vinit2-1L can be arranged in the first direction X in sequence, in the first direction X, the data signal line D of the first sub-pixel is located on the side of the first initial signal connection line Vinit1L away from the second power supply line VSS, and the data signal line D of the second sub-pixel and the data signal line D of the third sub-pixel can be located between the second second initial signal connection line Vinit2-3L and the first second initial signal connection line Vinit2-1L; the anode connection electrode ZL in the first sub-pixel is located between the first initial signal connection line Vinit1L and the second power supply line VSS, the anode connection electrode ZL in the second sub-pixel is located between the first power supply line VDD and the second power supply line VSS, and the anode connection electrode ZL in the third sub-pixel is located between the first second initial signal connection line Vinit2-1L and the second second initial signal connection line Vinit2-3L.

[0312] In the example embodiment, the size of the second power supply line VSS along the first direction X is greater than the size of the other signal lines along the first direction X, which can reduce the impedance of the first power supply line VSS in the display area.

[0313] So far, the driving circuit layer is prepared on the substrate, and the driving circuit layer is provided with the pixel driving circuit of the plurality of sub-pixels. FIGS. 7 to 14b show the planar structure schematic diagram of the pixel driving circuit of the sub-pixel in the display substrate. In the example embodiment, in the direction perpendicular to the plane of the display substrate, the driving circuit layer can include the first conductive layer, the second conductive layer, the semiconductor layer, the third conductive layer, the fourth conductive layer, and the fifth conductive layer which are sequentially arranged on the substrate.

[0314] In the example embodiment, in the direction perpendicular to the plane of the display substrate, the driving circuit layer can include the first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer, the fifth insulating layer, and the first planar layer. The first insulating layer is arranged between the first conductive layer and the second conductive layer. The second insulating layer is arranged between the second conductive layer and the semiconductor layer. The third insulating layer is arranged between the semiconductor layer and the third conductive layer. The fourth insulating layer is arranged between the third conductive layer and the fourth conductive layer. The fifth insulating layer and the first planar layer are arranged between the fourth conductive layer and the fifth conductive layer.

[0315] In the example embodiment, after the driving circuit layer is prepared, the light-emitting structure layer is prepared on the driving circuit layer. The preparation process of the light-emitting structure layer can include the following operations. The second planar layer pattern is formed, and the second planar layer is provided with at least an anode via hole. The anode pattern (i.e., the anode conductive layer) is formed, and the anode is connected to the anode connection electrode through the anode via hole. The anode pixel definition layer is formed, and the pixel definition layer is provided with a pixel opening which exposes the anode. The organic light-emitting layer is formed by using the evaporation or inkjet printing process. The cathode is formed on the organic light-emitting layer. The encapsulation layer is formed, and the encapsulation layer can include the first encapsulation layer, the second encapsulation layer, and the third encapsulation layer which are stacked. The first encapsulation layer and the third encapsulation layer can be made of inorganic materials, and the second encapsulation layer can be made of organic materials. The second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer, which can prevent the external water vapor from entering the light-emitting structure layer. The step of forming the anode conductive layer is as follows:

[0316] (110) The second planar layer pattern is formed. In the example embodiment, forming the second planar layer pattern can include: on the substrate on which the aforementioned patterns are formed, coating a second planar film, and patterning the second planar film by using a patterning process to form a second planar layer covering the fifth conductive layer pattern, and the second planar layer is provided with a plurality of via holes. As shown in FIG. 15, FIG. 15 is a planar structure diagram of three sub-pixels after the second planar layer is formed.

[0317] In an example embodiment, the plurality of vias can include at least a twenty-sixth via V26.

[0318] In an example embodiment, the via of each sub-pixel includes at least a twenty-sixth via V26. The orthogonal projection of the twenty-sixth via V26 on the substrate is within the range of the orthogonal projection of the anode connecting electrode ZL on the substrate, the second planar layer within the twenty-sixth via V26 is removed to expose the surface of the anode connecting electrode ZL, and the twenty-sixth via V26 is configured to allow the subsequently formed anode to be electrically connected to the anode connecting electrode ZL through the via.

[0319] (111) Forming an anode conductive layer pattern. In an example embodiment, forming the anode conductive layer pattern can include: depositing an anode conductive thin film on the substrate on which the aforementioned pattern is formed, and patterning the anode conductive thin film using a patterning process to form an anode conductive layer pattern disposed on the second planar layer, as shown in FIGS. 16a and 16b, FIG. 16a is a schematic diagram of the planar structure of three sub-pixels after forming the anode conductive layer, and FIG. 16b is a planar schematic diagram of the anode conductive layer in FIG. 16a.

[0320] In an example embodiment, the anode conductive layer pattern can include at least a plurality of anodes AN, which can include: a first anode AN1, a second anode AN2, and a third anode AN3. The area where the first anode AN1 is located can form a red light emitting unit that emits red light, the area where the second anode AN2 is located can form a green light emitting unit that emits green light, and the area where the third anode AN3 is located can form a blue light emitting unit that emits blue light.

[0321] In an example embodiment, the first anode AN1, the second anode AN2, and the third anode AN3 can be connected to the anode connecting electrode ZL in the corresponding sub-pixel through the twenty-sixth via V26, respectively. Since the anode connecting electrode ZL in the sub-pixel is electrically connected to the second electrode of the sixth transistor T6 (also the second electrode of the seventh transistor T7) through the via, the first anode AN1, the second anode AN2, and the third anode AN3 can be connected to the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7 through the anode connecting electrode ZL, respectively, thereby realizing the driving of the light emitting device by the pixel driving circuit.

[0322] In an example embodiment, the anode AN can include an anode main body part AN01 and an anode connecting part AN02. The anode main body part AN01 can be in a rectangular structure. The anode connecting part AN02 is connected to the anode main body part AN01 at one end and is electrically connected to the anode connecting electrode ZL through the twenty-sixth via hole V26 at the other end. The anode connecting part AN02 can be in a strip structure or a block structure extending along the first direction X or the second direction Y. The anode connecting part AN02 can be configured to compensate for differences in parasitic capacitance between the plurality of sub-pixels due to signal traces. By providing the anode connecting part AN02, the parasitic capacitances of the plurality of sub-pixels can be substantially uniform, thereby improving the display uniformity of the display substrate.

[0323] (112) Forming a pixel definition layer pattern. In an example embodiment, forming the pixel definition layer pattern can include: depositing a pixel definition layer film on the substrate on which the aforementioned pattern is formed, patterning the pixel definition layer using a patterning process, and forming the pixel definition layer pattern disposed on the anode conductive layer. As shown in FIGS. 17a and 17b, FIG. 17a is a schematic diagram of the planar structure of three sub-pixels after the pixel definition layer is formed, and FIG. 17b is a schematic diagram of the planar structure of the pixel definition layer in FIG. 17a.

[0324] In an example embodiment, the pixel definition layer pattern can include a plurality of pixel openings K0 that expose the anode AN. In an example embodiment, the orthographic projection of the pixel openings K0 on the substrate is within the range of the orthographic projection of the anode AN on the substrate. In an example embodiment, the pixel openings K0 can include a pixel opening K01 of the first sub-pixel, a pixel opening K02 of the second sub-pixel, and a pixel opening K03 of the third sub-pixel. The orthographic projection of the pixel opening K01 of the first sub-pixel on the substrate overlaps with the orthographic projection of the first anode AN1 on the substrate. The orthographic projection of the pixel opening K02 of the second sub-pixel on the substrate overlaps with the orthographic projection of the second anode AN2 on the substrate. The orthographic projection of the pixel opening K03 of the third sub-pixel on the substrate overlaps with the orthographic projection of the third anode AN3 on the substrate.

[0325] In the example embodiment, the shielding layer, the first conductive layer, the second conductive layer, the third conductive layer, the fourth conductive layer, and the fifth conductive layer can be made of any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or an alloy of the above-mentioned metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), and can be a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo, Ti / Al / Ti, etc. The first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer, and the fifth insulating layer can be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and can be a single layer, multiple layers, or a composite layer.

[0326] In the example embodiment, taking the three sub-pixels (one sub-pixel pixel driving circuit row and three sub-pixel pixel driving circuit columns) in the display area (AA) as an example, another preparation process of the display substrate can include the steps (101) to (112) described above, and the difference from the steps (101) to (112) described above is as follows.

[0327] The first conductive layer formed in the step (102) described above can be as shown in FIG. 18. The difference between the first conductive layer shown in FIG. 18 and the first conductive layer shown in FIG. 7 is that the second initial signal line Vinit2-3 is not provided in the first conductive layer pattern shown in FIG. 18.

[0328] The semiconductor layer formed in the step (104) described above can be as shown in FIGS. 19a and 19b. FIG. 19a is a planar structural diagram of the three sub-pixels after the semiconductor layer is formed, and FIG. 19b is a planar schematic diagram of the semiconductor layer in FIG. 19a. The difference between the semiconductor layer shown in FIG. 19b and the semiconductor layer shown in FIG. 9b is that the shape of the active layer AT5 of the fifth transistor T5 is in the shape of an “L” in the semiconductor layer pattern shown in FIG. 19b.

[0329] The fourth insulating layer formed in the step (106) described above can be as shown in FIG. 20. The difference between the fourth insulating layer pattern shown in FIG. 20 and the fourth insulating layer pattern shown in FIG. 11 is that the eighteenth via hole V18 is not provided in the fourth insulating layer pattern shown in FIG. 20.

[0330] The fourth conductive layer formed in the step (107) can be as shown in FIGS. 21a and 21b. FIG. 21a is a plan view of the three sub-pixels after the fourth conductive layer is formed, and FIG. 21b is a plan view of the fourth conductive layer in FIG. 21a. The difference between the fourth conductive layer pattern shown in FIG. 21b and the fourth conductive layer pattern shown in FIG. 12b is that, in the fourth conductive layer pattern shown in FIG. 21b, the seventh connection electrode L7 is not provided, and a second second initial signal line Vinit2-3 is newly added. The second second initial signal line Vinit2-3 is connected to the first area AT71 of the active layer AT7 of the seventh transistor T7 in the third sub-pixel through the eighth via V8 in the third sub-pixel. In the second direction Y, the second second initial signal line Vinit2-3 is located on the side of the first second initial signal line Vinit2-1 away from the third reset control line Reset3, and the sixth connection electrode is located between the second second initial signal line Vinit2-3 and the second reset control line Reset2.

[0331] The fifth insulating layer and the first planarization layer pattern formed in the step (108) can be as shown in FIG. 22. FIG. 22 is a plan view of the three sub-pixels after the first planarization layer is formed. The difference between the first planarization layer pattern shown in FIG. 22 and the first planarization layer pattern shown in FIG. 13 is that, in the first planarization layer pattern shown in FIG. 22, the orthographic projection of the twenty-third via V23 on the substrate is located within the range of the orthographic projection of the second second initial signal line Vinit2-3 on the substrate. The second second initial signal line Vinit2-3 is connected to the second second initial signal connection line formed subsequently through the twenty-third via V23.

[0332] The fifth conductive layer formed in the step (109) can be as shown in FIGS. 23a and 23b. FIG. 23a is a plan view of the three sub-pixels after the fifth conductive layer is formed, and FIG. 23b is a plan view of the fifth conductive layer in FIG. 23a. The difference between the fifth conductive layer pattern shown in FIG. 23b and the fifth conductive layer pattern shown in FIG. 14b is that, in the fourth conductive layer pattern shown in FIG. 22b, the shape of the anode connection electrode ZL in the second sub-pixel is approximately "L" shaped or polyline shaped, and the shape of the anode connection electrode ZL in the third sub-pixel is approximately "L" shaped or polyline shaped or "I" shaped. In the first direction X, the second second initial signal connection line Vinit2-3L is located on the side of the first second initial signal connection line Vinit2-1L away from the first power supply line VDD. The plan view of the three sub-pixels after the second planarization layer and the anode conductive layer are sequentially formed based on FIG. 23a is shown in FIG. 23c.

[0333] In the example embodiment, taking the 3 sub-pixels (1 sub-pixel pixel driving circuit row, 3 sub-pixel pixel driving circuit column) in the display area (AA) as an example, another preparation process of the display substrate can include the steps (101) to (112) as described above, and the difference from the steps (101) to (112) is as follows:

[0334] The first conductive layer formed in the step (102) can be as shown in FIG. 24a. The first conductive layer shown in FIG. 24a is different from the first conductive layer shown in FIG. 7 in that: no second second initial signal line Vinit2-3 is provided in FIG. 24a, and a first second initial signal line Vinit2-1 is newly added, and the first second initial signal line Vinit2-1 is connected with the first area AT71 of the active layer AT7 of the seventh transistor T7 in the first sub-pixel through the seventh connecting electrode L7 formed subsequently.

[0335] The semiconductor layer formed in the step (104) can be as shown in FIGS. 24a and 24b. FIG. 24a is a planar structure diagram of three sub-pixels after the semiconductor layer is formed, and FIG. 24b is a planar schematic diagram of the semiconductor layer in FIG. 24a. The semiconductor layer shown in FIG. 24b is different from the semiconductor layer shown in FIG. 9b in that: the shape of the active layer AT5 of the fifth transistor T5 in the semiconductor layer pattern shown in FIG. 24b is in the shape of an “L” letter.

[0336] The fourth insulating layer formed in the step (106) can be as shown in FIG. 25. The fourth insulating layer pattern shown in FIG. 25 is different from the fourth insulating layer pattern shown in FIG. 11 in that: the eighteenth via hole V18 in the fourth insulating layer pattern shown in FIG. 25 is located in the first sub-pixel of one pixel unit; and the eighteenth via hole V18 in the fourth insulating layer shown in FIG. 11 is located in the third sub-pixel of one pixel unit, or is located between the second sub-pixel and the second sub-pixel.

[0337] The fourth conductive layer formed in step (107) can be as shown in FIGS. 26a and 26b. FIG. 26a is a plan view of the three sub-pixels after the fourth conductive layer is formed, and FIG. 26b is a plan view of the fourth conductive layer in FIG. 26a. The difference between the fourth conductive layer pattern shown in FIG. 26b and the fourth conductive layer pattern shown in FIG. 12b is that, in the fourth conductive layer pattern shown in FIG. 26b, the first second initial signal line Vinit2-1 is not provided, a third second initial signal line Vinit2-2 is newly added, the third second initial signal line Vinit2-2 is connected to the first region AT71 of the active layer AT7 of the seventh transistor T7 in the second sub-pixel through the eighth via V8 in the second sub-pixel; a second second initial signal line Vinit2-3 is newly added, the second second initial signal line Vinit2-3 is connected to the first region AT71 of the active layer AT7 of the seventh transistor T7 in the third sub-pixel through the eighth via V8 in the third sub-pixel, in the second direction Y, the second second initial signal line Vinit2-3 is located on the side of the third second initial signal line Vinit2-2 away from the third reset control line Reset3, the sixth connection electrode is located between the second second initial signal line Vinit2-3 and the second reset control line Reset2; the seventh connection electrode L7 is located in the first sub-pixel of the pixel unit, and the seventh connection electrode L7 in FIG. 12b is located in the third sub-pixel of the pixel unit.

[0338] The fifth insulating layer and the first planarization layer pattern formed in step (108) can be as shown in FIG. 27. FIG. 27 is a plan view of the three sub-pixels after the first planarization layer is formed. The difference between the first planarization layer pattern shown in FIG. 27 and the first planarization layer pattern shown in FIG. 13 is that, in the first planarization layer pattern shown in FIG. 27, the orthogonal projection of the twenty-third via V23 on the substrate is located within the range of the orthogonal projection of the second second initial signal line Vinit2-3 on the substrate, the second second initial signal line Vinit2-3 is connected to the second second initial signal connection line Vinit2-3L formed subsequently through the twenty-third via V23; the orthogonal projection of the twenty-fourth via V24 on the substrate is located within the range of the orthogonal projection of the third second initial signal line Vinit2-2 on the substrate, the third second initial signal line Vinit2-2 is connected to the third second initial signal connection line Vinit2-2L formed subsequently through the twenty-fourth via V24.

[0339] The fifth conductive layer formed in step (109) can be as shown in FIGS. 28a and 28b. FIG. 28a is a plan view of three sub-pixels after the fifth conductive layer is formed, and FIG. 28b is a plan view of the fifth conductive layer in FIG. 28a. The difference between the fifth conductive layer pattern shown in FIG. 28b and the fifth conductive layer pattern shown in FIG. 14b is that the fourth conductive layer pattern shown in FIG. 28b does not have the first second initial signal connection line Vinit2-1L, and has a third second initial signal connection line Vinit2-2L. The third second initial signal connection line Vinit2-2L is connected to the third second initial signal line Vinit2-2 through the twenty-fourth via hole V24 in the second sub-pixel. The shape of the anode connection electrode ZL in the second sub-pixel is approximately an "L" shape or a polyline, and the shape of the anode connection electrode ZL in the third sub-pixel is approximately an "L" shape, a polyline, or an "I" shape. In the first direction X, the second second initial signal connection line Vinit2-3L is located on the side of the third second initial signal connection line Vinit2-2L away from the first power supply line VDD. The plan view of the display substrate after the second planarization layer and the anode conductive layer are sequentially formed based on FIG. 28a is shown in FIG. 28c.

[0340] In the example embodiment, the row and column of sub-pixels described in the embodiments of the present disclosure can be understood as the row and column of pixel driving circuits in the sub-pixels. The anode in the sub-pixel is connected to the pixel driving circuit in the corresponding sub-pixel, but the position of the anode in the sub-pixel does not necessarily correspond to the row and column of the pixel driving circuit connected thereto. For example, the orthographic projection of the anode AN3 of the third sub-pixel on the substrate can overlap with the orthographic projection of the pixel driving circuit of the first sub-pixel and the pixel driving circuit of the second sub-pixel on the substrate.

[0341] The foregoing structure and the preparation process thereof are merely exemplary, and in the example embodiment, the corresponding structure can be changed, and the patterning process can be increased or reduced according to actual needs. The display substrate can be applied to other display devices having pixel driving circuits, such as quantum dot displays, which are not limited in the present disclosure.

[0342] The present disclosure also provides a display device, as shown in FIG. 29. The display device can include the display substrate of any of the foregoing embodiments. The display device can be any product or component having a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, or the like.

[0343] The display substrate and the display device provided by the embodiments of the present disclosure include a plurality of pixel units and at least one type of initial signal lines, the same type of initial signal lines includes at least two types of initial signal lines, the same pixel unit includes at least two types of sub-pixels, and different types of initial signal lines in the same type of initial signal lines are connected with different types of sub-pixels in the pixel unit, which can avoid the defects of screen flickering or uneven brightness to some extent, thereby improving the display effect.

[0344] The drawings of the embodiments of the present disclosure only relate to the structures involved in the embodiments of the present disclosure, and other structures can be referred to the general design.

[0345] In the case of no conflict, the features in the embodiments of the present disclosure can be combined with each other to obtain new embodiments.

[0346] Although the embodiments disclosed by the embodiments of the present disclosure are as above, the content is only the implementation adopted for the purpose of facilitating the understanding of the embodiments of the present disclosure, and is not intended to limit the embodiments of the present disclosure. Any person skilled in the art of the present disclosure can make any modification and change in the implementation form and details without departing from the spirit and scope of the embodiments disclosed by the present disclosure, but the patent protection scope of the present disclosure shall be subject to the scope defined by the appended claims.

Claims

1. A display substrate, comprising: A substrate and a plurality of pixel units and at least one type of initial signal line arranged on one side of the substrate; In at least part of the type of initial signal line, the same type of initial signal line includes at least two types of initial signal lines; in at least part of the pixel unit, the same pixel unit includes at least two types of sub-pixels; In the same type of initial signal line, each type of initial signal line is connected to at least one type of sub-pixel in the pixel unit, and different types of initial signal lines are connected to different types of sub-pixels in the pixel unit. 2.The display substrate of claim 1, wherein, In at least part of the pixel unit, the type of sub-pixel in the same pixel unit includes at least a first sub-pixel, a second sub-pixel and a third sub-pixel; In at least part of the type of initial signal line, the same type of initial signal line includes at least a first type of initial signal line and a second type of initial signal line; the first type of initial signal line is connected to at least one of the first sub-pixel and the second sub-pixel, and is arranged to provide initial signal to at least one of the first sub-pixel and the second sub-pixel; the second type of initial signal line is connected to the third sub-pixel, and is arranged to provide initial signal to the third sub-pixel. 3.The display substrate of claim 2, wherein, In at least part of the type of initial signal line, the same type of initial signal line further includes a third type of initial signal line, the first type of initial signal line is connected to one of the first sub-pixel and the second sub-pixel; the third type of initial signal line is connected to the other of the first sub-pixel and the second sub-pixel. 4.The display substrate of claim 2, wherein, At least part of the sub-pixel includes a pixel driving circuit, and at least part of the pixel driving circuit includes a plurality of transistors and at least one capacitor; In the direction perpendicular to the plane where the substrate is located, the capacitor includes: a first electrode plate located on one side of the substrate, a second electrode plate located on the side of the first electrode plate away from the substrate; the transistor includes: an active layer located on the side of the second electrode plate away from the substrate, a control electrode located on the side of the active layer away from the substrate, a first electrode and a second electrode located on the side of the control electrode away from the substrate. 5.The display substrate of claim 4, wherein, The type of the initial signal line includes at least a second initial signal line, at least part of the sub-pixel includes an anode, and in the direction perpendicular to the plane where the substrate is located, the anode is located on the side of the first electrode and the second electrode away from the substrate; the plurality of transistors includes a seventh transistor as a reset transistor, the first electrode of the seventh transistor is connected to the corresponding type of second initial signal line, and the second electrode of the seventh transistor is connected to the anode; The plurality of pixel units form a plurality of rows, and the second initial signal line is connected to the first electrode of the seventh transistor of at least part of the sub-pixel in one row of pixel units, and is arranged to provide the second initial signal to the corresponding anode under the control of at least part of the seventh transistor in the row of pixel units; The second initial signal line is arranged in the same layer as one of the first electrode plate and the second electrode plate, or is arranged in the same layer as the first electrode and the second electrode. The type of the second initial signal line includes at least a first type of second initial signal line and a second type of second initial signal line; 6.The display substrate of claim 5, wherein, ​ The first second initial signal line is connected with at least one of the first electrode of the seventh transistor of the first sub-pixel and the first electrode of the seventh transistor of the second sub-pixel in one row of pixel units, and is configured to provide an initial signal to the corresponding anode under the control of at least one of the seventh transistor of the first sub-pixel and the seventh transistor of the second sub-pixel in the row of pixel units; The second second initial signal line is connected with the first electrode of the seventh transistor of the third sub-pixel in one row of pixel units, and is configured to provide an initial signal to the anode of the third sub-pixel in the row of pixel units under the control of the seventh transistor of the third sub-pixel in the row of pixel units; The second second initial signal line is arranged in the same layer as one of the first electrode plate and the second electrode plate, or is arranged in the same layer as the first electrode and the second electrode. 7.The display substrate of claim 6, wherein, In the structure in which the second second initial signal line is arranged in the same layer as one of the first electrode plate and the second electrode plate, the first second initial signal line is arranged in the same layer as the first electrode and the second electrode. In the structure in which the second second initial signal line is arranged in the same layer as the first electrode and the second electrode, the first second initial signal line is arranged in the same layer as the first electrode and the second electrode, or is arranged in the same layer as one of the first electrode plate and the second electrode.

8. The display substrate according to claim 7 or the display substrate, wherein In the structure in which the first second initial signal line and the second second initial signal line are arranged in different layers, the orthographic projection of the first second initial signal line and the second second initial signal line on the substrate at least partially overlaps.

9. The display substrate according to any one of claims 6-8, further comprising at least one first second initial signal connection line and at least one second second initial signal connection line, the first second initial signal connection line and the second second initial signal connection line being located on the side of the first electrode and the second electrode away from the substrate and on the side of the anode close to the substrate in the direction perpendicular to the plane in which the substrate is located; The first second initial signal connection line is connected with at least one first second initial signal line, and the second second initial signal connection line is connected with at least one second second initial signal line. 10.The display substrate of claim 6, wherein, The types of the second initial signal line further include a third second initial signal line; The first second initial signal line is connected with the first electrode of the seventh transistor of the first sub-pixel in one row of pixel units, and is configured to provide an initial signal to the anode of the first sub-pixel in the row of pixel units under the control of the seventh transistor of the first sub-pixel in the row of pixel units; The third second initial signal line is connected with the first electrode of the seventh transistor of the second sub-pixel in one row of pixel units, and is configured to provide an initial signal to the anode of the third sub-pixel in the row of pixel units under the control of the seventh transistor of the second sub-pixel in the row of pixel units; In the structure in which the second initial signal line of the second type is arranged in the same layer as the first electrode and the second electrode, one of the first initial signal line of the first type and the third initial signal line of the second type is arranged in the same layer as one of the first electrode plate and the second electrode plate, and the other is arranged in the same layer as the first electrode and the second electrode or the other of the first electrode plate and the second electrode plate; In the structure in which the second initial signal line of the second type is arranged in the same layer as one of the first electrode plate and the second electrode plate, the first initial signal line of the first type and the third initial signal line of the second type are arranged in the same layer as the first electrode and the second electrode, or one of the first initial signal line of the first type and the third initial signal line of the second type is arranged in the same layer as the first electrode and the second electrode, and the other is arranged in the same layer as the other of the first electrode plate and the second electrode plate.

11. The display substrate according to claim 10, further comprising a third second initial signal connection line, the third second initial signal connection line is located on the side of the first electrode and the second electrode away from the substrate and on the side of the anode close to the substrate in the direction perpendicular to the plane in which the substrate is located; The third second initial signal connection line is connected with at least one third second initial signal line.

12. The display substrate according to any one of claims 4 to 8, 10, wherein, The types of the initial signal lines include at least a first initial signal line; The plurality of transistors include a driving transistor and a first transistor as a reset transistor, the first electrode of the first transistor is connected with the first initial signal line, and the second electrode of the first transistor is connected with the control electrode of the driving transistor; The plurality of pixel units form a plurality of rows, the first initial signal line is connected with the first electrode of at least part of the first transistors in one row of pixel units, and is arranged to provide the initial signal to the control electrode of the corresponding driving transistor under the control of at least part of the first transistors in the row of pixel units; The first initial signal line is arranged in the same layer as the first electrode and the second electrode or in the same layer as the control electrode. The types of the first initial signal lines include a first first initial signal line and a second first initial signal line; 13.The display substrate of claim 12, wherein, The first first initial signal line is connected with at least one of the first electrode of the first transistors of the first sub-pixels and the first electrode of the first transistors of the second sub-pixels in one row of pixel units, and is arranged to provide the initial signal to the control electrode of the corresponding driving transistor under the control of at least one of the first transistors of the first sub-pixels and the first transistors of the second sub-pixels in the row of pixel units; The second first initial signal line is connected with the first electrode of the first transistors of the third sub-pixels in one row of pixel units, and is arranged to provide the initial signal to the control electrode of the driving transistor of the third sub-pixels in the row of pixel units under the control of the first transistors of the third sub-pixels in the row of pixel units; ​ One of the first initial signal lines of the first kind and the second kind is arranged in the same layer as the control electrode, and the other is arranged in the same layer as the first electrode and the second electrode.

14. The display substrate according to claim 13, further comprising at least one first initial signal connection line of the first kind and at least one first initial signal connection line of the second kind, the first initial signal connection line of the first kind and the first initial signal connection line of the second kind being located on a side of the first electrode and the second electrode away from the substrate in a direction perpendicular to a plane in which the substrate is located. The first initial signal connection line of the first kind is connected with at least one first initial signal line of the first kind, and the first initial signal connection line of the second kind is connected with at least one first initial signal line of the second kind. 15.The display substrate of claim 13, wherein, The first initial signal lines further include a third kind of first initial signal line. The first initial signal line of the first kind is connected with a first electrode of a first transistor of the first sub-pixel in one of the rows of pixel units, and is arranged to provide an initial signal to a control electrode of a drive transistor of the first sub-pixel in the row of pixel units under control of the first transistor of the first sub-pixel in the row of pixel units; and the third kind of first initial signal line is connected with a first electrode of a first transistor of the second sub-pixel in one of the rows of pixel units, and is arranged to provide an initial signal to a control electrode of a drive transistor of the second sub-pixel in the row of pixel units under control of the first transistor of the second sub-pixel in the row of pixel units. The third kind of first initial signal line is arranged in the same layer as the control electrode, or is arranged in the same layer as the first electrode and the second electrode.

16. The display substrate according to claim 15, further comprising at least one third initial signal connection line of the first kind, the third initial signal connection line of the first kind being located on a side of the first electrode and the second electrode away from the substrate in a direction perpendicular to a plane in which the substrate is located. The third initial signal connection line of the first kind is connected with at least one third initial signal line of the first kind. The plurality of transistors further include a second transistor as a reset transistor, and the at least one capacitor includes a first capacitor and a second capacitor. 17.The display substrate of claim 12, wherein, A first electrode of the second transistor is connected with the first initial signal line, a second electrode of the second transistor is connected with a first plate of the first capacitor and a first plate of the second capacitor, a second plate of the first capacitor is connected with a second electrode of the first transistor and a control electrode of the drive transistor, and a second plate of the second capacitor is connected with a second electrode of the drive transistor. The first initial signal line is further connected with a first electrode of the second transistor of at least part of the sub-pixels in one of the rows of pixel units, and is arranged to provide an initial signal to the first plate of the first capacitor and the first plate of the second capacitor in the corresponding sub-pixel under control of the at least part of the second transistors in the row of pixel units. In the same pixel unit, the first electrode of the first transistor and the first electrode of the second transistor are connected with the first initial signal line of the same kind. 18.The display substrate of claim 17, wherein, ​ 19. The display substrate of claim 4, further comprising a plurality of first power connection lines and a plurality of first power lines, the plurality of transistors comprising a fifth transistor as a light emitting control transistor and a driving transistor; The first power connection line is arranged in the same layer as the first electrode and the second electrode, and the first power line is located on the side of the first power connection line away from the substrate in the direction perpendicular to the plane in which the substrate lies, the first power connection line is connected with the first electrode of the fifth transistor and is arranged to provide a first power signal to the fifth transistor. at least part of the first power lines and at least part of the first power connection lines are connected by a via to form a grid-like structure; the first electrode of the fifth transistor is connected with the first power connection line, and the second electrode of the fifth transistor is connected with the first electrode of the driving transistor.

20. The display substrate of claim 5, further comprising a plurality of second power connection lines and a plurality of second power lines; the second power connection lines are arranged in the same layer as the first electrode and the second electrode, and the second power lines are located on the side of the second power connection lines away from the substrate and on the side of the anode close to the substrate in the direction perpendicular to the plane where the substrate is located. the first sub-pixel is a light emitting unit emitting red light, the second sub-pixel is a light emitting unit emitting green light, and the third sub-pixel is a light emitting unit emitting blue light.

21. The display substrate of any one of claims 2-8, 10, 19-20, wherein, the plurality of transistors are oxide transistors.

22. The display substrate of any one of claims 2-8, 10, 19-20, wherein, 23. A display device comprising the display substrate of any one of claims 1 to 22. ​

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