MEMS micromirror structure and packaging method

The MEMS micromirror packaging method using SOI wafer structure and anodic bonding solves the problem of MEMS micromirrors being susceptible to environmental influences, achieves hermetic packaging and improved heat dissipation, enhances the stability and reliability of the device, and is suitable for mass production.

CN122166710APending Publication Date: 2026-06-09CHENGDU XGIMI TECH CO LTD
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
CHENGDU XGIMI TECH CO LTD
Filing Date
2024-12-06
Publication Date
2026-06-09

AI Technical Summary

Technical Problem

MEMS micromirror structures are susceptible to external environmental factors, especially moisture and dust, which can lead to performance degradation and shortened lifespan. Effective hermetic encapsulation is required to ensure reliability and stability.

Method used

Using an SOI wafer structure, the glass cover is connected to the chip substrate by anodic bonding. Combined with getter and thermal conductive layer, hermetic packaging is achieved. Electrodes are brought out from the back side using TSV process to isolate CMOS circuits and micromirror array, thus improving heat dissipation.

Benefits of technology

This technology enables hermetic packaging of MEMS micromirrors, protecting the devices from contamination, improving stability and lifespan, while reducing production costs and simplifying the mass production process.

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Abstract

This invention belongs to the field of optical device technology. It proposes a MEMS micromirror structure and packaging method. The structure mainly includes the design and fabrication of a chip substrate, a glass cover, a getter, and a thermally conductive layer. A CMOS circuit and a movable micromirror array structure are fabricated on an SOI wafer structure layer. The glass cover is connected to the SOI wafer support layer via anodic bonding to achieve hermetically sealed packaging of the micromirror array. An AlN thin film is deposited on the back side of the substrate, and TSV technology is used to lead wires from the back side of the SOI wafer. This scheme uses the buried oxide layer of the SOI wafer to isolate the substrate layer from the micromirror array and CMOS circuit, avoiding the impact of high voltage on device performance and ensuring compatibility with CMOS processes. The back-side AlN thin film deposition improves heat dissipation during the process and device operation. Furthermore, the wafer-level packaging process offers advantages such as simple process, low cost, and ease of mass production.
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