Pressure sensor and method of manufacturing the same

Abstract

This disclosure provides a pressure sensor and its fabrication method, belonging to the field of sensor technology. The pressure sensor of this disclosure includes a first dielectric substrate having a first cavity formed along its thickness direction; a functional layer located on the side of the first dielectric substrate opposite to the opening of the first cavity; a pressure sensing circuit disposed on the functional layer, the pressure sensing circuit including at least a pressure sensing element; a second dielectric substrate disposed on the side of the pressure sensing circuit opposite to the first dielectric substrate, and a second cavity formed on the surface of the second dielectric substrate near the pressure sensing circuit; the orthographic projections of the pressure sensing element and the second cavity onto the plane of the functional layer at least partially overlap; the orthographic projection of the opening of the second cavity onto the plane of the functional layer is a second projection area, and the orthographic projection of the bottom of the first cavity onto the plane of the functional layer is a first projection area; the first projection area and the second projection area overlap, and the area of ​​the overlapping area is smaller than the area of ​​the first projection area.

Description

Technical Field

[0001] This disclosure belongs to the field of sensing technology, specifically relating to a pressure sensor and its fabrication method. Background Technology

[0002] Thanks to the rapid development of semiconductor processing technology, the performance of MEMS (Micro-Electro-Mechanical System) devices has been greatly improved, and their application scenarios have expanded to fields such as biology, industry, and aerospace.

[0003] Based on their sensing principles, pressure sensors are classified into four types: resistive pressure sensors, capacitive pressure sensors, resonant pressure sensors, and piezoelectric pressure sensors. Among them, silicon piezoresistive pressure sensors have become the mainstream product in the MEMS pressure sensor market due to their advantages such as simple manufacturing process, low cost, high reliability, and compatibility with metal-oxide-semiconductor technology. Summary of the Invention

[0004] This invention aims to at least solve one of the technical problems existing in the prior art. In one aspect, it provides a pressure sensor comprising: a first dielectric substrate having a first cavity formed along its thickness direction; a functional layer located on the side of the first dielectric substrate opposite to the opening of the first cavity; a pressure sensing circuit disposed on the functional layer, the pressure sensing circuit including at least a pressure sensing element; a second dielectric substrate disposed on the side of the pressure sensing circuit opposite to the first dielectric substrate, and a second cavity formed on the surface of the second dielectric substrate near the pressure sensing circuit; the pressure sensing element and the second cavity at least partially overlap in orthographic projection onto the plane of the functional layer; the orthographic projection of the opening of the second cavity onto the plane of the functional layer is a second projection area, and the orthographic projection of the bottom of the first cavity onto the plane of the functional layer is a first projection area; the first projection area and the second projection area have an overlapping area, and the area of ​​the overlapping area is smaller than the area of ​​the first projection area.

[0005] In some alternative embodiments, the overlapping region has the same area as the second projected region.

[0006] In some optional embodiments, the center of the second projection area is located on a straight line that passes through the center of the first projection area and extends along the first direction, where the first direction is the width direction or the length direction of the first projection area.

[0007] In some alternative embodiments, the area of ​​the overlapping region is smaller than the area of ​​the second projected region.

[0008] In some alternative embodiments, the ratio of the area of ​​the second projection area to the area of ​​the first projection area is between 0.2 and 0.9.

[0009] In some alternative embodiments, the first cavity has a sidewall, a bottom wall, and a connecting surface connecting at least a portion of the edges of the sidewall and the bottom wall; the connecting surface is a curved surface.

[0010] In some optional embodiments, when the area of ​​the overlapping region is smaller than the area of ​​the second projection region, the orthographic projection of the connecting surface onto the plane where the functional layer is located overlaps at least partially with the overlapping region.

[0011] In some optional embodiments, the connecting surface is a convex curved surface that protrudes toward the opening of the first cavity.

[0012] In some alternative embodiments, the orthographic projection of the connecting surface onto the plane where the functional layer is located forms a closed loop, and the closed loop surrounds the periphery of the orthographic projection of the bottom wall onto the plane where the functional layer is located.

[0013] In some alternative embodiments, the orthographic projection of the pressure sensing element onto the plane containing the functional layer is at least partially located in the overlapping region.

[0014] In some optional embodiments, the second dielectric substrate has a first connection via extending through its thickness direction; the pressure sensing circuit further includes a conductive element electrically connected to the pressure sensing element; the pressure sensor further includes: a first connection electrode disposed in the first connection via, the first connection electrode being electrically connected to the conductive element of the pressure sensing circuit; a connection pad located on the side of the second dielectric substrate opposite to the first dielectric substrate and connected to the first connection electrode; a signal processing circuit located on the side of the connection pad opposite to the first dielectric substrate and electrically connected to the connection pad; the signal processing circuit is configured to convert the electrical signal output by the pressure sensing circuit into a corresponding pressure signal.

[0015] Based on the same inventive concept, in a second aspect, this disclosure provides a method for fabricating a pressure sensor, the pressure sensor being as described in any embodiment of the first aspect above. The fabrication method includes: providing an initial first dielectric substrate; sequentially forming a functional layer and a pressure sensing circuit on the initial first dielectric substrate; the pressure sensing circuit including a pressure sensing element; providing an initial second dielectric substrate; forming a second cavity on the initial second dielectric substrate to obtain a second dielectric substrate; disposing the second dielectric substrate on the side of the pressure sensing circuit away from the initial first dielectric substrate, wherein the opening of the second cavity faces the pressure sensing circuit, and the pressure sensing element and the second cavity at least partially overlap in the orthographic projection of the second cavity onto the plane where the functional layer is located; forming a first cavity in the thickness direction of the initial first dielectric substrate to form a first dielectric substrate; the functional layer and the pressure sensing circuit are located on the side of the first dielectric substrate away from the opening of the first cavity; wherein the orthographic projection of the opening of the second cavity onto the plane where the functional layer is located is a second projection area, the orthographic projection of the bottom of the first cavity onto the plane where the functional layer is located is a first projection area, the first projection area and the second projection area have an overlapping area, and the area of ​​the overlapping area is smaller than the area of ​​the first projection area. Attached Figure Description

[0016] Figure 1 This is an exemplary structural diagram of a pressure sensor in the related art.

[0017] Figure 2 This is a schematic diagram of the pressure-sensitive chip.

[0018] Figure 3 This is the equivalent circuit diagram of a Wheatstone bridge.

[0019] Figure 4 This is a planar schematic diagram of the sensing film layer.

[0020] Figure 5 This is a schematic diagram of another pressure sensor in the related technology.

[0021] Figure 6 for Figure 5 The diagram shows a partial structural schematic of the pressure sensor.

[0022] Figure 7 A diagram showing the stress concentration areas when external pressure is applied to the pressure-sensing part.

[0023] Figure 8 This is a schematic diagram of the structure of the pressure sensor provided in the embodiments of this disclosure.

[0024] Figure 9 for Figure 8 The pressure sensor shown is a top perspective view.

[0025] Figure 10 This is a physical image of the pressure sensor provided in the embodiments of this disclosure.

[0026] Figure 11 This is a cross-sectional view of the pressure sensor provided in Example 2.

[0027] Figure 12 for Figure 11 The pressure sensor shown is a top perspective view.

[0028] Figure 13 This is a cross-sectional view of the pressure sensor provided in Example 3.

[0029] Figure 14 for Figure 13 A magnified view of the central AA region.

[0030] Figure 15 for Figure 14 The image shows a top perspective view of the first cavity.

[0031] Figures 16-21 for Figure 8 The diagram shows the fabrication process of the pressure sensor. Detailed Implementation

[0032] To enable those skilled in the art to better understand the technical solution of the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0033] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an,” “a,” or “the,” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “including,” “comprising,” or “containing,” and similar terms mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. The terms “connected,” “linked,” or similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” and “right,” etc., are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0034] As used herein, “parallel” and “perpendicular” include the described situation and situations that are similar to the described situation, within an acceptable range of deviation, which is determined by those skilled in the art taking into account the measurement under discussion and the error associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, “parallel” includes absolute parallelism and approximate parallelism, where an acceptable range of deviation for approximate parallelism may be, for example, within 5°; “perpendicular” includes absolute perpendicularity and approximate perpendicularity, where an acceptable range of deviation for approximate perpendicularity may also be, for example, within 5°.

[0035] It should be understood that when a layer or element is referred to as being on another layer or substrate, it can mean that the layer or element is directly on the other layer or substrate, or that there is an intermediate layer between the layer or element and the other layer or substrate.

[0036] In this article, "electrical connection" includes the situation where constituent elements are connected together by a component that has a certain electrical function. There are no particular restrictions on the "component that has a certain electrical function" as long as it enables the transmission and reception of electrical signals between the connected constituent elements. Examples of "components that have a certain electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0037] This document describes exemplary embodiments with reference to sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and regions is enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Therefore, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. Thus, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0038] As a necessary technical groundwork, before introducing the technical solution disclosed herein, we will first elaborate on the structure, principle, and technical problems of silicon piezoresistive sensors.

[0039] The basic principle of a silicon piezoresistive sensor is to use an SOI (Silicon On Insulator) substrate to create a silicon cup. A film layer at the bottom of the cup serves as the pressure-sensitive element, the pressure-sensing membrane. Piezoresistive strips are formed on this membrane, creating a Wheatstone bridge. Initially, the pressure-sensing membrane does not deform, and the Wheatstone bridge is in equilibrium. Upon sensing pressure, the membrane deforms, and the Wheatstone bridge begins to output current. The signal processing circuit obtains the change in resistance based on the output current, and then calculates the pressure change based on the change in resistance and the piezoresistive coefficient.

[0040] Figure 1 This is a schematic diagram of an exemplary structure of a pressure sensor in related technologies. Figure 1 As shown, the pressure sensor includes a pressure-sensing chip 1, a housing 2, a lead portion 3, a silicone oil filling 4, and an isolation diaphragm 5. The isolation diaphragm 5 directly contacts the measured pressure P, and through the elastic deformation of the isolation diaphragm 5, the pressure P is transmitted to the silicone oil 4; the silicone oil 4 serves as the pressure transmission medium, transmitting the elastic deformation of the isolation diaphragm 5 to the pressure-sensing chip 1; the pressure-sensing chip 1, as the core component of the pressure sensor, is used to convert the externally transmitted pressure into an electrical signal; the lead portion 3 is used to transmit the electrical signal output by the pressure-sensing chip 1 to an external signal processing circuit. Figure 1 (not shown in the image); the signal processing circuit calculates the measured pressure P based on the electrical signal and the parameters of the pressure sensing chip 1 (such as the piezoresistive coefficient).

[0041] Figure 2 This is a schematic diagram of the pressure-sensitive chip. Figure 2 As shown, the pressure-sensitive chip 1 includes a first substrate 11, an insulating layer 12, and a sensing film layer 13 stacked sequentially along its thickness direction (Z direction). The first substrate 11 and the sensing film layer 13 are made of monocrystalline silicon, and the insulating layer 12 is made of silicon dioxide. Commonly, the first substrate 11 is referred to as substrate silicon, and the monocrystalline silicon used in the sensing film layer 13 is referred to as top silicon. This top silicon can deform under pressure, and a measurement circuit is formed in a specific area on it, which can convert the deformation into an electrical signal. Typically, the insulating layer 12 is referred to as a buried oxide layer, and the substrate formed by the substrate silicon, silicon dioxide, and top silicon is called an SOI substrate. (Continuing to refer to...) Figure 1 A first cavity CV1 is formed on the side of the first substrate 11 opposite to the sensing film layer 13. The cross-sectional shape of the first cavity CV1 can be rectangular, trapezoidal, or irregular. Figure 1 (Take a trapezoid as an example).

[0042] The measurement circuit of pressure-sensing chip 1 is based on the Wheatstone bridge principle. Figure 3 This is the equivalent circuit diagram of a Wheatstone bridge. Figure 3As shown, the Wheatstone bridge consists of four arms, and the resistance values ​​of the four arms are respectively... , , and The external excitation voltage supplied to the Wheatstone bridge, i.e., the input voltage, is defined as... The potential difference between the two voltage divider points, i.e., the output voltage, is expressed as... In a Wheatstone bridge, it is typically designed so that the resistance values ​​of all four bridge arms are equal. At this point, the output voltage is directly proportional to the input voltage, and has the following relationship:

[0043]

[0044] in, The change in resistance is zero when the bridge arm is not subjected to any external force, and the output voltage is zero. When the bridge arm is subjected to external pressure, the change in resistance is non-zero, and the output voltage can characterize the magnitude of the external pressure.

[0045] Figure 4 This is a planar schematic diagram of the sensing film layer. (Refer to...) Figure 4 The sensing film layer 13 includes a varistor PR, resistor leads RL, an input electrode Ein, and an output electrode Eout. The varistor PR comprises four resistors: a first resistor R1, a second resistor R2, a third resistor R3, and a fourth resistor R4, each corresponding to one of the four arms of a Wheatstone bridge. The resistor leads RL include a second lead RL2 connected between the first resistor R1 and the second resistor R2, a third lead RL3 connected between the second resistor R2 and the third resistor R3, a fourth lead RL4 connected between the third resistor R3 and the fourth resistor R4, and a first lead RL1 connected between the first resistor R1 and the fourth resistor R4. The input electrode Ein includes a first input electrode Ein+ and a second input electrode Ein-, which are connected to the first lead RL1 and the third lead RL3, respectively. The output electrode Eout includes a first output electrode Eout+ and a second output electrode Eout2, which are connected to the second lead RL2 and the fourth lead RL4, respectively.

[0046] Continue to refer to Figure 1Specifically, the lead portion 3 of the pressure sensor includes bonding leads 31 and extension leads 32. The housing 2 includes a base 21 and side plates 22. Typically, the housing 2 is made of stainless steel to provide mechanical support and to form a sealed cavity filled with silicone oil 4. A reference pressure hole HR is formed on the base 21, extending along its thickness direction and communicating with the external atmospheric pressure. This reference pressure hole HR is used to generate a reference pressure on the side of the pressure-sensing chip 1 facing away from the isolation diaphragm 5. The extension leads 32 extend to the outside through a through-hole extending through the thickness direction of the base 21. Simultaneously, an insulating glass 600 is provided around the extension leads 32 to electrically isolate the extension leads 32 from the base 21. The isolation diaphragm 5 is usually made of a flexible metal diaphragm, filled with silicone oil 4 to buffer vibration and impact to protect the pressure-sensing chip 1.

[0047] Figure 5 This is a schematic diagram of another pressure sensor in related technologies. (Example) Figure 5 As shown, the pressure sensor includes a pressure-sensing chip 1 and a glass cover 6, wherein the pressure-sensing chip 1 is as follows: Figure 2 and 4 As described above, it will not be repeated here. The glass cover plate 6 includes a glass body 61, a conductive via 62 extending along the thickness direction of the glass body 61 and electrically connected to the pressure-sensitive film layer 13 of the pressure-sensitive chip 1, a redistribution layer 63 located on the side of the glass body 61 opposite to the pressure-sensitive chip 1, and a first connection pad 64 on the redistribution layer 63 for connection with external signal processing circuitry. A second cavity CV2 is formed on the side of the glass body 61 near the pressure-sensitive film layer 13.

[0048] Continue to refer to Figure 5 The pressure-sensitive film layer 13 specifically includes a pressure-sensitive layer 133, a varistor PR formed on the pressure-sensitive layer 133, and a connection portion 132. The varistor PR is encapsulated in a second cavity CV2 opened in the glass body 61, and the connection portion 132 is electrically connected to the redistribution layer 63 through a conductive via 62.

[0049] The measurement process of this pressure sensor is as follows: the pressure P to be measured is transmitted to the pressure-sensing layer 133 of the pressure-sensing film layer 13 through the cavity CV1 opened on the first substrate 11 in the pressure-sensing chip 1, causing the pressure-sensing layer 133 to deform, and the deformation is converted into an electrical signal by the pressure-sensitive resistor PR, which is then transmitted to the external signal processing circuit through the glass cover plate 6.

[0050] Figure 6 for Figure 5 The diagram shows a partial structural schematic of the pressure sensor. Figure 6 As shown, the pressure-sensitive layer 133 can be divided into a pressure-sensitive area A1 and other areas located around the pressure-sensitive area, based on its function. (Refer to...) Figure 6The first cavity CV1 has a cross-sectional shape with a first side B1, and the second cavity CV2 has a cross-sectional shape with a second side B2. The pressure-sensing region A1 is defined by the smaller of the first side B1 and the second side B2. That is to say, Figure 6 The dimension of the pressure-sensing region A1 of the pressure sensor along the first direction (i.e., the X direction) is the same as the dimension of the bottom of the first cavity CV1 along the first direction. The pressure-sensing layer 133 specifically includes a pressure-sensing portion 133a located in the pressure-sensing region A1 and other portions located in other regions. During measurement, only the pressure-sensing portion 133a can sense pressure and produce corresponding deformation. Figure 7 A diagram showing the stress concentration region when external pressure is applied to the pressure-sensing component, as shown below. Figure 7 As shown, for a square-shaped pressure-sensitive part 133a, when stress is applied to the pressure-sensitive part 133a, the stress will be concentrated in the edge region B1. The stress borne by the middle region B2 of the pressure-sensitive part 133a is much less than that borne by the edge region B1. In other words, the pressure borne by the edge of the pressure-sensitive part 133a is much greater than that borne by the middle part.

[0051] The performance requirements for pressure sensor chips vary across different application scenarios. For example, consumer-grade pressure sensors (used in mobile phones, smartwatches, and home appliances) have a low measurement range (between a few kPa and several hundred kPa), mature manufacturing processes, high yields, and relatively low burst strength (they can withstand a maximum pressure approximately three times their measurement range). Therefore, consumer-grade pressure sensors can currently be mass-produced on a large scale. However, automotive-grade pressure sensors (used in aircraft and new energy vehicles) require thermal management systems that can withstand temperatures ranging from -55°C to 150°C. Furthermore, in various refrigerant and aviation fuel environments, pressure sensors are required to have a large measurement range and high burst resistance (able to withstand 5 to 8 times their measurement range). However, due to limitations in R&D and manufacturing costs, the industry currently lacks a solution for the large-scale mass production of high-performance pressure sensors.

[0052] In chip manufacturing, etching processes and morphology directly affect the chip's stress resistance. This is because the edges of etched patterns are often stress concentration points. When the edges of the etched patterns are sharp right angles, stress concentrates at the right angles and cannot be released or dispersed, easily leading to the chip exploding under high pressure. Moreover, regardless of the etching process, varying degrees of etching damage will occur at the etched edges, further degrading the pressure sensor's stress resistance. Furthermore, parameters such as dislocations, stacking faults, and oxygen content in the material itself also affect the fracture strength of the raw material, often resulting in the actual fracture strength being lower than the theoretical strength during processing.

[0053] And for Figure 5and Figure 6 The pressure sensor shown has a stress distribution concentrated around the outer edge of its pressure-sensing part 133a when subjected to external force. The bottom edge of the cavity CV1 on the first substrate 11 is the point of maximum etching damage. At this time, the stress concentration point of the pressure-sensing layer 133 and the maximum etching damage point of the first substrate 11 are completely coincident in the orthogonal projection on the plane where the glass body 61 is located. As a result, the explosion resistance of the pressure sensor is further deteriorated.

[0054] Currently, the main methods for improving the burst strength of pressure sensors include dry etching chamfering, dry scallop morphology control, and reducing etching damage. These methods involve etching locations with abrupt geometric changes during etching, transforming sharp points into smooth, rounded surfaces, thus dispersing and guiding stress concentrated at these locations, thereby improving the burst resistance of the pressure sensor. However, these methods require extremely high precision in the etching process, typically demanding a high degree of consistency in etching rate and depth across different locations, with variations controlled within 1% of the average. Therefore, while these methods can effectively improve the burst resistance of pressure sensors, their high manufacturing costs, low yield, and lack of feasibility for mass production hinder their effectiveness. Furthermore, while these methods effectively improve burst resistance, their effect on structural strength is limited.

[0055] In order to solve at least one of the above-mentioned technical problems, in one respect, this disclosure provides a pressure sensor.

[0056] Figure 8 This is a schematic diagram of the structure of the pressure sensor provided in the embodiments of this disclosure; Figure 9 for Figure 8 The pressure sensor shown is a top perspective view. Figure 8 and Figure 9 As shown, the pressure sensor provided in this embodiment includes a first dielectric substrate DS, a functional layer FL, a pressure sensing circuit SC, and a second dielectric substrate GL, which are stacked sequentially along their thickness direction. It should be noted that, unless otherwise specified, the thickness direction of the pressure sensor in this disclosure is the Z direction marked in the figures, the first direction is the X direction marked in the figures, and the second direction is the Y direction marked in the figures.

[0057] The first dielectric substrate DS has a first cavity CV1 formed along its thickness direction. A functional layer FL is located on the side of the first dielectric substrate opposite to the opening of the first cavity CV1. A pressure sensing circuit SC is disposed on the functional layer FL, and includes at least a pressure sensing element SC1. A second dielectric substrate GL is disposed on the side of the pressure sensing circuit SC opposite to the first dielectric substrate DS, and a second cavity CV2 is formed on the surface of the second dielectric substrate GL near the pressure sensing circuit SC. The orthographic projections of the pressure sensing element SC1 and the second cavity CV2 onto the plane of the functional layer at least partially overlap.

[0058] Reference Figure 9 In the pressure sensor provided in this disclosure, the orthographic projection of the opening of the second cavity CV2 onto the plane where the functional layer FL is located (the first plane P1) is the second projection region Q2, and the orthographic projection of the first cavity CV1 onto the plane where the functional layer FL is located is the first projection region Q1. The first projection region Q1 and the second projection region Q2 have an overlapping region OA, and the area of ​​the overlapping region OA is smaller than the area of ​​the first projection region Q1.

[0059] For example, the pressure sensor provided in this disclosure can be a silicon pressure sensor. Specifically, the first dielectric substrate DS in the pressure sensor can include a substrate silicon layer DS1 and a silicon oxide layer DS2, the functional layer FL includes a top silicon layer, and a first cavity CV1 is formed on the substrate silicon layer DS1 and can penetrate along the thickness direction of the substrate silicon layer DS1. The top silicon layer serves as a pressure-sensitive diaphragm, converting the pressure applied from the first cavity CV1 into its own deformation, so that the pressure-sensing element SC1 formed thereon converts the deformation into a corresponding electrical signal. The second dielectric substrate GL can be a glass substrate or a silicon substrate.

[0060] It is understandable that the pressure-sensing diaphragm in the functional layer FL, which senses the pressure transmitted by the first cavity CV1, should be the "suspended portion." The "suspended portion" is defined as follows: the "suspended portion" is located in the overlapping area OA of the opening of the second cavity CV2 and the bottom of the first cavity CV1 projected onto the first plane P1. As mentioned above, when the pressure-sensing diaphragm has a square planar shape, when external pressure is applied, the stress will concentrate at the edges of the diaphragm; in other words, the edges of the diaphragm are stress concentration areas, and the stress in these areas is much higher than in the middle area. The etched damage area of ​​the first cavity CV1 is its bottom edge. When the pressure sensor... Figure 6 As shown, since the area of ​​the overlapping region between the bottom of the first cavity CV1 and the second cavity CV2 is the same as the bottom area of ​​the first cavity CV1, it means that the projection of the pressure-sensing diaphragm and the bottom of the first cavity CV1 overlaps on the first plane P1. Therefore, the stress concentration area of ​​the pressure-sensing diaphragm coincides with the etching damage area of ​​the first cavity CV1, resulting in poor burst resistance of the pressure sensor.

[0061] And this disclosure Figure 8 In the pressure sensor shown, the opening of the second cavity CV2 is projected onto the first plane P1 as the second projection area Q2, and the bottom of the first cavity CV1 is projected onto the first plane P1 as the first projection area Q1. The area of ​​the overlapping region OA of the first projection area Q1 and the second projection area Q2 is smaller than the area of ​​the first projection area Q1. This means that the edge of the pressure-sensing diaphragm does not coincide with the bottom edge of the first cavity CV1. Therefore, the stress concentration area of ​​the pressure-sensing diaphragm does not coincide with the etching damage area of ​​the first cavity CV1, thereby significantly improving the burst resistance of the pressure sensor. The inventors of this disclosure discovered through testing that… Figure 8 The pressure sensor shown has a blast resistance performance compared to Figure 6 For the pressure sensor shown, the pressure can be increased from 7MPa to 35MPa, which is about 5 times.

[0062] In addition, the pressure sensor provided in this disclosure, compared to related technologies, only requires improvements to the relative dimensions of the first cavity CV1 and the second cavity CV2. Conventional, low-cost, and low-precision etching processes can be used to form the first cavity CV1 and the second cavity CV2. Therefore, compared to solutions that improve the etching morphology of the first cavity CV1 by employing high-precision dry etching processes to enhance the pressure sensor's burst resistance, the solution provided in this disclosure is low-cost and highly suitable for mass production and large-scale manufacturing.

[0063] The following description, in conjunction with the accompanying drawings, details several embodiments of the pressure sensor provided in this disclosure.

[0064] Example 1

[0065] Figure 8 and Figure 9 This refers to the pressure sensor provided in Example 1. Its structure has been described above and will not be repeated here. Only other features of the pressure sensor will be described.

[0066] In Embodiment 1, the overlapping region OA of the pressure sensor has the same area as the second projected region CV2, meaning the second projected region Q2 is the overlapping region OA, and the second projected region Q2 is located within the first projected region Q1. At this time, the two sides of the overlapping region OA that are opposite each other along the X direction and the two sides that are opposite each other along the Y direction are both located within the first projected region Q1. This effectively offsets the four stress concentration areas of the pressure-sensing diaphragm from the four etched damage areas of the first cavity CV1, ensuring no overlap between any stress concentration area and any etched damage area, thereby maximizing the pressure sensor's burst resistance.

[0067] Additionally, as a preferred example, such as Figure 9 As shown, the center O2 of the second projection area Q2 is located on a straight line that passes through the center O1 of the first projection area Q1 and extends along either the first direction (X direction / length direction) or the second direction (Y direction / width direction). In other words, the second projection area Q2 is located at the center of the first projection area Q1 along the first direction, or at the center of the first projection area Q1 along the second direction. At this time, the distance d1 between the left edge of the pressure-sensitive film and the left edge of the first projection area Q1 is the same as the distance d2 between the right edge of the pressure-sensitive film and the right edge of the first projection area Q1. The distance d3 between the upper edge of the pressure-sensitive film and the upper edge of the first projection area Q1 is the same as the distance d4 between the lower edge of the pressure-sensitive film and the lower edge of the first projection area Q1. This symmetrical arrangement can make the etching damage distribution and stress distribution relatively uniform, avoiding excessive single-point etching damage or excessive stress concentration that could lead to breakage or explosion.

[0068] As an optional example, the ratio of the area of ​​the second projection region Q2 to the area of ​​the first projection region Q1 is between 0.2 and 0.9.

[0069] Figure 10 This is a physical diagram of the pressure sensor provided in the embodiments of this disclosure. To verify the beneficial effects of the pressure sensor provided in the embodiments of this disclosure, the inventors tested the burst strength of pressure sensors with area ratios of the second projection area Q2 and the first projection area Q1 of 1:1, 1:2, 1:3, 1:4, and 1:5. The test results show that when the area ratio of the second projection area Q2 to the first projection area Q1 is 1:1, the burst strength of the pressure sensor is... When the area ratio of the two is reduced to 1:5, the burst strength of the pressure sensor can be increased to This sufficiently demonstrates that by designing the overlapping area OA to be smaller than the area of ​​the first projected area Q1, the stress concentration area of ​​the pressure-sensitive diaphragm and the etching damage area of ​​the first cavity CV1 are staggered, which can significantly improve the burst resistance of the pressure sensor. This solution does not require high-precision etching processes to control the etching morphology, thus having the advantages of low cost and mass production capability.

[0070] It should be noted that this disclosure Figure 9 The example shown is based solely on the fact that the second projection area Q2, the first projection area Q1, and the overlapping area OA are all square. This does not constitute a limitation on the technical solution disclosed herein. In some other examples, the second projection area Q2, the first projection area Q1, and the overlapping area OA can be rectangular, circular, trapezoidal, or irregular in shape.

[0071] Example 2

[0072] Figure 11A cross-sectional view of the pressure sensor provided in Example 2; Figure 12 for Figure 11 The pressure sensor shown is a top perspective view.

[0073] like Figure 11 and Figure 12 As shown, the pressure sensor provided in Embodiment 2 also includes a first dielectric substrate DS, a functional layer FL, a pressure sensing circuit SC, and a second dielectric substrate GL stacked sequentially along its thickness direction. The first dielectric substrate DS has a first cavity CV1 formed along its thickness direction. The functional layer FL is located on the side of the first dielectric substrate opposite to the opening of the first cavity CV1. The pressure sensing circuit SC is disposed on the functional layer FL and includes at least a pressure sensing element SC1. The second dielectric substrate GL is disposed on the side of the pressure sensing circuit SC opposite to the first dielectric substrate DS, and a second cavity CV2 is formed on the surface of the second dielectric substrate GL near the pressure sensing circuit SC. The orthographic projections of the pressure sensing element SC1 and the second cavity CV2 onto the plane of the functional layer at least partially overlap.

[0074] The orthographic projection of the opening of the second cavity CV2 onto the plane where the functional layer FL is located (the first plane P1) is the second projection region Q2. The orthographic projection of the first cavity CV1 onto the plane where the functional layer FL is located is the first projection region Q1. The first projection region Q1 and the second projection region Q2 have an overlapping region OA, and the area of ​​the overlapping region OA is smaller than the area of ​​the first projection region Q1.

[0075] like Figure 12 As shown, unlike Embodiment 1, the pressure sensor provided in Embodiment 2 has an overlapping region OA with an area smaller than the area of ​​the second projection region Q2. In other words, at least one side of the overlapping region OA can partially overlap with a side of the first projection region Q1.

[0076] Specifically, in some examples, the three sides of the overlapping region OA may overlap with the three sides of the first projection region Q1, such as... Figure 12 As shown in (a), the left, upper, and lower sides of the overlapping region OA overlap with the left, upper, and lower sides of the first projection region Q1, respectively. In this case, the stress concentration region at the right edge of the pressure-sensitive membrane is interspersed with the etch damage region at the right edge of the first cavity CV1. Compared with the related art where the four stress concentration regions of the pressure-sensitive membrane coincide with the four etch damage regions of the first cavity CV1, this example can improve the burst resistance to a certain extent.

[0077] Preferably, the two sides of the overlapping region OA can overlap with the two sides of the first projection region Q1, such as... Figure 12As shown in (b), the left and lower edges of the overlapping region OA overlap with the left and lower edges of the first projected region Q1, respectively. In this case, the stress concentration areas at the upper and right edges of the pressure-sensitive membrane are interspersed with the etching damage areas at the upper and right edges of the first cavity CV1, respectively. This example is different from... Figure 12 The example shown in (a) demonstrates a better blast resistance effect.

[0078] Preferably, only one side of the overlapping region OA overlaps with one side of the first projection region Q1, such as... Figure 12 As shown in (c), the left side of the overlapping region OA overlaps with the left side of the first projected region Q1. In this case, the three stress concentration areas—the upper, right, and lower edges of the pressure-sensitive membrane—are interspersed with the three etching damage areas—the upper, right, and lower edges of the first cavity CV1, respectively. This example is different from... Figure 12 The example shown in (b) demonstrates a better improvement in blast resistance.

[0079] Furthermore, the accompanying drawings of this disclosure use rectangular cross-sectional shapes for the first cavity CV1 and trapezoidal cross-sectional shapes for the second cavity CV2 as examples, which do not constitute a limitation on the technical solutions of this disclosure.

[0080] Example 3

[0081] Figure 13 A cross-sectional view of the pressure sensor provided in Example 3; Figure 14 for Figure 13 A magnified view of the central AA region.

[0082] like Figure 13 and Figure 14As shown, the pressure sensor provided in Embodiment 2 also includes a first dielectric substrate DS, a functional layer FL, a pressure sensing circuit SC, and a second dielectric substrate GL stacked sequentially along its thickness direction. The first dielectric substrate DS has a first cavity CV1 formed along its thickness direction. The functional layer FL is located on the side of the first dielectric substrate opposite to the opening of the first cavity CV1. The pressure sensing circuit SC is disposed on the functional layer FL and includes at least a pressure sensing element SC1. The second dielectric substrate GL is disposed on the side of the pressure sensing circuit SC opposite to the first dielectric substrate DS, and a second cavity CV2 is formed on the surface of the second dielectric substrate GL near the pressure sensing circuit SC. The orthographic projections of the pressure sensing element SC1 and the second cavity CV2 onto the plane of the functional layer at least partially overlap. The orthographic projection of the opening of the second cavity CV2 onto the plane of the functional layer FL (first plane P1) is a second projection region Q2, and the orthographic projection of the first cavity CV1 onto the plane of the functional layer FL is a first projection region Q1. The first projection region Q1 and the second projection region Q2 have an overlapping region OA, and the area of ​​the overlapping region OA is smaller than the area of ​​the first projection region Q1.

[0083] Reference Figure 14 Unlike Embodiments 1 and 2, the pressure sensor provided in Embodiment 3 has a first cavity CV1 that not only has a side wall SW and a bottom wall BW, but also includes a connecting surface CW connecting at least a portion of the edges of the side wall SW and the bottom wall BW. This connecting surface CW is curved. Specifically, the connecting surface CW is a convex curved surface that protrudes towards the opening of the first cavity CV1.

[0084] In this embodiment, when etching to form the first cavity CV1, the morphology of the connection between the side wall SW and the bottom wall BW of the first cavity CV1 is controlled so that the connection between the side wall SW and the bottom wall BW presents a smooth rounded corner instead of a sharp right angle, thereby appropriately reducing or eliminating the stress concentration point at the bottom of the first cavity CV1 to improve its stress resistance and thus improve the burst performance of the pressure sensor.

[0085] Figure 15 for Figure 14 The image shows a top perspective view of the first cavity. Figure 15 As shown in (a), as an optional example, the orthographic projection of the connecting surface CW onto the plane where the functional layer FL is located is a closed loop, and the closed loop surrounds the outer perimeter of the orthographic projection of the bottom wall BW onto the plane where the functional layer FL is located. Figure 15 In the example shown in (a), stress concentration caused by etching damage can be eliminated to the greatest extent, but high precision is required for the etching process, typically requiring etching uniformity <1%. Figure 15 As shown in (b), as another alternative example, when the area of ​​the overlapping region OA is smaller than the area of ​​the second projected region Q2 (refer to...) Figure 12(In the three examples provided), the orthographic projection of the connecting surface CW onto the plane where the functional layer FL is located overlaps at least partially with the overlapping area OA. Figure 15 In example (b), taking the overlap between the left edge of the overlapping region OA and the left edge of the first projected region Q1 as an example, the connecting surface CW only overlaps with the left edge of the overlapping region OA. That is, when the stress concentration area of ​​the pressure-sensitive membrane and the etching damage area of ​​the first cavity CV1 overlap, the etching morphology of this etching damage area can be controlled separately to avoid the formation of sharp stress concentration points. It is understandable that, due to... Figure 15 (b) only improves the etching morphology in certain locations, compared to Figure 15 In the example in (a), the etching process control precision does not need to be too high, and the etching consistency can be appropriately reduced, so the cost is relatively low.

[0086] In some alternative embodiments, the orthographic projection of the pressure sensing element onto the plane containing the functional layer is at least partially located in the overlapping region.

[0087] In some optional embodiments, the second dielectric substrate has a first connection via extending through its thickness direction; the pressure sensing circuit further includes a conductive element electrically connected to the pressure sensing element; the pressure sensor further includes: a first connection electrode disposed in the first connection via, the first connection electrode being electrically connected to the conductive element of the pressure sensing circuit; a connection pad located on the side of the second dielectric substrate opposite to the first dielectric substrate and connected to the first connection electrode; a signal processing circuit located on the side of the connection pad opposite to the first dielectric substrate and electrically connected to the connection pad; the signal processing circuit is configured to convert the electrical signal output by the pressure sensing circuit into a corresponding pressure signal.

[0088] like Figure 8 , Figure 11 and Figure 13 As shown, the orthographic projection of the pressure sensing element SC1 onto the plane containing the functional layer FL is at least partially located in the overlapping region OA. The pressure sensing circuit SC also includes a conductive element SC2 electrically connected to the pressure sensing element SC1.

[0089] Furthermore, the second dielectric substrate GL has a first connection via V1 extending through its thickness direction. The pressure sensor also includes a first connection electrode E1, a connection pad BP, a redistribution layer RDL, and signal processing circuitry. Figure 8 , Figure 11 and Figure 13(Not shown in the diagram). The first connection electrode E1 is disposed in the first connection via V1, and is electrically connected to the conductive element SC2 of the pressure sensing circuit SC and the redistribution layer RDL. The connection pad BP is located on the side of the second dielectric substrate GL opposite to the first dielectric substrate DS and is connected to the first connection electrode E1. The signal processing circuit is located on the side of the connection pad BP opposite to the first dielectric substrate DS and is electrically connected to the connection pad BP. The signal processing circuit is configured to convert the electrical signal output by the pressure sensing circuit SC into a corresponding pressure signal.

[0090] Based on the same inventive concept, in a second aspect, this disclosure provides a method for preparing a pressure sensor.

[0091] This article is based on Figure 8 Taking the pressure sensor shown as an example, the fabrication process of the pressure sensor provided in this disclosure will be introduced. Figures 16-21 for Figure 8 The schematic diagram shown is a fabrication process diagram of the pressure sensor. (Refer to...) Figures 16-21 The method for fabricating the pressure sensor provided in this disclosure includes:

[0092] Step S1: Provide the initial first dielectric substrate DS', such as Figure 16 As shown.

[0093] like Figure 16 As shown, the initial first dielectric substrate DS' includes an initial substrate silicon layer DS1' and an initial silicon oxide layer DS2'. Optionally, the process of forming the initial first dielectric substrate DS' is roughly as follows: a single-crystal silicon wafer of appropriate thickness is selected, and oxidation is performed on the surface of the single-crystal silicon wafer to form a silicon oxide layer DS2' located above the single-crystal silicon wafer, and the unoxidized part of the single-crystal silicon wafer is the initial substrate silicon layer DS1'.

[0094] Step S2: Sequentially form a functional layer FL and a pressure sensing circuit SC on the initial first dielectric substrate DS', as follows: Figure 17 As shown.

[0095] The functional layer FL is the top silicon layer in SOI. The functional layer FL is formed on the initial first dielectric substrate DS' by the following steps: a single-crystal silicon wafer of appropriate thickness is selected, and the single-crystal silicon wafer and the initial first dielectric substrate DS' provided in step S1 are bonded together using silicon-silicon bonding, connecting the single-crystal silicon wafer and the silicon oxide layer DS2'; then, the surface of the single-crystal silicon wafer is mechanically polished and chemically etched until the thickness of the single-crystal silicon wafer reaches the required thickness of the top silicon layer. For ease of description, the substrate consisting of the initial substrate silicon layer DS1', the silicon oxide layer DS2', and the top silicon layer will be referred to as the SOI substrate.

[0096] The pressure sensing circuit SC is formed on the side of the functional layer FL facing away from the initial first dielectric substrate DS', and includes a pressure sensing element SC1 and a conductive element SC2. The general steps for forming the pressure sensing circuit SC include: cleaning the SOI substrate and oxidizing the top silicon layer to form a protective layer; coating the protective layer with photoresist, and performing exposure, development, and etching to remove portions of the protective layer, exposing the areas where the pressure sensing element SC1 and the conductive element SC2 need to be deposited; then, implanting ions into the top silicon layer to dope it, forming the pressure sensing element SC1 and the conductive element SC2; subsequently, high-temperature annealing to repair lattice damage caused by ion implantation, and removing the remaining photoresist and protective layer to obtain the SOI substrate with the pressure sensing circuit SC formed.

[0097] Step S3: Provide an initial second dielectric substrate GL', such as Figure 18 As shown. For example, the initial second dielectric substrate GL' can be a glass substrate or a silicon substrate, and the glass substrate can be soda-lime glass, tin silicate glass, fused silica, etc.

[0098] Step S4: A second cavity CV2 is formed on the initial second dielectric substrate GL', and a first connecting via V1 is formed penetrating along the thickness direction of the initial second dielectric substrate GL' to obtain the second dielectric substrate GL, as shown. Figure 19 As shown.

[0099] Taking the initial second dielectric substrate GL' as a glass substrate as an example, the steps for forming the second cavity CV2 and the first connection via V1 are roughly as follows: the area of ​​the glass substrate where the second cavity CV2 and the first connection via V1 need to be formed is laser modified; then, the laser modified glass substrate is immersed in a specific chemical etching solution (such as HF solution) to etch the laser modified part, thereby forming the second cavity CV2 and the first connection via V1 to obtain the second dielectric substrate GL.

[0100] Step S5: The second dielectric substrate GL is disposed on the side of the pressure sensing circuit SC away from the initial first dielectric substrate DS1', wherein the opening of the second cavity CV2 faces the pressure sensing circuit SC, and the orthographic projections of the pressure sensing element SC1 and the second cavity CV2 on the plane of the functional layer FL at least partially overlap, as shown below. Figure 20 As shown.

[0101] Step S5 essentially involves bonding the second dielectric substrate GL and the SOI substrate. The bonding method can be anodic bonding, and the process generally includes: in the bonding equipment, precisely aligning the SOI substrate with the pressure sensing circuit SC obtained in step S2 with the second dielectric substrate GL, ensuring that the second cavity CV2 covers the pressure sensing element SC1, and the first connecting via V1 is aligned with the conductive element SC2; by heating and pressurizing the environment inside the bonding equipment, the second dielectric substrate GL and the SOI substrate are tightly bonded together, eliminating gaps; then, high voltage is applied to the SOI substrate and the glass substrate, with the former connected to the negative electrode and the latter connected to the positive electrode, causing ion migration between the SOI substrate and the glass substrate, achieving atomic-level bonding.

[0102] Step S6: A first cavity CV1 is formed in the thickness direction of the initial first dielectric substrate DS1' to form the first dielectric substrate DS, wherein the functional layer FL and the pressure sensing circuit SC are located on the side of the first dielectric substrate DS away from the opening of the first cavity CV1, as shown below. Figure 21 As shown. Figure 9 As shown, the orthographic projection of the opening of the second cavity CV2 onto the plane where the functional layer FL is located is the second projection region Q2, and the orthographic projection of the bottom of the first cavity CV1 onto the plane where the functional layer FL is located is the first projection region Q1. The first projection region Q1 and the second projection region Q2 have an overlapping region OA, and the area of ​​the overlapping region OA is smaller than the area of ​​the first projection region Q1.

[0103] Specifically, the steps for forming the first cavity CV1 in the thickness direction of the initial first dielectric substrate DS1' generally include: spin-coating photoresist on the side of the initial first dielectric substrate DS1' opposite to the first dielectric substrate GL, and performing exposure, development, and etching using a photomask to remove the portion of the photoresist corresponding to the first cavity CV1; subsequently, dry etching is performed using plasma (e.g., SF6 gas) to form the first cavity CV1, wherein the silicon oxide layer DS2 in the SOI substrate serves as an etching self-stopping layer. Of course, a wet etching process can also be used to form the second cavity CV2, and this disclosure does not limit this.

[0104] Step S7: Form a first connection electrode E1 penetrating the first connection via V1, a redistribution layer RDL located on the side of the second dielectric substrate GL opposite to the first dielectric substrate DS, and a connection pad BP electrically connected to the redistribution layer RDL, wherein the first connection electrode E1 is electrically connected to the conductive element SC2 and the redistribution layer RDL. Thus, a connection is formed. Figure 8 The pressure sensor shown.

[0105] The step of forming the first connecting electrode E1 in step S7 generally includes: depositing a seed layer on the sidewall of the first connecting via V1 using a PVD sputtering process. The seed layer can be a composite film layer such as Ti / Cu, Cr / Cu, or TiW / Cu; and electroplating the seed layer to form the first connecting electrode E1.

[0106] The steps in step S7 to form the redistribution layer RDL generally include: spin-coating photoresist onto the surface of the second dielectric substrate GL facing away from the first dielectric substrate DS; exposing, developing, and etching the photoresist to remove the portion of the photoresist corresponding to the first connection electrode E1, thereby exposing the end of the first connection electrode E1; depositing a seed layer on the photoresist using a PVD sputtering process; coating the seed layer with photoresist and exposing, developing, and etching it to expose the area in the seed layer where signal lines in the redistribution layer RDL need to be formed; electroplating the seed layer to form signal lines of a predetermined thickness; and removing the remaining photoresist and seed layer to form the redistribution layer RDL.

[0107] The formation of the connection pad BP in step S7 can be achieved using a screen printing process. That is, solder paste is applied to specific locations using screen printing, followed by a reflow soldering process to form the connection pad BP. It should be noted that in some examples, connection pads are already formed on the signal processing circuit; in this case, the step of forming the connection pad BP in step S7 can be omitted.

[0108] It is understood that the above embodiments are merely exemplary implementations used to illustrate the principles of the present invention, and the present invention is not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and essence of the present invention, and these modifications and improvements are also considered to be within the scope of protection of the present invention.

Claims

1. A pressure sensor, comprising: A first dielectric substrate having a first cavity formed along its thickness direction; The functional layer is located on the side of the first dielectric substrate opposite to the opening of the first cavity; A pressure sensing circuit is disposed on the functional layer, and the pressure sensing circuit includes at least a pressure sensing element; The second dielectric substrate is disposed on the side of the pressure sensing circuit away from the first dielectric substrate, and a second cavity is formed on the surface side of the second dielectric substrate near the pressure sensing circuit. The pressure sensing element and the second cavity at least partially overlap in the orthographic projection of the plane where the functional layer is located. The feature is that the orthographic projection of the opening of the second cavity onto the plane where the functional layer is located is a second projection area, the orthographic projection of the bottom of the first cavity onto the plane where the functional layer is located is a first projection area, the first projection area and the second projection area have an overlapping area, and the area of ​​the overlapping area is smaller than the area of ​​the first projection area.

2. The pressure sensor according to claim 1, characterized in that, The overlapping region has the same area as the second projection region.

3. The pressure sensor according to claim 2, characterized in that, The center of the second projection area is located on a straight line that passes through the center of the first projection area and extends along a first direction, where the first direction is either the width direction or the length direction of the first projection area.

4. The pressure sensor according to claim 2, characterized in that, The ratio of the area of ​​the second projection area to the area of ​​the first projection area is between 0.2 and 0.

9.

5. The pressure sensor according to claim 1, characterized in that, The area of ​​the overlapping region is smaller than the area of ​​the second projection region.

6. The pressure sensor according to any one of claims 1-5, characterized in that, The first cavity has a sidewall, a bottom wall, and a connecting surface connecting at least a portion of the edges of the sidewall and the bottom wall; the connecting surface is a curved surface.

7. The pressure sensor according to claim 6, characterized in that, When the area of ​​the overlapping region is smaller than the area of ​​the second projection region, the orthographic projection of the connecting surface onto the plane where the functional layer is located overlaps with the overlapping region in at least part.

8. The pressure sensor according to claim 6, characterized in that, The connecting surface is a convex curved surface that protrudes towards the opening of the first cavity.

9. The pressure sensor according to claim 6, characterized in that, The orthographic projection of the connecting surface onto the plane where the functional layer is located forms a closed loop, and the closed loop surrounds the periphery of the orthographic projection of the bottom wall onto the plane where the functional layer is located.

10. The pressure sensor according to claim 1, characterized in that, The orthographic projection of the pressure sensing element onto the plane of the functional layer is at least partially located in the overlapping region.

11. The pressure sensor according to claim 1, characterized in that, The second dielectric substrate has a first connection via extending through its thickness direction; the pressure sensing circuit further includes a conductive element electrically connected to the pressure sensing element; The pressure sensor also includes: A first connection electrode is disposed in the first connection through hole, and the first connection electrode is electrically connected to the conductive element of the pressure sensing circuit. The connecting pad is located on the side of the second dielectric substrate opposite to the first dielectric substrate and is connected to the first connecting electrode; A signal processing circuit is located on the side of the connection pad opposite to the first dielectric substrate and is electrically connected to the connection pad; the signal processing circuit is configured to convert the electrical signal output by the pressure sensing circuit into a corresponding pressure signal.

12. A method for manufacturing a pressure sensor, characterized in that, The pressure sensor is as described in any one of claims 1-11, and the preparation method comprises: Provide an initial first dielectric substrate; A functional layer and a pressure sensing circuit are sequentially formed on the initial first dielectric substrate; the pressure sensing circuit includes a pressure sensing element. Provide an initial second dielectric substrate; A second cavity is formed on the initial second dielectric substrate to obtain a second dielectric substrate; The second dielectric substrate is disposed on the side of the pressure sensing circuit away from the initial first dielectric substrate, wherein the opening of the second cavity faces the pressure sensing circuit, and the pressure sensing element and the orthographic projection of the second cavity on the plane where the functional layer is located at least partially overlap. A first cavity is formed in the thickness direction of the initial first dielectric substrate to form the first dielectric substrate; the functional layer and the pressure sensing circuit are located on the side of the first dielectric substrate opposite to the opening of the first cavity. Wherein, the orthographic projection of the opening of the second cavity onto the plane where the functional layer is located is the second projection area, and the orthographic projection of the bottom of the first cavity onto the plane where the functional layer is located is the first projection area. The first projection area and the second projection area have an overlapping area, and the area of ​​the overlapping area is smaller than the area of ​​the first projection area.

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