High resolution spad array for lidar using micro-assembly process

Abstract

An optical sensor includes an integrated circuit including an array of time-to-digital converters and a first array of interconnects connected to the array of time-to-digital converters. A plurality of single photon avalanche photodiode circuits includes a second interconnect. Each of the plurality of single photon avalanche photodiode circuits corresponds to a single pixel. The plurality of single photon avalanche photodiode circuits are individually arranged on the integrated circuit with the second interconnect of the plurality of single photon avalanche photodiode circuits connected to a corresponding one of the first interconnects of the integrated circuit.

Description

[0001] introduction The information provided in this section is for the purpose of presenting the overall context of this disclosure. The work of the currently named inventors—to the extent described in this section—and aspects of this description that may otherwise not qualify as prior art at the time of filing are neither expressly nor implicitly considered to be prior art to this disclosure.

[0002] This disclosure relates to optical sensors, and more specifically to an optical sensor comprising a single-photon avalanche photodiode (SPAD) array formed using micro-assembly techniques.

[0003] Vehicles may include driver assistance controllers that support fully autonomous or partially autonomous driving modes. These vehicles include one or more sensors, such as radio detection and ranging (radar) sensors and / or light detection and ranging (LiDAR) sensors, which output radio or light pulses and receive reflections from objects in the vehicle's path. In some examples, the receiver for the LiDAR sensor includes a single-photon avalanche photodiode (SPAD) array, which is monolithically formed on an integrated circuit. Summary of the Invention

[0004] A sensor includes an integrated circuit comprising a time-to-digital converter array and a first interconnect array connected to the time-to-digital converter array. A plurality of single-photon avalanche photodiode circuits include a second interconnect. Each of the plurality of single-photon avalanche photodiode circuits corresponds to a single pixel. The plurality of single-photon avalanche photodiode circuits are individually arranged on the integrated circuit, wherein the second interconnect of the plurality of single-photon avalanche photodiode circuits is connected to a corresponding first interconnect in the first interconnect of the integrated circuit.

[0005] Among other features, multiple single-photon avalanche photodiode circuits are spaced apart on the integrated circuit with a fixed pitch. Alternatively, multiple single-photon avalanche photodiode circuits may be spaced apart on the integrated circuit with a variable pitch. The first and second interconnects of the multiple single-photon avalanche photodiode circuits include hybrid copper interconnects. The integrated circuit further includes interconnect layers.

[0006] Among other features, an interconnect layer is arranged between the time-to-digital converter array and the first interconnect array. The sensor forms part of the receiver of the light detection and ranging sensor.

[0007] A sensor includes a backplane substrate. Multiple integrated circuits include a time-to-digital converter and a first interconnect providing a connection to the time-to-digital converter, each of the multiple integrated circuits corresponding to a single pixel. Multiple single-photon avalanche photodiode circuits include a second interconnect. Each of the multiple single-photon avalanche photodiode circuits corresponds to a single pixel. The multiple single-photon avalanche photodiode circuits are individually arranged on the multiple integrated circuits, wherein the second interconnect of the multiple single-photon avalanche photodiode circuits is connected to a corresponding first interconnect in the first interconnect of the integrated circuits. The multiple integrated circuits are arranged on a backplane substrate.

[0008] Among other features, multiple single-photon avalanche photodiode circuits and multiple integrated circuits are spaced apart on a backplane substrate with a fixed pitch. Alternatively, the multiple single-photon avalanche photodiode circuits and multiple integrated circuits are spaced apart on a backplane substrate with a variable pitch. The first interconnect and the second interconnect include hybrid copper interconnects. The multiple integrated circuits further include an interconnect layer. The interconnect layer is disposed between the time-to-digital converter and the first interconnect.

[0009] Among other features, the backplane substrate is either planar or non-planar. The sensor forms part of the receiver of a light detection and ranging sensor.

[0010] A vehicle includes a light detection and ranging sensor, the sensor including an integrated circuit including a time-to-digital converter array and a first interconnect array connected to the time-to-digital converter array. A plurality of single-photon avalanche photodiode circuits each include a second interconnect. Each of the plurality of single-photon avalanche photodiode circuits corresponds to a single pixel. The plurality of single-photon avalanche photodiode circuits are individually arranged on the integrated circuit, wherein the second interconnects of the plurality of single-photon avalanche photodiode circuits are connected to corresponding first interconnects in the first interconnects of the integrated circuit. A controller includes an autonomous driving module configured to support at least one of partial autonomous driving or fully autonomous driving in response to the light detection and ranging sensor.

[0011] Among other features, multiple single-photon avalanche photodiode circuits are spaced apart on the integrated circuit with a fixed pitch. Alternatively, multiple single-photon avalanche photodiode circuits can be spaced apart on the integrated circuit with a variable pitch. The first and second interconnects of the multiple single-photon avalanche photodiode circuits include hybrid copper interconnects.

[0012] Among other features, the integrated circuit further includes an interconnect layer. The interconnect layer is disposed between the time-to-digital converter array and the first interconnect array.

[0013] Further areas of applicability of this disclosure will become apparent from the detailed description, claims, and drawings. The detailed description and specific examples are intended for illustrative purposes only and are not intended to limit the scope of this disclosure. Attached Figure Description

[0014] This disclosure will be more fully understood from the detailed description and the accompanying drawings, in which: Figure 1 This is a functional block diagram of an example vehicle including light detection and ranging (LiDAR) sensors according to the present disclosure; Figure 2A This is a side cross-section of an example of a substrate comprising multiple single-photon avalanche photodiode (SPAD) pixels; Figure 2B This is a side cross-section of an example of a SPAD pixel after dicing according to this disclosure; Figure 2C This is a side cross-section of an example of a SPAD pixel according to this disclosure; Figure 3 This is a side cross-section of an example substrate according to the present disclosure, the substrate including an integrated circuit including a time-digital circuit array and an interconnect layer; Figure 4 Based on this disclosure Figure 3 A side cross-section of an example substrate having SPAD pixels attached at a fixed pitch using a micro-assembly process; Figure 5 Based on this disclosure Figure 3 A side cross-section of an example substrate having SPAD pixels attached at variable pitch using a micro-assembly process; Figure 6 This is a side cross-section of an example of a SPAD pixel according to the present disclosure, which is mounted on a corresponding time-digital (TDC) integrated circuit (IC) and arranged on a planar backplane substrate; Figure 7 This is a side cross-section of an example of a SPAD pixel according to the present disclosure, which is mounted on a corresponding TDC integrated circuit and arranged on a curved backplane substrate; and Figure 8A and Figure 8B This is an example of a method for manufacturing a SPAD array according to the present disclosure.

[0015] In the accompanying drawings, reference numerals may be used repeatedly to identify similar and / or identical elements. Detailed Implementation

[0016] While the following description pertains to light detection and imaging (LiDAR) sensors for vehicles, LiDAR sensors can be used in stationary applications or other types of applications.

[0017] Some lidar sensors include a monolithically formed substrate comprising a SPAD array. The SPAD array includes multiple single-photon avalanche photodiode (SPAD) macropixels (or pixels). Each pixel in the SPAD array may include a subpixel (or micropixel). In some examples, each pixel in the SPAD array is associated with a time-to-digital converter (TDC) (e.g., nominally one TDC per SPAD macropixel). The substrate includes an array of contacts (corresponding to each pixel in the SPAD array) that are bonded and optionally annealed to contacts of an integrated circuit (IC) including a time-to-digital converter for each SPAD pixel.

[0018] The physical size of the time-to-digital converter (TDC) for each pixel is larger than the SPAD pixel, which complicates the development of high-resolution SPAD arrays. The unique approach described in this paper uses micro-assembly techniques to decouple the size constraints of the SPAD array and the TDC IC. Therefore, it is possible to fabricate SPAD arrays with higher resolution (e.g., higher pixel count).

[0019] Individual SPAD pixels are fabricated and cut. The SPAD pixels are placed, joined, and optionally annealed to the TDC IC using micro-assembly techniques. This approach enables high-resolution arrays and allows for the generation of non-uniform SPAD arrays that compensate for optical distortion. This approach enables better optimization in LiDAR applications to maintain resolution across the field of view. Forming SPAD arrays using the micro-assembly process also provides a faster path to custom array configurations by avoiding the up to 1.5 years required for the design, layout, and fabrication of custom monolithic SPAD arrays.

[0020] Now for reference Figure 1 The vehicle 10 includes a controller 8, which includes an autonomous driving module 12 configured to support fully autonomous driving mode and / or partially autonomous driving mode based on data captured by a light detection and ranging (LiDAR) sensor 24, one or more radar sensors 22 and / or one or more cameras 23.

[0021] The lidar sensor 24 optionally includes one or more scanners 28, one or more lasers 30, and one or more single-photon avalanche photodiode (SPAD) arrays including SPAD pixels. In some embodiments, the lasers 30 include one or more vertical cavity surface-emitting lasers (VCSELs). In some embodiments, the VCSELs operate in flash mode without scanners. The lidar sensor 24 further includes a time-to-digital converter (TDC) IC 38 configured to determine the elapsed time from the generation of a light pulse to its return. The lidar sensor 24 optionally includes a point cloud generator / storage device 42 configured to store a point cloud based on the return. In some examples, data from the lidar sensor 24 and / or other controllers is used to generate an obstacle mesh, which includes object data in the path of the vehicle 10. In some examples, the lidar sensor 24 measures the reflectivity of a calibrated target for each return.

[0022] Vehicle 10 may further include a global positioning system / compass 20 configured to provide GPS coordinates and / or vehicle orientation. Vehicle 10 may further include a radio detection and ranging (radar) system 22 configured to generate radio signals and receive returned signals. Vehicle 10 includes control inputs 50, such as a steering wheel, accelerator pedal, brake pedal, turn signals, etc.

[0023] Now for reference Figures 2A to 2C The substrate 114 is fabricated to include multiple single-photon avalanche photodiode (SPAD) pixels 110-1, 110-2...110-N (collectively referred to as SPAD pixels 110). Although Figure 2A A single row is shown, but SPAD pixels 110 can be arranged in an array of M×N pixels, where M and N are integers greater than zero.

[0024] exist Figure 2B In this process, SPAD pixels 110-1, 110-2...110-N are separated into individual SPAD pixels 110-1, 110-2...110-N. Individual SPAD pixels 110-1, 110-2...110-N are separated and diced into individual SPAD pixels 110 using established wafer dicing techniques (mechanical, laser, etc.) and loaded into cartridges or other carriers compatible with the micro-assembly process.

[0025] exist Figure 2CIn the SPAD pixel 110, a lens 130 and a light guide portion 134 are included. The light guide portion 134 guides the LiDAR return between the sidewalls 136 to an avalanche region 144, which is disposed above an n+ region 146 located between p+ regions 138 and 140 of the diode. Contacts 148 disposed in an insulating layer 149 are made of a conductive material and are connected to the n+ regions 146 and / or p+ regions 138 and 140. One or more contact pads 150 connect the contacts 148 of one or more of the n+ regions 146 and / or p+ regions 138 and 140 to the TDC IC.

[0026] Now for reference Figure 3 The substrate 200 includes a TDC IC 222, which includes a TDC array and / or a point cloud generator / storage device. An interconnect layer 210 is disposed on one side of the TDC IC 222 and includes contact pads 214 for connection to contact pads 150 of the SPAD pixel 110. In some examples, contact pads 214 and 150 include hybrid copper interconnects. In some examples, one or both of contact pads 214 and 150 are made of copper and are surrounded by a dielectric layer (e.g., an oxide layer, such as silicon oxide (SiO2)) prior to microassembly and annealing.

[0027] In some examples, multiple individual SPAD pixels are connected to a single digital logic IC using fixed or variable spacing. In other examples, multiple individual SPAD pixels are connected to an individual TDC IC and then mounted on a backplane substrate using fixed or variable spacing. The individual digital logic ICs can be manufactured in a similar manner to the individual SPAD pixels (manufacturing an array, followed by cutting the individual TDC ICs).

[0028] Now for reference Figure 4 , showed Figure 3 The substrate 200 has SPAD pixels 110 arranged at a fixed pitch (d1) using a micro-assembly process. After micro-assembly, an annealing step can be performed to strengthen the bonding between the contact pads 214 and 150.

[0029] Now for reference Figure 5 , showed Figure 3 The substrate 200 has SPAD pixels 110, which are assembled using a micro-assembly process with a variable pitch (e.g., d1). <d2<d3......d1> (d2>d3...or other patterns) arrangement. In this example, the spacing increases from the center to the edge of the SPAD array. However, other variable spacing patterns can be used. After micro-assembly, an annealing step can be performed to strengthen the bonding of the contact pads 214 and 150.

[0030] Now for reference Figure 6 and Figure 7 SPAD pixels and TDC ICs can be fabricated on a substrate and then diced as described above to form individual SPAD pixels and TDC circuits 310-1, 310-2, ..., and 310-N. The SPAD pixels and TDC ICs 310-1, 310-2, ..., and 310-N each include interconnect layers 314-1, 314-2, ..., and 314-N and TDC layers 318-1, 318-2, ..., and 318-N. The SPAD pixels and TDC ICs 310-1, 310-2, ..., and 310-N are arranged on a planar backplane substrate 322. Figure 7 In this design, SPAD pixels and TDC ICs 310-1, 310-2, ... and 310-N are arranged on a curved backplane substrate to compensate for optical distortion.

[0031] Now for reference Figure 8A and Figure 8B An example of a method for manufacturing SPAD arrays is shown. Figure 8A At 410, multiple SPAD pixels are fabricated on a substrate. At 414, the SPAD pixels are cut into individual pixels. At 418, the SPAD pixels are placed on a substrate including an interconnect layer and multiple digital logic circuits (e.g., TDC ICs and / or point cloud storage devices). At 422, annealing is optionally performed to enhance bonding.

[0032] exist Figure 8B At point 510, multiple SPAD pixels, interconnects, and TDC ICs are fabricated on the substrate. At point 514, the SPAD pixels, interconnects, and TDC ICs are diced into individual SPAD pixels, interconnects, and TDC ICs. At point 518, the SPAD pixels, interconnects, and ICs are placed on the backplane substrate. At point 522, annealing is optionally performed to enhance bonding.

[0033] Although the above description refers to optical sensors used in the receiver of lidar sensors, optical sensors can also be used for near-infrared imaging.

[0034] The foregoing description is merely illustrative in nature and is by no means intended to limit this disclosure, its application, or its use. The broad teachings of this disclosure can be implemented in various forms. Therefore, while this disclosure includes specific examples, its true scope should not be so limited, as other modifications will become apparent upon examination of the drawings, specification, and the following claims. It should be understood that one or more steps within the method may be performed in a different order (or simultaneously) without altering the principles of this disclosure. Furthermore, although each embodiment is described above as having certain features, any one or more of those features described with respect to any embodiment of this disclosure may be implemented in and / or combined with features of any other embodiment, even if such combination is not explicitly described. In other words, the described embodiments are not mutually exclusive, and permutations of one or more embodiments with each other remain within the scope of this disclosure.

[0035] Spatial and functional relationships between components (e.g., between modules, circuit elements, semiconductor layers, etc.) are described using various terms including “connection,” “joint,” “coupled,” “proximity,” “closest,” “above,” “under,” and “set.” Unless explicitly described as “direct,” when describing the relationship between the first and second components in the above disclosure, the relationship can be a direct relationship in which no other intervening components exist between the first and second components, or an indirect relationship in which one or more intervening components (either spatially or functionally) exist between the first and second components. As used herein, the phrase “at least one of A, B, and C” should be interpreted as meaning the logic of using a non-exclusive logical “OR” (A or B or C) and should not be interpreted as meaning “at least one of A, at least one of B, and at least one of C.”

[0036] In the diagrams, the direction of the arrows, as indicated by the arrowhead, typically indicates the flow of information (such as data or instructions) of interest for that diagram. For example, when components A and B exchange various information, but the information transmitted from component A to component B is relevant to this diagram, the arrow may point from component A to component B. This unidirectional arrow does not imply that no other information is transmitted from component B to component A. Furthermore, for information sent from component A to component B, component B may send a request for or confirmation of receipt of that information to component A.

[0037] In this application, including the following definitions, the term "module" or "controller" may be replaced by the term "circuit". The term "module" may refer to, be part of, or include the following: application-specific integrated circuit (ASIC); digital, analog, or mixed-signal analog / digital discrete circuit; digital, analog, or mixed-signal analog / digital integrated circuit; combinational logic circuit; field-programmable gate array (FPGA); processor circuitry (shared, dedicated, or grouped) that executes code; memory circuitry (shared, dedicated, or grouped) that stores code executed by the processor circuitry; other suitable hardware components that provide the described functionality; or some or all of the foregoing, such as in a system-on-a-chip.

[0038] A module may include one or more interface circuits. In some examples, the interface circuit may include a wired or wireless interface connected to a local area network (LAN), the Internet, a wide area network (WAN), or a combination thereof. The functionality of any given module of this disclosure may be distributed among multiple modules connected via the interface circuit. For example, multiple modules may allow for load balancing. In a further example, a server (also referred to as a remote or cloud) module may perform some functions on behalf of a client module.

[0039] The term "code," as used above, can include software, firmware, and / or microcode, and can refer to programs, routines, functions, classes, data structures, and / or objects. The term "shared processor circuitry" covers a single processor circuitry that executes some or all of the code from multiple modules. The term "group processor circuitry" covers processor circuitry that executes some or all of the code from one or more modules in conjunction with additional processor circuitry. References to multiple processor circuitry cover multiple processor circuitry on a discrete die, multiple processor circuitry on a single die, multiple cores of a single processor circuitry, multiple threads of a single processor circuitry, or a combination of the foregoing. The term "shared memory circuitry" covers a single memory circuitry that stores some or all of the code from multiple modules. The term "group memory circuitry" includes memory circuitry that stores some or all of the code from one or more modules in conjunction with additional memory.

[0040] The term "memory circuit" is a subset of the term "computer-readable medium." As used herein, the term "computer-readable medium" does not cover non-transitory electrical or electromagnetic signals propagated through a medium (such as on a carrier wave); therefore, the term "computer-readable medium" can be considered tangible and non-transitory. Non-limiting examples of non-transitory tangible computer-readable media are non-volatile memory circuits (such as flash memory circuits, erasable programmable read-only memory circuits, or mask-mode read-only memory circuits), volatile memory circuits (such as static random access memory circuits or dynamic random access memory circuits), magnetic storage media (such as analog or digital magnetic tape or hard disk drives), and optical storage media (such as CDs, DVDs, or Blu-ray discs).

[0041] The apparatus and methods described in this application can be implemented, in part or in whole, by a special-purpose computer created by configuring a general-purpose computer to perform one or more specific functions embodied in a computer program. The function blocks, flowchart components, and other elements described above serve as software specifications that can be translated into computer programs through the routine work of a skilled technician or programmer.

[0042] A computer program includes processor-executable instructions stored on at least one non-transitory tangible computer-readable medium. A computer program may also include or depend on stored data. A computer program may encompass a basic input / output system (BIOS) that interacts with the hardware of a special-purpose computer, device drivers that interact with specific devices of the special-purpose computer, one or more operating systems, user applications, background services, background applications, etc.

[0043] Computer programs may include: (i) descriptive text to be parsed, such as HTML (Hypertext Markup Language), XML (Extensible Markup Language), or JSON (JavaScript Object Notation); (ii) assembly code; (iii) object code generated by a compiler from source code; (iv) source code for execution by an interpreter; and (v) source code for compilation and execution by a just-in-time (JIT) compiler, etc. As an example only, source code may be written using syntax from languages ​​including: C, C++, C#, Objective-C, Swift, Haskell, Go, SQL, R, Lisp, etc. Fortran, Perl, Pascal, Curl, OCaml, HTML5 (Hypertext Markup Language 5), Ada, ASP (Active Server Pages), PHP (PHP: Hypertext Preprocessor), Scala, Eiffel, Smalltalk, Erlang, Ruby, Visual Lua, MATLAB, SIMULINK and

Claims

1. A sensor, comprising: Integrated circuits, including: Time-to-digital converter arrays; and A first interconnect array is connected to a time-to-digital converter array; and Multiple single-photon avalanche photodiode circuits, each circuit including a second interconnect. Each of the plurality of single-photon avalanche photodiode circuits corresponds to a single pixel. The plurality of single-photon avalanche photodiode circuits are individually arranged on an integrated circuit, and the second interconnection of the plurality of single-photon avalanche photodiode circuits is connected to a corresponding first interconnection in the first interconnection of the integrated circuit.

2. The sensor according to claim 1, wherein the plurality of single-photon avalanche photodiode circuits are spaced apart at a fixed interval on an integrated circuit.

3. The sensor according to claim 1, wherein the plurality of single-photon avalanche photodiode circuits are spaced apart on an integrated circuit with a variable pitch.

4. The sensor of claim 1, wherein the first interconnect and the second interconnect of the plurality of single-photon avalanche photodiode circuits comprise hybrid copper interconnects.

5. The sensor of claim 1, wherein the integrated circuit further includes an interconnect layer.

6. The sensor of claim 5, wherein the interconnect layer is disposed between the time-to-digital converter array and the first interconnect array.

7. The sensor of claim 1, wherein the sensor forms part of the receiver of the light detection and ranging sensor.

8. A light sensor, comprising: backplane substrate; Multiple integrated circuits, each integrated circuit including: Time-to-digital converter; and A first interconnect provides a connection to a time-to-digital converter, each of the plurality of integrated circuits corresponding to a single pixel; and Multiple single-photon avalanche photodiode circuits, each circuit including a second interconnect, each of the multiple single-photon avalanche photodiode circuits corresponding to a single pixel; The plurality of single-photon avalanche photodiode circuits are individually arranged on the plurality of integrated circuits, the second interconnection of the plurality of single-photon avalanche photodiode circuits is connected to a corresponding first interconnection in the first interconnection of the integrated circuit, and the plurality of integrated circuits are arranged on a backplane substrate.

9. The sensor according to claim 8, wherein the plurality of single-photon avalanche photodiode circuits and the plurality of integrated circuits are spaced apart at a fixed interval on a backplane substrate.

10. The sensor of claim 8, wherein the plurality of single-photon avalanche photodiode circuits and the plurality of integrated circuits are spaced apart at a variable pitch on a backplane substrate.

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