Low dropout linear regulator and output regulation circuit and output regulation method thereof

Abstract

The application discloses a low-dropout linear voltage regulator and an output adjusting circuit and method thereof. The low-dropout linear voltage regulator comprises a power transistor and an error amplifier. The output adjusting circuit comprises a transient detection circuit, a load current sampling circuit and a drive current adjusting circuit. The transient detection circuit generates a transient current related to the change amplitude and speed of the input voltage of the power supply end when the input voltage of the power supply end changes rapidly. The load current sampling circuit samples the DC load current of the power transistor and outputs a current characteristic signal which changes with the DC load current. The drive current adjusting circuit generates a drive current according to the transient current and the current characteristic signal to adjust the gate voltage of the power transistor and suppress the change of the output voltage. The drive current is related to the transient change of the input voltage and the size of the DC load current in the application, which can accelerate the transient response speed of the circuit, adaptively adjust the drive current, effectively suppress the deviation of the output voltage and expand the application range.

Description

Technical Field

[0001] This application relates to the field of linear regulator technology, specifically to a low-dropout linear regulator and its output regulation circuit and output regulation method. Background Technology

[0002] A low dropout regulator (LDO) converts an unstable input voltage into an adjustable DC output voltage for use as a power supply for other systems. Due to its simple structure, low quiescent power consumption, and low output voltage ripple, linear regulators are commonly used for on-chip power management in mobile consumer electronics chips.

[0003] Figure 1 A schematic diagram of the basic circuit structure of a prior art low-dropout linear regulator is shown. (Example) Figure 1 As shown, the low-dropout linear regulator 10 includes a power transistor M1 and an error amplifier EA. The power transistor M1 provides an output voltage Vout to the downstream load (e.g., a series resistor Rs and a resistor RL) based on the input voltage VIN provided by the power supply. The error amplifier EA compares the sampled signal Vcs of the output voltage Vout with a reference voltage Vref and generates an adjustment signal Vctrl based on the error signal between the two to adjust the gate-source voltage drop of the power transistor M1, thereby adjusting the output current Iout of the power transistor M1 to output a stable output voltage. Due to its limited bandwidth, when the input voltage VIN undergoes a rapid rise or fall transient change, the gate voltage of the power transistor M1 cannot immediately follow, resulting in overshoot or undershoot of the output voltage Vout. Existing technology adds an auxiliary circuit 20, which immediately pulls up or down the gate voltage when the auxiliary circuit 20 detects a rise or fall in the input voltage VIN, thus quickly stabilizing the output voltage. The auxiliary circuit 20 typically uses a resistor-capacitor structure to detect the rise or fall of the input voltage VIN, and adjusts the gate voltage of the power transistor M1 by using a fixed pull-down current with an NMOS transistor or a fixed pull-up current with a PMOS transistor. However, this auxiliary circuit 20 still suffers from slow transient response, and adjusting the gate voltage with a fixed pull-up or pull-down current has significant limitations, being effective only when the DC load current is within a certain range. When the DC load current is too large, it may not effectively suppress overshoot and undershoot, while when the DC load current is too small, over-adjustment may actually induce undershoot or overshoot, resulting in poor adjustment performance. Summary of the Invention

[0004] This application provides a low-dropout linear regulator, its output regulation circuit, and its output regulation method to solve the problems in the prior art.

[0005] According to one aspect of the present invention, an output regulation circuit for a low-dropout linear regulator is provided. The low-dropout linear regulator includes a power transistor located between a power supply terminal and an output terminal and an error amplifier connected to a control terminal of the power transistor. The output regulation circuit includes: a transient detection circuit that generates a transient current related to the amplitude and rate of change of the input voltage when the input voltage at the power supply terminal changes rapidly; a load current sampling circuit that samples the DC load current of the power transistor and outputs a current characterization signal that varies with the DC load current; and a drive current regulation circuit that generates a drive current based on the transient current and the current characterization signal to regulate the gate voltage of the power transistor and suppress changes in the output voltage.

[0006] Optionally, when the input voltage changes rapidly, the transient current gradually decreases from the first amplitude current until the output voltage stabilizes. The greater the amplitude of the input voltage change, the greater the first amplitude current; the faster the input voltage changes, the greater the first amplitude current.

[0007] Optionally, the driving current increases with the increase of the DC load current and decreases with the decrease of the DC load current; and the driving current increases with the increase of the transient current and decreases with the decrease of the transient current.

[0008] Optionally, when the power transistor is a PMOS transistor, the drive current regulation circuit generates a pull-down current when the input voltage drops rapidly, and a pull-up current when the input voltage rises rapidly; when the power transistor is an NMOS transistor, the drive current regulation circuit generates a pull-up current when the input voltage drops rapidly, and a pull-down current when the input voltage rises rapidly.

[0009] Optionally, the drive current regulation circuit includes: a reference transistor, the first end of which is connected to a control terminal to receive the transient current, the second end of which is connected to a power supply terminal, and the reference transistor generating a gate reference voltage based on the transient current; a mirror transistor, the control terminal of which is connected to the control terminal of the reference transistor to conduct according to the gate reference voltage, the first end of which provides a mirror current, which is then converted into the drive current, the mirror transistor and the reference transistor being transistors of the same type; and an adjustment transistor, the control terminal of which receives the current characterization signal, the first end of which is connected to the second end of the mirror transistor, the second end of which is connected to the power supply terminal, and the equivalent resistance of the adjustment transistor changing negatively with the DC load current.

[0010] Optionally, the transient detection circuit includes: a first detection circuit connected to a first type of reference transistor, which generates a first transient current when the input voltage drops rapidly, making the mirror current a pull-down current; and a second detection circuit connected to a second type of reference transistor, which generates a second transient current when the input voltage rises rapidly, making the mirror current a pull-up current.

[0011] Optionally, the first detection circuit includes: a first resistor and a first capacitor connected in series between a power supply terminal and a ground terminal, providing a node voltage from their common node; a first P-type transistor and a first current source connected in series between the power supply terminal and the ground terminal; and a second P-type transistor and a second current source connected in series between the common node of the first resistor and the first capacitor and the ground terminal, wherein the intermediate node of the second P-type transistor and the second current source provides the first transient current, wherein the first P-type transistor, the second P-type transistor, the first current source and the second current source form a current mirror structure.

[0012] Optionally, the second detection circuit includes: a second capacitor and a second resistor connected in series between the power supply terminal and the ground terminal; and a first N-type transistor whose control terminal is connected to the common node of the second capacitor and the second resistor, the first end of the first N-type transistor being grounded and the second end being connected to the control terminal of the reference transistor and the mirror transistor, the first N-type transistor providing the second transient current.

[0013] Optionally, when the power transistor is a PMOS transistor, when the input voltage drops rapidly, the drive current regulation circuit uses the N-type reference transistor and the mirror transistor to directly use the mirror current as the drive current; when the input voltage rises rapidly, the drive current regulation circuit uses the P-type reference transistor and the mirror transistor to directly use the mirror current as the drive current.

[0014] Optionally, when the power transistor is an NMOS transistor, the drive current regulation circuit further includes a current mirror to convert the mirrored current into the reverse drive current. When the input voltage drops rapidly, the drive current regulation circuit uses the N-type reference transistor and the mirror transistor, as well as the P-type current mirror; when the input voltage drops rapidly, the drive current regulation circuit uses the P-type reference transistor and the mirror transistor, as well as the N-type current mirror.

[0015] Optionally, when the P-type regulating transistor is connected, the load current sampling circuit includes a first filter network, the first filter network including a third capacitor and a third resistor connected in series between the power supply terminal and the control terminal of the power transistor; when the N-type regulating transistor is connected, the load current sampling circuit includes a load current mirror branch and a second filter network, the second filter network including a fourth resistor and a fourth capacitor connected between the load current mirror branch and the ground terminal.

[0016] Optionally, when the power transistor is a PMOS transistor, the drive current regulation circuit uses an N-type regulating transistor when the input voltage drops rapidly, and uses a P-type regulating transistor when the input voltage rises rapidly; when the power transistor is an NMOS transistor, the drive current regulation circuit uses an N-type regulating transistor for both the rapid drop and rapid rise of the input voltage.

[0017] Optionally, when the power transistor is a PMOS transistor, the load current mirror branch includes: a third P-type transistor, the first end of which is connected to the power supply terminal and the control terminal of which is connected to the control terminal of the power transistor; and a second N-type transistor, the first end of which is connected to the second end of the third P-type transistor, the second end of which is grounded, and the control terminal of which is connected to the second filter network.

[0018] Optionally, when the power transistor is an NMOS transistor, the load current mirror branch includes: a third N-type transistor, a fourth P-type transistor, and a fourth N-type transistor connected in series between the power supply terminal and the ground terminal; and a fifth P-type transistor and a fifth N-type transistor connected in series between the output terminal and the ground terminal of the power transistor, in parallel with the load resistor, wherein the fourth N-type transistor and the fifth N-type transistor constitute a current mirror structure, and the fourth P-type transistor and the fifth P-type transistor also constitute a current mirror structure.

[0019] Optionally, the output regulation circuit further includes: an initial drive unit, which keeps the mirror transistor in a conducting state when no load is applied, so as to provide a minimum drive current for the power transistor, the initial drive unit including a resistor connected in parallel with the regulation transistor.

[0020] According to another aspect of the present invention, an output regulation method for a low-dropout linear regulator is provided. The low-dropout linear regulator includes a power transistor located between a power supply terminal and an output terminal, and an error amplifier connected to a control terminal of the power transistor. The output regulation method includes: generating a transient current related to the magnitude and rate of change of the input voltage when the input voltage at the power supply terminal changes rapidly; sampling the DC load current of the power transistor and outputting a current characterization signal that varies with the DC load current; and generating a drive current based on the transient current and the current characterization signal to regulate the gate voltage of the power transistor and suppress changes in the output voltage.

[0021] According to another aspect of the present invention, a low dropout linear regulator is provided, comprising: a power transistor connected between a power supply terminal and an output terminal; an error amplifier whose output terminal is connected to the control terminal of the power transistor, the two input terminals of the error amplifier receiving an output voltage and a reference voltage respectively; and the aforementioned output regulation circuit, the output regulation circuit providing a drive current to the power transistor.

[0022] The low-dropout linear regulator (LDO) and its output regulation circuit and method provided by this invention generate a transient current when the input voltage changes rapidly through a transient detection circuit, characterizing the change in input voltage. A load current sampling circuit samples the DC load current to obtain a related current characterization signal. A drive current regulation circuit then determines the drive current based on the transient current and the current characterization signal, pulling up or pulling down the gate voltage of the power transistor. This allows for a timely response to changes in input voltage, exhibiting strong transient response capability. Furthermore, it can adjust the pull-up or pull-down current magnitude in a timely manner according to the load changes of the LDO, significantly reducing the peak deviation of the output voltage while improving transient response capability, effectively suppressing output voltage overshoot and undershoot. It demonstrates good output voltage transient suppression under both full load and no-load conditions, significantly expanding the applicable load range of the LDO.

[0023] Furthermore, the pull-up and pull-down currents are made to change in a positive correlation with the DC load current of the power transistor and with the magnitude of the transient current limit, thus avoiding insufficient or excessive transient suppression of the output voltage caused by using fixed-current pull-up and pull-down. This enhances the flexibility of the transient suppression circuit, enabling it to suppress output voltage overshoot and undershoot when the power supply voltage changes rapidly over a wider load current range.

[0024] Furthermore, the same output regulation circuit architecture is applicable to both PMOS and NMOS power transistors, and can be expanded into a bidirectional transient suppression circuit with pull-up and pull-down modes. This means that the circuit modules required for pull-up and pull-down can be integrated together without additional process or device changes, resulting in strong versatility and scalability.

[0025] It should be noted that the above general description and the following detailed description are exemplary and explanatory only, and do not limit the present invention. Attached Figure Description

[0026] Figure 1 A schematic diagram of the basic circuit structure of a prior art low-dropout linear regulator is shown.

[0027] Figure 2 A schematic diagram of the circuit structure of a low-dropout linear regulator and its output regulation circuit according to an embodiment of the present invention is shown.

[0028] Figure 3 A schematic circuit diagram of an output adjustment circuit according to a first embodiment of the present invention is shown;

[0029] Figure 4 It shows that according to Figure 3 A schematic diagram of the waveforms of each signal in the output regulation circuit when the input voltage drops rapidly;

[0030] Figure 5 A schematic circuit diagram of an output adjustment circuit according to a second embodiment of the present invention is shown;

[0031] Figure 6 A schematic circuit diagram of an output adjustment circuit according to a third embodiment of the present invention is shown;

[0032] Figure 7 It shows that according to Figure 6 A schematic circuit diagram of the load current sampling circuit in the output regulation circuit;

[0033] Figure 8 A schematic flowchart illustrating the output regulation method of a low-dropout linear regulator according to an embodiment of the present invention is provided. Detailed Implementation

[0034] To facilitate understanding of the present invention, a more complete description will be given below with reference to the accompanying drawings. Preferred embodiments of the invention are shown in the drawings. However, the invention can be implemented in various forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a thorough and complete understanding of the disclosure of the invention.

[0035] Figure 2 A schematic diagram of the circuit structure of a low-dropout linear regulator and its output regulation circuit according to an embodiment of the present invention is shown.

[0036] like Figure 2As shown, the low-dropout linear regulator 100 of the present invention includes a power transistor M1, an error amplifier EA, and an output regulation circuit. The power transistor M1 is connected between the power supply terminal and the output terminal, receiving the input voltage VIN from the power supply terminal, and obtaining the output voltage Vout according to the control of the error amplifier EA. One input terminal of the error amplifier EA receives a reference voltage Vref, and the other input terminal receives a sampled voltage Vcs of the output voltage Vout. The output terminal is connected to the control terminal of the power transistor M1. Resistors Rs and RL are connected between the power transistor M1 and the reference ground GND. The common node of resistors Rs and RL provides the sampled voltage Vcs. The power transistor M1 is used to provide the output voltage Vout to the downstream load (e.g., resistors Rs and RL) according to the input voltage VIN provided by the power supply terminal. The error amplifier EA is used to compare the sampled voltage Vcs with the reference voltage Vref to generate an adjustment signal Vctrl based on the error between the two to adjust the gate-source voltage drop of the power transistor M1, thereby changing the output current (or input current) Iout on the power transistor M1 and stabilizing the output voltage Vout.

[0037] Furthermore, the output regulation circuit provided in this embodiment of the invention is used to optimize the transient response of the LDO when the input voltage VIN changes rapidly, to adjust the output current in a timely manner, and to suppress changes in the output voltage, so as to accurately protect the circuit. For example... Figure 2 As shown, the output regulation circuit includes a transient detection circuit, a load current sampling circuit, and a drive current regulation circuit, which together form a transient compensation network. The transient detection circuit is connected between the power supply terminal and the ground terminal. When the input voltage VIN at the power supply terminal changes rapidly, it generates a transient current I1 related to the amplitude and rate of change of the input voltage VIN until the output voltage stabilizes. For example, once the transient detection circuit detects a rapid rise or fall in the input voltage VIN, it generates a transient current I1 proportional to the amplitude and rate of change. A rapid change refers to a rise or fall whose rate and amplitude are significantly greater than the steady state. The load current sampling circuit samples the DC load current of the power transistor by sampling the output current Iout or the output voltage Vout, and outputs a current characterization signal VB that varies with the DC load current. The drive current regulation circuit generates a drive current I2 based on the transient current I1 and the current characterization signal VB to regulate the gate voltage of the power transistor M1.

[0038] Furthermore, when the input voltage VIN changes rapidly, the transient current I1 gradually decreases from the first amplitude current until the output voltage Vout stabilizes. The greater the amplitude of the input voltage VIN change, the larger the first amplitude current; the faster the input voltage VIN changes, the larger the first amplitude current. The current characterization signal VB also exhibits a correlation with the DC load current, for example, a positive or negative correlation, and is generally represented by the output current Iout. Therefore, the drive current I2 increases with increasing DC load current Iout and decreases with decreasing DC load current Iout; and the drive current I2 increases with increasing transient current I1 and decreases with decreasing transient current I1. The load current sampling circuit obtains the current characterization signal VB, which reflects only the DC component, after low-pass filtering of the DC load current Iout of the mirror power transistor M1. This signal, along with the transient current I1, is input to the drive current adjustment circuit, which outputs the drive current I2 of the power transistor M1. In this way, when the input voltage VIN experiences a step drop or rise, the drive current regulation circuit immediately generates a pull-up or pull-down current proportional to the current DC load current Iout as the drive current I2, rapidly adjusting the gate voltage of the power transistor M1 to quickly suppress the overshoot or undershoot of the output voltage VIN. The entire process does not require waiting for the bandwidth response of the error amplifier EA, thus significantly improving the transient performance of the LDO.

[0039] In this embodiment, the power transistor M1 can be either a PMOS or an NMOS transistor. The pull-up and pull-down types of the drive current I2 differ depending on the type of power transistor. Specifically, when the power transistor M1 is a PMOS transistor, the drive current regulation circuit generates a pull-down current I2 when the input voltage VIN drops rapidly, and a pull-up current I2 when the input voltage VIN rises rapidly. Conversely, when the power transistor M1 is an NMOS transistor, the drive current regulation circuit generates a pull-up current I2 when the input voltage VIN drops rapidly, and a pull-down current I2 when the input voltage VIN rises rapidly. The following is a further explanation... Figures 3-7 The specific circuit will be illustrated with an example.

[0040] Figure 3 A schematic circuit diagram of an output regulation circuit according to a first embodiment of the present invention is shown.

[0041] To further illustrate the above functions, Figure 3 The detailed circuit implementation of the first embodiment is given. In this embodiment, the power transistor PM0 is a PMOS transistor. The output regulation circuit 200 includes a transient detection circuit 210, a load current sampling circuit 220, and a drive current regulation circuit 230. The functions of these three circuits are as follows: Figure 2As previously described, the drive current regulation circuit 230 includes three transistors: a reference transistor, a mirror transistor, and an adjustment transistor. The reference transistor and the mirror transistor form a current mirror structure, and both have the same transistor type. The reference transistor converts its transient current I1 into a gate voltage to drive the mirror transistor, causing it to conduct and generate a mirror current, which is then converted into a drive current I2. The adjustment transistor, under the control of the current characterization signal VB, acts as a variable resistor, controlling the conduction level of the mirror transistor to adjust the magnitude of the drive current I2 according to the DC load current Iout.

[0042] like Figure 3 As shown, in this embodiment, taking the power transistor PMO as a PMOS transistor and the input voltage VIN dropping rapidly as an example, the drive current regulation circuit 230 uses an N-type reference transistor, a mirror transistor, and an adjustment transistor, namely, reference transistor NM1, mirror transistor NM2, and adjustment transistor NM3. The first terminal of reference transistor NM1 is connected to the control terminal, receiving the transient current I1, and the second terminal is connected to the power supply terminal. The first terminal, second terminal, and control terminal of reference transistor NM1 are the drain, source, and gate, respectively. Its drain receives the transient current I1 and is connected to the gate, while its source is grounded, with the ground terminal serving as the power supply terminal. The control terminal of mirror transistor NM2 is connected to the control terminal of reference transistor NM1. Reference transistor NM1 generates a gate reference voltage based on the transient current I1, and mirror transistor NM2 conducts based on the gate reference voltage, providing a mirror current from its first terminal, which is then converted into a drive current I2. The first terminal and second terminal of mirror transistor NM2 are the drain and source, respectively. The first terminal of the regulating transistor NM3 is connected to the second terminal of the mirror transistor NM2, which is connected to the power supply terminal. The control terminal receives the current characterization signal VB. The first and second terminals of the regulating transistor NM3 are the drain and source, respectively, with the source grounded. The grounded terminal is used as the power supply terminal. Furthermore, the equivalent resistance of the regulating transistor NM3 changes negatively with the DC load current Iout. In this embodiment, when the input voltage VIN drops rapidly, the mirror current is directly used as the drive current I2.

[0043] The transient detection circuit 210 includes a first detection circuit and a second detection circuit. The first detection circuit is connected to a first type of reference transistor, and the second detection circuit is connected to a second type of reference transistor. The first type is, for example, N-type, and the second type is, for example, P-type. In this embodiment, since it is connected to the N-type reference transistor NM1, the first detection circuit is used. It generates a sinking-type first transient current when the input voltage VIN drops rapidly, making the mirrored current a pull-down current. In this embodiment, the transient detection circuit 210 uses the first detection circuit, and the first transient current is used as the transient current I1 generated by the transient detection circuit 210. The first detection circuit includes a first resistor R1 and a first capacitor C1 connected in series between the power supply terminal and the ground terminal, and a current mirror structure connected to their common node. The current mirror structure includes a first P-type transistor PQ1 and a first current source A1 connected in series between the power supply terminal and the ground terminal, and a second P-type transistor PQ2 and a second current source A2 connected in series between the common node of the first resistor R1 and the first capacitor C1 and the ground terminal. A node voltage Vs is provided from the common node of the first resistor R1 and the first capacitor C1. The width-to-length ratio of the first P-type transistor PQ1 and the second P-type transistor PQ2 are equal, and the first current source A1 and the second current source A2 are the same, meaning that they generate the same current. Specifically, the two ends of the first resistor R1 are connected to the input voltage VIN and the upper plate of the first capacitor C1, respectively. The lower plate of the first capacitor C1 is grounded. The source of the first P-type transistor PQ1 is connected to the input voltage VIN. The gate and drain of the first P-type transistor PQ1 and the gate of the second P-type transistor PQ2 are connected to the positive terminal of the first current source A1. The source of the second P-type transistor PQ2 is connected to the upper plate of the first capacitor C1, and the drain is connected to the positive terminal of the second current source A2. The difference between the drain-source current of the second P-type transistor PQ2 and the current generated by the second current source A2 is the transient current I1. When the input voltage VIN is stable, due to the voltage drop across the first resistor R1, the drain-source current of the second P-type transistor PQ2 is less than that of the first P-type transistor PQ1, making the transient current I1 zero. This pulls down the gate of the reference transistor NM1, resulting in a zero pull-down drive current I2 for the power transistor PM0. However, when the input voltage VIN drops rapidly, the gate voltage of the second P-type transistor PQ2 immediately follows the drop in VIN. Meanwhile, the source voltage of the second P-type transistor PQ2 remains constant momentarily due to the effect of the first resistor R1 and the first capacitor C1, and drops slowly. This causes the drain-source current of the second P-type transistor PQ2 to be greater than that of the first P-type transistor PQ1, resulting in a transient current I1 that is related to the magnitude and speed of the drop in the input voltage VIN until the output voltage Vout stabilizes.

[0044] Furthermore, when the N-type regulating transistor NM3 is connected, the load current sampling circuit 220 includes a load current mirror branch 221 and a second filter network 222. The second filter network 222 includes a fourth resistor R4 and a fourth capacitor C4 connected between the load current mirror branch 221 and the ground terminal. When the power transistor PM0 is a PMOS transistor, the load current mirror branch 221 includes a third P-type transistor PQ3 and a second N-type transistor NQ2 connected in series between the power supply terminal and the ground terminal. The first terminal of the third P-type transistor PQ3 is connected to the power supply terminal, and its control terminal is connected to the control terminal of the power transistor PM0. The first terminal of the second N-type transistor NQ2 is connected to the second terminal of the third P-type transistor PQ3, and the second terminal of the second N-type transistor NQ2 is grounded. The control terminal of the second N-type transistor NQ2 is connected to the second filter network 222. The first and second terminals of the third P-type transistor PQ3 are the source and drain, respectively, and the first and second terminals of the second N-type transistor NQ2 are the drain and source, respectively. The first terminal of the fourth resistor R4 is connected to the drain and gate of the second N-type transistor NQ2, and the second terminal of the fourth resistor R4 is connected to the first terminal of the fourth capacitor C4. The second terminal of the fourth capacitor C4 is grounded. A current characterization signal VB is provided from the intermediate node of the fourth resistor R4 and the fourth capacitor C4. In the load current sampling circuit 230, the third P-type transistor PQ3 and the power transistor PM0 form a current mirror. The third P-type transistor PQ3 mirrors the current of the power transistor PM0 proportionally, so that the gate voltage of the second N-type transistor NQ2 increases (decreases) as the DC load current Iout of the power transistor PM0 increases (decreases). The fourth resistor R4 and the fourth capacitor C4 filter the gate voltage of the second N-type transistor NQ2 to obtain a current characterization signal VB that is only related to the DC load current Iout of the power transistor PM0. The current characterization signal VB is applied to the gate of the regulating transistor NM3, so that the regulating transistor NM3 becomes a resistor that decreases (increases) as the DC load current Iout increases (decreases). The mirror transistor NM2 and the regulating transistor NM3 form a source resistor negative feedback structure, causing the drive current I2 to increase (decrease) as the DC load current Iout and the transient current I1 increase (decrease). When the input voltage VIN drops rapidly, a corresponding drive current I2 is generated to pull down the gate voltage of the power transistor PM0, reducing the undershoot of the output voltage Vout.

[0045] In this embodiment, the output regulation circuit 200 further includes an initial drive unit, which keeps the mirror transistor NM2 in a conducting state when no load is applied, so as to provide minimum drive current for the power transistor PM0. Figure 3In this embodiment, when the power transistor PM0 is a P-type transistor, the regulating transistor NM3 is an N-type transistor, and the output voltage IN drops rapidly, the initial drive unit includes a third current source A3 connected between the power supply terminal and the drain of the second N-type transistor NQ2. Furthermore, a resistor R5 can be connected between the source of the second N-type transistor NQ2 and the ground terminal. The function of the third current source A3 and the resistor R5 is to maintain a certain voltage for the current characterization signal VB even under light load, allowing the regulating transistor NM3 to enter the linear region and exhibit resistive characteristics. Of course, a general initial drive unit in this embodiment may include a resistor (not shown in the figure) connected in parallel across the regulating transistor NM3, which will be mentioned in the subsequent description of the figures.

[0046] Figure 4 It shows that according to Figure 3 The waveform diagram of each signal in the output regulation circuit when the input voltage drops rapidly.

[0047] Figure 4 Before time t1, the input voltage VIN remains stable, the node voltage Vs is a fixed value, the transient current I1 is 0, the drive current I2 is 0, the current characterization signal VB remains stable, the gate voltage Vctrl of the power transistor PM0 remains stable, and the output voltage Vout remains stable. At time t1, the input voltage VIN drops rapidly, the node voltage Vs is pulled down instantaneously, and the conduction of the second P-type transistor PQ2 increases, generating a large sinking transient current I1. Due to the filtering effect of the second filter network 222, the current characterization signal VB experiences a slight fluctuation when the load current decreases instantaneously due to the transient change, but it remains essentially constant, stabilizing the resistance of the regulating transistor NM3 and ensuring the stability of the undershoot suppression circuit. The mirror transistor NM2 mirrors the transient current I1 into a mirror current, obtaining a pull-down drive current I2, which pulls down the gate voltage, reducing the gate voltage Vctrl, thereby causing the output voltage Vout to rise slowly. During the time interval t1-t2, the node voltage Vs gradually decreases, the transient current I1 gradually decreases from the initial amplitude current If1 until the output voltage stabilizes, and the drive current I2 also gradually decreases, causing the gate voltage Vctrl to stabilize at a relatively low level, and the output voltage Vout gradually recovers. After time t2, it enters a steady state again.

[0048] In addition, since the gate of the regulating transistor NM3 is controlled by the current characterization signal VB, its equivalent resistance decreases as the DC load current Iout increases, causing the drive current I2 to increase as the DC load current Iout increases. Figure 4In the diagram, the solid line represents the DC load current Iout1 in the first steady state, and the dashed line represents the DC load current Iout2 in the second steady state, with Iout1 < Iout2. It can be seen that when the DC load current increases from Iout1 to Iout2, the current characterization signal VB increases accordingly, the drive current I2 increases accordingly, the gate voltage Vctrl is pulled down more quickly, the undershoot of the output voltage Vout is significantly reduced, and it reaches stability more quickly, thus verifying the effectiveness of this invention over a wide load range.

[0049] Figure 5 A schematic circuit diagram of an output adjustment circuit according to a second embodiment of the present invention is shown.

[0050] Figure 3 A pull-down drive current I2 can only be generated when the power transistor PMO is a PMOS transistor and the input voltage VIN drops rapidly, in order to quickly suppress the undershoot of the output voltage. In actual use, when the input voltage VIN rises rapidly, the output voltage will also overshoot, and it is also necessary to suppress the overshoot of the output voltage. Therefore, in this embodiment... Figure 3 A second detection circuit was added to the existing embodiment.

[0051] like Figure 5 As shown, the output regulation circuit 200 of this embodiment includes a transient detection circuit 210, a load current sampling circuit 220, and a drive current regulation circuit 230. The transient detection circuit 210 includes a first detection circuit 211 and a second detection circuit 212. The load current sampling circuit 220 includes a load current mirror branch 221, a second filter network 222, and a first filter network 223. The drive current regulation circuit 230 includes a first drive current circuit 231 and a second drive current circuit 232. The first detection circuit 211, the first drive current circuit 231, the load current mirror branch 221, and the second filter network 222 together constitute... Figure 3 The output regulation circuit of this embodiment. A first detection circuit 211 provides a first transient current I11 (sinking type), making the mirrored current a pull-down current (drawing type), thereby generating a first pull-down drive current I21. A second filter network 222 provides a first current characterization signal VB to control the conduction level of the regulating transistor NM3. The circuit involved here is similar to... Figure 3 The similarities in circuit structure and working principle will not be elaborated further.

[0052] In this embodiment, taking the power transistor PM0 as a PMOS transistor and the input voltage VIN rising rapidly as an example, the second drive current circuit 232 uses a P-type reference transistor, a mirror transistor, and an adjustment transistor, namely, reference transistor PM1, mirror transistor PM2, and adjustment transistor PM3. When both reference transistor PM1 and adjustment transistor PM1 are PMOS transistors, they are connected to the second detection circuit 212 and the first filter network 223, respectively. The functions of reference transistor PM1, mirror transistor PM2, and adjustment transistor PM3 are... Figure 3 The implementation is the same, and the connection method is similar. The second detection circuit 212 generates a decimated second transient current I12 when the input voltage VIN rises rapidly, making the mirrored current a sink-type pull-up current, and directly using the mirrored current as the second drive current I22. The second transient current I12 increases (decreases) as the rise amplitude and speed of the input voltage VIN increase (decreases). The second detection circuit 212 includes a second capacitor C2 and a second resistor R2 connected in series between the power supply terminal and the ground terminal, and a first N-type transistor NQ1 whose control terminal is connected to the common node of the second capacitor C2 and the second resistor R2. The first terminal of the first N-type transistor NQ1 is grounded, and the second terminal provides the second transient current I12. The first terminal and the second terminal of the first N-type transistor NQ1 are the drain and source, respectively. When the input voltage VIN rises rapidly, the gate voltage of the first N-type transistor NQ1 is raised, thereby generating the decimated second transient current I12. The first filter network 223 includes a third capacitor C3 and a third resistor R3 connected in series between the power supply terminal and the control terminal of the power transistor PMO, and the second current characterization signal VB2 is provided by the common node of the two.

[0053] Furthermore, Figure 5 In this circuit, the source of reference transistor PM1 is connected to the power supply, its drain receives the second transient current I12, and its gate is connected to the gate of mirror transistor PM2. The source of mirror transistor PM2 is connected to the drain of regulating transistor PM3. The gate of regulating transistor PM3 receives the second current characterization signal VB2, its source is connected to the power supply, and the drain of mirror transistor PM2 provides the mirror current, which serves as the second drive current I22. The third capacitor C3 and the third resistor R3, connected in series between the power supply and the control terminal of power transistor PM0, are essentially based on the gate-source voltage of power transistor PM0 to obtain the second current characterization signal VB2. When the DC load current Iout increases, the gate-source voltage of power transistor PM0 decreases, the second current characterization signal VB2 decreases, and it is input to the control terminal of regulating transistor PM3, causing the resistance of regulating transistor PM3 to decrease and the second drive current I22 to increase. Therefore, the second drive current I22 increases (decreases) as the DC load current Iout increases (decreases), showing a positive correlation.

[0054] In this embodiment, the initial drive unit includes a resistor Rn1 connected in parallel with the regulating transistor NM3 and a resistor Rn2 connected in parallel with the regulating transistor PM3. Resistors Rn1 and Rn2 are relatively large resistors that keep the mirror transistors NM2 and PM2 at a certain degree of conduction when no load is applied, so as to provide the minimum drive current for the power transistors.

[0055] Figure 5 This embodiment is an application scheme that combines pull-up and pull-down drive currents, which can suppress the overshoot of the output voltage Vout when the input voltage VIN rises and the undershoot of the output voltage Vout when the input voltage VIN falls. When applied only to scenarios where the input voltage VIN rises or falls, the output regulation circuit can also be separated.

[0056] Figure 6 A schematic circuit diagram of an output adjustment circuit according to a third embodiment of the present invention is shown.

[0057] The above embodiments illustrate the circuit structure and working principle of the output regulation circuit when the power transistor is a PMOS transistor. In practical applications, the power transistor can also be an NMOS transistor. Figure 6 As shown, in this embodiment, the power transistor NM0 is an NMOS transistor, and the output regulation circuit can simultaneously regulate the overshoot and undershoot of the output voltage Vout as an example.

[0058] like Figure 6 As shown, when the power transistor NM0 is an NMOS transistor, the output regulation circuit 300 includes a transient detection circuit 210, a load current sampling circuit 320, and a drive current regulation circuit 330. The drive current regulation circuit 330 includes a first drive current circuit 331 and a second drive current circuit 332, and the transient detection circuit 210 includes a first detection circuit and a second detection circuit. The first detection circuit is connected to the N-type reference transistor and generates a sinking-type first transient current I11 when the input voltage VIN drops rapidly, making the mirror current a pull-down current. The second detection circuit is connected to the P-type reference transistor and generates a pull-down-type second transient current I12 when the input voltage VIN rises rapidly, making the mirror current a sinking-type pull-up current. The first and second detection circuits in this embodiment can be connected to... Figure 5 The embodiments are exactly the same, so they will not be described in detail here.

[0059] The first driving current circuit 331 and the second driving current circuit 332 are also related to Figure 5Similarly, both include a reference transistor, a mirror transistor, and a regulating transistor. Furthermore, when the power transistor NM0 is an NMOS transistor, both the first drive current circuit 331 and the second drive current circuit 332, in addition to the reference transistor, mirror transistor, and regulating transistor, may also include a current mirror. The current mirror is used to convert the mirrored current into a reverse drive current. Specifically, the first drive current circuit 331, used to suppress the undershoot of the output voltage Vout when the input voltage VIN drops rapidly, uses an N-type reference transistor NM1, a mirror transistor NM2, and a regulating transistor NM3, as well as a P-type current mirror. The second drive current circuit 332, used to suppress the overshoot of the output voltage Vout when the input voltage VIN rises rapidly, uses a P-type reference transistor PM1 and a mirror transistor PM2, an N-type regulating transistor NM31, and an N-type current mirror. Due to the use of the current mirror, when the power transistor is an NMOS transistor, the drive current regulation circuit 330 can use N-type regulating transistors (NM3 and NM31) when the input voltage VIN drops and rises rapidly, and the load current sampling circuit 320 generates a single current characterization signal VB.

[0060] like Figure 6 As shown, the first driving current circuit 331 includes a reference transistor NM1, a mirror transistor NM2, an adjustment transistor NM3, and a current mirror 333. The reference transistor NM1, the mirror transistor NM2, and the adjustment transistor NM3 are connected to... Figure 5 The implementation is completely identical and will not be repeated here. The current mirror 333 includes transistors PM4 and PM5. The source and gate of transistor PM4 are connected to the source and gate of transistor PM5, respectively, and the sources of both transistors PM4 and PM5 receive the supply voltage VCC. The drain and gate of transistor PM4 are connected and receive a mirrored current, generating a first drive current I21 from the drain of transistor PM5. This first drive current I21 is a sink-type pull-up current, increasing the gate voltage Vctrl of power transistor NM0 to reduce the undershoot of the output voltage Vout. The second drive current circuit 332 includes a reference transistor PM1, a mirror transistor PM2, an adjustment transistor NM31, and a current mirror 334. The reference transistor PM1 and the mirror transistor PM2 are connected to... Figure 5 The implementation is completely identical and will not be repeated here. The current mirror 334 includes transistors NM4 and NM5. The gate of transistor NM4 is connected to the gate of transistor NM5, and the source of transistor NM4 is grounded. The source of transistor NM5 is connected to the drain of regulating transistor NM31, and the source of regulating transistor NM31 is grounded. Its gate receives the current characterization signal VB. The drain and gate of transistor NM4 are connected, and it receives the mirrored current. A second drive current I22 is generated from the drain of transistor NM5. This second drive current I22 is a pull-down current, which reduces the gate voltage Vctrl of power transistor NM0 to reduce the overshoot of the output voltage Vout.

[0061] The working principle of the output regulation circuit when the power transistor is an NMOS transistor Figure 5 Similarly, this will not be elaborated further here. The output regulation circuit of this embodiment can also be split according to the actual changes in the input voltage and requirements; this is not a limitation.

[0062] Figure 7 It shows according to Figure 6 A schematic circuit diagram of the load current sampling circuit in the output regulation circuit.

[0063] like Figure 7 As shown, when connecting the N-type regulating transistor, the load current sampling circuit 320 includes a load current mirror branch 321 and a second filter network 322. The second filter network 322 includes a fourth resistor R4 and a fourth capacitor C4 connected between the load current mirror branch 321 and the ground terminal. The load current mirror branch 321 includes a third N-type transistor NQ3, a fourth P-type transistor PO4, and a fourth N-type transistor NQ4 connected in series between the power supply terminal and the ground terminal, and a fifth P-type transistor PQ5 and a fifth N-type transistor NQ5 connected in series between the output terminal of the power transistor NM0 and the ground terminal. The fifth P-type transistor PQ5 and the fifth N-type transistor NQ5 are connected in parallel with the load resistor RL. Among them, the fourth N-type transistor NQ4 and the fifth N-type transistor NQ5 form a current mirror structure, and the fourth P-type transistor PQ4 and the fifth P-type transistor PQ5 also form a current mirror structure. Therefore, due to the existence of the two current mirror structures, the current in the branch where the fourth P-type transistor PQ4 is located is equal to the current in the branch where the fifth P-type transistor PQ5 is located, so their gate-source voltages are the same. The source of the fifth P-type transistor PQ5 receives the output voltage Vout, and the gate of the fourth P-type transistor PQ4 is connected to the gate of the fifth P-type transistor PQ5. Therefore, the source voltage of the fourth P-type transistor PQ4 is also the output voltage Vout. This is equivalent to the third N-type transistor NQ3 and the power transistor NM0 having the same gate-source voltage. That is, the third N-type transistor NQ3 mirrors the DC load current Iout of the power transistor NM0. Then, the current characterization signal VB related to the DC load current Iout is obtained through the second filter network 322.

[0064] Figure 8 A schematic flowchart illustrating the output regulation method of a low-dropout linear regulator according to an embodiment of the present invention is provided.

[0065] like Figure 8 As shown, the present invention also provides an output regulation method for a low-dropout linear regulator, which is applicable to the above-mentioned... Figures 2-7 The operating principles and connections of all output regulation circuits and LDOs described in the embodiments will not be repeated here. The output regulation method of this embodiment includes steps S101-S103.

[0066] In step S101, a transient current is generated when the input voltage at the power supply terminal changes rapidly, which is related to the magnitude and rate of change of the input voltage.

[0067] In step S102, the DC load current of the power transistor is sampled, and a current characterization signal that varies with the DC load current is output.

[0068] In step S103, a drive current is generated based on the transient current and the current characterization signal to adjust the gate voltage of the power transistor and suppress changes in the output voltage.

[0069] It should be noted that the numerical values ​​in this article are for illustrative purposes only. In other embodiments of the present invention, other numerical values ​​may be sampled to implement this solution. The specific values ​​should be reasonably set according to the actual situation, and the present invention does not limit them.

[0070] Finally, it should be noted that the above embodiments are merely examples for clearly illustrating the present invention and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations. However, obvious variations or modifications derived therefrom are still within the scope of protection of this invention.

[0071] It should also be understood that the terminology and expressions used herein are for descriptive purposes only, and one or more embodiments described herein should not be limited to these terms and expressions. The use of these terms and expressions does not exclude any illustrative and descriptive equivalent features (or parts thereof), and it should be recognized that various modifications that may exist should also be included within the scope of the claims. Other modifications, variations, and substitutions may also exist. Accordingly, the claims should be considered to cover all such equivalents.

Claims

1. An output regulation circuit for a low-dropout linear regulator, the low-dropout linear regulator comprising a power transistor located between a power supply terminal and an output terminal and an error amplifier connected to the control terminal of the power transistor, wherein, The output regulation circuit includes: The transient detection circuit generates a transient current related to the amplitude and rate of change of the input voltage when the input voltage at the power supply terminal changes rapidly. A load current sampling circuit samples the DC load current of the power transistor and outputs a current characterization signal that varies with the DC load current; and The drive current regulation circuit generates a drive current based on the transient current and the current characterization signal to regulate the gate voltage of the power transistor and suppress changes in the output voltage.

2. The output adjustment circuit according to claim 1, wherein, When the input voltage changes rapidly, the transient current gradually decreases from the first amplitude current until the output voltage stabilizes. The greater the amplitude of the input voltage change, the greater the first amplitude current; the faster the input voltage changes, the greater the first amplitude current.

3. The output adjustment circuit according to claim 1, wherein, The driving current increases as the DC load current increases and decreases as the DC load current decreases; and the driving current increases as the transient current increases and decreases as the transient current decreases.

4. The output adjustment circuit according to claim 1, wherein, When the power transistor is a PMOS transistor, the drive current regulation circuit generates a pull-down current when the input voltage drops rapidly, and a pull-up current when the input voltage rises rapidly. When the power transistor is an NMOS transistor, the drive current regulation circuit generates a sink-type pull-up current when the input voltage drops rapidly, and a pull-down current when the input voltage rises rapidly.

5. The output adjustment circuit according to claim 1, wherein, The drive current regulation circuit includes: A reference transistor, the first end of which is connected to the control terminal to receive the transient current, and the second end of which is connected to the power supply terminal, generates a gate reference voltage based on the transient current; A mirror transistor, wherein the control terminal of the mirror transistor is connected to the control terminal of the reference transistor to conduct according to the gate reference voltage, and the first terminal of the mirror transistor provides a mirror current, which is then converted into the driving current. The mirror transistor and the reference transistor are transistors of the same type. The regulating transistor has a control terminal that receives the current characterization signal, a first terminal that is connected to the second terminal of the mirror transistor, a second terminal that is connected to the power supply terminal, and an equivalent resistance that changes negatively with the DC load current.

6. The output adjustment circuit according to claim 5, wherein, The transient detection circuit includes: The first detection circuit is connected to the first type of reference transistor and generates a first transient current when the input voltage drops rapidly, so that the mirror current is a pull-down current. The second detection circuit, connected to the second type of reference transistor, generates a second transient current when the input voltage rises rapidly, making the mirror current a sink-type pull-up current.

7. The output adjustment circuit according to claim 6, wherein, The first detection circuit includes: A first resistor and a first capacitor connected in series between the power supply terminal and the ground terminal provide the node voltage from their common node; A first P-type transistor and a first current source connected in series between the power supply terminal and the ground terminal; and A second P-type transistor and a second current source are connected in series between the common node of the first resistor and the first capacitor and the ground terminal. The intermediate node of the second P-type transistor and the second current source provides the first transient current. The first P-type transistor, the second P-type transistor, the first current source, and the second current source together form a current mirror structure.

8. The output adjustment circuit according to claim 6, wherein, The second detection circuit includes: A second capacitor and a second resistor connected in series between the power supply terminal and the ground terminal; and A first N-type transistor is connected to the common node of the second capacitor and the second resistor at the control terminal. The first terminal of the first N-type transistor is grounded, and the second terminal is connected to the control terminal of the reference transistor and the mirror transistor. The first N-type transistor provides the second transient current.

9. The output adjustment circuit according to claim 6, wherein, When the power transistor is a PMOS transistor When the input voltage drops rapidly, the drive current regulation circuit uses the N-type reference transistor and mirror transistor to directly use the mirror current as the drive current. When the input voltage rises rapidly, the drive current regulation circuit uses the P-type reference transistor and mirror transistor to directly use the mirror current as the drive current.

10. The output adjustment circuit according to claim 6, wherein, When the power transistor is an NMOS transistor, the drive current regulation circuit further includes a current mirror to convert the mirrored current into the reversed drive current. When the input voltage drops rapidly, the drive current regulation circuit uses the N-type reference transistor and mirror transistor, as well as the P-type current mirror; When the input voltage drops rapidly, the drive current regulation circuit uses the P-type reference transistor and mirror transistor, as well as the N-type current mirror.

11. The output adjustment circuit according to claim 5, wherein, When the P-type regulating transistor is connected, the load current sampling circuit includes a first filter network, which includes a third capacitor and a third resistor connected in series between the power supply terminal and the control terminal of the power transistor. When the N-type regulating tube is connected, the load current sampling circuit includes a load current mirror branch and a second filter network. The second filter network includes a fourth resistor and a fourth capacitor connected between the load current mirror branch and the ground terminal.

12. The output adjustment circuit according to claim 11, wherein, When the power transistor is a PMOS transistor, the drive current regulation circuit uses an N-type regulating transistor when the input voltage drops rapidly, and uses a P-type regulating transistor when the input voltage rises rapidly. When the power transistor is an NMOS transistor, the drive current regulation circuit uses the N-type regulating transistor during both the rapid decrease and rapid increase of the input voltage.

13. The output adjustment circuit according to claim 12, wherein, When the power transistor is a PMOS transistor, the load current mirror branch includes: A third P-type transistor, wherein the first end of the third P-type transistor is connected to the power supply terminal, and the control terminal is connected to the control terminal of the power transistor; and The second N-type transistor has its first end connected to the second end of the third P-type transistor, and its second end grounded. The control terminal of the second N-type transistor is connected to the second filter network.

14. The output adjustment circuit according to claim 12, wherein, When the power transistor is an NMOS transistor, the load current mirror branch includes: A third N-type transistor, a fourth P-type transistor, and a fourth N-type transistor connected in series between the power supply terminal and the ground terminal; and The fifth P-type transistor and the fifth N-type transistor, connected in series between the output terminal and the ground terminal of the power transistor, are connected in parallel with the load resistor. The fourth N-type transistor and the fifth N-type transistor constitute a current mirror structure, and the fourth P-type transistor and the fifth P-type transistor also constitute a current mirror structure.

15. The output adjustment circuit according to claim 9, further comprising: An initial drive unit keeps the mirror transistor on when unloaded to provide a minimum drive current for the power transistor. The initial drive unit includes a resistor connected in parallel with the regulating transistor.

16. A method for output regulation of a low-dropout linear regulator, the low-dropout linear regulator comprising a power transistor located between a power supply terminal and an output terminal and an error amplifier connected to the control terminal of the power transistor, wherein, The output adjustment method includes: When the input voltage at the power supply terminal changes rapidly, a transient current is generated that is related to the magnitude and rate of change of the input voltage. Sample the DC load current of the power transistor and output a current characterization signal that varies with the DC load current; and A drive current is generated based on the transient current and the current characterization signal to adjust the gate voltage of the power transistor and suppress changes in the output voltage.

17. A low-dropout linear regulator, comprising: A power transistor connected between the power supply terminal and the output terminal; An error amplifier whose output is connected to the control terminal of the power transistor has two input terminals that receive the output voltage and the reference voltage, respectively. as well as The output regulation circuit according to any one of claims 1-15 provides a drive current to the power transistor.

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