A current limiting protection circuit and low dropout linear regulator

Abstract

The application provides a current limiting protection circuit and a low dropout linear regulator, and belongs to the technical field of integrated circuits, and is applied to a target circuit containing a power tube, and comprises: a current comparison unit configured to compare a sampling current sampled from the power tube with a reference current; the reference current is a mirror current of the sum of a first bias current and a second bias current which is gated by an output voltage of the target circuit; a current limiting control unit configured to generate a current limiting control signal under the control of a current comparison signal; and a clamping unit configured to be controllably connected between the input end and the control end of the current limiting control unit under the control of the current limiting control signal. Beneficial effects: when the output voltage decreases, the second bias current no longer participates in the current comparison, and a return type current limiting is realized; meanwhile, the input end and the control end voltage of the current limiting control unit are clamped, abnormal triggering of the current limiting protection mechanism due to abnormal increase of the output current is avoided, and the stability and reliability of the circuit are improved.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a current limiting protection circuit and a low dropout linear regulator. Background Technology

[0002] With the rapid evolution of modern high-performance computing, communication and portable electronic devices, the process nodes of core chips such as processors, field programmable gate arrays (FPGAs) and application-specific integrated circuits (ASICs) are constantly shrinking, and the operating voltage of chips is continuously decreasing, now down to below 1V, while the current demand is rising sharply, reaching tens or even hundreds of amperes. At the same time, the load current will change drastically within nanoseconds, which brings huge challenges to the power management of electronic systems.

[0003] Traditional power management technologies are no longer sufficient to meet the power stability and response speed requirements of these high-performance chips. Against this backdrop, technological innovation in low dropout regulators (LDOs) is particularly urgent. The development of LDOs with fast transient response under high current conditions (tens or even hundreds of amperes) has become a key support for the evolution of electronic systems towards higher performance and lower power consumption.

[0004] However, when the circuit starts up or the transient current of the downstream load changes, the output current of the high-current LDO may increase abnormally, which may trigger the current limiting protection mechanism abnormally, causing the LDO to fail to work properly, and thus affecting the stability and reliability of the entire electronic system. Summary of the Invention

[0005] To address the above technical problems, the present invention provides a current limiting protection circuit; on the other hand, it provides a low dropout linear regulator.

[0006] The technical problem solved by this invention can be achieved by the following technical solutions: A current-limiting protection circuit, applied to a target circuit containing a power transistor, includes: A current comparison unit is used to compare the sampled current sampled from the power transistor with a reference current and output a current comparison signal; wherein, the reference current is a mirror copy of the sum of a first bias current and a second bias current controlled by the output voltage gating of the target circuit. A current limiting control unit is connected to the current comparison unit and generates a current limiting control signal under the control of the current comparison signal. The clamping unit is controllably connected between the input terminal and the control terminal of the current limiting control unit under the control of the current limiting control signal, so as to clamp the voltage at the input terminal and the control terminal of the current limiting control unit.

[0007] The current limiting protection circuit of the present invention includes a clamping unit comprising: A transistor, wherein the base of the transistor is connected to the current limiting control signal, and the collector of the transistor is connected to the input terminal of the current limiting control unit; The first PMOS transistor has its gate and drain connected to the control terminal of the current limiting control unit, and its source connected to the emitter of the transistor.

[0008] In the current limiting protection circuit of the present invention, the first bias current is provided by a first current branch, and the first current branch includes: A first current source, one end of which is connected to the input terminal of the target circuit, and the other end of which is used to generate the first bias current; The second PMOS transistor has its source connected to the first bias current, its gate connected to the first reference voltage, and its drain used to output the first bias current.

[0009] The current limiting protection circuit of the present invention further includes: The third PMOS transistor has its gate connected to the output voltage of the target circuit via a third resistor, its source connected to the first bias current, and its drain connected to ground.

[0010] In the current limiting protection circuit of the present invention, the second bias current is provided by a second current branch, which includes: A second current source, one end of which is connected to the input terminal of the target circuit, and the other end of which is used to generate the second bias current; The first NMOS transistor has its drain connected to the second bias current, its gate connected to the second reference voltage, and its source used to output the second bias current.

[0011] The current limiting protection circuit of the present invention comprises a first bias current provided by a first current branch, a second bias current provided by a second current branch, and a reference current generated by a mirror replication unit, the mirror replication unit comprising: The second NMOS transistor has its gate connected to the second bias current and its drain connected to the output terminal of the first current branch. The third NMOS transistor has its gate connected to the second bias current, its drain connected to the source of the second NMOS transistor, and its source connected to ground. A fourth NMOS transistor and a fifth NMOS transistor are provided, with the gates of the fourth and fifth NMOS transistors respectively connected to the second bias current, the sources of the fourth and fifth NMOS transistors respectively connected to the ground terminal, the drain of the fourth NMOS transistor being used to provide a first reference current, and the drain of the fifth NMOS transistor being used to provide a second reference current.

[0012] The current limiting protection circuit of the present invention, wherein the sampling current is generated by a current sampling unit, the current sampling unit comprising: The fourth PMOS transistor has its gate connected to the gate of the power transistor, its drain connected to the drain of the power transistor, and its source used to generate the sampling current.

[0013] The current limiting protection circuit of this invention includes a current comparison unit comprising: a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, a first resistor, and a second resistor. The gates of the fifth, sixth, seventh, and eighth PMOS transistors are connected together. The source of the fifth PMOS transistor is connected to the sampling current and, through the first resistor, to the input terminal of the target circuit. The drain of the fifth PMOS transistor is connected to the source of the sixth PMOS transistor. The drain and gate of the sixth PMOS transistor are shorted and connected to the drain of the seventh NMOS transistor. The gate of the seventh NMOS transistor is connected to the bias voltage. The source of the seventh NMOS transistor is connected to the first reference current. The source of the seventh PMOS transistor is connected to the input terminal of the target circuit through the second resistor. The drain of the seventh PMOS transistor is connected to the source of the eighth PMOS transistor. The drain of the eighth PMOS transistor is connected to the drain of the sixth NMOS transistor. The gate of the sixth NMOS transistor is connected to the bias voltage. The source of the sixth NMOS transistor is connected to the second reference current.

[0014] The current limiting protection circuit of the present invention includes a current limiting control unit comprising: The eighth NMOS transistor has its gate connected to the current comparison signal, its drain connected to the input terminal of the target circuit, and its source used to generate the current limiting control signal.

[0015] On the other hand, a low-dropout linear regulator is provided, comprising: The main operational amplifier circuit is a multi-stage operational amplifier. A current limiting protection module, comprising the current limiting protection circuit described above, to generate a current limiting control signal to the input of the second-stage operational amplifier.

[0016] The advantages or beneficial effects of the technical solution of this invention are as follows: This invention compares the sampled current from the power transistor with a reference current using a current comparison unit. The current limiting control unit then generates a current limiting control signal based on the current comparison signal, achieving current limiting protection. Since the reference current is a mirror image of the sum of the first bias current and the second bias current controlled by the output voltage of the target circuit, when the output voltage decreases, the second bias current no longer participates in the current comparison, reducing the current limiting value and achieving foldback current limiting. Simultaneously, the clamping unit clamps the input and control voltages of the current limiting control unit based on the current limiting control signal, preventing abnormal triggering of the current limiting protection mechanism due to an abnormal increase in output current during circuit startup or when the transient current of the downstream load changes. This ensures normal circuit operation and improves circuit stability and reliability. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of a current limiting protection circuit in a preferred embodiment of the present invention; Figure 2 This is a schematic diagram of the main operational amplifier circuit of a low-dropout linear regulator, which is a preferred embodiment of the present invention. Detailed Implementation

[0018] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0019] It should be noted that, unless otherwise specified, the embodiments and features described in the present invention can be combined with each other.

[0020] The present invention will be further described below with reference to the accompanying drawings and specific embodiments, but this is not intended to limit the scope of the invention.

[0021] See Figure 1 In a preferred embodiment of the present invention, based on the above-mentioned problems existing in the prior art, a current limiting protection circuit is provided, applied to a target circuit including a power transistor, comprising: The current comparison unit 1 is used to compare the sampled current of the power transistor with the reference current and output a current comparison signal; wherein, the reference current is a mirror copy of the sum of the first bias current Ibias1 and the second bias current Ibias2 controlled by the output voltage gating of the target circuit. The current limiting control unit 2 is connected to the current comparison unit 1, and generates the current limiting control signal OCP_OUT under the control of the current comparison signal; Clamping unit 3 is controllably connected between the input terminal and the control terminal of current limiting control unit 2 under the control of current limiting control signal OCP_OUT, so as to clamp the voltage at the input terminal and the control terminal of current limiting control unit 2.

[0022] Specifically, this invention provides a highly reliable current-limiting protection circuit for target circuits. This current-limiting protection circuit is mainly applied to target circuits with high current and fast transient response characteristics. Its principle is as follows: The load current of the target circuit is detected and used as a sampling current. The detected sampling current is compared with a set reference current. At this time, the second bias current Ibias2 is controlled by the output voltage of the target circuit and is turned on. That is, the reference current is a mirror copy of the sum of the first bias current Ibias1 and the second bias current Ibias2, denoted as I1. When the sampling current is greater than the set reference current I1, the current-limiting control unit 2 generates a current-limiting control signal OCP_OUT, triggering current-limiting protection and keeping the load current provided by the power transistor constant.

[0023] Simultaneously, the output voltage of the target circuit decreases, shutting off the second bias current Ibias2, so that the second bias current Ibias2 no longer participates in the current comparison. At this time, the reference current is a mirror copy of the first bias current Ibias1, denoted as I2. Compared with I1, using the reference current I2 as the current limiting value, the current limiting value is reduced, realizing foldback current limiting protection.

[0024] Furthermore, in response to the problem that an abnormal increase in the output current of a high-current LDO in the prior art may trigger the current limiting protection mechanism abnormally, this invention sets up a clamping unit 3 to form a clamping voltage and raises the control terminal voltage of the current limiting control unit 2, so that the current limiting protection can only be triggered normally when the operating point of the power transistor gate changes due to an increase in the load current.

[0025] This invention adds a function to prevent false triggering of current limiting protection, thus avoiding affecting the normal operation of high-current target circuits, and achieves secondary foldback current limiting, which has the characteristics of high reliability.

[0026] In the current limiting protection circuit of the present invention, the sampling current is generated by the current sampling unit 4, and the current sampling unit 4 includes: The fourth PMOS transistor PM4 has its gate connected to the gate of the power transistor, its drain connected to the drain of the power transistor, and its source used to generate the sampling current.

[0027] Specifically, in this embodiment, the fourth PMOS transistor PM4 serves as a sampling transistor to detect the output current supplied by the drain of the power transistor. The port connection method of the sampling transistor is consistent with that of the power transistor to ensure accurate sampling of the load current of the target circuit.

[0028] In the current limiting protection circuit of the present invention, the first bias current Ibias1 is provided by a first current branch, which includes: A first current source, one end of which is connected to the input terminal of the target circuit, and the other end of which is used to generate a first bias current Ibias1. The second PMOS transistor has its source connected to the first bias current Ibias1 and its gate connected to the first reference voltage V. B1 The drain of the second PMOS transistor is used to output the first bias current Ibias1.

[0029] In the current limiting protection circuit of the present invention, the second bias current Ibias2 is provided by a second current branch, which includes: The second current source has one end connected to the input terminal of the target circuit, and the other end is used to generate the second bias current Ibias2. The first NMOS transistor NM1 has its drain connected to the second bias current Ibias2, and its gate connected to the second reference voltage V. B2 The source of the first NMOS transistor NM1 is used to output the second bias current Ibias2.

[0030] In this embodiment, the first bias current Ibias1 and the second bias current Ibias2 are bias currents provided internally by the target circuit; the first reference voltage V B1 Second reference voltage V B2 This is a voltage divider for the internal reference voltage of the target circuit.

[0031] The current limiting protection circuit of the present invention further includes: The gate of the third PMOS transistor PM3 is connected to the output voltage V of the target circuit through the third resistor R3. OUTThe source of the third PMOS transistor PM3 is connected to the first bias current Ibias1, and the drain of the third PMOS transistor PM3 is connected to the ground terminal.

[0032] Specifically, in this embodiment, the first bias current Ibias1 is controlled by the third PMOS transistor PM3 to determine whether it participates in the current comparison. When the output voltage V of the target circuit... OUT When the current limit is reduced, the third PMOS transistor PM3 is turned on, and the first bias current Ibias1 no longer participates in the current comparison, thus reducing the current limit value; when the output voltage V OUT When the current increases, the third PMOS transistor PM3 is turned off, and the first bias current Ibias1 continues to participate in the current comparison, causing the current limit value to rise.

[0033] In the current-limiting protection circuit of the present invention, the reference current is generated by a mirror replication unit, which includes: The second NMOS transistor NM2 has its gate connected to the second bias current Ibias2 and its drain connected to the output terminal of the first current branch. The third NMOS transistor NM3 has its gate connected to the second bias current Ibias2, its drain connected to the source of the second NMOS transistor NM2, and its source connected to the ground terminal. The fourth NMOS transistor NM4 and the fifth NMOS transistor NM5 are connected to the second bias current Ibias2, respectively. The source of the fourth NMOS transistor NM4 and the source of the fifth NMOS transistor NM5 are connected to the ground terminal, respectively. The drain of the fourth NMOS transistor NM4 is used to provide the first reference current, and the drain of the fifth NMOS transistor NM5 is used to provide the second reference current.

[0034] Specifically, the first bias current Ibias1 and the second bias current Ibias2 are replicated by a current mirror composed of the first NMOS transistor NM1, the second NMOS transistor NM2, the third NMOS transistor NM3, the fourth NMOS transistor NM4 and the fifth NMOS transistor NM5, and then used as the reference current of the current comparison unit 1. The first bias current Ibias1 is controlled by the third PMOS transistor PM3 to determine whether it participates in the current comparison.

[0035] The current limiting protection circuit of the present invention includes a current comparison unit 1 comprising: a fifth PMOS transistor PM5, a sixth PMOS transistor PM6, a seventh PMOS transistor PM7, an eighth PMOS transistor PM8, a sixth NMOS transistor NM6, a seventh NMOS transistor NM7, a first resistor R1, and a second resistor R2; the gates of the fifth PMOS transistor PM5, the sixth PMOS transistor PM6, the seventh PMOS transistor PM7, and the eighth PMOS transistor PM8 are connected together; the source of the fifth PMOS transistor PM5 is connected to the sampling current and the input terminal of the target circuit through the first resistor R1; and the drain of the fifth PMOS transistor PM5 is connected to the source of the sixth PMOS transistor PM6. The drain and gate of the sixth PMOS transistor PM6 are shorted and connected to the drain of the seventh NMOS transistor NM7. The gate of the seventh NMOS transistor NM7 is connected to the bias voltage Vbias. The source of the seventh NMOS transistor NM7 is connected to the first reference current. The source of the seventh PMOS transistor PM7 is connected to the input terminal of the target circuit through the second resistor R2. The drain of the seventh PMOS transistor PM7 is connected to the source of the eighth PMOS transistor PM8. The drain of the eighth PMOS transistor PM8 is connected to the drain of the sixth NMOS transistor NM6. The gate of the sixth NMOS transistor NM6 is connected to the bias voltage Vbias. The source of the sixth NMOS transistor NM6 is connected to the second reference current.

[0036] Specifically, the sampling current of the fourth PMOS transistor PM4 is compared with the reference current by a current comparator composed of the fifth PMOS transistor PM5, the sixth PMOS transistor PM6, the seventh PMOS transistor PM7, and the eighth PMOS transistor PM8 to obtain a current comparison signal.

[0037] The current limiting protection circuit of the present invention includes a current limiting control unit 2 comprising: The eighth NMOS transistor, NM8, has its gate connected to the current comparison signal, its drain connected to the input terminal of the target circuit, and its source used to generate a current limiting control signal.

[0038] Specifically, in this embodiment, the current comparison signal generates a current-limiting protection control signal OCP_OUT through the eighth NMOS transistor NM8, controlling the target circuit (such as the LDO main operational amplifier) ​​to achieve the current-limiting protection function. After the current-limiting protection is activated, the output voltage V... OUT As the current limit continues to decrease, the third PMOS transistor PM3 turns on, causing the first bias current Ibias1 to no longer participate in the current comparison. This triggers the foldback function, further reducing the current limit value and achieving foldback-type current limiting.

[0039] The current limiting protection circuit of the present invention includes clamping unit 3, which comprises: Transistor Q1, the base of transistor Q1 is connected to the current limiting control signal OCP_OUT, and the collector of transistor Q1 is connected to the input terminal of the current limiting control unit 2; The first PMOS transistor PM1 has its gate and drain connected to the control terminal of the current limiting control unit, and its source connected to the emitter of the transistor.

[0040] Specifically, in this embodiment, the clamping unit 3 is equipped with a transistor Q1 and a first PMOS transistor PM1 connected in the form of a diode to form a clamping voltage, which raises the source voltage of the eighth NMOS transistor NM8 output by the current comparison unit 1, so that the current limiting protection can be triggered normally only when the operating point of the power transistor gate changes due to the increase of the load current.

[0041] In the preferred embodiment described above, the current limiting protection circuit is as follows: Figure 1 As shown. Figure 1 In the diagram, IN is the LDO input pad, GND is the power ground, Ibias1 and Ibias2 are the bias currents provided internally by the LDO, Vbias is the bias voltage provided internally by the LDO, and V... B1 and V B2 V is the voltage divider of the LDO's internal reference voltage. OUT V is the output voltage of the LDO. GPOW OCP_OUT is the gate voltage of the power transistor, and OCP_OUT is the current limiting control signal output by the current limiting protection circuit.

[0042] The fourth PMOS transistor, PM4, serves as the sampling transistor, with its port connection matching that of the power transistor to ensure accurate sampling of the output current provided by the power transistor. The first bias current Ibias1 and the second bias current Ibias2 are replicated by a current mirror composed of the first NMOS transistor NM1, the second NMOS transistor NM2, the third NMOS transistor NM3, the fourth NMOS transistor NM4, and the fifth NMOS transistor NM5, and then used as the reference current for the current comparator. The first bias current Ibias1 is controlled by the second PMOS transistor PM2 to determine whether it participates in the current comparison. The sampling current from the fourth PMOS transistor PM4 is compared with the reference current by a current comparator composed of the fifth PMOS transistor PM5, the sixth PMOS transistor PM6, the seventh PMOS transistor PM7, and the eighth PMOS transistor PM8. The comparison result between the sampling current and the reference current generates a current-limiting protection control signal OCP_OUT through the eighth NMOS transistor NM8. This signal controls the LDO main operational amplifier to implement the current-limiting protection function. After the current limiting protection is activated, as the output voltage VOUT continues to decrease, the second PMOS transistor PM2 turns on, causing the first bias current Ibias1 to no longer participate in the current comparison. This triggers the foldback function, further reducing the current limiting value and achieving foldback-type current limiting. The first NPN transistor Q1 and the first PMOS transistor PM1 can clamp the gate-source voltage of the eighth NMOS transistor NM8, ensuring that the current limiting protection is only triggered normally when the operating point of the power transistor changes due to an increase in load current. This prevents the high-current LDO from causing an abnormal increase in output current and abnormally triggering the current limiting protection during circuit startup or transient current changes in the downstream load.

[0043] This invention provides a low dropout linear regulator, comprising: The main operational amplifier circuit is a multi-stage operational amplifier. The current limiting protection module includes the current limiting protection circuit described above, to generate a current limiting control signal to the input of the second-stage operational amplifier.

[0044] Specifically, the target circuit containing the power transistor is preferably a low-dropout linear regulator (LDO). Applying the highly reliable current-limiting protection circuit of this invention to the LDO can effectively ensure the safe and stable operation of the LDO with high current and fast transient response.

[0045] Main operational amplifier circuit such as Figure 2 As shown, Figure 2 In this diagram, Vb1, Vb2, Vb3, Vb4, and Vb5 are the internal bias voltages of the LDO, VREF is the reference voltage generated internally by the LDO, VFB is the output feedback voltage, OUT is the LDO output PAD, IN is the LDO input PAD, and GND is the power ground.

[0046] The main operational amplifier circuit is a multi-stage operational amplifier, including a main loop and an auxiliary loop. The main loop drives the LDO power transistor, while the auxiliary loop primarily improves the transient response performance of the LDO. The current-limiting protection control signal OCP_OUT controls the input of the second-stage operational amplifier. After triggering the current-limiting protection, the current-limiting protection circuit replaces the first-stage folded amplifier and participates in the main operational amplifier circuit's control of the power transistor's output state.

[0047] like Figure 2 As shown, the main operational amplifier circuit includes the ninth to eighteenth PMOS transistors, the ninth to eighteenth NMOS transistors, the fourth to seventh resistors, the first feedback resistor RF1 and the second feedback resistor RF2, the first capacitor C1 and the second capacitor C2.

[0048] The first stage of the main operational amplifier is a folded amplification stage. The gates of the ninth PMOS transistor PM9, the twelfth PMOS transistor PM12, and the thirteenth PMOS transistor PM13 are all connected to the bias voltage Vb1, and their sources are all connected to the LDO input pad IN. The gate of the tenth PMOS transistor PM10 is connected to the output feedback voltage VFB, and its source is connected to the drain of the ninth PMOS transistor PM9 and the drain of the eleventh NMOS transistor NM11. The drain is connected to the source of the ninth NMOS transistor NM9 and one end of the sixth resistor R6. The gate of the eleventh PMOS transistor PM11 is connected to the reference voltage VREF, and its source is connected to the drain of the ninth PMOS transistor PM9. The drain is connected to the source of the tenth NMOS transistor NM10. The gate of the ninth NMOS transistor NM9 is connected to the second bias voltage Vb2, and its drain is connected to the twelfth PMOS transistor PM10. The drain and source of transistor PM12 are connected to one end of the sixth resistor R6. The gate of the tenth NMOS transistor NM10 is connected to the second bias voltage Vb2, and its drain is connected to the drain of the thirteenth PMOS transistor PM13. Its sources are connected to one end of the seventh resistor R7 and one end of the fourth resistor R4, respectively. The other end of the fourth resistor R4 is connected to the LDO output pad OUT through the first capacitor C1. The gates of the eleventh NMOS transistor NM11 and the twelfth NMOS transistor NM12 are connected to the drain of the twelfth PMOS transistor PM12. The sources of the eleventh NMOS transistor NM11 and the twelfth NMOS transistor NM12 are both connected to GND. The drain of the eleventh NMOS transistor NM11 is connected to the other end of the sixth resistor R6, and the drain of the twelfth NMOS transistor NM12 is connected to the other end of the seventh resistor R7. The output of the first stage of the main operational amplifier is taken from the connection point between the drain of the thirteenth PMOS transistor PM13 and the drain of the tenth NMOS transistor NM10, serving as the input of the second stage operational amplifier.

[0049] The second stage of the main operational amplifier is a gain amplification stage. The gate of the fifteenth PMOS transistor PM15 is connected to the output of the first stage, and its source is connected to the drain of the fourteenth PMOS transistor PM14. The drain is connected to the LDO output pad OUT. The gate of the fourteenth PMOS transistor PM14 is connected to the third bias voltage Vb3, and its source is connected to IN. One end of the fifth resistor R5 is connected to the gate of the fifteenth PMOS transistor PM15, and the other end is connected to IN through the second capacitor C2. The gate and drain of the thirteenth NMOS transistor NM13 are shorted and connected to the drain of the fifteenth PMOS transistor PM15. The source of the thirteenth NMOS transistor NM13 is connected to GND. The output of the second stage of the main operational amplifier is taken from the drain of the fifteenth PMOS transistor PM15, serving as the input to the third stage of the main loop and the third stage of the auxiliary loop.

[0050] The current limiting protection signal OCP_OUT output by the current limiting protection circuit of the present invention is connected to the gate of the fifteenth PMOS transistor PM15, and controls its gate potential when current limiting is triggered.

[0051] The third stage of the main loop is the output driver stage. The gate of the fourteenth NMOS transistor NM14 is connected to the output of the second stage of the main operational amplifier. The drain of the fourteenth NMOS transistor NM14 is connected to the source of the fifteenth NMOS transistor NM15, and the source of the fourteenth NMOS transistor NM14 is connected to GND. The gate of the fifteenth NMOS transistor NM15 is connected to the fifth bias voltage Vb5, and its drain is connected to the source of the sixteenth NMOS transistor NM16. The gate of the sixteenth NMOS transistor NM16 is connected to the fourth bias voltage Vb4, and its source is connected to IN. The output of the third stage of the main operational amplifier is taken from the junction of the source of the sixteenth NMOS transistor NM16 and the drain of the fifteenth NMOS transistor NM15, serving as the gate voltage of the power transistor.

[0052] The sixteenth PMOS transistor, PM16, is used as a power transistor, and its gate is connected to the power transistor gate voltage V. GPOW The source is connected to IN, and the drain is connected to OUT.

[0053] The third stage of the auxiliary loop is a transient response enhancement stage. The gate of the seventeenth NMOS transistor NM17 is connected to the output of the second stage of the main operational amplifier. The drain of the seventeenth NMOS transistor NM17 is connected to the source of the eighteenth NMOS transistor NM18. The source of the seventeenth NMOS transistor NM17 is connected to GND. The gate of the eighteenth NMOS transistor NM18 is connected to the fifth bias voltage Vb5, and its drain is connected to the drain of the seventeenth PMOS transistor PM17. The gate and drain of the seventeenth PMOS transistor PM17 are shorted, and its source is connected to IN.

[0054] The gate of the eighteenth PMOS transistor PM18 is connected to the drain of the eighteenth NMOS transistor NM18, the source is connected to IN, and the drain is connected to OUT; the first feedback resistor RF1 and the second feedback resistor RF2 are connected in series between OUT and GND, and the feedback voltage VFB is generated from the voltage divider node between the first feedback resistor RF1 and the second feedback resistor RF2.

[0055] The above are merely preferred embodiments of the present invention and are not intended to limit the implementation methods and protection scope of the present invention. Those skilled in the art should recognize that any equivalent substitutions and obvious changes made using the content of this specification and illustrations should be included within the protection scope of the present invention.

Claims

1. A current-limiting protection circuit, characterized in that, Applied to target circuits containing power transistors, including: A current comparison unit is used to compare the sampled current sampled from the power transistor with a reference current and output a current comparison signal; wherein, the reference current is a mirror copy of the sum of a first bias current and a second bias current controlled by the output voltage gating of the target circuit. A current limiting control unit is connected to the current comparison unit and generates a current limiting control signal under the control of the current comparison signal. The clamping unit is controllably connected between the input terminal and the control terminal of the current limiting control unit under the control of the current limiting control signal, so as to clamp the voltage at the input terminal and the control terminal of the current limiting control unit.

2. The current limiting protection circuit according to claim 1, characterized in that, The clamping unit includes: A transistor, wherein the base of the transistor is connected to the current limiting control signal, and the collector of the transistor is connected to the input terminal of the current limiting control unit; The first PMOS transistor has its gate and drain connected to the control terminal of the current limiting control unit, and its source connected to the emitter of the transistor.

3. The current limiting protection circuit according to claim 1, characterized in that, The first bias current is provided by a first current branch, which includes: A first current source, one end of which is connected to the input terminal of the target circuit, and the other end of which is used to generate the first bias current; The second PMOS transistor has its source connected to the first bias current, its gate connected to the first reference voltage, and its drain used to output the first bias current.

4. The current limiting protection circuit according to claim 1, characterized in that, Also includes: The third PMOS transistor has its gate connected to the output voltage of the target circuit via a third resistor, its source connected to the first bias current, and its drain connected to ground.

5. The current limiting protection circuit according to claim 1, characterized in that, The second bias current is provided by a second current branch, which includes: A second current source, one end of which is connected to the input terminal of the target circuit, and the other end of which is used to generate the second bias current; The first NMOS transistor has its drain connected to the second bias current, its gate connected to the second reference voltage, and its source used to output the second bias current.

6. The current limiting protection circuit according to claim 1, characterized in that, The first bias current is provided by a first current branch, the second bias current is provided by a second current branch, and the reference current is generated by a mirror replication unit, which includes: The second NMOS transistor has its gate connected to the second bias current and its drain connected to the output terminal of the first current branch. The third NMOS transistor has its gate connected to the second bias current, its drain connected to the source of the second NMOS transistor, and its source connected to ground. A fourth NMOS transistor and a fifth NMOS transistor are provided, with the gates of the fourth and fifth NMOS transistors respectively connected to the second bias current, the sources of the fourth and fifth NMOS transistors respectively connected to the ground terminal, the drain of the fourth NMOS transistor being used to provide a first reference current, and the drain of the fifth NMOS transistor being used to provide a second reference current.

7. The current limiting protection circuit according to claim 1, characterized in that, The sampling current is generated by a current sampling unit, which includes: The fourth PMOS transistor has its gate connected to the gate of the power transistor, its drain connected to the drain of the power transistor, and its source used to generate the sampling current.

8. The current limiting protection circuit according to claim 1, characterized in that, The current comparison unit includes: a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, a first resistor, and a second resistor. The gates of the fifth PMOS transistor, the sixth PMOS transistor, the seventh PMOS transistor, and the eighth PMOS transistor are connected together. The source of the fifth PMOS transistor is connected to the sampling current and is connected to the input terminal of the target circuit through the first resistor. The drain of the fifth PMOS transistor is connected to the source of the sixth PMOS transistor. The drain and gate of the sixth PMOS transistor are shorted and connected to the drain of the seventh NMOS transistor. The gate of the seventh NMOS transistor is connected to a bias voltage. The source of the seventh NMOS transistor is connected to a first reference current. The source of the seventh PMOS transistor is connected to the input terminal of the target circuit through the second resistor. The drain of the seventh PMOS transistor is connected to the source of the eighth PMOS transistor. The drain of the eighth PMOS transistor is connected to the drain of the sixth NMOS transistor. The gate of the sixth NMOS transistor is connected to the bias voltage. The source of the sixth NMOS transistor is connected to a second reference current.

9. The current limiting protection circuit according to claim 1, characterized in that, The current limiting control unit includes: The eighth NMOS transistor has its gate connected to the current comparison signal, its drain connected to the input terminal of the target circuit, and its source used to generate the current limiting control signal.

10. A low-dropout linear regulator, characterized in that, include: The main operational amplifier circuit is a multi-stage operational amplifier. A current limiting protection module, comprising the current limiting protection circuit as described in any one of claims 1-9, for generating a current limiting control signal to the input terminal of the second-stage operational amplifier.

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