Programmable reset circuit and control method

Abstract

The application provides a programmable reset circuit and a control method, wherein the circuit comprises: a start timing module, provided with a first timer, used for delaying the start of a running monitoring module, and a replaceable first capacitor arranged outside the first timer, used for programming the start timing; a running monitoring module, connected with the start timing module, provided with a second timer, used for timing monitoring the normal running stage of an operating system, and triggering a reset signal in the case of monitoring that the processor module runs abnormally, and the timing programming time of the second timer is less than the timing programming time of the first timer; and a power supply control module, provided with a load switch, connected with the second timer, used for receiving the reset signal and controlling the turn-off and turn-on of the power supply in response to the reset signal. The above scheme solves the problem that different stages of timing monitoring cannot be differentially controlled, and achieves the technical effect that different stages of timing monitoring are adaptively controlled.

Description

Technical Field

[0001] This application belongs to the field of electronic circuit technology, and in particular relates to a programmable reset circuit and control method. Background Technology

[0002] In operating system-based industrial electronic equipment, the reset circuit is a critical hardware module. Its performance directly determines the success rate of system power-on startup and the stability of long-term operation. In existing implementations, a watchdog timer circuit is typically used as the system monitoring and fault recovery mechanism. When this circuit detects an abnormal processor startup or operational failure, it triggers a reset signal to force the processor to perform a hardware reset, allowing the system to return to normal operation.

[0003] However, a single watchdog reset circuit has the problem of poor flexibility in practical applications and cannot meet the differentiated needs of timing monitoring at different stages.

[0004] There is currently no effective solution to the above problems. Summary of the Invention

[0005] The purpose of this application is to provide a programmable reset circuit and control method that can meet the adaptive control requirements for timing monitoring at different stages.

[0006] This application provides a programmable reset circuit and control method implemented as follows: A programmable reset circuit includes: a start-up timing module, a running monitoring module, a power supply control module, and a processor module, wherein: The startup timing module is equipped with a first timer to delay the startup of the monitoring module, and a replaceable first capacitor is deployed outside the first timer. The operation monitoring module is connected to the startup timing module and is equipped with a second timer for periodically monitoring the normal operation phase of the operating system. When an abnormal operation of the processor module is detected, a reset signal is triggered. A replaceable second capacitor is deployed outside the second timer. The timing programming time of the second timer is less than the timing programming time of the first timer. The power supply control module is equipped with a load switch connected to the second timer, which is used to receive the reset signal and control the power supply to turn off and on in response to the reset signal. The startup timing module is a purely delayed timer independent of the operation monitoring module, and the operation monitoring function of the startup timing module is disabled during the delay period.

[0007] In one embodiment, after the target device is powered on, the startup timing module enters the working state and provides a power-on startup signal to the operation monitoring module. The power-on startup signal includes: an initial high-level signal, a low-level signal of a first set duration, and a rising edge signal. During the initial high-level signal, each device component of the target device starts working synchronously. During the low-level signal of the first set duration, the startup timing module controls the operation monitoring module to stop working. After the rising edge signal is activated, the operation monitoring module starts working.

[0008] In one embodiment, a replaceable third capacitor is deployed externally to the load switch, the third capacitor being used to configure the voltage rise time.

[0009] In one embodiment, the capacitance value of the third capacitor is determined by the power-on curve of the device and the voltage rise time.

[0010] In one implementation, the timing programming time of the first timer is greater than or equal to 30 seconds, and the timing programming time of the second timer is less than or equal to 10 seconds.

[0011] In one embodiment, the second timer is connected to the load switch via a voltage monitor, which is used to monitor the processor module and peripheral chip devices for undervoltage. When an undervoltage condition is detected in the processor module or peripheral chip device, a reset signal is triggered.

[0012] In one embodiment, it further includes: a logic gate circuit, one end of which is connected to the processor module and the other end of which is connected to the second timer.

[0013] A method for control via the above-described programmable reset circuit includes: After the target device is powered on, the start timing module sends a power-on start signal to the operation monitoring module. The power-on start signal includes: an initial high-level signal, a low-level signal of a first set duration, and a rising edge signal. During the initial high-level signal period, all components of the target device start working synchronously. During the first set duration of the low-level signal period, the timing module is activated to control the operation monitoring module to stop working. After the rising edge signal is activated, the control operation monitoring module starts working.

[0014] In one implementation, after the rising edge signal initiates the operation, the control and monitoring module begins to work, including: During the normal operation of the operating system, the processor module periodically outputs alternating level signals to the logic gates; The logic gate flips the level alternation signal and sends the flipped signal to the dog feed signal input terminal of the second timer of the operation monitoring module to control the running status of the second timer; If the operation monitoring module detects an abnormal operation of the processor module, it triggers a reset signal and sends the reset signal to the load switch to control the power supply to turn off and on.

[0015] In one implementation, the duration of the low-level signal of the first set duration is greater than or equal to the maximum duration required for the operating system to power on and start, and the startup timing module is triggered only once in a power supply cycle.

[0016] This application provides a programmable reset circuit and control method. The programmable reset circuit includes: a startup timing module with a first timer for delaying the startup of a running monitoring module, and a replaceable first capacitor deployed outside the first timer; a running monitoring module connected to the startup timing module, with a second timer for periodically monitoring the normal operation phase of the operating system, triggering a reset signal when an abnormality is detected in the processor module, and a replaceable second capacitor deployed outside the second timer, wherein the timing programming time of the second timer is shorter than the timing programming time of the first timer; and a power supply control module with a load switch connected to the second timer for receiving the reset signal and controlling the power supply to turn on and off in response to the reset signal. That is, by setting two timers (the first and second timers) for segmented control, the technical problem of existing reset circuits being unable to perform differentiated control of timing monitoring at different stages is solved, achieving the technical effect of adaptive control of timing monitoring at different stages. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a structural block diagram of one embodiment of the programmable reset circuit provided in this application; Figure 2 This is a flowchart of one embodiment of the method for control via the above-described programmable reset circuit provided in this application; Figure 3 This is a schematic diagram of the structure of a programmable reset circuit provided in this application; Figure 4 This is a schematic diagram of the timer configuration and reset circuit provided in this application; Figure 5 This is a structural diagram of the system reset and operation phases provided in this application; Figure 6 This is a schematic diagram of the hardware and software collaborative hierarchical control method provided in this application. Detailed Implementation

[0019] To enable those skilled in the art to better understand the technical solutions in this application, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of this application.

[0020] It should also be noted that in the embodiments of this specification, certain software, components, models and other existing solutions in the industry may be mentioned. These should be regarded as exemplary and are only intended to illustrate the feasibility of implementing the technical solution of this application. However, it does not mean that the applicant has used or necessarily used the solution.

[0021] To address the problems existing in practical applications of existing single watchdog reset circuits, this example provides a programmable reset circuit, such as... Figure 1 As shown, it may include: a start-up timing module 101, a running monitoring module 102, a power supply control module 103, and a processor module 104, wherein: The start timing module 101 is equipped with a first timer 1011, which is used to delay the start of the monitoring module. A replaceable first capacitor 10111 is provided outside the first timer. The operation monitoring module 102 is connected to the startup timing module 101 and is equipped with a second timer 1021 for periodic monitoring of the normal operation phase of the operating system. When the processor module 104 is detected to be operating abnormally, a reset signal is triggered. A replaceable second capacitor 10211 is provided outside the second timer 1021. The timing programming time of the second timer 1021 is less than the timing programming time of the first timer 1011. The power supply control module 103 is equipped with a load switch 1031, which is connected to the second timer 1021. It is used to receive the reset signal and control the power supply to turn off and on in response to the reset signal. The startup timing module is a purely delayed timer independent of the operation monitoring module, and the operation monitoring function of the startup timing module is disabled during the delay period.

[0022] In other words, the startup timing module is a pure delay timer independent of the operation monitoring module. During the delay period, it completely disables the operation monitoring function, thus effectively resolving the compatibility issue between the short operation monitoring time and the long operating system startup time. The aforementioned startup timing module, operation monitoring module, and power supply control module constitute a combination of a reset circuit and a power soft-start circuit. By sequentially combining power-on startup, operation monitoring, and power control, an integrated design of the reset and soft-start circuits can be achieved, improving the system startup success rate and operational reliability.

[0023] Specifically, after the target device (i.e., the device where the aforementioned programmable reset circuit is located) is powered on, the start-up timing module 101 enters the working state and provides a power-on start signal to the operation monitoring module 102. The power-on start signal may include: an initial high-level signal, a low-level signal of a first set duration, and a rising edge signal. During the initial high-level signal period, each device component of the target device starts working synchronously. During the low-level signal of the first set duration, the start-up timing module 101 controls the operation monitoring module 102 to stop working. After the rising edge signal starts, the operation monitoring module 102 starts working.

[0024] To reduce the impact of surge current and eliminate secondary startup phenomena, a third capacitor is installed externally to the load switch. This third capacitor is replaceable, and its capacitance value can be configured based on the matching results of parameters such as the device's power-on curve and voltage rise time. This allows for the configuration of the soft-start time and a smooth rise trend. In other words, a replaceable third capacitor can be installed externally to the load switch to configure the voltage rise time; the capacitance value of the third capacitor can be determined using the device's power-on curve and voltage rise time.

[0025] Considering the relatively long programming time of the first timer, the timing period can be set to no less than 30 seconds to meet the requirement of a long operating system power-on time. The shorter programming time of the second timer is generally no more than 10 seconds, with a timing accuracy of up to 2.5%, to meet the requirement of rapid fault recovery during operating system operation. That is, the programming time of the first timer is greater than or equal to 30 seconds, and the programming time of the second timer is less than or equal to 10 seconds.

[0026] In implementation, the second timer can be directly connected to the load switch, or it can be connected to the load switch through a voltage monitor. The voltage monitor is used to monitor the undervoltage of the processor module and peripheral chip devices. When an undervoltage condition is detected in the processor module or peripheral chip device, a reset signal is triggered to achieve consistent restoration of the system-level state.

[0027] In one embodiment, the programmable reset circuit can also be a logic gate circuit, with one end connected to the processor module and the other end connected to the second timer. The logic gate circuit is used to process the feedback signal, and performs conversion and toggling of the feedback signal.

[0028] Figure 2 This is a flowchart illustrating one embodiment of the method for control via the aforementioned programmable reset circuit provided in this application. While this application provides method operation steps or apparatus structures as shown in the following embodiments or accompanying drawings, more or fewer operation steps or module units may be included in the method or apparatus based on conventional or non-inventive effort. In steps or structures where there is no logically necessary causal relationship, the execution order of these steps or the module structure of the apparatus is not limited to the execution order or module structure described in the embodiments and accompanying drawings of this application. When the method or module structure is applied in actual devices or terminal products, it can be executed sequentially or in parallel according to the method or module structure shown in the embodiments or accompanying drawings (e.g., in a parallel processor or multi-threaded processing environment, or even a distributed processing environment).

[0029] Specifically, such as Figure 2 As shown, the method of control via the above-described programmable reset circuit may include the following steps: Step 201: After the target device is powered on, the start timing module sends a power-on start signal to the operation monitoring module. The power-on start signal includes: an initial high-level signal, a low-level signal of a first set duration, and a rising edge signal. Step 202: During the initial high-level signal period, all components of the target device start working synchronously. During the first set duration of the low-level signal period, the timing module is activated to control the operation monitoring module to stop working. Step 203: After the rising edge signal is activated, the control operation monitoring module starts working.

[0030] Specifically, after the rising edge signal initiates the operation, the control and monitoring module begins to work, which may include: S1: During the normal operation of the operating system, the processor module periodically outputs alternating level signals to the logic gates; S2: The logic gate flips the level alternation signal and sends the flipped signal to the dog feed signal input terminal of the second timer of the operation monitoring module to control the running state of the second timer; S3: When the operation monitoring module detects an abnormal operation of the processor module, a reset signal is triggered and sent to the load switch to control the power supply to turn off and on.

[0031] Specifically, the duration of the low-level signal with the first set duration is greater than or equal to the maximum power-on startup duration required by the operating system, and the startup timing module is triggered only once per power supply cycle. That is, the startup timing module does not depend on the processor module or the operation monitoring module for operation, and is a key component in realizing system power-on startup monitoring.

[0032] The above method will be described below with reference to a specific embodiment. However, it should be noted that this specific embodiment is only for better illustration of this application and does not constitute an improper limitation of this application.

[0033] To address the issue that existing single watchdog reset circuits cannot simultaneously handle the timing differences between the power-on startup and stable operation phases of the operating system, this example presents a segmented programmable reset circuit. This circuit adds a timer to the existing watchdog circuit. The added timer meets the timing requirements during the operating system startup phase, while the watchdog timer monitors the operating system's normal operation, thereby improving the startup reliability and operational stability of the electronic system under complex conditions.

[0034] In this example, a programmable reset circuit and control method are provided. The programmable reset circuit includes: a start timing module, a running monitoring module, a power supply control module, and a processor module. The start timing module is connected to the running monitoring module, the running monitoring module is connected to both the power supply control module and the processor module, and the power supply control module is connected to both the running monitoring module and the processor module.

[0035] The aforementioned startup timing module can be a timer and its associated circuitry with power gating functionality. It serves as a timer during the power-on startup phase, setting the maximum startup duration for the operating system to delay the startup time of the monitoring module and provide sufficient time for the operating system to boot normally. The programmable timing interval of the startup timing module can reach more than one minute, fully covering the maximum startup duration requirement of the operating system. Furthermore, it triggers only once per power supply cycle, independent of the processor module and the monitoring module, making it a crucial component for implementing system power-on startup monitoring.

[0036] The aforementioned operation monitoring module is selected from either a watchdog timer with integrated voltage monitoring or a watchdog timer without integrated voltage monitoring. It also includes logic gate circuits. The watchdog timer is a timer for the stable operation phase, used to monitor the normal operation of the processor module. When the processor module malfunctions, a reset circuit is activated, and the control system restarts. The watchdog timer can be a programmable watchdog timer with multiple enable configurations. Different operating states of the watchdog can be achieved through enable control. This method offers high timing accuracy and can quickly identify abnormal states during system operation, restoring the system to normal operation by controlling the reset circuit.

[0037] The aforementioned power supply control module can be a load switch, or a combination of a load switch and a power management chip. This module controls the power supply to the processor module and its peripherals. It can be a programmable rise time power switch, providing unified control over the power supply to the processor module and peripherals, thus enabling comprehensive system startup and reset to ensure the synchronization of critical system components. Furthermore, the voltage rise time can be configured to meet system soft-start requirements and address system startup anomalies caused by excessive power-on inrush current.

[0038] The processor module selection mentioned above can be one or more of ARM (Advanced RISC Machine), x86, and FPGA.

[0039] In implementation, when the watchdog timer does not integrate a voltage monitor, the monitoring module includes a watchdog timer and a voltage monitor. The watchdog timer is connected to both the first timer and the voltage monitor, and the voltage monitor is connected to a load switch. The load switch can be connected to the power management chip, which in turn can be connected to a processor. The processor can be connected to logic gates, which can be connected to a second timer.

[0040] Furthermore, this example also provides a hierarchical control method combining hardware and software: on one hand, the processor software executes the method, prioritizing software reset to resolve faults based on fault type; on the other hand, the hardware watchdog reset circuit described above serves as a backup for software reset failures. Specifically, this method may include: periodically outputting alternating level signals from the processor; high and low level signals are sent to the input of a logic gate circuit, the output of which is connected to the input of a second timer. The signal is then inverted and sent to the "feed" signal input of the second timer to control its operating state. The second timer is connected to a voltage monitor or a load switch, which controls the processor. The watchdog timer is directly connected to the load switch, or connected via a voltage monitor, which controls the power management chip. By controlling power on and off, a unified reset of the processor and peripherals is achieved. The load switch can be programmably configured with the rise time of the power supply voltage to reduce inrush current, resolving startup failures caused by excessive inrush current and ensuring reliable system startup.

[0041] In the example above, by introducing a segmented programmable timer circuit, segmented programmable timing configuration for system power-on startup and operation monitoring is achieved, meeting the diverse timing requirements of system monitoring. Hierarchical hardware and software control allows for tiered reset handling of various fault types. Controlling the system power supply via a load switch enables synchronous reset of the system processor and critical peripheral components, ensuring the coordinated operation of system components. Using a load switch to control the power rise time enables a soft-start circuit; the load switch's switching action is reliable, its structure is simple, its cost is low, and its reliability is high. Specifically, the segmented programmable configuration of the timing circuit solves the problem of insufficient flexibility in a single watchdog timer, meeting the diverse needs of long power-on startup times and short, high-precision stable operation monitoring times. Integrating the reset circuit and soft-start circuit into a unified power supply control solution provides higher power-on reliability. Hardware and software reset control schemes are provided for various fault types, comprehensively covering abnormal situations during system startup and operation, and resolving system state asynchrony issues caused by single processor resets or unreset peripherals, achieving consistent system-level state recovery. Furthermore, the processor is highly adaptable, supporting various processor types such as ARM (Advanced RISC Machine), x86, and FPGA.

[0042] like Figure 3 The diagram shown is a schematic of a segmented programmable reset circuit provided in an embodiment of this application. It may include: a start-up timing module 1, a running monitoring module 2, a power supply control module 3, and a processor module 4. The processor module 4 is connected to the running monitoring module 2 and the power supply control module 3, respectively. The running monitoring module 2 is connected to the start-up timing module 1.

[0043] The aforementioned startup timing module 1 is a first timer T1 with gating function, used to delay the operation of the monitoring module during the power-on startup phase, thereby providing sufficient startup time for the operating system. After the device is powered on, the startup timing module 1 starts working, providing a power-on startup signal to the operation monitoring module 2. This power-on startup signal may include: an initial high-level signal, a low-level signal of a first set duration, and a rising edge signal. During the initial high-level signal, all device components start working synchronously. During the low-level signal of the first set duration, the startup timing module 1 controls the operation monitoring module 2 to stop working. After the rising edge signal is triggered, the operation monitoring module 2 starts working. Furthermore, the first timer T1 is equipped with a capacitor C1 to realize the programming configuration of the timing time of the first timer T1.

[0044] like Figure 4 As shown, the aforementioned operation monitoring module 2 includes a second timer T2 and a logic gate circuit U4. The second timer T2 can be either a watchdog timer without integrated voltage regulator U1 or a watchdog timer with integrated voltage regulator U1. The watchdog timer is used for timed monitoring during the normal operation of the operating system to realize fault recovery from abnormal states during system operation. Furthermore, the second timer T2 is equipped with a capacitor C2 to realize the programming configuration of the timing of the second timer T2.

[0045] Furthermore, the first timer T1 has a longer programming time, generally not less than 30 seconds, to meet the requirement of a longer power-on time for the operating system. The second timer T2 has a shorter programming time, generally not more than 10 seconds, and a timing accuracy of up to 2.5%, to meet the requirement of rapid fault recovery during operating system operation.

[0046] The aforementioned power supply control module 3 selects either load switch U2 or a combination of load switch U2 and power management chip U3. It controls the power supply to turn on and off through load switch U2, thereby achieving a unified reset of processor U5 and its peripheral components. This solves the problem of asynchronous reset between the processor and peripheral components caused by a single processor reset. For processor U5 circuits that do not use power management chip U3 for power supply, load switch U2 directly controls the power supply. For processor U5 circuits that use power management chip U3, load switch U2 indirectly controls the power supply through the power management chip.

[0047] Furthermore, the load switch U2 of the aforementioned power supply control module 3 is equipped with capacitor C3, and the voltage rise time of the load switch U2 can be programmed. The capacitance value of C3 is configured based on the matching calculation results of parameters such as device power-on curve and voltage rise time. On the one hand, this reduces the impact of power-on surge current and eliminates the secondary startup phenomenon. On the other hand, it adapts to the different rise time requirements of different power management chips, thereby ensuring the normal startup of the system equipment.

[0048] The processor module 4 mentioned above can be any of ARM (Advanced RISC Machine), X86, or FPGA, and is used to implement normal system functions, software fault monitoring and handling, and hardware fault monitoring and handling.

[0049] like Figure 5 As shown, after the system is powered on, during the startup phase, the first timer T1 starts working and the operating system starts. The timing period of the first timer T1 needs to cover the normal startup time of the operating system. After the operating system starts normally, the second timer T2 starts running normally. The operating system needs to send periodic input signals to the second timer T2 at regular intervals. When the second timer T2 fails to receive input signals after the timing period, the second timer restarts the system through the load switch, and the entire system restarts and resumes normal operation.

[0050] like Figure 6 As shown, after the system enters operation, it employs hierarchical hardware and software control to handle various types of faults through tiered reset processes. The main system software is equipped with a watchdog timer to monitor the status of each process or thread in real time. When a single software process or thread malfunctions, software intervention is prioritized, offering high real-time performance and minimizing impact. If the system watchdog timer malfunctions, a hardware reset circuit serves as a backup safety measure, using a comprehensive tiered reset approach to enable the entire system to quickly identify abnormal states and restore normal operation.

[0051] The programmable reset circuit and control method provided in the example above, by introducing a segmented programmable configuration circuit, realizes the status monitoring of system power-on startup and operation to meet the needs of system monitoring timing differences. Through hierarchical hardware and software control, it solves the hierarchical reset handling of multiple types of faults, prioritizing software processing and using hardware reset as a backup. By controlling the system power supply through a load switch, it achieves synchronous reset of the system processor and critical peripheral components, ensuring the coordination of system component operation. Furthermore, the load switch is used to control the power rise time, realizing a soft-start circuit for the system and reducing the surge current impact during initial power-on. The entire reset circuit and control method effectively solves the problems encountered in existing technologies, such as flexible timing configuration, a single reset control strategy, and asynchronous fault reset, effectively improving the stability and reliability of system operation.

[0052] This application also provides a specific implementation of an electronic device capable of implementing all steps of the control method via a programmable reset circuit in the above embodiments. The electronic device specifically includes: a processor, a memory, a communication interface, and a bus; wherein the processor, memory, and communication interface communicate with each other via the bus; the processor is used to call a computer program in the memory, and when the processor executes the computer program, it implements all steps of the control method via a programmable reset circuit in the above embodiments. For example, when the processor executes the computer program, it implements the following steps: Step 1: After the target device is powered on, the start timing module sends a power-on start signal to the operation monitoring module. The power-on start signal includes: an initial high-level signal, a low-level signal of a first set duration, and a rising edge signal. Step 2: During the initial high-level signal period, all components of the target device start working synchronously. During the first set duration of the low-level signal period, the timing module is activated to control the operation monitoring module to stop working. Step 3: After the rising edge signal is activated, the control operation monitoring module starts working.

[0053] Embodiments of this application also provide a computer-readable storage medium capable of implementing all steps of the method controlled by a programmable reset circuit in the above embodiments. The computer-readable storage medium stores a computer program that, when executed by a processor, implements all steps of the method controlled by a programmable reset circuit in the above embodiments. For example, when the processor executes the computer program, it implements the following steps: Step 1: After the target device is powered on, the start timing module sends a power-on start signal to the operation monitoring module. The power-on start signal includes: an initial high-level signal, a low-level signal of a first set duration, and a rising edge signal. Step 2: During the initial high-level signal period, all components of the target device start working synchronously. During the first set duration of the low-level signal period, the timing module is activated to control the operation monitoring module to stop working. Step 3: After the rising edge signal is activated, the control operation monitoring module starts working.

[0054] As described above, the embodiments of this application, through the setting of a timer, can achieve segmented control of the power-on phase and normal operation state calculations, and can solve the hierarchical reset processing of multiple types of faults. By controlling the system power supply through a load switch, synchronous reset of the system processor and key peripheral components can be achieved, thereby ensuring the coordination of system components.

[0055] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to interchangeably. Each embodiment focuses on its differences from other embodiments. In particular, hardware + program embodiments are relatively simple in description because they are fundamentally similar to method embodiments; relevant parts can be referred to the descriptions in the method embodiments.

[0056] The foregoing has described specific embodiments of this specification. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recited in the claims may be performed in a different order than that shown in the embodiments and may still achieve the desired result. Furthermore, the processes depicted in the drawings do not necessarily require the specific or sequential order shown to achieve the desired result. In some embodiments, multitasking and parallel processing are possible or may be advantageous.

[0057] While this application provides the method operation steps as described in the embodiments or flowcharts, more or fewer operation steps may be included based on conventional or non-inventive labor. The order of steps listed in the embodiments is merely one possible execution order among many and does not represent the only execution order. In actual device or client product execution, the methods shown in the embodiments or drawings can be executed sequentially or in parallel (e.g., in a parallel processor or multi-threaded processing environment).

[0058] While this specification provides method operation steps as described in the embodiments or flowcharts, more or fewer operation steps may be included based on conventional or non-inventive means. The order of steps listed in the embodiments is merely one possible execution order among many and does not represent the only execution order. In actual device or end product execution, the methods shown in the embodiments or drawings may be executed sequentially or in parallel (e.g., in a parallel processor or multi-threaded processing environment, or even a distributed data processing environment). The terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, product, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, product, or apparatus. Without further limitations, the presence of other identical or equivalent elements in the process, method, product, or apparatus that includes said elements is not excluded.

[0059] For ease of description, the above devices are described in terms of function, divided into various modules. Of course, in implementing the embodiments of this specification, the functions of each module can be implemented in one or more software and / or hardware components, or a module that performs the same function can be implemented by a combination of multiple sub-modules or sub-units. The device embodiments described above are merely illustrative. For example, the division of units is only a logical functional division; in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces, or indirect coupling or communication connection between devices or units, and may be electrical, mechanical, or other forms.

[0060] Those skilled in the art will also know that, besides implementing the controller using purely computer-readable program code, the same functions can be achieved by logically programming the method steps, making the controller function as logic gates, switches, application-specific integrated circuits (ASICs), programmable logic controllers (PLCs), and embedded microcontrollers. Therefore, such a controller can be considered a hardware component, and the devices within it used to implement various functions can also be considered structures within that hardware component. Alternatively, the devices used to implement various functions can be considered as both software modules implementing the method and structures within a hardware component.

[0061] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0062] Those skilled in the art will understand that the embodiments of this specification can be provided as methods, systems, or computer program products. Therefore, the embodiments of this specification can take the form of entirely hardware embodiments, entirely software embodiments, or embodiments combining software and hardware aspects. Furthermore, the embodiments of this specification can take the form of computer program products implemented on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0063] The embodiments described in this specification can be described in the general context of computer-executable instructions, such as program modules, that are executed by a computer. Generally, program modules include routines, programs, objects, components, data structures, etc., that perform a specific task or implement a specific abstract data type. The embodiments of this specification can also be practiced in distributed computing environments where tasks are performed by remote processing devices connected via a communication network. In distributed computing environments, program modules can reside in local and remote computer storage media, including storage devices.

[0064] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, system embodiments are basically similar to method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions in the method embodiments. In the description of this specification, the terms "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the embodiments in this specification. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described can be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification and the features of different embodiments or examples.

[0065] The above description is merely an embodiment of the present specification and is not intended to limit the embodiments of the present specification. For those skilled in the art, various modifications and variations can be made to the embodiments of the present specification. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principle of the embodiments of the present specification should be included within the scope of the claims of the embodiments of the present specification.

Claims

1. A programmable reset circuit, characterized in that, include: The system comprises a startup timing module, a runtime monitoring module, a power supply control module, and a processor module, among which: The startup timing module is equipped with a first timer to delay the startup of the monitoring module. A replaceable first capacitor is deployed outside the first timer for programming and configuring the first timer to keep time. The operation monitoring module is connected to the startup timing module and is equipped with a second timer for periodically monitoring the normal operation phase of the operating system. When an abnormal operation of the processor module is detected, a reset signal is triggered. A replaceable second capacitor is deployed outside the second timer. The timing programming time of the second timer is less than the timing programming time of the first timer. The power supply control module is equipped with a load switch connected to the second timer, which is used to receive the reset signal and control the power supply to turn off and on in response to the reset signal. The startup timing module is a purely delayed timer independent of the operation monitoring module, and the operation monitoring function of the startup timing module is disabled during the delay period.

2. The programmable reset circuit according to claim 1, characterized in that, After the target device is powered on, the startup timing module enters the working state and provides a power-on startup signal to the operation monitoring module. The power-on startup signal includes an initial high-level signal, a low-level signal of a first set duration, and a rising edge signal. During the initial high-level signal, each component of the target device starts working synchronously. During the low-level signal of the first set duration, the startup timing module controls the operation monitoring module to stop working. After the rising edge signal starts, the operation monitoring module starts working.

3. The programmable reset circuit according to claim 1, characterized in that, The load switch is equipped with a replaceable third capacitor, which is used to configure the voltage rise time.

4. The programmable reset circuit according to claim 3, characterized in that, The capacitance value of the third capacitor is determined by the power-on curve of the device and the voltage rise time.

5. The programmable reset circuit according to claim 1, characterized in that, The timing programming time of the first timer is greater than or equal to 30 seconds, and the timing programming time of the second timer is less than or equal to 10 seconds.

6. The programmable reset circuit according to claim 1, characterized in that, The second timer is connected to the load switch via a voltage monitor. The voltage monitor is used to monitor the undervoltage of the processor module and peripheral chip devices. When an undervoltage condition is detected in the processor module or peripheral chip devices, a reset signal is triggered.

7. The programmable reset circuit according to claim 1, characterized in that, Also includes: The logic gate circuit has one end connected to the processor module and the other end connected to the second timer.

8. A method for control via a programmable reset circuit as described in any one of claims 1 to 7, characterized in that, include: After the target device is powered on, the start timing module sends a power-on start signal to the operation monitoring module. The power-on start signal includes: an initial high-level signal, a low-level signal of a first set duration, and a rising edge signal. During the initial high-level signal period, all components of the target device start working synchronously. During the first set duration of the low-level signal period, the timing module is activated to control the operation monitoring module to stop working. After the rising edge signal is activated, the control operation monitoring module starts working.

9. The method according to claim 8, characterized in that, After the rising edge signal initiates the operation, the control and monitoring module begins to work, including: During the normal operation of the operating system, the processor module periodically outputs alternating level signals to the logic gates; The logic gate flips the level alternation signal and sends the flipped signal to the dog feed signal input terminal of the second timer of the operation monitoring module to control the running status of the second timer; If the operation monitoring module detects an abnormal operation of the processor module, it triggers a reset signal and sends the reset signal to the load switch to control the power supply to turn off and on.

10. The method according to claim 8, characterized in that, The duration of the low-level signal with the first set duration is greater than or equal to the maximum duration required for the operating system to power on and start, and the startup timing module is triggered only once in one power supply cycle.

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