System starting apparatus, method and chip

Abstract

This application discloses a system boot device, method, and chip, belonging to the field of integrated circuit design technology. The device is applied to an embedded system, which includes a read-only memory area, an erasable and rewritable memory area, and multiple hardware devices. The read-only memory area stores a bootloader. The device includes: a boot module for starting the bootloader after the embedded system is powered on; an execution module for loading control information from the erasable and rewritable memory area through the bootloader, the control information indicating the hardware device mapped to each priority level, a first address, and a second address; and updating the initialization logic of the bootloader according to the control information, and performing initialization operations on multiple hardware devices in an orderly manner according to the priority levels indicated by the updated initialization logic, to read the configuration information of the corresponding hardware device from the second address, and configure the read configuration information into the hardware device pointed to by the corresponding first address. The initialization priority of the hardware devices can be flexibly adjusted.

Description

Technical Field

[0001] This application relates to the field of integrated circuit design technology, and in particular to a system startup device, method and chip. Background Technology

[0002] In embedded operating systems, before the operating system kernel runs, the hardware devices are initialized by a bootloader to prepare the correct environment for the operating system to start. The bootloader is the first piece of code executed by the chip carrying the operating system (such as a microcontroller unit (MCU)) after power-on. Hardware devices include intellectual property (IP) modules, which are reusable circuit modules with specific functions, such as clock management modules and serial communication interfaces. The bootloader initializes these hardware devices by reading the configuration information of each IP module from the chip's memory and then configuring the configuration information into the registers of each IP module sequentially according to the initialization order set in the bootloader, enabling the IP modules to function according to their respective configuration information.

[0003] As firmware, the BootLoader is stored in read-only memory, so its initialization order for each IP module is fixed and cannot be changed. However, different IP modules have different timing requirements (depending on the initialization order). If the timing of an IP module needs to be adjusted, the MCU's BootLoader usually needs to be redesigned and programmed, which is difficult and costly. Summary of the Invention

[0004] This application provides a system startup device, method, and chip to solve at least some of the problems raised in related technologies. The technical solution is as follows: In a first aspect, this application provides a system booting device applied to an embedded system. The embedded system includes a read-only memory area, an erasable and rewritable memory area, and multiple hardware devices. The read-only memory area stores a bootloader. The device includes: a boot module for starting the bootloader after the embedded system is powered on; an execution module for loading control information from the erasable and rewritable memory area through the bootloader. The control information indicates the hardware device mapped to each priority level, a first address, and a second address. The first address is the address of the hardware device at each priority level, and the second address is the address where the configuration information of the hardware device at each priority level is located. The execution module is further configured to update the initialization logic of the bootloader according to the control information, and to perform initialization operations on multiple hardware devices in an orderly manner according to the priority levels indicated by the updated initialization logic. The initialization operations include: reading the configuration information of the corresponding hardware device from the second address, and configuring the read configuration information into the hardware device pointed to by the corresponding first address.

[0005] In some possible implementations, the control information includes group numbers corresponding to N priority levels, each group number having a mapping relationship with at least one hardware device, where N is a positive integer; the execution module is used to: perform parallel initialization operations on all hardware devices mapped to the same group number during the process of performing initialization operations on multiple hardware devices in an orderly manner according to the priority levels indicated by the updated initialization logic through the bootloader.

[0006] In some possible implementations, the control information also includes N priority levels of enable states, which are used to indicate whether to perform initialization operations on the hardware devices of the corresponding priority level; the execution module is used to: through the bootloader, perform initialization operations on all hardware devices mapped to each group number whose enable state is valid in an orderly manner according to the priority level indicated by the updated initialization logic and the enable states.

[0007] In some possible implementations, the control information includes group numbers corresponding to N priority levels, and the first group number among the N group numbers is mapped to the first group register in the first hardware device, and the second group number is mapped to the second group register in the first hardware device; the first hardware device is one of multiple hardware devices; the execution module is used to: perform parallel initialization operations on the first group register in the first timing corresponding to the first group number according to the updated initialization logic through the bootloader, and perform parallel initialization operations on the second group register in the second timing corresponding to the second group number.

[0008] In some possible implementations, the control information includes group numbers corresponding to N priority levels. The third group number among the N group numbers has a mapping relationship with the third group register in the second hardware device. The second hardware device is one of multiple hardware devices, and the third group register is a part of the registers to be initialized in the second hardware device. The execution module is used to: perform parallel initialization operations on the third group register in the third timing corresponding to the third group number through the bootloader and according to the updated initialization logic.

[0009] In some possible implementations, the control information includes group numbers corresponding to N priority levels, and the number of the fourth register to be configured in the third hardware device. The third hardware device is one of multiple hardware devices, and the third hardware device has a mapping relationship with the fourth group number among the N group numbers. The priority level of the fourth register number is higher than the priority level corresponding to the fourth group number. The execution module is used to: perform initialization operations on the register corresponding to the fourth register number after the timing corresponding to the previous group number and before the fourth timing corresponding to the fourth group number, according to the updated initialization logic through the bootloader.

[0010] Secondly, a system startup method is provided, applied to an embedded system. The system includes a read-only memory area, an erasable and rewritable memory area, and multiple hardware devices. The read-only memory area stores a bootloader. The method includes: starting the bootloader after the embedded system is powered on; loading control information from the erasable and rewritable memory area through the bootloader, the control information indicating the hardware device mapped to each priority level, a first address, and a second address, the first address being the address of the hardware device at each priority level, and the second address being the address where the configuration information of the hardware device at each priority level is located; updating the initialization logic of the bootloader according to the control information; and performing initialization operations on the multiple hardware devices in an orderly manner according to the priority levels indicated by the updated initialization logic, the initialization operations including: reading the configuration information of the corresponding hardware device from the second address, and configuring the read configuration information into the hardware device pointed to by the corresponding first address.

[0011] In some possible implementations, the control information includes group numbers corresponding to N priority levels, each group number having a mapping relationship with at least one or more hardware devices, where N is a positive integer; multiple hardware devices are initialized in an orderly manner according to the priority levels indicated by the updated initialization logic, including: during the process of initializing multiple hardware devices in an orderly manner according to the priority levels indicated by the updated initialization logic through the bootloader, all hardware devices mapped to the same group number are initialized in parallel.

[0012] In some possible implementations, the control information also includes N priority levels of enable states, which are used to indicate whether to configure the hardware devices of the corresponding priority level; and to perform initialization operations on multiple hardware devices in an orderly manner according to the priority level indicated by the updated initialization logic, including: through the bootloader, performing initialization operations on all hardware devices mapped to each group number whose enable state is valid in an orderly manner according to the priority level indicated by the updated initialization logic and the enable states.

[0013] In some possible implementations, the control information includes group numbers corresponding to N priority levels, and the first group number among the N group numbers is mapped to the first group register in the first hardware device, and the second group number is mapped to the second group register in the first hardware device; the first hardware device is one of multiple hardware devices; the multiple hardware devices are initialized in an orderly manner according to the priority levels indicated by the updated initialization logic, including: by using a bootloader, according to the updated initialization logic, performing parallel initialization operations on the first group register in the first timing corresponding to the first group number, and performing parallel initialization operations on the second group register in the second timing corresponding to the second group number.

[0014] In some possible implementations, the control information includes group numbers corresponding to N priority levels. The third group number among the N group numbers is mapped to the third group register in the second hardware device. The second hardware device is one of multiple hardware devices, and the third group register is a subset of registers to be initialized in the second hardware device. The multiple hardware devices are initialized in an orderly manner according to the priority levels indicated by the updated initialization logic, including: by using a bootloader, the third group register is initialized in parallel at the third timing corresponding to the third group number according to the updated initialization logic.

[0015] In some possible implementations, the control information includes N priority level group numbers and the fourth register number to be configured in the third hardware device. The third hardware device is at least one of multiple hardware devices, and the third hardware device has a mapping relationship with the fourth group number among the N group numbers. The priority level of the fourth register number is higher than the priority level corresponding to the fourth group number. The multiple hardware devices are initialized in an orderly manner according to the priority level indicated by the updated initialization logic, including: by means of a bootloader, according to the updated initialization logic, initializing the register corresponding to the fourth register number after the timing corresponding to the previous group number and before the fourth timing corresponding to the fourth group number.

[0016] Thirdly, a chip is provided, which includes the system boot device of the first aspect and any possible implementation thereof.

[0017] Fourthly, an electronic device is provided, which includes the chip of the third aspect.

[0018] Fifthly, a computer device is provided, comprising a processor and a memory, wherein at least one computer program is stored in the memory, and the at least one computer program is loaded and executed by the processor to enable the computer device to implement the methods of the first aspect and any possible implementation thereof.

[0019] In a sixth aspect, a computer-readable storage medium is also provided, wherein at least one computer program is stored therein, the at least one computer program being loaded and executed by a processor to enable a computer to implement the methods of the first aspect and any possible implementation thereof.

[0020] In a seventh aspect, a computer program product or computer program is also provided, comprising computer instructions stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the computer device to perform the methods described in the first aspect and any possible implementation thereof.

[0021] The technical solution provided in this application brings at least the following beneficial effects: In this application, by injecting corresponding control information into the erasable and writable memory area of ​​the embedded system, after the embedded system powers on and starts the bootloader, it first reads this control information to update the initialization logic of the hardware devices in the current system. Then, it drives the bootloader to load and initialize each hardware device in an orderly manner according to the priority level indicated by the updated initialization logic. Compared with related technologies that set an unchangeable hardware device initialization order internally in the firmware, this application can flexibly adjust the timing of hardware devices without modifying the chip's firmware, resulting in higher efficiency and lower cost. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 This is a schematic diagram of an electronic device provided in an embodiment of this application; Figure 2 This is a schematic diagram of the structure of a system startup device provided in an embodiment of this application; Figure 3 This is a timing diagram for hardware device initialization provided in an embodiment of this application; Figure 4 This is a timing diagram for hardware device initialization provided in an embodiment of this application; Figure 5 This is a timing diagram for hardware device initialization provided in an embodiment of this application; Figure 6 This is a timing diagram for hardware device initialization provided in an embodiment of this application; Figure 7 This is a timing diagram for hardware device initialization provided in an embodiment of this application; Figure 8 This is a timing diagram for hardware device initialization provided in an embodiment of this application; Figure 9 This is a flowchart illustrating a system startup method provided in an embodiment of this application. Detailed Implementation

[0024] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0025] In related technologies, the MCU's firmware (i.e., the bootloader) is burned into read-only memory (ROM) and cannot be changed. Therefore, the initialization order of various hardware devices (such as IP modules) in the MCU by the bootloader is fixed. Consequently, when the timing of hardware devices is adjusted, the MCU also needs to adjust the initialization order of these hardware devices accordingly. This generally requires redesigning the MCU firmware and re-burning it into ROM, making it difficult, costly, and inefficient.

[0026] This application provides a system boot device. The device injects control information into the erasable and writable memory area of ​​the embedded system and updates the initialization priority of each hardware device in the bootloader based on the control information. Therefore, it can flexibly adjust the initialization order of hardware devices without making too many changes to the bootloader in the embedded system ROM, which is highly efficient and low cost.

[0027] To facilitate understanding of the technical solution of this application, an electronic device provided in the embodiments of this application will be described below.

[0028] For example, Figure 1 A schematic diagram of an electronic device according to an embodiment of this application is shown. This electronic device is, for example, a smart TV, tablet computer, monitor, or other display device, but is not limited thereto. (Reference) Figure 1The electronic device 00 includes an embedded system 01, which may include a chip (e.g., MCU 10), system-level memory 02 connected to the chip, and input / output interfaces 03, etc. The input / output interfaces 03 can be used to connect peripherals such as displays, etc. Furthermore, the embedded system 01 may also include firmware (e.g., a bootloader), an operating system (OS), or other applications (not listed) running on the MCU 10. Figure 1 (The Chinese logo is shown), so I will not elaborate further.

[0029] Next, combined Figure 1 This application describes a chip provided in an embodiment.

[0030] For example, continue to refer to Figure 1 The chip provided in this application embodiment is, for example, implemented as... Figure 1 The MCU 10 shown is not limited to this. As an example, the MCU 10 may include a processor 110, internal memory 120, and a communication interface 130. The processor 110 may include a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), a Neural Network Processing Unit (NPU), a Tensor Processing Unit (TPU), a System-on-Chip (SOC), or other types of processors with data processing and / or program execution capabilities. The processor 110 may be a general-purpose processor or a special-purpose processor.

[0031] For example, the internal memory 120 can be implemented as one or more forms of computer-readable storage media, such as non-volatile memory and volatile memory. Non-volatile memory includes, but is not limited to, read-only memory (ROM), hard disk, electrically erasable programmable read-only memory (EEPROM), portable compact disc read-only memory (CD-ROM), USB storage, flash memory, etc. Volatile memory includes, but is not limited to, random access memory (RAM) and / or cache memory, which can directly exchange data with the processor 110.

[0032] In this example, the ROM included in the internal memory 120 can provide a read-only memory area for the embedded system 01, which can be used to store the bootloader. Furthermore, the EEPROM, Flash, etc., included in the internal memory 120 can provide an erasable memory area for the embedded system 01. This erasable memory area is used to store and update some critical data / information (such as configuration information, control information about initialization timing, etc.) required after the embedded system 01 is powered on and the bootloader is started. Optionally, in other examples, this erasable memory area can also be provided by the system-level memory 02 or the internal storage space of the processor 110.

[0033] For example, communication interface 130 is used to communicate with external devices under the control of processor 110, thereby supporting data exchange between MCU 10 and external devices. By way of example and not limitation, communication interface 130 may include, for example, a Universal Asynchronous Receiver / Transmitter (UART), a Serial Peripheral Interface (SPI), an Inter-Integrated Circuit (I2C), an Ethernet interface, a Bluetooth interface (BT), a High-Definition Multimedia Interface (HDMI), and so on, to name a few.

[0034] For example, the MCU10 can also integrate various functional IP modules. An IP module refers to a reusable circuit module with corresponding functions; in this document, an IP module is also referred to as a "hardware device," such as... Figure 1 The hardware devices 20A, 20B, 20C, ... shown are, for example, a clock management unit (CMU), a power management unit (PMU), a timer / counter, an Ethernet MAC, an audio interface, a memory controller, etc., but are not limited to these.

[0035] Among them, hardware devices 20A, 20B, 20C, ... each include their own register file ( Figure 1(Unmarked in the image), the register file is a collection of read-write registers inside a hardware device, used to store configuration information of that hardware device. The register file provides the MCU10 with an interface for operating and monitoring the hardware device. Each register has a unique address and number, and the MCU10 can access these registers through the bus.

[0036] In this example, the number of hardware devices 20A, 20B, 20C, ... can be one or more, and each hardware device 20A, 20B, 20C, ... has its own timing sequence. After the MCU10 is powered on, it first starts the bootloader and loads control information from the aforementioned erasable memory area. This control information describes the initialization priority level of hardware devices 20A, 20B, 20C, ..., thereby driving the bootloader to perform initialization operations on hardware devices 20A, 20B, 20C, ... in an orderly manner according to the initialization priority level described in the control information. The initialization operation is to read the configuration information of hardware devices 20A, 20B, 20C, ... from the internal memory 120 and then configure them one by one into the registers of hardware devices 20A, 20B, 20C, ...

[0037] It should be noted that Figure 1 The structures shown are merely illustrative of the possible structures of an electronic device 00 provided in this application embodiment, and are not intended to be the sole limitation on the structure or function of the electronic device 00. In fact, the electronic device 00 can be implemented in a manner more complex than... Figure 1 The structure shown may have more or fewer components.

[0038] The following describes a system startup device provided in an embodiment of this application.

[0039] For example, Figure 2 The diagram shows a structural schematic of a system startup device according to an embodiment of this application. This device 200 can be applied to, for example... Figure 1 The embedded system 01 or MCU10 shown is an example, but not limited to. Figure 2 As shown, the device 200 may include a startup module 201 and an execution module 202.

[0040] The startup module 201 can be used to start the bootloader after the embedded system 01 is powered on; the execution module 202 can be used to load control information from the aforementioned erasable memory area through the bootloader. The control information indicates the hardware device mapped to each priority level, a first address, and a second address. The first address is the address of the hardware device at each priority level, and the second address is the address where the configuration information of the hardware device at each priority level is located. For example, the control information indicates that the priority levels corresponding to hardware devices 20A, 20B, 20C, and 20D are priority 0 to 3, respectively. That is, hardware device 20A has priority 0 and is initialized first, while hardware device 20D has priority 3 and is initialized last. In addition, the control information includes the address of the hardware device mapped to each priority level, as well as the address where the configuration information of the hardware device mapped to each priority level is located.

[0041] Next, the execution module 202 is also used to update the initialization logic of the bootloader according to the control information, and to perform initialization operations on multiple hardware devices in an orderly manner according to the priority level indicated by the updated initialization logic. The initialization operations include: reading the configuration information of the corresponding hardware device from the second address, and configuring the read configuration information into the hardware device pointed to by the corresponding first address. That is to say, the initialization logic of the bootloader stored in the read-only memory area in this example is updatable. It is equivalent to not setting the initialization order of each hardware device inside the bootloader, but setting it by the control information after the bootloader starts.

[0042] In this way, when the timing of hardware devices 20A, 20B, 20C, ... needs to be adjusted, the initialization priority of MCU10 for hardware devices 20A, 20B, 20C, ... can be flexibly changed by updating the control information of the erasable and writable memory area. There is no need to redesign the firmware of MCU10, which reduces development costs and facilitates the rapid and orderly configuration of hardware devices in scenarios where the timing of hardware devices needs to be adjusted.

[0043] In some possible examples, the format and content of the control information of MCU10 can be seen in Table 1 below.

[0044]

[0045] Table 1 In this example, the register file in MCU10 can be used to store the aforementioned control information. The first two columns in Table 1 are register addresses (the first column is the decimal address, and the second column is the hexadecimal address; two addresses in the same row can index a register in MCU10). Based on the registers corresponding to these addresses, the description information in the third column of Table 1 can be accessed sequentially. For example, in the register pointed to by address "0" in Table 1, the [15:08] bit field is used to store the enable status of priority levels 15 to 08. It should be noted that when the enable status of a priority level is valid, MCU10 configures (i.e., initializes) the hardware devices with valid enable status at the priority level; otherwise, it does not configure them. As another example, in the register pointed to by address "2" in Table 1, the [07:02] bit field is used to store the group number (Module ID) corresponding to priority level 0, and the [01:00] bit field is used to store the high-order part of the data length field for priority level 0, that is, bits [09:08] of the data length field. Further details are omitted.

[0046] In this example, the group number represents the priority level. For instance, group number Module 0 indicates priority level 0, which is the highest priority level. Hardware devices with the highest priority are configured first during initialization. Group number Module 1 indicates priority level 1, which is the second highest priority level. Hardware devices with the second highest priority are configured after those with priority level 0 during initialization, and so on. In other possible examples, a smaller group number can indicate a lower priority level.

[0047] In this example, referring to the description information in the third column of Table 1, each group number (Module 0 to Module 15) can map to the identifier of one or more hardware devices, thereby assigning a corresponding priority level to the hardware devices. This allows MCU 10 to find the hardware device corresponding to the current priority level based on the group number. In this description information, the data offset is used to determine the address (i.e., the first address) of hardware devices 20A, 20B, 20C, ... within MCU 10; the start address and data length are used to determine the address (i.e., the second address) of the configuration information of the corresponding hardware device in internal memory 120; and the priority level enable state is used to control whether to configure the hardware device of that priority level.

[0048] Thus, with control information (also referred to as "first control information" in this document) stored in the erasable and writable memory area, execution module 202 can also be used to obtain updated control information (also referred to as "second control information" in this document). Compared to the first control information, the second control information changes the priority levels of at least some hardware devices 20A, 20B, 20C, ... Then, during the power-on startup process of embedded system 01, execution module 202 can sequentially read the configuration information of the corresponding hardware devices from the second address according to the priority level indicated by the second control information, and configure the configuration information into the corresponding hardware device pointed to by the first address.

[0049] In other words, when it is necessary to adjust the timing of any hardware device 20A, 20B, 20C, ..., the initialization logic of the BootLoader can be adjusted flexibly, efficiently, and conveniently through control information similar to that in Table 1, thereby enabling the MCU10 to modify the initialization priority order of hardware devices 20A, 20B, 20C, ... It should be noted that when adjusting the timing of hardware devices, the updated control information enters the MCU10. After the MCU10 is powered on again, it can read the updated control information input before its own power-on, and then determine the current initialization priority of hardware devices 20A, 20B, 20C, ... It can be understood that when the embedded system 01 is powered on or reset, the BootLoader starts execution from address 0x0000, thereby initializing the hardware devices and establishing a memory space mapping before the kernel of the embedded system 01 runs, in order to prepare for the startup of the corresponding operating system. Further details are omitted.

[0050] In some possible implementations, the control information may include group numbers corresponding to N priority levels, and each group number may be mapped to one or more hardware devices, where N is a positive integer.

[0051] Therefore, in this implementation, the execution module 202 can also be used to perform parallel initialization operations on all hardware devices mapped by the same group number during the process of performing initialization operations on multiple hardware devices 20A, 20B, 20C, ... in an orderly manner according to the priority level of the updated initialization logic indication by the bootloader.

[0052] For example Figure 3As shown, for the current hardware devices 20A, 20B, 20C, ..., the control information of the erasable and writable memory areas includes N priority levels corresponding to group numbers Module 0 to Module N. Module 0 to Module N each map to the identifiers of two hardware devices. For example, Module 0 maps to hardware devices 20A and 20B, Module 1 maps to hardware devices 20E and 20H, and so on. The initialization priority of Module 0 to Module N decreases sequentially. That is, all hardware devices 20A and 20B mapped to Module 0 are configured with the highest priority at the same time, and so on. All hardware devices mapped to Module N are configured last at the same time.

[0053] In this way, hardware devices can be grouped according to priority levels (20A, 20B, 20C, ...), and hardware devices of the same priority level can share the same initialization timing, enabling parallel configuration and accelerating hardware device initialization.

[0054] In some possible implementations, the control information may include N priority levels of enable states, which are used to control whether to perform initialization operations on the hardware devices of the corresponding priority level. Therefore, in this implementation, the execution module 202 can also be used to: through the bootloader, perform initialization operations on all hardware devices mapped to each group number whose enable state is valid, according to the priority level and enable state indicated by the updated initialization logic.

[0055] For example Figure 4 As shown, for the current hardware devices 20A, 20B, 20C, ..., the control information of the erasable memory area indicates that the enable state of Module 0 and Module 2 is valid (i.e., enable=1), and the enable state of Module 1 is invalid (i.e., enable=0). Therefore, during the initialization process, all hardware devices 20A and 20B that are mapped to Module 0 are initialized with the highest priority at the same time point, followed by the initialization of all hardware devices 20C and 20D that are mapped to Module 2, while all hardware devices that are mapped to Module 1 are not initialized.

[0056] In this way, the configuration capabilities of hardware devices can be flexibly enabled or disabled according to the different hardware device usage needs of different users, so that some hardware devices that users do not need do not need to be initialized, which helps to speed up the hardware device initialization process, reduce system power consumption, and reduce power consumption.

[0057] In some possible implementations, MCU10 initializes hardware devices 20A, 20B, 20C, ..., that is, it writes the configuration information of hardware devices 20A, 20B, 20C, ... into the register files of hardware devices 20A, 20B, 20C, ... Therefore, in this implementation, the control information includes group numbers corresponding to N priority levels. The first group number (i.e., one of the N group numbers, such as Module 0) can be mapped to the first group of registers to be configured in the first hardware device, and the second group number (i.e., one of the N group numbers, such as Module 1) can be mapped to the second group of registers in the first hardware device. Here, the first hardware device is one of multiple hardware devices, and both the first and second group registers can include one or more registers. Multiple registers in the same group can be address-contiguous or non-contiguous.

[0058] Therefore, the execution module 202 can also be used to: perform parallel initialization operations on the first group of registers in the first timing corresponding to the first group number, according to the updated initialization logic, through the bootloader, and perform parallel initialization operations on the second group of registers in the second timing corresponding to the second group number.

[0059] This is equivalent to segmenting the register file within a hardware device. One application scenario for this implementation can be found in [reference needed]. Figure 5 As shown, a hardware device 20A may have many registers, such as 500, exceeding the maximum number of registers that the MCU10 can support in a single configuration cycle (e.g., 255), or exceeding the register access capability of the MCU10 in a single configuration. Therefore, the control information can instruct that at least some of the registers to be configured in the first hardware device 20A (e.g., registers numbered 0-254) have a mapping relationship with the first group of numbers, and the remaining registers (e.g., registers numbered 255-499) have a mapping relationship with the second group of numbers, with the timing of the second group of numbers being later than that of the first group of numbers. Then, during the initialization of hardware devices 20A, 20B, 20C, ... by the MCU10, registers numbered 0-254 in hardware device 20A can be configured first in the first timing corresponding to the first group of numbers (Module0), and the remaining registers numbered 255-499 can be configured in the second timing corresponding to the second group of numbers (Module1). In this way, a hardware device is divided into two priority-level ordered segmented configurations to meet the initialization requirements.

[0060] Another application scenario for this implementation method can be found in [link to relevant documentation]. Figure 6As shown, a hardware device 20A may have many registers, such as 150. However, only the registers at the beginning and end need to be configured. The registers in the middle section already have default values ​​and do not need to be configured, or if the registers in the middle section are known to have defects (bugs), they are not configured to avoid causing system startup failure. Therefore, the 150 registers in the hardware device 20A can be divided into three segments: the first 50 registers (i.e., the first group of registers, including registers numbered 0 to 49) are mapped to the same group number (e.g., the first group number Module 0); the last 50 registers (i.e., the second group of registers, including registers numbered 100 to 149) are mapped to the same group number (e.g., the second group number Module 2); and the middle 50 registers are not mapped to any group number or the mapped group number is in an enabled state and invalid. During the initialization of hardware devices 20A, 20B, 20C, ... by MCU10, registers numbered 0 to 49 in hardware device 20A can be initialized in the first timing sequence corresponding to the first group number. The middle 50 registers will retain their original values ​​(i.e., this part of the registers will be skipped during this initialization and will not be configured). Registers numbered 100 to 149 will be initialized in the second timing sequence corresponding to the second group number.

[0061] Therefore, different registers in the same hardware device can be mapped to different priority levels, enabling segmented configuration of non-contiguous registers within the same hardware device, offering high flexibility. Furthermore, the hardware device initialization timing can be adjusted via control information in various scenarios, resulting in strong reusability of configuration logic. Additionally, register combinations with the same timing requirements can be mapped to the same group number and configured in parallel during the same initialization phase, demonstrating strong composability and ease of implementation. Moreover, registers that do not currently require configuration (e.g., those with existing default values ​​or known bugs, as mentioned above) can be skipped during initialization via control information, thus reducing the number of registers configured in the hardware device, shortening initialization time, and consequently accelerating the initialization process.

[0062] Similarly, in some possible implementations, the control information includes group numbers corresponding to N priority levels. The third group number (e.g., Module 1) among these N group numbers is mapped to the third group register in the second hardware device. The second hardware device is one of multiple hardware devices, and the third group register is a portion of the registers to be initialized in the second hardware device. That is, the third group register includes all the registers to be initialized in the second hardware device.

[0063] Therefore, the execution module 202 can also be used to: perform parallel initialization operations on the third group registers in the third timing corresponding to the third group number by means of the bootloader and according to the updated initialization logic.

[0064] This is equivalent to segmenting (or grouping) the register file within a hardware device. For example... Figure 7 As shown, the 150 registers within a hardware device 20A are divided into three segments. The first 50 and last 50 registers are not mapped to any group number, or the mapped group number is enabled but invalid. The middle 50 registers (i.e., the third group of registers, including registers numbered 50 to 99) are mapped to the same group number (e.g., the third group number Module 1). During the initialization of hardware devices 20A, 20B, 20C, ... by MCU10, registers numbered 50 to 99 in hardware device 20A can be configured in the third timing sequence corresponding to the third group number. Registers numbered 0 to 49 and 100 to 149 retain their original values ​​(i.e., this part is skipped in this initialization and no configuration is performed).

[0065] In other words, this solution can configure the registers that require configuration in the same hardware device separately, and skip the remaining registers that do not require configuration in the hardware device during the initialization process. This reduces the number of registers that are initialized in the hardware device, which helps to shorten the initialization time. Therefore, it is highly flexible and helps to speed up the initialization process.

[0066] In some possible implementations, the control information includes group numbers corresponding to N priority levels and the number of the fourth register to be configured in the third hardware device. The third hardware device is one of multiple hardware devices, and the third hardware device has a mapping relationship with the fourth group number among the N group numbers. The priority level of the fourth register number is higher than the priority level corresponding to the fourth group number.

[0067] Therefore, execution module 202 can also be used to: through the bootloader, according to the updated initialization logic, perform initialization operations on the register corresponding to the fourth register number after the timing corresponding to the previous group number of the fourth group number and before the fourth timing corresponding to the fourth group number. That is, for example... Figure 8 As shown, the third hardware device (i.e., hardware device 20B) is mapped to the fourth group number (such as the fourth group number Module 1). During initialization, registers 0 to 149 in hardware device 20B are almost all configured on the fourth timing corresponding to the fourth group number. However, since the register corresponding to the fourth register number in hardware device 20B (such as register X0) has certain special characteristics (the value of register X0 is always 0 and cannot be modified), the priority of register X0 should preferably be higher than the priority of the hardware device to simplify the complexity of configuring it simultaneously with other general-purpose registers. Therefore, register X0 will be configured after hardware device 20A of the previous group number of the fourth group number has been configured and before the timing corresponding to Module 1.

[0068] This allows for the individual configuration of special registers within the same hardware device, offering high flexibility.

[0069] It should be noted that the above embodiments only illustrate the division of the above functional modules when implementing their functions. In actual applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above.

[0070] Based on the same technical concept as the apparatus provided in the above embodiments, this embodiment also provides a system startup method. Next, a system startup method provided by an embodiment of this application will be described.

[0071] For example, Figure 9 The diagram illustrates a flowchart of a system startup method provided in an embodiment of this application. This method can be applied to embedded systems, such as... Figure 1 The embedded system 01 shown includes a read-only memory area, an erasable and rewritable memory area, and multiple hardware devices. The read-only memory area stores the bootloader. Then, refer to... Figure 9 The method may include steps S510 to S540: S510 starts the bootloader after the embedded system is powered on; S520 loads control information from the erasable memory area through the bootloader. The control information is used to indicate the hardware device mapped to each priority level, the first address and the second address. The first address is the address of the hardware device of each priority level, and the second address is the address where the configuration information of the hardware device of each priority level is located. S530 updates the bootloader's initialization logic based on control information; S540 performs initialization operations on multiple hardware devices in an orderly manner according to the priority level of the updated initialization logic indication. The initialization operations include: reading the configuration information of the corresponding hardware device from the second address, and configuring the read configuration information into the hardware device pointed to by the corresponding first address.

[0072] In some possible implementations, the control information includes group numbers corresponding to N priority levels, each group number having a mapping relationship with at least one or more hardware devices, where N is a positive integer; S540, performing initialization operations on multiple hardware devices in an orderly manner according to the priority levels indicated by the updated initialization logic, including: during the process of performing initialization operations on multiple hardware devices in an orderly manner according to the priority levels indicated by the updated initialization logic through the bootloader, all hardware devices mapped to the same group number are initialized in parallel.

[0073] In some possible implementations, the control information also includes N priority levels of enable states, which are used to indicate whether to configure the hardware devices of the corresponding priority levels; S540, perform initialization operations on multiple hardware devices in an orderly manner according to the priority levels indicated by the updated initialization logic, including: through the bootloader, perform initialization operations on all hardware devices mapped to each group number whose enable state is valid in an orderly manner according to the priority levels indicated by the updated initialization logic and the enable states.

[0074] In some possible implementations, the control information includes group numbers corresponding to N priority levels, and the first group number among the N group numbers is mapped to the first group register in the first hardware device, and the second group number is mapped to the second group register in the first hardware device; the first hardware device is one of multiple hardware devices; S540, the multiple hardware devices are initialized in an orderly manner according to the priority levels indicated by the updated initialization logic, including: by using the bootloader, the first group register is initialized in the first timing corresponding to the first group number according to the updated initialization logic, and the second group register number is initialized in the second timing corresponding to the second group number.

[0075] In some possible implementations, the control information includes group numbers corresponding to N priority levels. The third group number among the N group numbers has a mapping relationship with the third group register in the second hardware device. The second hardware device is one of multiple hardware devices, and the third group register is a part of the registers to be initialized in the second hardware device. S540, the multiple hardware devices are initialized in an orderly manner according to the priority levels indicated by the updated initialization logic, including: by using the bootloader, the third group register is initialized in the third timing corresponding to the third group number according to the updated initialization logic.

[0076] In some possible implementations, the control information includes N priority level group numbers and the fourth register number to be configured in the third hardware device. The third hardware device is at least one of multiple hardware devices, and the third hardware device has a mapping relationship with the fourth group number among the N group numbers. The priority level of the fourth register number is higher than the priority level corresponding to the fourth group number. S540, the multiple hardware devices are initialized in an orderly manner according to the priority level indicated by the updated initialization logic, including: by means of the bootloader, according to the updated initialization logic, the register corresponding to the fourth register number is initialized after the timing corresponding to the previous group number of the fourth group number and before the fourth timing corresponding to the fourth group number.

[0077] It should be noted that, for information regarding the functions or beneficial effects of each step in the above system startup method, please refer to the relevant descriptions of the system startup device in the foregoing embodiments, which will not be repeated here.

[0078] In an exemplary embodiment, a computer device is also provided, comprising a processor and a memory, wherein at least one computer program is stored in the memory. The at least one computer program is loaded and executed by one or more processors to enable the computer device to implement any of the above-described system startup methods.

[0079] In an exemplary embodiment, a computer-readable storage medium is also provided, storing at least one computer program. This computer program is loaded and executed by a processor of a computer device to enable the computer to implement any of the aforementioned system boot methods. The aforementioned computer-readable storage medium may be a read-only memory (ROM), a random access memory (RAM), a compact disc read-only memory (CD-ROM), magnetic tape, floppy disk, or optical data storage device, etc.

[0080] In an exemplary embodiment, a computer program product or computer program is also provided, which includes computer instructions stored in a computer-readable storage medium. The processor of a computer device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the computer device to perform any of the above-described system startup methods.

[0081] It should be understood that "multiple" as used in this article refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. The character " / " generally indicates that the preceding and following related objects have an "or" relationship.

[0082] The above description is merely an exemplary embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the principles of this application should be included within the protection scope of this application.

Claims

1. A system startup device, characterized in that, The device is applied to an embedded system, which includes a read-only memory area, an erasable and rewritable memory area, and multiple hardware devices. The read-only memory area stores a bootloader program. The device includes: A startup module is used to start the bootloader after the embedded system is powered on. An execution module is used to load control information from the erasable memory area through the bootloader. The control information is used to indicate the hardware device mapped to each priority level, a first address, and a second address. The first address is the address of the hardware device for each priority level, and the second address is the address where the configuration information of the hardware device for each priority level is located. The execution module is further configured to update the initialization logic of the bootloader according to the control information, and to perform initialization operations on the plurality of hardware devices in an orderly manner according to the priority level indicated by the updated initialization logic. The initialization operations include: reading the configuration information of the corresponding hardware device from the second address, and configuring the read configuration information into the hardware device pointed to by the corresponding first address.

2. The apparatus according to claim 1, characterized in that, The control information includes group numbers corresponding to N priority levels, and each group number has a mapping relationship with at least one hardware device, where N is a positive integer. The execution module is used for: During the initialization process of the plurality of hardware devices by means of the bootloader, in an orderly manner according to the priority level indicated by the updated initialization logic, all hardware devices mapped to the same group number are initialized in parallel.

3. The apparatus according to claim 2, characterized in that, The control information also includes N priority levels of enable states, which are used to indicate whether to perform initialization operations on the corresponding priority level hardware devices. The execution module is used for: The bootloader performs the initialization operation in an orderly manner on all hardware devices mapped to each group number whose enable state is valid, based on the priority level and enable state indicated by the updated initialization logic.

4. The apparatus according to any one of claims 1-3, characterized in that, The control information includes group numbers corresponding to N priority levels, and the first group number among the N group numbers has a mapping relationship with the first group register in the first hardware device, and the second group number has a mapping relationship with the second group register in the first hardware device; the first hardware device is one of the plurality of hardware devices; The execution module is used for: Through the bootloader, according to the updated initialization logic, the first group of registers is initialized in parallel at the first timing corresponding to the first group number, and the second group of registers is initialized in parallel at the second timing corresponding to the second group number.

5. The apparatus according to any one of claims 1-3, characterized in that, The control information includes group numbers corresponding to N priority levels. The third group number among the N group numbers has a mapping relationship with the third group register in the second hardware device. The second hardware device is one of the plurality of hardware devices. The third group register is a part of the registers to be initialized in the second hardware device. The execution module is used for: The bootloader performs parallel initialization operations on the third group of registers according to the updated initialization logic in the third timing corresponding to the third group number.

6. The apparatus according to any one of claims 1-3, characterized in that, The control information includes group numbers corresponding to N priority levels, and a fourth register number to be configured in the third hardware device. The third hardware device is one of the plurality of hardware devices. The third hardware device has a mapping relationship with the fourth group number among the N group numbers. The priority level of the fourth register number is higher than the priority level corresponding to the fourth group number. The execution module is used for: According to the updated initialization logic, the initialization operation is performed on the register corresponding to the fourth register number after the timing corresponding to the previous group number of the fourth group number and before the fourth timing corresponding to the fourth group number by the bootloader.

7. A system startup method, characterized in that, The method is applied to an embedded system, which includes a read-only memory area, an erasable and rewritable memory area, and multiple hardware devices. The read-only memory area stores a bootloader program. The method includes: The bootloader is started after the embedded system is powered on; The bootloader loads control information from the erasable memory area. The control information is used to indicate the hardware device mapped to each priority level, a first address, and a second address. The first address is the address of the hardware device for each priority level, and the second address is the address where the configuration information of the hardware device for each priority level is located. The initialization logic of the bootloader is updated according to the control information; The plurality of hardware devices are initialized in an orderly manner according to the priority level indicated by the updated initialization logic. The initialization operation includes: reading the configuration information of the corresponding hardware device from the second address, and configuring the read configuration information into the hardware device pointed to by the corresponding first address.

8. The method according to claim 7, characterized in that, The control information includes group numbers corresponding to N priority levels, and each group number has a mapping relationship with at least one or more hardware devices, where N is a positive integer. The initialization operation of the plurality of hardware devices in an orderly manner according to the priority level indicated by the updated initialization logic includes: During the initialization process of the plurality of hardware devices by means of the bootloader, in an orderly manner according to the priority level indicated by the updated initialization logic, all hardware devices mapped to the same group number are initialized in parallel.

9. The method according to claim 8, characterized in that, The control information also includes N priority levels of enable states, which are used to indicate whether to configure the hardware device of the corresponding priority level. The initialization operation of the plurality of hardware devices in an orderly manner according to the priority level indicated by the updated initialization logic includes: The bootloader performs the initialization operation in an orderly manner on all hardware devices mapped to each group number whose enable state is valid, based on the priority level and enable state indicated by the updated initialization logic.

10. The method according to any one of claims 7-9, characterized in that, The control information includes group numbers corresponding to N priority levels, and the first group number among the N group numbers has a mapping relationship with the first group register in the first hardware device, and the second group number has a mapping relationship with the second group register in the first hardware device; the first hardware device is one of the plurality of hardware devices; The initialization operation of the plurality of hardware devices in an orderly manner according to the priority level indicated by the updated initialization logic includes: Through the bootloader, according to the updated initialization logic, the first group of registers is initialized in parallel at the first timing corresponding to the first group number, and the second group of registers is initialized in parallel at the second timing corresponding to the second group number.

11. The method according to any one of claims 7-9, characterized in that, The control information includes group numbers corresponding to N priority levels. The third group number among the N group numbers has a mapping relationship with the third group register in the second hardware device. The second hardware device is one of the plurality of hardware devices. The third group register is a part of the registers to be initialized in the second hardware device. The initialization operation of the plurality of hardware devices in an orderly manner according to the priority level indicated by the updated initialization logic includes: The bootloader performs parallel initialization operations on the third group of registers according to the updated initialization logic in the third timing corresponding to the third group number.

12. The method according to any one of claims 7-9, characterized in that, The control information includes N priority level group numbers and a fourth register number to be configured in the third hardware device. The third hardware device is at least one of the plurality of hardware devices. The third hardware device has a mapping relationship with the fourth group number among the N group numbers. The priority level of the fourth register number is higher than the priority level corresponding to the fourth group number. The initialization operation of the plurality of hardware devices in an orderly manner according to the priority level indicated by the updated initialization logic includes: According to the updated initialization logic, the initialization operation is performed on the register corresponding to the fourth register number after the timing corresponding to the previous group number of the fourth group number and before the fourth timing corresponding to the fourth group number by the bootloader.

13. A chip, characterized in that, include: The system startup device according to any one of claims 1-6.

14. An electronic device, characterized in that, Includes the chip described in claim 13.

Images