Error processing method and device of NAND FLASH controller, electronic equipment and storage medium
By capturing and processing errors in stages and hierarchically within the NAND FLASH controller, the problem of inaccurate and inefficient error handling in existing technologies is solved, achieving high-efficiency data security and system performance assurance. It is suitable for solid-state drives, embedded memory cards, and mobile devices.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SHANDONG YUNHAI GUOCHUANG CLOUD COMPUTING EQUIP IND INNOVATION CENT CO LTD
- Filing Date
- 2026-03-24
- Publication Date
- 2026-06-09
AI Technical Summary
Existing error handling methods for NAND flash controllers are insufficient to fully identify various error types, are not precise enough, and are inefficient, failing to meet the needs of high-performance storage systems and easily leading to data loss or metadata corruption.
By identifying the error types of the NAND FLASH controller at different operational stages, errors are captured and processed in stages and at different levels, including recoverable and unrecoverable errors. Measures such as reset operations, data retransmission, and system panic states are adopted to ensure data security and system performance.
It enables precise and efficient handling of NAND FLASH operation errors, maximizes data security and system performance, shortens troubleshooting time, and improves the reliability and processing efficiency of storage devices.
Smart Images
Figure CN122173323A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of data storage technology, and in particular to error handling methods, apparatus, electronic devices, and storage media for NAND FLASH controllers. Background Technology
[0002] With the rapid development of information technology, the demand for data storage has exploded. NAND flash memory, due to its advantages such as high storage density, non-volatility, low power consumption, and fast read / write speeds, has become the mainstream storage solution in solid-state drives, embedded memory cards, and various mobile devices. In a storage system, the NAND flash controller (NFC) is a key hardware module connecting upper-layer software (such as the flash translation layer FTL) and the underlying NAND flash chip. It is responsible for accurately executing erase, programming (write), and read operation instructions from the host and managing the data transmission process.
[0003] However, in actual operation, due to the limitations of NAND FLASH technology, changes in the working environment, and increased circuit complexity, NFC inevitably encounters various errors during operation. These errors have diverse and complex origins, but can be mainly summarized as follows:
[0004] First, due to the physical characteristics of the NAND FLASH medium itself, such as the generation of bad blocks in the storage cells during use, the erase or write operation on that block cannot be completed within the specified time, thus causing an operation timeout error.
[0005] Second, the problem stems from a malfunction in the functional modules integrated within NFC, such as the Direct Memory Access (DMA) controller, which may malfunction when transferring data, causing the data transfer completion flag to fail to be set correctly, i.e., a DMA completion error.
[0006] Third, the data error stems from the disruption of data integrity along the data path. For example, a bit flip in the Static Random-Access Memory (SRAM) used for temporary data storage can cause inconsistencies between the written and read data. During the data reading process, data errors may be detected when checking the data using Cyclic Redundancy Check (CRC) or Error Correction Code (ECC).
[0007] Fourth, communication problems stemming from the NAND FLASH interface, such as timing deviations or logic errors in response signals leading to response errors.
[0008] Fifth, it stems from abnormal states of stored pages, such as reading an unprogrammed empty page.
[0009] Existing NFC error handling methods have certain limitations in addressing the aforementioned types of errors. Specifically, some existing technical solutions are designed only for single types of errors (such as handling only ECC errors or bad blocks), lacking a systematic and comprehensive approach to handling complex errors and struggling to cope with concurrent or cascading failure scenarios. Furthermore, some error handling mechanisms fail to fully consider the profound impact of error types on subsequent operational processes and data status, and their recovery strategies may be overly simplistic and crude, easily leading to user data loss or metadata corruption. Moreover, some error recovery processes are designed to be cumbersome, involving excessive hardware and software interactions or redundant reset steps, resulting in excessively long recovery times and low processing efficiency, failing to meet the needs of high-performance storage systems or applications with high real-time requirements.
[0010] Therefore, how to provide a NAND FLASH error handling method that can comprehensively identify various NAND FLASH operation errors, accurately and efficiently handle different error types, and maximize data security and system performance has become a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention
[0011] This application provides an error handling method, apparatus, electronic device, and storage medium for a NAND FLASH controller, which can comprehensively identify various NAND FLASH operation errors, perform accurate and efficient processing according to different error types, and maximize data security and system performance.
[0012] The technical solution of this application embodiment is implemented as follows: In a first aspect, embodiments of this application provide an error handling method for a NAND FLASH controller, the method comprising: Determine the operational phase to which the error belongs during the NAND FLASH controller's management of NAND FLASH, wherein the operational phase includes at least one of the following: write phase, read phase, and erase phase; The error type is determined based on the operational stage to which the error belongs and the cause of the error. If the error type is an unrecoverable error, then control the operating system to enter a kernel panic state; If the error type is a recoverable error, then error handling shall be performed according to the error type.
[0013] In some embodiments, determining the error type based on the operational stage to which the error belongs and the cause of the error includes: If the operation stage to which the error belongs is the erase stage, and the cause of the error is a circuit failure of the NAND FLASH, then the error type is determined to be NAND timeout; If the operation stage to which the error belongs is the erase stage, and the cause of the error is damage to the NAND FLASH storage cell, then the error type is determined to be a bad block.
[0014] In some embodiments, determining the error type based on the operational stage to which the error belongs and the cause of the error includes: If the operation phase to which the error belongs is the write phase, and the cause of the error is a write operation timeout, then the error type is determined to be NAND timeout. If the operation stage to which the error belongs is the write stage, and the cause of the error is the inability to generate a DMA completion signal, then the error type is determined to be a DMA completion error.
[0015] In some embodiments, determining the error type based on the operational stage to which the error belongs and the cause of the error includes: If the operation phase to which the error belongs is the read phase, and the cause of the error is a read operation timeout, then the error type is determined to be NAND timeout. If the operation stage to which the error belongs is the read stage, and the cause of the error is the inability to generate a DMA completion signal, then the error type is determined to be a DMA completion error.
[0016] In some embodiments, determining the error type based on the operational stage to which the error belongs and the cause of the error includes: If the operation stage to which the error belongs is the read stage, and the cause of the error is a cache failure in the NAND FLASH controller, then the error type is determined to be a cache error. If the operation stage to which the error belongs is the read stage, and the cause of the error is an error in the transmission of the response signal by the NAND FLASH controller, then the error type is determined to be a response error.
[0017] In some embodiments, determining the error type based on the operational stage to which the error belongs and the cause of the error includes: If the operation stage to which the error belongs is the reading stage, and the cause of the error is an error in the verification process, then the error type is determined to be a verification error. If the operation stage to which the error belongs is the reading stage, and the cause of the error is reading an empty page, then the error type is determined to be an empty page error.
[0018] In some embodiments, if the error type is a recoverable error, then error handling according to the error type includes: If the error type is NAND timeout, then a reset operation is performed on the logic cell of the NAND FLASH.
[0019] In some embodiments, if the error type is a recoverable error, then error handling according to the error type includes: If the error type is DMA completion error, then a reset operation is performed on the NAND FLASH controller.
[0020] In some embodiments, after performing a reset operation on the NAND FLASH controller, the method further includes: If the read operation is not completed, the read operation will be re-executed; If the write operation is not completed, the write operation is marked as a write operation error, and the write command corresponding to the write operation is sent to the FTL; the erase and write command for the write operation is executed repeatedly.
[0021] In some embodiments, if the error type is a recoverable error, then error handling according to the error type includes: If the error type is a page null error, the error information corresponding to the page null error is sent to the FTL so that the FTL can perform a reread operation based on the error information.
[0022] In some embodiments, if the error type is a recoverable error, then error handling according to the error type includes: If the error type is a verification error, then a soft decoding operation is performed on the erroneous data; If the software decoding operation fails, all data will be retransmitted and re-verified. If the verification fails again, an error message is sent to the FTL so that the FTL can perform a data recovery operation.
[0023] In some embodiments, the step of controlling the operating system to enter a panic state if the error type is an unrecoverable error includes: If the error type is a cache error or a response error, control the operating system to enter a kernel panic state.
[0024] Secondly, embodiments of this application provide an error handling apparatus for a NAND FLASH controller, the apparatus comprising: The first determining module is used to determine the operation phase to which the error belongs in the process of the NAND FLASH controller managing the NAND FLASH, wherein the operation phase includes at least one of the following: write phase, read phase, and erase phase; The second determining module is used to determine the error type based on the operation stage to which the error belongs and the cause of the error. The control module is used to control the operating system to enter a panic state if the error type is an unrecoverable error. The processing module is used to perform error processing according to the error type if the error type is a recoverable error.
[0025] In some embodiments, the second determining module is specifically used to determine the error type as NAND timeout if the operation stage to which the error belongs is the erase stage and the cause of the error is a circuit fault in the NAND FLASH. If the operation stage to which the error belongs is the erase stage, and the cause of the error is damage to the NAND FLASH storage cell, then the error type is determined to be a bad block.
[0026] In some embodiments, the second determining module is specifically used to determine the error type as NAND timeout if the operation stage to which the error belongs is the write stage and the cause of the error is a write operation timeout; If the operation stage to which the error belongs is the write stage, and the cause of the error is the inability to generate a direct memory access (DMA) completion signal, then the error type is determined to be a DMA completion error.
[0027] In some embodiments, the second determining module is specifically used to determine the error type as NAND timeout if the operation stage to which the error belongs is the read stage and the cause of the error is a read operation timeout; If the operation stage to which the error belongs is the read stage, and the cause of the error is the inability to generate a DMA completion signal, then the error type is determined to be a DMA completion error.
[0028] In some embodiments, the second determining module is specifically used to determine the error type as a cache error if the operation stage to which the error belongs is the read stage and the cause of the error is a cache failure of the NAND FLASH controller; If the operation stage to which the error belongs is the read stage, and the cause of the error is an error in the transmission of the response signal by the NAND FLASH controller, then the error type is determined to be a response error.
[0029] In some embodiments, the second determining module is specifically used to determine the error type as a verification error if the operation stage to which the error belongs is the reading stage and the cause of the error is an error in the verification process; If the operation stage to which the error belongs is the reading stage, and the cause of the error is reading an empty page, then the error type is determined to be an empty page error.
[0030] In some embodiments, the processing module is specifically configured to perform a reset operation on the logic cells of the NAND FLASH if the error type is NAND timeout.
[0031] In some embodiments, the processing module is specifically configured to perform a reset operation on the NAND FLASH controller if the error type is a DMA completion error.
[0032] In some embodiments, the processing module is specifically configured to re-execute the read operation if the read operation has not been completed. If the write operation is not completed, the write operation is marked as a write operation error, and the write command corresponding to the write operation is sent to the flash translation layer (FTL); the erase and write commands for the write operation are executed repeatedly.
[0033] In some embodiments, the processing module is specifically used to send the error information corresponding to the empty page error to the FTL if the error type is an empty page error, so that the FTL performs a reread operation based on the error information.
[0034] In some embodiments, the processing module is specifically used to perform a soft decoding operation on the erroneous data if the error type is a verification error; If the software decoding operation fails, all data will be retransmitted and re-verified. If the verification fails again, an error message is sent to the FTL so that the FTL can perform a data recovery operation.
[0035] In some embodiments, the control module is specifically used to control the operating system to enter a panic state if the error type is a cache error or a response error.
[0036] Thirdly, embodiments of this application provide an electronic device, the electronic device comprising: a processor and a memory communicatively connected to the processor; wherein... The processor memory stores instructions that can be executed by the processor, which are then executed by the processor to enable the processor to perform the error handling method of the NAND FLASH controller described above.
[0037] Fourthly, embodiments of this application provide a computer-readable storage medium storing executable instructions for implementing the above-described error handling method for a NAND FLASH controller when executed by a processor.
[0038] Fifthly, embodiments of this application provide a computer program product, the computer program product including a computer program / instruction, which, when processed and executed, implements the above-described error handling method for the NAND FLASH controller.
[0039] This application provides an error handling method for a NAND FLASH controller. The method includes: determining the operational stage to which an error belongs during the NAND FLASH management process, wherein the operational stage includes at least one of the following: a write stage, a read stage, and an erase stage; determining the error type based on the operational stage to which the error belongs and the cause of the error; if the error type is an unrecoverable error, controlling the operating system to enter a kernel panic state; if the error type is a recoverable error, performing error handling according to the error type. This application embodiment, by locking onto the specific hardware operation stage where the error occurs, allows the system to quickly narrow down the scope of fault diagnosis. By capturing errors in stages and handling them in layers, NAND FLASH operation errors can be handled accurately and efficiently, maximizing data security and system performance; and maximizing error recovery efficiency while ensuring absolute data security. Attached Figure Description
[0040] Figure 1 This is a schematic diagram of an optional processing flow of the error handling method for the NAND FLASH controller provided in the embodiments of this application; Figure 2 This is a schematic diagram of the error handling process for DMA completion errors provided in an embodiment of this application; Figure 3 This is a detailed flowchart illustrating an error handling method for a NAND FLASH controller provided in an embodiment of this application. Figure 4 This is a schematic diagram of the composition structure of the error handling device for the NAND FLASH controller provided in the embodiments of this application; Figure 5 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation
[0041] To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings. The described embodiments should not be regarded as limitations on this application. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0042] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.
[0043] In the following description, the terms "first" and "second" are used merely to distinguish similar objects and do not represent a specific ordering of objects. It is understood that "first" and "second" may be interchanged in a specific order or sequence where permitted, so that the embodiments of this application described herein can be implemented in an order other than that illustrated or described herein.
[0044] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit this application.
[0045] The scientific terms used in the embodiments of this application are explained below.
[0046] 1) The NAND Flash Controller (NFC) is the core hardware / firmware integration module that connects the host system and the NAND Flash storage chip. It is also the "brain" of NAND Flash storage devices (such as SSDs, USB flash drives, and embedded flash memory modules). It is responsible for coordinating and managing all data interactions between the host and the NAND Flash, solving the physical limitations of the NAND Flash itself (such as limited erase / write cycles, block erase / page read / write, and susceptibility to bit errors), and providing core functions such as error handling, data scheduling, and protocol conversion, allowing the host system to use the NAND Flash as efficiently and reliably as it would use a regular storage device.
[0047] 2) Panic state is an "emergency shutdown protection" state that is actively triggered when the system encounters a fatal error that it cannot repair itself and that may lead to data corruption. When the system enters panic state, it will immediately perform the following actions: stop all executing commands (erase, write, and read are all suspended); stop responding to new operation requests; lock the hardware state to prevent erroneous operations from continuing to damage the data; report the error and trigger alarms; and remain in a shutdown state until manual intervention or restart.
[0048] 3) The Flash Translation Layer (FTL) is a core firmware / software module running in the NAND Flash Controller (NFC). It acts as both a "translator" and a "resource manager" connecting the host system's logical addresses with the NAND Flash chip's physical addresses. The host can only recognize logical addresses (such as logical block addresses), while the NAND Flash only recognizes physical addresses (such as flash block and page addresses). The FTL is responsible for mapping and converting between the two, and also handles all the associated management tasks arising from the physical characteristics of flash memory. It is one of the most crucial components of the NFC firmware.
[0049] It should be understood that in the various embodiments of this application, the sequence number of each implementation process does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.
[0050] A schematic diagram of an optional processing flow of the error handling method for a NAND FLASH controller provided in this application embodiment is shown below. Figure 1 As shown, it includes at least the following steps: Step S101: Determine the operation phase to which the error belongs in the NAND FLASH controller's management of NAND FLASH. The operation phase includes at least one of the following: write phase, read phase, and erase phase.
[0051] In some embodiments, after the NAND FLASH controller detects an error, it needs to uniquely bind it to one of the write, read, and erase stages based on the time point of the error trigger, the participating unit of the hardware failure, and the data flow status. An error belongs to only one core stage.
[0052] In some embodiments, the operation stage to which the error belongs can be determined by the time point when the error is triggered: the execution interval of which operation the error occurs in determines which stage it belongs to; for example, a NAND timeout that occurs after the erase command is sent and before the erase response is returned belongs to the erase stage.
[0053] In some embodiments, the fault can also be determined by the participating unit of the hardware failure: if a piece of hardware only participates in the operation in a specific stage, the error caused by its failure belongs to that stage; for example, if SRAM only participates in the write / read stage, the SRAM error belongs only to the write stage or the read stage, and cannot belong to the erase stage.
[0054] In some embodiments, the error can also be determined by the data flow direction: no data interaction (erase), data downlink (from NAND FLASH controller to NAND FLASH, which is data writing), and data uplink (from NAND FLASH to NAND FLASH controller, which is data reading). The operation corresponding to the data flow direction is the stage to which the error belongs (e.g., DMA completion error; if it is a DMA transfer abnormality during writing, it belongs to the writing stage; if it is a DMA transfer abnormality during reading, it belongs to the reading stage).
[0055] In some embodiments, the erase phase includes: the NAND FLASH controller sending a block erase command to the NAND FLASH to perform an erase operation on the specified physical block (the corresponding block must be erased before data is written to the NAND FLASH; erasure is a block-level operation). The hardware executing the erase phase includes: an NFC command parsing unit, a NAND FLASH block erase circuit, and a timing control unit (without DMA transfer, SRAM cache involvement, or data interaction). The erase phase is defined as the period from when the NAND FLASH controller sends the erase command until the NAND FLASH returns an erase completion / failure response; this interval constitutes the erase phase.
[0056] In some embodiments, the write phase includes: the NAND FLASH controller writes the data to be stored, sent by the host, to a designated physical page of the NAND FLASH after ECC error correction encoding and DMA transfer (page-level operation), which is a "downlink process of data from the NAND FLASH controller to the NAND FLASH". The hardware executing the write phase includes: the ECC unit of the NAND FLASH controller, the DMA controller, the SRAM cache (temporarily storing data), the instruction parsing unit, and the page programming circuitry of the NAND FLASH. The boundary of the write phase is defined as the period from when the NAND FLASH controller receives a write instruction from the host and loads the data to be written into the SRAM, until the data is transferred via DMA and the NAND FLASH returns a write completion / failure response.
[0057] In some embodiments, the read phase includes: the NAND FLASH controller sending a page read command to the NAND FLASH, transferring the data of the specified physical page via DMA, performing ECC error correction and decoding, buffering it in SRAM, and reporting it to the host; this is the "uplink process of data from NAND FLASH to NFC". Hardware components involved include: the ECC unit of the NAND FLASH controller, the DMA controller, the SRAM buffer, the response parsing unit, and the page read circuit of the NAND FLASH. The boundary of the read phase is defined as the period from when the NAND FLASH controller sends the read command until the data transfer is completed via DMA, the ECC verification is completed, and the data is returned to the host.
[0058] In this embodiment of the application, by locking the error to a specific operation stage, "indiscriminate handling of errors" can be avoided. For example, NAND timeout in the erase stage and NAND timeout in the read stage are both "NAND timeout" errors, but they occur at different stages, and the subsequent reset objects and retry logic will be different.
[0059] Step S102: Determine the error type based on the operation stage to which the error belongs and the cause of the error.
[0060] In some embodiments, if the operation stage to which the error belongs is the erase stage, and the cause of the error is a circuit failure in the NAND FLASH, which will prevent the erase operation from being completed within a specified time, then the error type is determined to be NAND timeout. If the operation stage to which the error belongs is the erase stage, and the cause of the error is damage to the NAND FLASH memory cell, then the error type is determined to be bad block; if some memory cells of the NAND FLASH are damaged during manufacturing or use, bad blocks will be formed, and an erase error will occur when performing an erase operation on the bad blocks; the error type in this case is bad block.
[0061] In other embodiments, if the operation phase to which the error belongs is the write phase, and the cause of the error is a write operation timeout, then the error type is determined to be NAND timeout. Specifically, a write operation timeout may occur if the NAND flash malfunctions or if interference occurs during data transmission.
[0062] If the error pertains to a write operation and the cause is the inability to generate a Direct Memory Access (DMA) completion signal, then the error type is determined to be a DMA completion error. Specifically, within the NAND flash controller, data is transferred via DMA. A DMA completion signal is generated upon completion of the DMA transfer. If an anomaly occurs during the DMA transfer process, such as a DMA controller failure or data transmission path interruption, the DMA completion signal cannot be generated correctly, thus triggering a DMA completion error.
[0063] In some other embodiments, if the operation stage to which the error belongs is the read stage, and the cause of the error is a read operation timeout, then the error type is determined to be NAND timeout. Specifically, when reading data from NAND FLASH, if there is a problem with the NAND FLASH read circuit, or if the stored data is corrupted, it may cause the read operation to time out, resulting in a NAND timeout error.
[0064] If the error pertains to the read phase of the operation, and the cause of the error is the inability to generate a DMA completion signal, then the error type is determined to be a DMA completion error. Specifically, if an anomaly occurs during DMA transfer, such as a DMA controller malfunction or data transmission path interruption, the DMA completion signal cannot be generated normally, thus triggering a DMA completion error.
[0065] If the error pertains to the read phase of the operation, and the cause of the error is a cache failure in the NAND flash controller, then the error type is determined to be a cache error. Specifically, the NAND flash controller typically uses SRAM as a cache for temporary storage of read and write data. If the SRAM fails, such as due to damaged storage cells or abnormal read / write control circuitry, errors will occur in the data stored in the SRAM, thus causing a cache error.
[0066] If the error pertains to the read phase of the operation, and the cause of the error is an error in the NAND FLASH controller's transmission of a response signal, then the error type is determined to be a response error. Specifically, the NAND FLASH controller interacts with other modules (such as FTL) through response signals. If interference occurs during the transmission of the response signal, or if the response signal is not correctly identified, a response error will result.
[0067] If the error pertains to the read phase of the operation, and the cause of the error is an error during the verification process, then the error type is determined to be a verification error. Specifically, during data transmission and storage, to ensure data integrity, Cyclic Redundancy Check (CRC) or Error Correction Code (ECC) techniques are typically used to verify the data. If an error is detected during the verification process, it will cause a verification error.
[0068] If the operation phase to which the error belongs is the read phase, and the cause of the error is reading a blank page, then the error type is determined to be a blank page error. Specifically, when the NAND FLASH controller reads data from the NAND FLASH, if it reads a blank page (i.e., a page that has not been written with data), a blank page error will occur.
[0069] Step S103: If the error type is an unrecoverable error, then control the operating system to enter a kernel panic state.
[0070] In some embodiments, cache errors and response errors are unrecoverable errors; if the error type is a cache error or a response error, the operating system is controlled to enter a panic state. Specifically, the cause of cache errors and response errors is a problem or error in other modules besides the NAND FLASH controller. The NAND FLASH controller cannot locate the specific cause of the error, therefore, the operating system is controlled to enter a panic state to allow for timely manual troubleshooting and repair.
[0071] Step S104: If the error type is a recoverable error, then perform error handling according to the error type.
[0072] In this embodiment, errors caused by the NAND FLASH controller itself, other than cache errors and response errors, are all recoverable errors.
[0073] In some embodiments, during the erase phase, if the error type is a NAND timeout error, a reset operation is performed on the logical cells of the NAND FLASH. Specifically, a NAND LUN (logical cell number) reset operation can be performed to reset the faulty logical cell; after the reset is completed, the erase operation on the target block is re-executed to verify whether the erase function has been restored.
[0074] During the erase phase, if the error type is a bad block error, the NAND FLASH controller reports the bad block information to the FTL; so that the FTL updates the bad block table, marks the block as unusable, allocates a spare physical block to replace the faulty bad block, migrates the original block (if there is valid data) to the spare block, and then re-executes the erase / service operation.
[0075] In other embodiments, during the write phase, if the error type is a NAND timeout error, a NAND LUN reset operation is performed to reset the corresponding NAND FLASH logic cell; after the reset is completed, the write operation of the target data is re-executed to verify whether the write function has been restored.
[0076] During the write phase, if the error type is DMA completion error, a complete NAND FLASH controller reset operation is performed to restore the controller to normal working state. Since NAND FLASH cannot skip word lines (WL) during writing, the incomplete write command is marked as an error and returned to FTL. To avoid data loss, the erase and write command is repeated after the reset to ensure that the data is written correctly.
[0077] In some other embodiments, during the read phase, if the error type is a NAND timeout error, a NAND LUN reset operation is performed to reset the faulty logic unit; after the reset is completed, a reread operation is performed to reread data from the target physical page to verify whether the read function has been restored.
[0078] During the read phase, if the error type is DMA completion error, a complete NAND FLASH controller reset operation is performed to restore the controller to normal working state; if there are incomplete read commands, the read command is re-executed directly after the reset to complete the reread operation.
[0079] During the read phase, if the error type is a verification error, a three-level recovery process is executed: Level 1: A software decoding operation is performed on the erroneous data, attempting to correct the error using a software algorithm. If the correction is successful, subsequent processing continues. Level 2: If the software decoding fails, a retry all operation is performed, retrying all related data transmission and verification operations. Level 3: If retry all still fails, the error information is reported to the FTL, which initiates a RAID recovery operation to reconstruct the damaged data using redundant data and restore its integrity.
[0080] During the read phase, if the error type is a page null error, the NAND FLASH controller reports the page null error information to the FTL; the FTL relocates the correct physical page of the target data through the address mapping table; the FTL instructs the NAND FLASH controller to perform a reread operation based on the new physical address to obtain valid data.
[0081] In this application embodiment, a schematic diagram of the error handling process for DMA completion errors is shown, as follows: Figure 2 As shown, Step S201: Perform a reset operation on the NAND FLASH controller.
[0082] In some embodiments, the NFC controller is restored to normal operation by performing a reset operation on the NAND FLASH controller.
[0083] Step S202: Determine whether the read command or write command has been completed.
[0084] In some embodiments, if the read command is not completed, step S203 is executed. If the write command is not completed, step S204 is executed.
[0085] Step S203: Re-execute the read command operation.
[0086] Step S204: Re-execute the write command operation, mark the write command as an error, and return it to FTL.
[0087] In some embodiments, because NAND FLASH write operations have the characteristic of not skipping word lines (WL), to avoid data inconsistency caused by WL not being written, the write command is directly marked as an error and returned to the FTL after the NAND FLASH controller is reset. Simultaneously, to prevent data loss, the write command is repeated after the NAND FLASH controller is reset to ensure that data can be correctly written to the NAND FLASH.
[0088] In this embodiment, all errors are categorized into recoverable and unrecoverable errors based on whether they can be recovered through collaborative operation of the NAND FLASH controller itself or other external modules (such as FTL). Cache errors and response errors are unrecoverable, while the remaining errors are recoverable. For different error types, NAND timeout errors only require a partial NAND LUN reset (only for the faulty flash logic cell); DMA completion errors require a complete NAND FLASH controller reset (for the NAND FLASH controller itself). The reset granularity is precisely matched to the cause of the fault.
[0089] For bad block errors, empty page errors, and check errors, FTL needs to participate in the collaborative processing, which reflects the error handling closed loop that combines the low-level detection of the NAND FLASH controller and the upper-level recovery of FTL.
[0090] For cache errors and response errors that cannot be traced and will inevitably lead to data corruption if continued operation is carried out, a panic state is triggered to prevent the error from spreading and to prioritize data protection.
[0091] In this embodiment, the NAND FLASH controller may also experience a stuck state. To promptly detect and handle such situations, the system or NAND FLASH employs a command logging mechanism. Each command sent to the NAND FLASH controller is recorded in a command table. The record in the command table includes the command type (e.g., erase command, write command, read command, etc.) and a timestamp (recording the time the command was sent). In this way, the execution status of each command can be clearly tracked.
[0092] In some embodiments, the system can also add a check process to periodically check the commands in the command table. During the check, it determines whether a command has timed out based on its type and a preset timeout threshold. If a timeout record is found, a NAND FLASH controller reset operation is performed to restore the NAND FLASH controller to its normal operating state. The same process is used to handle DMA completion errors, i.e., after reset, appropriate operations such as rereading or marking errors are performed based on the command type.
[0093] This application embodiment uses a command table to record commands and a timeout check mechanism, which can promptly detect errors such as NAND FLASH controller jamming and quickly take processing measures such as NAND FLASH controller recovery, thereby reducing the impact of errors on storage device performance and improving error handling efficiency.
[0094] The following example illustrates the detailed processing flow of the NAND FLASH controller error handling method provided in this application embodiment, using a DMA completion error that occurs during data reading by the NAND FLASH controller as an example. Figure 3 As shown, it includes at least the following steps: In step S301, the storage device sends a command to the NAND FLASH controller to read data, and the storage device records the command in the command table.
[0095] In some embodiments, the command table records the command type as "read command" and also records the timestamp of the read command being sent.
[0096] In step S302, the NAND FLASH controller confirms a DMA completion error when performing a data read operation.
[0097] In some embodiments, when the NAND FLASH controller performs a data read operation, it detects an anomaly in the DMA transfer, causing the DMA completion signal to fail to be generated normally, thereby causing a DMA completion error.
[0098] In step S303, the NAND FLASH controller returns error status information to the storage device.
[0099] Step S304: The storage device determines the error type as a DMA completion error.
[0100] In some embodiments, the driver in the storage device determines the operation phase as a read phase and determines the error type as a DMA completion error based on the error status information.
[0101] In step S305, the storage device performs error handling based on the error type.
[0102] In some instances, the storage device generates a NAND LUN reset command and sends it to the NAND FLASH controller to reset the controller. It then checks the command table for any incomplete read commands. If the read command is incomplete, the error handling module re-executes it, performing a re-read operation to retrieve data from the storage device. After the re-read operation is complete, the storage device receives a normal response signal from the NAND FLASH controller, at which point the record for the read command is deleted from the command table.
[0103] The storage device described in this application embodiment can be any storage device using NAND FLASH storage medium. The hardware architecture of the storage device typically includes a main control chip, NAND FLASH storage chips, SRAM cache, etc. The main control chip integrates a NAND FLASH controller, which is responsible for controlling the operation of the NAND FLASH.
[0104] In this application embodiment, various errors that may occur during the operation of NAND FLASH by the NAND FLASH controller are classified in detail to ensure comprehensive coverage of various error scenarios and improve the reliability of the storage device. Different handling measures are adopted for each error type to guarantee data security and integrity.
[0105] This invention provides an error handling device for a NAND FLASH controller. A schematic diagram of the device's structure is shown below. Figure 4 As shown, it includes at least: The first determining module 501 is used to determine the operation stage to which the error belongs in the process of the NAND FLASH controller managing the NAND FLASH, wherein the operation stage includes at least one of the following: a write stage, a read stage, and an erase stage; The second determining module 502 is used to determine the error type based on the operation stage to which the error belongs and the cause of the error. The control module 503 is used to control the operating system to enter a panic state if the error type is an unrecoverable error. The processing module 504 is used to perform error processing according to the error type if the error type is a recoverable error.
[0106] In some embodiments, the second determining module 502 is specifically used to determine the error type as NAND timeout if the operation stage to which the error belongs is the erase stage and the cause of the error is a circuit fault in the NAND FLASH. If the operation stage to which the error belongs is the erase stage, and the cause of the error is damage to the NAND FLASH storage cell, then the error type is determined to be a bad block.
[0107] In some embodiments, the second determining module 502 is specifically used to determine the error type as NAND timeout if the operation stage to which the error belongs is the write stage and the cause of the error is a write operation timeout; If the operation stage to which the error belongs is the write stage, and the cause of the error is the inability to generate a direct memory access (DMA) completion signal, then the error type is determined to be a DMA completion error.
[0108] In some embodiments, the second determining module 502 is specifically used to determine the error type as NAND timeout if the operation stage to which the error belongs is the read stage and the cause of the error is a read operation timeout; If the operation stage to which the error belongs is the read stage, and the cause of the error is the inability to generate a DMA completion signal, then the error type is determined to be a DMA completion error.
[0109] In some embodiments, the second determining module 502 is specifically used to determine the error type as a cache error if the operation stage to which the error belongs is the read stage and the cause of the error is a cache failure of the NAND FLASH controller; If the operation stage to which the error belongs is the read stage, and the cause of the error is an error in the transmission of the response signal by the NAND FLASH controller, then the error type is determined to be a response error.
[0110] In some embodiments, the second determining module 502 is specifically used to determine the error type as a verification error if the operation stage to which the error belongs is the reading stage and the cause of the error is an error in the verification process; If the operation stage to which the error belongs is the reading stage, and the cause of the error is reading an empty page, then the error type is determined to be an empty page error.
[0111] In some embodiments, the processing module 504 is specifically configured to perform a reset operation on the logic cells of the NAND FLASH if the error type is NAND timeout.
[0112] In some embodiments, the processing module is specifically configured to perform a reset operation on the NAND FLASH controller if the error type is a DMA completion error.
[0113] In some embodiments, the processing module 504 is specifically used to re-execute the read operation if the read operation has not been completed. If the write operation is not completed, the write operation is marked as a write operation error, and the write command corresponding to the write operation is sent to the FTL; the erase and write command for the write operation is executed repeatedly.
[0114] In some embodiments, the processing module is specifically used to send the error information corresponding to the empty page error to the FTL if the error type is an empty page error, so that the FTL performs a reread operation based on the error information.
[0115] In some embodiments, the processing module 504 is specifically used to perform a soft decoding operation on the erroneous data if the error type is a verification error; If the software decoding operation fails, all data will be retransmitted and re-verified. If the verification fails again, an error message is sent to the FTL so that the FTL can perform a data recovery operation.
[0116] In some embodiments, the control module 503 is specifically used to control the operating system to enter a panic state if the error type is a cache error or a response error.
[0117] This application provides an electronic device, and a schematic diagram of the structure of the electronic device is shown below. Figure 5 As shown, the device includes a processor 410 and a memory 450 communicatively connected to the processor 410. The electronic device also includes a bus 440; various modules of the electronic device are coupled together via the bus 440. Multiple processors may be included. It is understood that the bus 440 is used to implement communication between these modules. In addition to a data bus, the bus 440 also includes a power bus, a control bus, and a status signal bus. However, for clarity, in… Figure 5 The general labeled all buses as Bus 440.
[0118] The processor 410 has signal processing capabilities, such as a general-purpose processor, a digital signal processor (DSP), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware models, etc., wherein the general-purpose processor can be a microprocessor or any conventional processor, etc.
[0119] The memory 450 stores executable instructions for implementing the error handling method of the NAND FLASH controller provided in the embodiments of this application; the memory 450 may be removable, non-removable, or a combination thereof. Exemplary hardware devices include solid-state memory, hard disk drives, optical disk drives, etc. The memory 450 may optionally include one or more storage devices physically located away from the processor core 410.
[0120] In some embodiments, memory 450 is capable of storing data to support various operations, examples of which include programs, modules, and data structures or subsets or supersets thereof.
[0121] In some embodiments, the electronic device may further include: Operating system 451 includes system programs for handling various basic system services and performing hardware-related tasks, such as the framework layer, core library layer, driver layer, etc., for implementing various basic business functions and handling hardware-based tasks; The network communication module 452 is used to reach other computing devices via one or more (wired or wireless) network interfaces 420, exemplary network interfaces 420 including Bluetooth, WiFi, and Universal Serial Bus (USB).
[0122] This application provides a computer-readable storage medium storing executable instructions. When these executable instructions are executed by a processor, they trigger the processor to execute the error handling method for the NAND flash controller provided in this application. For example, ... Figures 1 to 3 The error handling method for the NAND FLASH controller is shown.
[0123] In some embodiments, the computer-readable storage medium may be a ferroelectric random access memory (FRAM), a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), flash memory, magnetic surface memory, optical disc, or CD-ROM, etc.; or it may be a device that includes one or any combination of the above-mentioned memories.
[0124] In some embodiments, executable instructions may take the form of a program, software, software module, script, or code, written in any form of programming language (including compiled or interpreted languages, or declarative or procedural languages), and may be deployed in any form, including as a standalone program or as a module, model, subroutine, or other unit suitable for use in a computing environment.
[0125] As an example, executable instructions can be deployed to execute on a single computing device, or on multiple computing devices located in one location, or on multiple computing devices distributed across multiple locations and interconnected via a communication network.
[0126] This application provides a computer program product, which includes a computer program / instruction. When the computer program / instruction is executed by a processor, it implements the error handling method for the NAND FLASH controller described in this application.
[0127] The above are merely embodiments of this application and are not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions, and improvements made within the spirit and scope of this application are included within the scope of protection of this application.
Claims
1. A method for handling errors in a NAND FLASH controller, characterized in that, The method includes: Determine the operational phase to which the error belongs during the NAND FLASH controller's management of NAND FLASH, wherein the operational phase includes at least one of the following: write phase, read phase, and erase phase; The error type is determined based on the operational stage to which the error belongs and the cause of the error. If the error type is an unrecoverable error, then control the operating system to enter a kernel panic state; If the error type is a recoverable error, then error handling shall be performed according to the error type.
2. The method according to claim 1, characterized in that, Determining the error type based on the operational stage to which the error belongs and the cause of the error includes: If the operation stage to which the error belongs is the erase stage, and the cause of the error is a circuit failure of the NAND FLASH, then the error type is determined to be NAND timeout; If the operation stage to which the error belongs is the erase stage, and the cause of the error is damage to the NAND FLASH storage cell, then the error type is determined to be a bad block.
3. The method according to claim 1, characterized in that, Determining the error type based on the operational stage to which the error belongs and the cause of the error includes: If the operation phase to which the error belongs is the write phase, and the cause of the error is a write operation timeout, then the error type is determined to be NAND timeout. If the operation stage to which the error belongs is the write stage, and the cause of the error is the inability to generate a direct memory access (DMA) completion signal, then the error type is determined to be a DMA completion error.
4. The method according to claim 1, characterized in that, Determining the error type based on the operational stage to which the error belongs and the cause of the error includes: If the operation phase to which the error belongs is the read phase, and the cause of the error is a read operation timeout, then the error type is determined to be NAND timeout. If the operation stage to which the error belongs is the read stage, and the cause of the error is the inability to generate a DMA completion signal, then the error type is determined to be a DMA completion error.
5. The method according to claim 1, characterized in that, Determining the error type based on the operational stage to which the error belongs and the cause of the error includes: If the operation stage to which the error belongs is the read stage, and the cause of the error is a cache failure in the NAND FLASH controller, then the error type is determined to be a cache error. If the operation stage to which the error belongs is the read stage, and the cause of the error is an error in the transmission of the response signal by the NAND FLASH controller, then the error type is determined to be a response error.
6. The method according to claim 1, characterized in that, Determining the error type based on the operational stage to which the error belongs and the cause of the error includes: If the operation stage to which the error belongs is the reading stage, and the cause of the error is an error in the verification process, then the error type is determined to be a verification error. If the operation stage to which the error belongs is the reading stage, and the cause of the error is reading an empty page, then the error type is determined to be an empty page error.
7. The method according to claim 1, characterized in that, If the error type is a recoverable error, then error handling is performed according to the error type, including: If the error type is NAND timeout, then a reset operation is performed on the logic cell of the NAND FLASH.
8. The method according to claim 1, characterized in that, If the error type is a recoverable error, then error handling is performed according to the error type, including: If the error type is DMA completion error, then a reset operation is performed on the NAND FLASH controller.
9. The method according to claim 8, characterized in that, After performing a reset operation on the NAND FLASH controller, the method further includes: If the read operation is not completed, the read operation will be re-executed; If the write operation is not completed, the write operation is marked as a write operation error, and the write command corresponding to the write operation is sent to the flash translation layer (FTL); the erase and write commands for the write operation are executed repeatedly.
10. The method according to claim 1, characterized in that, If the error type is a recoverable error, then error handling is performed according to the error type, including: If the error type is a page null error, the error information corresponding to the page null error is sent to the FTL so that the FTL can perform a reread operation based on the error information.
11. The method according to claim 1, characterized in that, If the error type is a recoverable error, then error handling is performed according to the error type, including: If the error type is a verification error, then a soft decoding operation is performed on the erroneous data; If the software decoding operation fails, all data will be retransmitted and re-verified. If the verification fails again, an error message is sent to the FTL so that the FTL can perform a data recovery operation.
12. The method according to claim 1, characterized in that, If the error type is an unrecoverable error, then controlling the operating system to enter a kernel panic state includes: If the error type is a cache error or a response error, control the operating system to enter a panic state.
13. An error handling device for a NAND FLASH controller, characterized in that, The device includes: The first determining module is used to determine the operation phase to which the error belongs in the process of the NAND FLASH controller managing the NAND FLASH, wherein the operation phase includes at least one of the following: write phase, read phase, and erase phase; The second determining module is used to determine the error type based on the operation stage to which the error belongs and the cause of the error. The control module is used to control the operating system to enter a kernel panic state if the error type is an unrecoverable error. The processing module is used to perform error processing according to the error type if the error type is a recoverable error.
14. An electronic device, characterized in that, The electronic device includes: A processor and a memory communicatively connected to the processor; wherein, The processor memory stores instructions that can be executed by the processor to enable the processor to perform the error handling method of the NAND FLASH controller according to any one of claims 1 to 12.
15. A computer-readable storage medium, characterized in that, It stores executable instructions for implementing the error handling method of the NAND FLASH controller as described in any one of claims 1 to 12 when executed by a processor.
16. A computer program product, characterized in that, The computer program product includes a computer program / instruction that, when executed by a processor, implements the error handling method for a NAND FLASH controller as described in any one of claims 1 to 12.