Processor instruction fetch system and instruction fetch address processing method

Abstract

The present disclosure relates to a processor instruction fetching system and an instruction fetching address processing method, and relates to the technical field of computers, which realizes simple implementation and strong universality by judging and storing an instruction loop body through an instruction fetching address. The processor instruction fetching system comprises a processor core, a hit judgment module and a cache, wherein the processor core is connected with the hit judgment module and the cache, and the hit judgment module is connected with the cache; the cache comprises a loop detection unit, a control unit and a storage unit.

Description

Technical Field

[0001] This disclosure relates to the field of computer technology, and more specifically, to a processor instruction fetching system and an instruction fetch address processing method. Background Technology

[0002] In related technologies, processors fetch instructions from the instruction cache. To detect instruction loop bodies, it's typically necessary to first decode the instruction, then determine the loop start and end addresses based on the instruction type and jump target address, increasing the latency of instruction loop body detection. Different instruction sets have different definitions of branch instructions, further increasing the difficulty and complexity of loop body detection and limiting its versatility. Furthermore, storing instruction address information, instruction tags, and other data occupies a significant area and consumes considerable power. Summary of the Invention

[0003] To address the shortcomings of related technologies, this disclosure provides a processor instruction fetching system and an instruction fetch address processing method.

[0004] To achieve the above objectives, in a first aspect, this disclosure provides a processor instruction fetching system, comprising: The processor core, the hit detection module, and the cache are provided, wherein the processor core is connected to the hit detection module and the cache, and the hit detection module is connected to the cache; the cache includes a loop detection unit, a control unit, and a storage unit. The loop detection unit is used to detect address bounce based on the fetch address sent by the processor core, and to determine the instruction loop body based on the address bounce result. The instruction loop body represents a set of a certain number of instructions to be executed cyclically. The storage unit is used to store at least a portion of the instructions in the instruction loop body; The hit determination module is used to determine whether the current fetch address sent by the processor core hits the memory unit; The control unit is used to return the instruction corresponding to the fetch address in the memory unit to the processor core when the hit determination module determines that the current fetch address sent by the processor core hits the memory unit.

[0005] Secondly, this disclosure provides an instruction fetch address processing method applied to a processor instruction fetch system, the processor instruction fetch system including a processor core, a hit determination module, and a cache, wherein the processor core is connected to the hit determination module and the cache, and the hit determination module is connected to the cache; The instruction fetch address processing method includes: The address bounce is detected based on the fetch address sent by the processor core, and the instruction loop body is determined based on the address bounce result. The instruction loop body represents a set of a certain number of instructions to be executed cyclically. At least a portion of the instructions in the instruction loop body are stored in the storage unit of the cache; When the hit determination module determines that the current fetch address sent by the processor core hits the memory unit, it returns the instruction in the memory unit corresponding to the fetch address to the processor core.

[0006] The processor instruction fetch system, as described above, includes a processor core, a hit detection module, and a register. The processor core is connected to both the hit detection module and the register. The hit detection module is also connected to the register. The register's loop detection unit detects address bounces based on the fetch address sent by the processor core and determines the instruction loop body based on the bounce result. The entire instruction loop body detection process does not require instruction decoding and is unaffected by the processor's architecture, exhibiting strong versatility. The register's storage unit stores at least a portion of the instructions in the instruction loop body; that is, the register only stores the instructions themselves, saving cache space and reducing power consumption. The register's control unit, when the hit detection module determines that the current fetch address sent by the processor core hits a storage unit, returns the instruction corresponding to the fetch address in the storage unit to the processor core. Compared to related technologies that decode and execute instructions, this disclosure simplifies the entire process, eliminates the need for complex decoding, shortens fetch time, reduces latency, and only requires storing part or all of the instructions in the instruction loop body, resulting in smaller area overhead and lower fetch power consumption.

[0007] Other features and advantages of this disclosure will be described in detail in the following detailed description section. Attached Figure Description

[0008] The accompanying drawings are provided to further illustrate the present disclosure and form part of the specification. They are used together with the following detailed description to explain the present disclosure, but do not constitute a limitation thereof. In the drawings: Figure 1a This is a schematic diagram of the structure of an existing microprocessor.

[0009] Figure 1b This is a schematic diagram of an existing microprocessor-readable memory hierarchy.

[0010] Figure 2 This is a flowchart illustrating an instruction fetch address processing method according to an exemplary embodiment of the present disclosure.

[0011] Figure 3 This is a flowchart illustrating another instruction fetch address processing method according to an exemplary embodiment of the present disclosure.

[0012] Figure 4 This is a flowchart illustrating yet another instruction fetch address processing method according to an exemplary embodiment of the present disclosure.

[0013] Figure 5 This is a schematic diagram of the structure of a processor instruction fetching system according to an exemplary embodiment of the present disclosure.

[0014] Figure 6 A schematic diagram of the structure of a storage cell is shown according to an exemplary embodiment of this disclosure.

[0015] Figure 7 This is a schematic diagram of the structure of another processor instruction fetching system according to an exemplary embodiment of the present disclosure.

[0016] Figure 8 This is a schematic diagram illustrating the data flow of a buffer according to an exemplary embodiment of the present disclosure.

[0017] Figure 9 This is a storage schematic diagram of a storage unit according to an exemplary embodiment of the present disclosure.

[0018] Figure 10 This is a storage schematic diagram of another storage unit shown according to an exemplary embodiment of the present disclosure.

[0019] Figure 11 This is a storage schematic diagram of another storage unit shown according to an exemplary embodiment of the present disclosure. Detailed Implementation

[0020] The specific embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustration and explanation only and are not intended to limit this disclosure.

[0021] As mentioned in the background section, in the related art, Chinese patent publication number CN104516829B discloses a microprocessor and a method for using an applicable instruction loop cache, such as... Figure 1aAs shown, this microprocessor includes a Central Processing Unit Core (CPU Core), an instruction cache, main memory, and auxiliary memory. When the microprocessor needs to fetch an instruction, its CPU Core sends the fetch address of the instruction to the instruction cache. The fetch address corresponds to the instruction stream, which includes one or more instructions. If the instruction is stored in the instruction cache, the instruction cache directly provides the instruction to the CPU Core. Otherwise, the instruction cache fetches the instruction from the memory where the instruction resides (main memory or auxiliary memory), stores it, and then provides the instruction to the CPU Core.

[0022] It is understandable that, such as Figure 1b As shown, the types of memory that the CPU can directly or indirectly access, arranged in a typical hierarchical structure from fastest to slowest speed, smallest to largest capacity, and highest to lowest cost, include: registers, cache (such as cache memory), main memory (RAM), secondary storage (such as disks), and special and emerging storage (external storage, such as magnetic tapes and optical discs). The cache can be divided into four levels, in descending order of speed: L1 Cache, L2 Cache, L3 Cache, and L4 Cache.

[0023] The inventors discovered that, in the related technologies, accessing the instruction loop involves two aspects: instruction loop body monitoring and instruction loop body storage.

[0024] I. The following technical defects exist regarding instruction loop body monitoring: 1. After reading the instruction, it is necessary to decode and judge the instruction. Based on whether the instruction is a branch instruction or a jump instruction, the start address and end address of the instruction loop body are determined. This is dependent on the instruction set, has poor versatility, large area overhead, and large latency.

[0025] 2. Monitoring instruction loop bodies is complex. The complexity of judging the type of branch instructions (such as unconditional branches, conditional branches, and indirect branches) and predicting branches (forward jumps and backward jumps) increases the difficulty and complexity of detecting instruction loop bodies, and also leads to a large judgment area overhead.

[0026] 3. The monitoring process of the instruction loop body requires deep interaction with the processor's processing pipeline, which increases the design coupling and complexity of the processor and instruction cache.

[0027] II. The following technical defects exist regarding the storage of instruction loop bodies: 1. The decoded instructions need to be stored, including but not limited to instruction type, micro-opcode, operand register, and destination register. This results in large storage requirements, significant area overhead, and high power consumption. Furthermore, some decoded instructions also require storing the arithmetic unit number used for instruction execution, as well as the way number in the set-associative instruction cache, etc.

[0028] 2. It requires storing instruction tags, which increases the area overhead.

[0029] 3. There are length restrictions on the instruction loop body.

[0030] In view of this, this disclosure provides a processor instruction fetching system and an instruction fetch address processing method. The instruction fetch address processing method provided in this disclosure will be described first.

[0031] Figure 2 This is a flowchart illustrating an instruction fetch address processing method according to an exemplary embodiment of the present disclosure. The instruction fetch address processing method is applied to a processor instruction fetch system, which includes a processor core, a hit determination module, and a register. The processor core is connected to the hit determination module and the register, and the hit determination module is connected to the register. like Figure 2 As shown, the instruction fetch address processing method may include: In step S11, address bounce is detected based on the fetch address sent by the processor core, and the instruction loop body is determined based on the address bounce result. The instruction loop body represents a set of a certain number of instructions to be executed cyclically.

[0032] In step S12, at least a portion of the instructions in the instruction loop body are stored in the storage unit of the cache.

[0033] In step S13, when the hit determination module determines that the current fetch address sent by the processor core hits the memory unit, the instruction corresponding to the fetch address in the memory unit is returned to the processor core.

[0034] In this embodiment, within the current clock cycle, address backtracking detection is performed based on the fetch address (i.e., the program counter, PC) sent by the processor core. The instruction loop body is determined based on the address backtracking result, and some or all of the instructions in the instruction loop body are stored in the loop buffer. When the hit detection module determines that the fetch address sent by the processor core hits the buffer, the instruction corresponding to the current fetch address in the buffer is returned to the processor core, completing the fetch operation.

[0035] In the above technical solution, the processor instruction fetch system includes a processor core, a hit detection module, and a register. The processor core is connected to the hit detection module and the register, and the hit detection module is connected to the register. The register's loop detection unit detects address bounce based on the fetch address sent by the processor core and determines the instruction loop body based on the address bounce result. The entire instruction loop body detection process does not require instruction decoding and is not affected by the processor's own architecture, thus exhibiting strong versatility. The storage unit in the register is used to store at least a portion of the instructions in the instruction loop body; that is, the register only stores the instructions themselves, saving cache space and reducing power consumption. The control unit in the register is used to return the instruction corresponding to the fetch address in the storage unit to the processor core when the hit detection module determines that the current fetch address sent by the processor core hits the storage unit. Compared with related technologies that decode and execute instructions for judgment and bounce, the entire process of this disclosure is simple to implement, does not require complex decoding processing, shortens the instruction fetch time, reduces latency, and only needs to store part or all of the instructions in the instruction loop body, resulting in smaller area overhead and lower instruction fetch power consumption.

[0036] To facilitate a better understanding of the instruction fetch address processing method provided in this disclosure by those skilled in the art, the instruction fetch address processing method will be described in detail below.

[0037] In one feasible embodiment, the buffer includes a loop detection unit, which includes a first register, a second register, a third register, a loop start address register, a loop end address register, and a back bounce detector; This instruction fetch address processing method may also include: The address of the last instruction fetch sent by the processor core is stored in the first register; When the bounce detector detects a new potential instruction loop body based on the address bounce result, it stores the current instruction fetch address as the bounce target address in the second register; When the bounce detector detects a new potential instruction loop body based on the address bounce result, it stores the previous instruction fetch address as the bounce address in the third register; The bounce detector also includes a counter, and the instruction fetch address processing method may further include: When the bounce detector detects a bounce at the same address, the bounce counter is incremented by one. When a bounce at a different address is detected, the counter is reset. A bounce at the same address means that the current fetch address is the same as the bounce target address and the previous fetch address is the same as the bounce address. When the bounce count of the counter exceeds a preset value, the bounce target address is determined as the loop start address and stored in the loop start address register, and the bounce address is determined as the loop end address and stored in the loop end address register. The preset value can be configured according to instruction fetch requirements or cache requirements, and this disclosure does not limit it.

[0038] In this embodiment, the first register can be an instruction fetch address register, which stores the instruction fetch address previously sent by the processor core. Each time the processor core sends an instruction fetch address, it updates the instruction fetch address register, overwriting the previously stored fetch address, preparing for address bounce detection. The second register can be a bounce target address register, and the third register can be a bounce address register. When the bounce detector detects a new potential instruction loop based on the address bounce result, it stores the current instruction fetch address as the bounce target address in the bounce target address register and the previous instruction fetch address as the bounce address in the bounce address register. The counter can be a bounce counter, used to count when the bounce detector detects an address bounce. For example, when it detects that the current instruction fetch address is the same as the bounce target address and the previous instruction fetch address is the same as the bounce address, the bounce counter is incremented by one. When it detects that the current instruction fetch address is different from the bounce target address or the previous instruction fetch address is different from the bounce address, the bounce counter is reset. Resetting includes setting the bounce counter to 1 or 0.

[0039] It's worth noting that when the bounce detector detects a new potential instruction loop body based on the address bounce result, it needs to update the bounce target address in the bounce target address register and the bounce address in the bounce address register, and further determine whether the new potential instruction loop body is indeed an instruction loop body by combining this with a preset value. If the bounce count of the bounce counter is greater than the preset value, the detected new potential instruction loop body is determined to be an instruction loop body, and the loop start address register and loop end address register need to be updated. At this time, the bounce target address is stored as the loop start address of the instruction loop body in the loop start address register, and the bounce address is stored as the loop end address of the instruction loop body in the loop end address register. If the bounce count of the bounce counter is less than or equal to the preset value, then the loop start address in the loop start address register and the loop end address in the loop end address register are not updated. Therefore, the bounce target address and the loop start address can be the same or different, and the bounce address and the loop end address can also be the same or different.

[0040] In the above technical solution, it is determined whether a new potential instruction loop body has been detected by judging whether the current fetch address in the fetch address register is the same as the jump target address in the jump target address register, and whether the previous fetch address in the fetch address register is the same as the jump address in the jump address register. When a new potential instruction loop body is detected, the counter in the jump detector is used to further determine whether the new potential instruction loop body is indeed an instruction loop body, and the loop start address and loop end address of the instruction loop body are stored in the loop start address register and loop end address register, respectively. The entire process does not require complex decoding and judgment of the instructions, is not affected by the processor's own architecture, and has strong versatility. Moreover, the cache only stores at least a portion of the instructions in the instruction loop body, and only stores the instructions themselves, without storing the data after the instructions are decoded, saving cache space and reducing power consumption.

[0041] In one feasible embodiment, the instruction fetch address processing method may further include: If the loop start address is not stored in the loop start address register and the loop end address is not stored in the loop end address register, and if the current fetch address is less than the previous fetch address, and the current fetch address is different from the jump target address in the second register and / or the previous fetch address is different from the jump address in the third register, then a new potential instruction loop body is detected.

[0042] If the current fetch address is less than the previous fetch address, it indicates that a bounce has been detected. In this case, it is necessary to further combine the current fetch address and / or the previous fetch address to determine whether a new potential instruction loop body has been detected, so as to update the instruction addresses stored in the second and third registers.

[0043] It should be understood that if the loop start address register does not store the loop start address and the loop end address register does not store the loop end address, it indicates that the loop detection unit may not have detected the instruction loop body based on the fetch address, but it may have detected a potential instruction loop body. Therefore, the loop start address register and the loop end address register are empty, but the jump target address register and the jump address register may store the jump target address and the jump address. In this case, if the current fetch address is less than the previous fetch address, the current fetch address is different from the jump target address, and / or the previous fetch address is different from the jump address, then it is determined that a new potential instruction loop body has been detected.

[0044] It's worth noting that if the current fetch address is less than the previous fetch address and the current fetch address is different from the jump target address, it indicates that the jump target address of the new potential instruction loop body is greater than or less than the jump target address of the already detected potential instruction loop body, and the jump address of the new potential instruction loop body is equal to the jump address of the already detected potential instruction loop body. That is, the new potential instruction loop body may be a potential instruction loop body with the same jump address as the already detected potential instruction loop body and completely covered by the already detected potential instruction loop body; the new potential instruction loop body may also be a potential instruction loop body with the same jump address as the already detected potential instruction loop body and completely covered by the already detected potential instruction loop body.

[0045] If the current fetch address is less than the previous fetch address, and the previous fetch address is different from the jump address, it indicates that the jump address of the new potential instruction loop body is greater than or less than the jump address of the already detected potential instruction loop body, and the jump target address of the new potential instruction loop body is equal to the jump target address of the already detected potential instruction loop body. That is, the new potential instruction loop body may be a potential instruction loop body with the same jump target address as the already detected potential instruction loop body and completely covered by the already detected potential instruction loop body; the new potential instruction loop body may also be a potential instruction loop body with the same jump target address as the already detected potential instruction loop body and completely covered by the already detected potential instruction loop body.

[0046] If the current fetch address is less than the previous fetch address, and both the current fetch address and the jump target address are different, and both the previous fetch address and the jump address are different, it indicates that the jump target address of the new potential instruction loop body is greater than or less than the jump target address of the already detected potential instruction loop body, and the jump address of the new potential instruction loop body is greater than or less than the jump address of the already detected potential instruction loop body. That is, the new potential instruction loop body may be one where both the jump target address and the jump address fall within the already detected potential instruction loop body, and it is completely covered by the already detected potential instruction loop body; in this case, the already detected potential instruction loop body contains the new potential instruction loop body. Alternatively, the new potential instruction loop body may be one where neither the jump target address nor the jump address falls within the already detected potential instruction loop body, and it completely covers the already detected potential instruction loop body; in this case, the new potential instruction loop body contains the already detected potential instruction loop body.

[0047] In the above technical solution, when both the loop start address register and the loop end address register are empty, upon detecting a bounce, it is necessary to determine whether a new potential instruction loop body has been detected by considering the relationship between the current fetch address and the bounce target address in the second register, and / or the relationship between the previous fetch address and the bounce target address in the third register, thereby updating the fetch addresses in the second and third registers. If the fetch addresses in the second and third registers are updated only upon detecting a bounce, the counter's counting logic may become confused when the second and third registers store fetch addresses for different potential instruction loop bodies, leading to unreliable counter results.

[0048] In one feasible embodiment, the instruction fetch address processing method may further include: If the loop start address is stored in the loop start address register and the loop end address is stored in the loop end address register, and if the current fetch address is less than the previous fetch address, and at least one of the current fetch address or the previous fetch address is not within the range of the loop start address and the loop end address, then a new potential instruction loop body is detected.

[0049] It should be understood that if the loop start address register stores the loop start address and the loop end address register stores the loop end address, it indicates that the loop detection unit has detected the instruction loop body based on the fetch address, and the loop start address and loop end address of the instruction loop body have been stored in the corresponding loop start address register and loop end address register. At this point, if the current fetch address is less than the previous fetch address, and at least one of the current fetch address or the previous fetch address is not within the range of the loop start address and loop end address, then it is determined that a new potential instruction loop body has been detected.

[0050] It is worth noting that when the current fetch address is not within the range of the loop start address and loop end address, it can be indicated that the jump target address of the new potential instruction loop body is less than the loop start address of the cached instruction loop body; when the current fetch address is not within the range of the loop start address and loop end address, it can be indicated that the jump address of the new potential instruction loop body is greater than the loop end address of the cached instruction loop body; when both the current fetch address and the previous fetch address are not within the range of the loop start address and loop end address, it can be indicated that the jump target address of the new potential instruction loop body is less than the loop start address of the cached instruction loop body, and the jump address of the new potential instruction loop body is greater than the loop end address of the cached instruction loop body.

[0051] Therefore, if a loop instruction body is already cached in the register, and a bounce is detected, the relationship between the fetch address and the start and end addresses of the cached loop instruction body is determined. Only if the potential loop instruction body corresponding to the detected bounce covers the cached loop instruction body will the potential loop instruction body be treated as a new potential loop instruction body. If the potential loop instruction body corresponding to the detected bounce is covered by the cached loop instruction body, it indicates that the instruction in the potential loop instruction body corresponding to the detected bounce is already stored in the register's memory. In this case, there is no need to start a counter to count the potential loop instruction body corresponding to the detected bounce, avoiding repeated checks on the instructions in the cached loop instruction body and reducing power consumption.

[0052] In one feasible embodiment, the hit determination module includes a fourth register and a fifth register, and the instruction fetch address processing method may further include: When the loop detection unit detects the instruction loop body, at least a portion of the instructions in the instruction loop body is stored in the memory unit; The address of the first instruction fetched in at least a portion of the instructions in the instruction loop body is stored as the cache start address in the fourth register; The address of the instruction fetching end of at least a portion of the instructions in the instruction loop body is stored as the cache end address in the fifth register; The processor core determines whether the current fetch address sent by the processor core hits the memory unit based on the cache start address and cache end address.

[0053] It's worth noting that the fourth register can be a cache start address register, used to store the address of the cached first instruction in the instruction loop body (cache start address); the fifth register can be a cache end address register, used to store the address of the cached last instruction in the instruction loop body (cache end address). During the caching of the instruction loop body, if the number of instructions that can be stored in the memory location is less than the detected instruction loop body, only a portion of the instructions in the instruction loop body can be stored in the memory location; if the number of instructions that can be stored in the memory location is greater than or equal to the detected instruction loop body, then all of the instructions in the instruction loop body can be stored in the memory location.

[0054] Accordingly, during the hit determination phase, if the memory location only stores a portion of the instructions in the instruction loop body, a hit determination needs to be performed based on the cache start address and cache end address before instruction fetching can proceed. Therefore, the cache start address and cache end address of the cached portion of the instructions need to be stored separately using the cache start address register and cache end address register. If the memory location stores all the instructions in the instruction loop body, then the loop start address is the same as the cache start address, and the loop end address is the same as the cache end address. Similarly, a hit determination can be performed based on the cache start address and cache end address before instruction fetching can proceed.

[0055] It should be understood that if the fetch address is less than or equal to the cache end address stored in the fourth register, and greater than or equal to the cache start address, it indicates that the fetch address sent by the processor core is within the range between the loop start address and the loop end address. In this case, it is determined that the fetch address hits the memory cell, and the instruction corresponding to the fetch address is read from the memory cell and returned to the processor core.

[0056] In the above technical solution, the instruction fetch address is compared to determine whether the instruction fetch address is within the range of the cache start address and the cache end address to determine whether the instruction fetch address has been hit. The whole process does not require instruction parsing, which is simple to implement. It also does not require storing the decoded instruction information, has low area overhead, strong versatility, and is not affected by the CPU's own architecture.

[0057] It is worth noting that the new instruction loop body and the stored instruction loop body may have the following situations: Situation 1, the new instruction loop body and the stored instruction loop body belong to two completely different instruction loop bodies; Situation 2, the new instruction loop body and the stored instruction loop body have instruction overlap.

[0058] In case one, the new instruction loop body and the stored instruction loop body are two completely different instruction loop bodies.

[0059] In one feasible embodiment, the instruction fetch address processing method may further include: If at least a portion of the instructions in the instruction loop body already exists in the memory cell, and a new instruction loop body is detected, it is determined whether there is an overlapping address between the first address range corresponding to the at least a portion of the instructions in the instruction loop body and the second address range corresponding to the new instruction loop body. If there are no overlapping addresses, clear all instructions of the instruction loop body stored in the memory cell and write at least part of the instructions of the new instruction loop body into the memory cell.

[0060] It should be understood that because the start and end addresses of the instruction loop body are different, as are the execution conditions and number of times the loop body is executed, the detection of the instruction loop body is continuous and ongoing. After the detection of the current instruction loop body is completed based on the fetch address sent by the processor core, the detection of the instruction loop body continues based on the subsequent fetch addresses sent by the processor core. At least some of the instructions in the current instruction loop body will be stored in the memory unit. If a new instruction loop body is detected, and the new instruction loop body and the previous instruction loop body are two completely different instruction loop bodies, then the previous instruction loop body is invalidated, and at least some of the instructions in the new instruction loop body are stored in the cache memory space.

[0061] For example, when the current fetch address sent by the processor core is less than the previous fetch address, and the current fetch address is different from the jump target address in the second register and / or the previous fetch address is different from the jump address in the third register, it indicates that a new potential instruction loop body may appear or the original instruction loop body may be exited. At this time, the counter is reset to mark the end of the detection count of the previous potential instruction loop body. At the same time, the current fetch address is stored as the new jump target address in the second register, updating the jump target address in the second register. The current fetch address is also stored as the new jump address in the third register, updating the jump address in the third register. This process continues until the jump count of the new potential instruction loop body is greater than a preset value, at which point the new potential instruction is determined. The loop body is a new instruction loop body. The jump target address in the second register is stored as the loop start address in the loop start address register, and the jump address in the third register is stored as the loop end address in the loop end address register. At least part of the instructions in the new instruction loop body are stored in the memory location. The fetch address of the start instruction in at least part of the instructions in the new instruction loop body is stored as the cache start address in the fourth register, and the fetch address of the end instruction in at least part of the instructions in the new instruction loop body is stored as the cache end address in the fifth register. The subsequent hit detection module determines whether the fetch address sent by the processor core hits the memory location based on the cache start address and the cache end address, and then performs the fetch.

[0062] For example, such as Figure 3 As shown, when the new instruction loop body and the stored instruction loop body belong to two completely different instruction loop bodies, the instruction fetch address processing method may include the following steps: In step S31, the current instruction fetch address sent by the processor core is received.

[0063] In step S32, the current instruction fetch address is compared with the previous instruction address stored in the instruction fetch address register.

[0064] In step S33, it is determined whether the current fetch address is less than the previous fetch address. If yes, step S34 is executed. If no, the current fetch address is stored as the new previous fetch address in the fetch address register, and the process returns to step S31.

[0065] In step S34, it is determined whether the current instruction fetch address is consistent with the jump target address in the jump target address register, and whether the previous instruction fetch address is consistent with the jump address in the jump address register. If yes, then steps S35~S38 are executed; otherwise, step S39 is executed.

[0066] In step S35, the bounce count of the counter in the bounce detector is incremented by one.

[0067] In step S36, it is determined whether the bounce count of the counter is greater than a preset value. If yes, then step S37 is executed; otherwise, the process returns to step S31.

[0068] In step S37, it is determined that a new instruction loop body has been detected. At least a portion of the instructions in the new instruction loop body are stored in the storage unit of the cache. The jump target address is stored as the loop start address in the loop start address register, and the jump address is stored as the loop end address in the loop end address register. The fetch address of the start instruction in at least a portion of the instructions in the new instruction loop body is stored as the cache start address in the fourth register, and the fetch address of the end instruction in at least a portion of the instructions in the new instruction loop body is stored as the cache end address in the fifth register.

[0069] In step S38, when the hit determination module determines that the current fetch address sent by the processor core is within the address range between the cache start address and the cache end address, the current fetch address sent by the processor core hits the memory unit, the instruction stored in the memory unit is returned to the processor core, and the execution returns to step S31.

[0070] In step S39, a new potential instruction loop body is detected, the counter is reset, the current fetch address is stored as the new jump target address in the jump target address register, the previous fetch address is stored as the new jump address in the jump address register, and the process returns to step S31.

[0071] In scenario two, the new instruction loop body overlaps with a portion of the instructions in the already stored instruction loop body.

[0072] In one feasible embodiment, the instruction fetch address processing method may further include: If at least some of the instructions in a valid instruction loop body already exist in the memory cell, and a new instruction loop body is detected, it is determined whether there is an overlapping address between the first address range corresponding to at least some of the instructions in the instruction loop body and the second address range corresponding to the new instruction loop body. If overlapping addresses exist and there is free storage space in the memory cell, then while keeping the instruction corresponding to the overlapping address valid in the memory cell, at least a portion of the instructions in the new instruction loop body, excluding the instruction corresponding to the overlapping address, are stored in the free storage space.

[0073] It is worth noting that if the storage space of the storage unit is less than the storage space required for all the instructions of the current instruction loop body, then the storage unit only stores a portion of the instructions of the current instruction loop body; if the storage space of the storage unit is greater than or equal to the storage space required for all the instructions of the current instruction loop body, then the storage unit stores all the instructions of the current instruction loop body.

[0074] It should be understood that because the start and end addresses of the instruction loop body are different, as are the execution conditions and number of times the loop body is executed, the detection of the instruction loop body is continuous and ongoing. After the detection of the current instruction loop body is completed based on the fetch address sent by the processor core, the detection of the instruction loop body continues based on the subsequent fetch addresses sent by the processor core. At least some of the instructions in the current instruction loop body will be stored in the memory unit. If a new instruction loop body is detected, and the addresses of some instructions in the new instruction loop body overlap with those of the previous instruction loop body, then only at least some of the instructions in the new instruction loop body, excluding the instructions corresponding to the overlapping addresses, need to be stored in the free memory space.

[0075] For example, if only a portion of the current instruction loop body is stored in the memory cell, and a new instruction loop body is detected, it is determined whether there is an overlapping address between the first address range corresponding to the portion of the current instruction loop body and the second address range corresponding to the new instruction loop body. If there is an overlapping address, all instructions except those corresponding to the overlapping address are cleared from the memory cell. While keeping the instructions corresponding to the overlapping address valid in the memory cell, at least a portion of the instructions in the new instruction loop body, excluding those corresponding to the overlapping address, are stored in the free storage space of the memory cell.

[0076] If the memory cell contains all the instructions of the current instruction loop body, and a new instruction loop body is detected, it is determined whether there is an overlapping address between the first address range corresponding to the current instruction loop body and the second address range corresponding to the new instruction loop body. If there is an overlapping address, all instructions except those corresponding to the overlapping address are cleared from the memory cell. While keeping the instructions corresponding to the overlapping address valid in the memory cell, at least a portion of the instructions in the new instruction loop body, excluding those corresponding to the overlapping address, are stored in the free memory space of the memory cell.

[0077] Specifically, the overlapping address between the first address range corresponding to at least a portion of the instructions in the instruction loop body stored in the memory unit and the second address range corresponding to the new instruction loop body includes two cases. Case 1: The first address range corresponding to at least a portion of the instructions in the instruction loop body stored in the memory unit is completely covered by the second address range corresponding to the new instruction loop body. In this case, only at least a portion of the instructions in the new instruction loop body, excluding the instructions corresponding to the overlapping addresses, needs to be stored in the free memory space. Case 2: The first address range corresponding to at least a portion of the instructions in the instruction loop body stored in the memory unit is partially covered by the second address range corresponding to the new instruction loop body. In this case, all instructions in the at least a portion of the instructions in the instruction loop body stored in the memory unit, excluding the instructions corresponding to the overlapping addresses, need to be cleared, and at least a portion of the instructions in the new instruction loop body, excluding the instructions corresponding to the overlapping addresses, needs to be stored in the free memory space.

[0078] It is worth noting that for nested loops, the storage unit can store both the outermost loop and the inner loop simultaneously. In this case, the outer loop instruction can be stored according to the instruction PC, and the start and end addresses of the cache storing the outermost instruction loop can be updated.

[0079] For example, when the current fetch address sent by the processor core is less than the previous fetch address, and the current fetch address is different from the jump target address in the second register and / or the previous fetch address is different from the jump address in the third register, it indicates that a new potential instruction loop body may appear or the original instruction loop body may be exited. At this time, the counter is reset to mark the end of the detection count of the previous potential instruction loop body. At the same time, the current fetch address is stored as the new jump target address in the second register, the jump target address in the second register is updated, and the current fetch address is stored as the new jump address in the third register, the jump address in the third register is updated, until the jump count of the new potential instruction loop body is greater than a preset value. Then, the new potential instruction loop body is determined to be the new instruction loop body. The jump target address in the second register is stored as the loop start address in the loop start address register, and the jump address in the third register is stored as the loop end address in the loop end address register. If the memory unit stores all the instructions of the original instruction loop body, it is determined whether there is an overlap between the first address range corresponding to the original instruction loop body and the second address range of the new instruction loop body. If overlapping addresses exist and there is free storage space in the memory location, at least a portion of the instructions in the new instruction loop body, excluding the instructions corresponding to the overlapping addresses, are stored in the free storage space. If the start and end addresses of the existing instruction loop body are both within the second address range of the new instruction loop body, the fetch address of the start instruction in at least a portion of the instructions in the new instruction loop body is stored as the cache start address in the fourth register, and the fetch address of the end instruction in at least a portion of the instructions in the new instruction loop body is stored as the cache end address in the fifth register. Subsequently, the hit detection module determines whether the fetch address sent by the processor core hits the memory location based on the cache start address and cache end address, and performs instruction fetching.

[0080] For example, such as Figure 4 As shown, when the memory cell stores all the instructions of the original instruction loop body and the new instruction loop body overlaps with part of the instructions of the instruction loop body already stored in the memory cell, the instruction fetch address processing method may include the following steps: In step S41, the current instruction fetch address sent by the processor core is received.

[0081] In step S42, the current instruction fetch address is compared with the previous instruction fetch address stored in the instruction fetch address register.

[0082] In step S43, it is determined whether the current fetch address is less than the previous fetch address. If yes, step S44 is executed. If no, the current fetch address is stored as the new previous fetch address in the fetch address register, and the process returns to step S41.

[0083] In step S44, it is determined whether the current instruction fetch address is consistent with the jump target address in the jump target address register, and whether the previous instruction fetch address is consistent with the jump address in the jump address register. If yes, then steps S45~S49 are executed; otherwise, step S410 is executed.

[0084] In step S45, the bounce count of the counter in the bounce detector is incremented by one.

[0085] In step S46, it is determined whether the bounce count of the counter is greater than a preset value. If yes, then step S47 is executed; otherwise, the process returns to step S41.

[0086] In step S47, it is determined that a new instruction loop body has been detected. If there is an overlap between the first address range corresponding to the stored instruction loop body and the second address range corresponding to the new instruction loop body, and there is free storage space in the storage unit, then while keeping the instruction corresponding to the overlap address valid in the storage unit, at least a portion of the instructions in the new instruction loop body other than the instruction corresponding to the overlap address is stored in the free storage space.

[0087] In step S48, if the start address and end address of the existing instruction loop body are both within the second address range of the new instruction loop body, the fetch address of the start instruction in at least a portion of the instructions in the new instruction loop body is stored as the cache start address in the fourth register, and the fetch address of the end instruction in at least a portion of the instructions in the new instruction loop body is stored as the cache end address in the fifth register.

[0088] In step S49, when the hit determination module determines that the current fetch address sent by the processor core is within the address range between the cache start address and the cache end address, the current fetch address sent by the processor core hits the memory unit, and the process returns to step S41.

[0089] In step S410, a new potential instruction loop body is detected, the counter is reset, the current fetch address is stored as the new jump target address in the jump target address register, the previous fetch address is stored as the new jump address in the jump address register, and the process returns to step S41.

[0090] In one feasible embodiment, the instruction fetch address is a multiple of 4, and the instruction fetch address processing method may further include: For any fetch address between the loop start address and the loop end address, determine the bit value of the fetch address in the target bit position. The target bit position is the (N+1)th to the 2nd bit. The capacity of the storage unit is 2 to the power of N, where N is a positive integer. The storage location of the instruction corresponding to the fetch address in the memory unit is determined based on the bit value; Store the instruction at the fetch address in the storage location in the storage unit.

[0091] Another example is that if the fetch address is a multiple of 8, the fetch address processing method may further include: For any fetch address between the loop start address and the loop end address, determine the bit value of the fetch address at the target bit positions. The target bit positions are the (N + 2)-th to the 3rd bit, the capacity of the buffer is 2 to the power of N, and N is a positive integer. Determine the storage location of the instruction corresponding to the fetch address in the storage unit according to the bit value; Store the instruction at the fetch address in the storage location in the storage unit.

[0092] It should be noted that the storage space of the instruction loop body is 2N Entry (item) instruction cache entries, where N is equal to 1, 2, 3,... When implemented, it can achieve a trade-off balance between the cache space and the chip area overhead, and is configured according to the length Len (i.e., the number of instructions) of the instruction loop body to be supported as needed. For example, when the requirement is Len ≤ 8 instructions, N can be configured as 3, and the number of cache entries is 2^3 = 8, that is, a buffer with a capacity of 8 is constructed. When the requirement is 8 < Len ≤ 16 instructions, N can be configured as 4, and the number of cache entries is 2^4 = 16, that is, a buffer with a capacity of 16 is constructed.

[0093] It should be noted that in the case where the jump-back target address is the loop start address and the jump-back address is the loop end address, if the fetch address sent by the subsequent processor core is greater than the jump-back target address and less than or equal to the fetch address of the jump-back address, it indicates that the fetch address belongs to the instruction address in the instruction loop body. At this time, if the instruction corresponding to the fetch address is stored in the storage unit, the corresponding instruction can be read from the storage unit according to the fetch address and returned to the processor core; if the instruction corresponding to the fetch address is not stored in the storage unit, the corresponding instruction can be read from the lower-level buffer according to the fetch address and returned to the processor core. Among them, the storage method is limited by the relationship between the number of instructions in the instruction loop body and the number of instruction storage spaces in the storage unit.

[0094] Specifically, there are two cases: the number of instructions in the instruction loop body is less than or equal to the number of instruction storage spaces in the storage unit, and the number of instructions in the instruction loop body is greater than the number of instruction storage spaces in the storage unit.

[0095] For example, if the number of instructions in the instruction loop body is less than the number of instruction storage spaces in the memory unit, and the instruction loop body has 5 instructions and the memory unit has 8 instruction storage spaces, then all 5 instructions in the instruction loop body can be stored in the instruction storage spaces in the memory unit. The addresses corresponding to each instruction are PC+0, PC+4, PC+8, PC+12, and PC+16. Then the cache start address of the instruction loop body is PC+0, and the cache end address of the instruction loop body is PC+16.

[0096] In another example, when the number of instructions in the instruction loop body is greater than the number of instruction storage spaces in the memory unit, if the instruction loop body has 10 instructions and there are 8 instruction storage spaces in the memory unit, then the first 8 instructions of the instruction loop body are stored in the 8 instruction storage spaces in the memory unit respectively, with corresponding addresses of PC+0, PC+4, ..., PC+28. Therefore, the cache start address of the instruction loop body is PC+0, and the cache end address of the instruction loop body is PC+28. The last two instructions are not stored in the memory unit, so the cache end address of the instruction loop body is not PC+36.

[0097] In one feasible embodiment, the storage unit includes multiple storage locations and a valid flag bit corresponding to each storage location; Instruction fetch address processing methods may also include: When a new instruction is written to each storage location, the valid identifier corresponding to that storage location is marked as valid; The cache is located between the processor core and the next-level cache. Instruction fetch address processing methods may also include: If the corresponding instruction stored in the lower-level cache is cleared, the valid flag of the storage location of the corresponding instruction in the cache's storage unit is set to invalid, and / or, if the lower-level cache is invalidated, the valid flag of all storage locations in the cache's storage unit is set to invalid.

[0098] The lower-level memory includes, but is not limited to, instruction caches, which are not limited in this disclosure.

[0099] In the above technical solution, the effective flag bit corresponding to the storage location in the storage unit is adjusted in real time to avoid execution errors caused by the inconsistency between the actual cache state of the storage location in the storage unit and the effective flag bit, thereby optimizing the management of cache storage space in the storage unit.

[0100] Based on the same inventive concept, this disclosure also provides a processor instruction fetching system. Figure 5 This is a schematic diagram of a processor instruction fetching system according to an exemplary embodiment of the present disclosure, such as... Figure 5 As shown, it includes: The processor core, the hit detection module, and the cache are connected together. The processor core is connected to the hit detection module and the cache, and the hit detection module is connected to the cache. The cache includes a loop detection unit, a control unit, and a storage unit. The loop detection unit is used to detect address bounce based on the fetch address sent by the processor core, and to determine the instruction loop body based on the address bounce result. The instruction loop body represents a set of a certain number of instructions to be executed cyclically. The storage unit is used to store at least a portion of the instructions in the instruction loop body; The hit detection module is used to determine whether the current fetch address sent by the processor core hits a memory unit; The control unit is used to return the instruction corresponding to the fetch address in the memory unit to the processor core when the hit determination module determines that the current fetch address sent by the processor core hits the memory unit.

[0101] The execution principles and steps of the loop detection unit, control unit, and hit judgment module can be found in the instruction fetch address processing method, and will not be repeated here.

[0102] In this embodiment, the Loop Detector is used to detect address loops based on the fetch address sent by the processor core, and then determine whether there is an instruction loop body in the instruction stream executed by the processor core based on the address loop result. The detection approach includes: determining whether the fetch address sent by the core processor is performing loop fetching within a fixed fetch address space, that is, repeatedly fetching instructions starting from one address, such as address A, sequentially fetching instructions until another address, such as address B, is reached, then jumping back to start fetching instructions from A again, fetching instructions to address B again, and so on, repeating this process until the loop ends. The Loop Controller is used to access memory units.

[0103] It is worth noting that, such as Figure 6 As shown, the storage unit is used to store at least a portion of the instructions in the instruction loop body. The storage unit includes a validity flag and an instruction cache entry. The validity flag indicates whether the current entry is valid, and the instruction cache entry stores only the instruction itself. The configuration of the storage space in the storage unit can be referred to the instruction fetch address processing method described above, and will not be repeated here.

[0104] In this embodiment, the storage unit does not need to store the data content after instruction decoding, saving storage space. For example, for a 32-bit processor, each instruction item only requires 32 bits of storage space (register or SRAM). The instruction cache does not need to store the address corresponding to the instruction, further saving space. Cache is only started from the loop start address of the instruction loop body, and a maximum of 2N instructions can be recorded. If the instruction fetch address of the instruction in the instruction loop body is greater than (start address + 2N × 4), it will not be stored in the storage unit.

[0105] In the above technical solution, the processor instruction fetch system includes a processor core, a hit detection module, and a register. The processor core is connected to the hit detection module and the register, and the hit detection module is connected to the register. The register's loop detection unit detects address bounce based on the fetch address sent by the processor core and determines the instruction loop body based on the address bounce result. The entire instruction loop body detection process does not require instruction decoding and is not affected by the processor's own architecture, thus exhibiting strong versatility. The storage unit in the register is used to store at least a portion of the instructions in the instruction loop body; that is, the register only stores the instructions themselves, saving cache space and reducing power consumption. The control unit in the register is used to return the instruction corresponding to the fetch address in the storage unit to the processor core when the hit detection module determines that the current fetch address sent by the processor core hits the storage unit. Compared with related technologies that decode and execute instructions, the entire process of this disclosure is simple to implement, does not require complex decoding processing, shortens the time required for instruction fetching, reduces latency, and only needs to store part or all of the instructions in the instruction loop body, resulting in smaller area overhead and lower instruction fetch power consumption.

[0106] To facilitate a better understanding of the processor instruction fetch system provided in this disclosure by those skilled in the art, the processor instruction fetch system will be described in detail below.

[0107] In one feasible embodiment, such as Figure 7 As shown, the loop detection unit includes a first register, a second register, a third register, a loop start address register, a loop end address register, and a back jump detector; The first register is used to store the address of the previous instruction fetch sent by the processor core. The second register is used to store the current fetch address as the bounce target address when the bounce detector detects a new potential instruction loop body based on the address bounce result. The third register is used to store the previous instruction fetch address as the bounce address when the bounce detector detects a new potential instruction loop body based on the address bounce result. The bounce detector also includes a counter, which increments the bounce count when the bounce detector detects a bounce at the same address and resets it when a bounce at a different address is detected. A bounce at the same address means that the current fetch address is the same as the bounce target address and the previous fetch address is the same as the bounce address. The loop detection unit is used to determine the loop start address as the loop start address and store it in the loop start address register when the loop count of the counter is greater than a preset value, and to determine the loop end address as the loop end address and store it in the loop end address register.

[0108] In this embodiment, the first register can be an instruction fetch address register, which records the last instruction fetch address of the CPU Core. The program counter (PC) sent by the CPU Core updates the instruction fetch address register, overwriting the previously stored instruction fetch address, and is used for comparison with the next instruction fetch address sent by the CPU Core. The loop detection unit overwrites the previously stored instruction fetch address in the instruction fetch address register with the instruction fetch address sent by the processor core this time, updating the previous instruction fetch address and preparing for the next detection of the instruction loop body based on the instruction fetch address.

[0109] The second register can be the jump target address register, and the third register can be the jump address register. When the jump detector detects a new potential instruction loop body based on the address jump result, it will store the current fetch address as the jump target address in the jump target address register and store the previous fetch address as the jump address in the jump address register.

[0110] The counter can be a bounce counter, used to count when the bounce detector detects an address bounce. For example, if the current fetch address is the same as the bounce target address and the previous fetch address is the same as the bounce address, the bounce counter is incremented by one. If the current fetch address is different from the bounce target address or the previous fetch address is different from the bounce address, the bounce counter is reset. Resetting includes setting the bounce counter to 1 or 0.

[0111] It is worth noting that if no new instruction loop body is detected, the existing instruction loop body will be retained until a new instruction loop body appears; if a new loop body is detected, at the beginning of the next loop, starting from the first instruction of the loop, when reading instructions from the lower-level cache, the read instructions will be returned to the processor core and updated in the memory unit.

[0112] The operating principles of the various registers in the loop detection unit and the bounce detector in the above technical solution are explained in detail in the aforementioned instruction fetch address processing method, and will not be repeated here.

[0113] In one feasible embodiment, the bounce detector is used to determine that a new potential instruction loop body has been detected if, in the case that the loop start address is not stored in the loop start address register and the loop end address is not stored in the loop end address register, the current fetch address is less than the previous fetch address, and the current fetch address is different from the bounce target address in the second register and / or the previous fetch address is different from the bounce address in the third register.

[0114] It's worth noting that if both the jump address register and the jump target address register contain valid jump addresses and jump target addresses, then if the current fetch address is inconsistent with the jump target address in the second register, and / or the previous fetch address is inconsistent with the jump address in the third register, it can be considered that a potential new instruction loop body has been discovered. In this case, the counter is reset. Since nested loops are not considered at this time, the addresses stored in the second and third registers need to be updated using the jump address and / or jump target address of the potential new instruction loop body to facilitate determining whether the jump count of the potential new instruction loop body has reached the threshold.

[0115] It should be understood that, given the existence of a bounce, when the bounce detector detects a discrepancy between the current fetch address sent by the processor core and the bounce target address, the current fetch address is used to overwrite the bounce target address in the bounce target address register, thus updating the bounce target address. Similarly, when the bounce detector detects a discrepancy between the previous fetch address sent by the processor core and the bounce address, the bounce address overwritten by the previous fetch address sent by the processor core is used to update the bounce address.

[0116] In this embodiment, the loop detection unit may include a fetch address register, a jump address register, a jump target address register, a loop start address register, a loop end address register, and a jump detector. If a jump execution is determined based on the fetch address sent by the CPU Core, the jump address is recorded in the jump address register, the jump target address is recorded in the jump target address register, and the counter in the jump detector is incremented. The CPU Core fetches and executes instructions starting from the jump target address. When the fetch address sent by the CPU Core reaches the jump address again for instruction fetching, if it is determined that the CPU Core will execute forward, the counter is reset; if it is determined that the CPU Core will jump execution again, and if the jump address is the same as the previously recorded jump address and the jump target address is the same as the previously recorded jump target address, the counter is incremented; if the jump address is different from the previously recorded jump address and / or the jump target address is different from the previously recorded jump target address, the counter is reset, and the current jump address and jump target address are updated in the corresponding registers. After each bounce counter increments by one, the bounce count value in the counter is compared with the configured preset value. If it is, it is determined that an instruction loop body has been detected, and a flag signal, as well as the bounce address and bounce target address, are sent to the control unit. If not, the control unit continues to detect the instruction fetch address subsequently sent by the processor core.

[0117] In one feasible embodiment, the bounce detector is used to determine that a new potential instruction loop body has been detected if, when the loop start address register stores the loop start address and the loop end address register stores the loop end address, the current fetch address is less than the previous fetch address, and at least one of the current fetch address or the previous fetch address is not within the range of the loop start address and the loop end address.

[0118] In this embodiment, please refer to the relevant embodiments in the above-described instruction fetch address processing method, which will not be repeated here.

[0119] Correspondingly, if the fetch address sent by the processor core is less than the cache start address or greater than the cache end address, it indicates a cache miss. In this case, the control unit reads the corresponding instruction from the lower-level cache according to the fetch address.

[0120] In one feasible embodiment, the hit determination module includes a fourth register and a fifth register; The control unit is used to store at least a portion of the instructions in the instruction loop body into the storage unit when the loop detection unit detects the instruction loop body; The fourth register is used to store the fetch address of the start instruction of at least a portion of the instructions in the instruction loop body as the cache start address; The fifth register is used to store the fetch address of the end instruction in at least part of the instructions in the instruction loop body as the cache end address; The hit determination module is used to determine whether the current fetch address sent by the processor core hits the memory unit based on the cache start address and cache end address.

[0121] For example, if the control unit receives a cache access hit flag from the hit determination module, it reads the instruction from the storage unit and returns it to the processor core; if it receives a flag from the loop detection unit indicating that a new instruction loop body has been detected, it updates the storage unit with at least a portion of the instructions read from the lower-level cache during the next loop execution; if the hit determination module generates a cache access miss flag, the hit determination module receives the instruction returned by the lower-level cache and returns it directly to the processor core.

[0122] It is worth noting that, such as Figure 8 As shown, the cache also includes an instruction cache access gating unit. The hit determination module sends the fetch address sent by the CPU Core to the instruction cache through the instruction cache access gating unit. For the current fetch address sent by the CPU Core, if the hit determination module determines that the current fetch address hits a memory location, the instruction cache access gating unit intercepts the access to the instruction cache for this fetch, and the control unit directly returns the instruction corresponding to the current fetch address to reduce the number of accesses to the instruction cache, thereby saving access power. If the hit determination module determines that the fetch address does not hit a memory location, the instruction cache access gating unit sends the current fetch address to the instruction cache for normal access, and the control unit returns the instruction returned by the instruction cache to the processor core.

[0123] Another example, such as Figure 8 As shown, the processor core sends the instruction fetch address to the cache hit detection module, which determines whether the fetch address hits the cache. When the fetch address hits the cache, the control unit inside the cache accesses the memory location within the cache and returns the target instruction to the processor core. Simultaneously, this instruction fetch access is intercepted by the instruction cache access gating unit, and no fetch access is sent to the instruction cache. When the fetch address misses the cache, the control unit inside the cache controls the instruction cache access gating unit to send an instruction fetch access to the instruction cache based on the fetch address sent by the processor core, and receives the instruction returned by the instruction cache. The control unit then directly returns the instruction returned by the instruction cache to the processor core.

[0124] In one feasible embodiment, the loop detection unit is used to determine whether there is an overlapping address between the first address range corresponding to the at least part of the instructions in the instruction loop body and the second address range corresponding to the new instruction loop body if a new instruction loop body is detected, when at least part of the instructions in the instruction loop body already exist in the memory unit. The control unit is configured to, if there is an overlapping address and there is free storage space in the storage unit, store at least a portion of the instructions other than the instruction corresponding to the overlapping address in the free storage space, while keeping the instruction corresponding to the overlapping address valid in the storage unit.

[0125] The specific execution methods of the loop detection unit and the control unit in this embodiment can be found in the relevant embodiments of the aforementioned instruction fetch address processing method where the new instruction loop body overlaps with a portion of the stored instruction loop body, and will not be repeated here.

[0126] In one feasible embodiment, the fetch address is a multiple of 4; The control unit is used to determine the bit value of the fetch address in the target bit position for any fetch address between the loop start address and the loop end address. The target bit position is the (N+1)th to the 2nd bit position, and the capacity of the storage unit is 2 to the power of N, where N is a positive integer. The storage location of the instruction corresponding to the fetch address in the memory unit is determined based on the bit value; The instruction fetched from the address is stored in the memory location.

[0127] It's worth noting that when reading instructions from the instruction loop body, the selection is based on the index. For example, in a 32-bit system, Index = PC[N+1:2], where N is a positive integer. In a 64-bit system, Index = PC[N+2:3], where N is a positive integer.

[0128] For example, taking a 32-bit system as an example, the byte address of a 32-bit system includes, but is not limited to: 0x04, 0x08, 0x0C, 0x10, 0x14, 0x18, 0x1C, 0x20.

[0129] With a total of 5 instructions in the instruction loop body and 8 instruction storage spaces, there are three storage methods. Scenario 1 involves the storage and access of the instruction loop body in the storage space as follows: Figure 9 As shown, the five instructions are sequentially stored in the third to seventh instruction storage spaces in the memory unit; in case two, the storage and access of the instruction loop body in the memory unit are as follows. Figure 10As shown, the five instructions are sequentially stored in the sixth to eighth instruction storage spaces and the first and second instruction storage spaces in the memory unit. Case three: The storage and access of the instruction loop body in the memory unit is as follows. Figure 11 As shown, the five instructions are stored sequentially in the second to third instruction storage spaces and the fifth to seventh instruction storage spaces in the memory unit, skipping the fourth instruction storage space in the memory unit.

[0130] For a 32-bit system, N=3, and the corresponding Index=PC[3+1:2]=PC[4:2], meaning the instruction cache address is PC[4:2], representing bits 4 to 2 of the fetch address sent by the CPU core. Since the byte address is a multiple of 4, the first and zeroth bits of the fetch address are always 0, i.e., PC[1:0] = 00b. Therefore, bits 4 to 2 are used to limit the cache address using three bits. Bits 4 to 2 of the loop start address may be 010b (corresponding to...) Figure 9 Cache item 3 in the middle), or 101b (corresponding to Figure 10 Cache item 6 in the middle.

[0131] As another example, if the instruction fetch address is a multiple of 8, then at least a portion of the instructions between the jump address and the jump target address are stored in the register, which may include: Based on the bit value of the target bit of the fetch address, the storage location of the instruction corresponding to the fetch address in the register is determined. The target bit is from the (N+2)th to the 3rd bit. The capacity of the register is 2 to the power of N, where N is a positive integer greater than or equal to 2.

[0132] For example, taking a 64-bit system as an example, the byte address of a 64-bit system includes, but is not limited to: 0x08, 0x10, 0x18, 0x20, 0x28, 0x30, 0x38, 0x40.

[0133] For a 64-bit system with N=3, the corresponding Index = PC[3+2:3] = PC[5:3], meaning the instruction cache address is PC[5:3]. This represents bits 5 to 3 of the fetch address sent by the CPU core. Since byte addresses are multiples of 8, the second, first, and zeroth bits of the fetch address are always 0, i.e., PC[2:0] = 000b. Therefore, bits 5 to 3 are used to limit the cache address. Bits 5 to 3 of the loop start address can be 010b or 101b.

[0134] In one feasible embodiment, the storage unit includes multiple storage locations and a valid flag bit corresponding to each storage location; The control unit is used for: When a new instruction is written to each storage location, the valid identifier corresponding to that storage location is marked as valid; The cache is located between the processor core and the lower-level cache. When the corresponding instruction stored in the lower-level cache is cleared, the valid flag of the storage location of the corresponding instruction in the cache's storage unit is invalidated, and / or, when the lower-level cache is invalidated, the valid flag of all storage locations in the cache's storage unit is invalidated.

[0135] It should be understood that lower-level caches include, but are not limited to, instruction caches. Taking the instruction cache as an example, when the instruction loop body stored in the instruction cache is cleared, the valid flag bit of the corresponding instruction's storage space in the cache should be invalidated. For example, if a cacheline replace occurs and the cacheline containing the instruction loop body in the instruction cache is replaced, then the valid flag bit of the corresponding storage space in the cache should also be invalidated accordingly.

[0136] It's worth noting that the contents of the cache must be synchronized with the contents of the instruction cache. If the cache line containing the instruction loop body in the instruction cache is replaced, the instructions in the instruction loop body stored in the cache must also be cleared. This means the valid flag of the corresponding Entry must be cleared, rendering the corresponding Entry invalid. If the instruction cache is invalidated, all valid flag positions corresponding to all Entries in the instruction loop body are cleared to zero, maintaining storage consistency between the cache and the instruction cache.

[0137] The processor instruction fetch system provided in this disclosure does not require storing instruction address information; it directly stores the instruction itself. The fetch process does not require instruction type determination; it only records the address stream of instruction execution, including the address of the jump instruction and the jump target address, thereby determining the instruction loop body. This is simple to implement, highly versatile, and unaffected by the processor core's architecture, simplifying system design. Furthermore, combining the jump count threshold for instruction loop determination allows for flexible adjustment of the instruction loop body detection strategy, optimizing power consumption; it can reduce cache update power consumption. For example, if the loop body itself executes twice, execution continues after the loop is complete, and the loop stops, there is no need to record the instruction in the loop body. Increasing the threshold can also prevent misjudgments of the instruction loop body caused by erroneous jumps in the instruction stream due to branch miss prediction. In addition, by comparing whether the fetch address is within the range of the cache start address and cache end address, it determines whether the cache access has a hit. This is simple to implement, has low area overhead, is highly versatile, and unaffected by the processor's architecture. Moreover, instruction fetching is based on the cache, reducing latency.

[0138] The preferred embodiments of this disclosure have been described in detail above with reference to the accompanying drawings. However, this disclosure is not limited to the specific details of the above embodiments. Within the scope of the technical concept of this disclosure, various simple modifications can be made to the technical solutions of this disclosure, and these simple modifications all fall within the protection scope of this disclosure.

[0139] It should also be noted that the various specific technical features described in the above embodiments can be combined in any suitable manner without contradiction. To avoid unnecessary repetition, this disclosure will not describe the various possible combinations separately.

[0140] Furthermore, various different embodiments of this disclosure can be combined in any way, as long as they do not violate the spirit of this disclosure, they should also be regarded as the content disclosed in this disclosure.

Claims

1. A processor instruction fetching system, characterized in that, include: The processor core, the hit detection module, and the cache are provided, wherein the processor core is connected to the hit detection module and the cache, and the hit detection module is connected to the cache; the cache includes a loop detection unit, a control unit, and a storage unit. The loop detection unit is used to detect address bounce based on the fetch address sent by the processor core, and to determine the instruction loop body based on the address bounce result. The instruction loop body represents a set of a certain number of instructions to be executed cyclically. The storage unit is used to store at least a portion of the instructions in the instruction loop body; The hit determination module is used to determine whether the current fetch address sent by the processor core hits the memory unit; The control unit is used to return the instruction corresponding to the fetch address in the memory unit to the processor core when the hit determination module determines that the current fetch address sent by the processor core hits the memory unit.

2. The processor instruction fetching system according to claim 1, characterized in that, The loop detection unit includes a first register, a second register, a third register, a loop start address register, a loop end address register, and a back jump detector; The first register is used to store the address of the previous instruction fetch sent by the processor core; The second register is used to store the current fetch address as the jump target address when the jump detector detects a new potential instruction loop body based on the address jump result; The third register is used to store the previous instruction fetch address as the jump address when the jump detector detects a new potential instruction loop body based on the address jump result. The bounce detector also includes a counter, which is used to increment the bounce count by one when the bounce detector detects a bounce at the same address and to reset it when a bounce at a different address is detected. A bounce at the same address means that the current fetch address is the same as the bounce target address and the previous fetch address is the same as the bounce address. The loop detection unit is used to determine the loop start address as the loop start address and store it in the loop start address register when the loop count of the counter is greater than a preset value, and to determine the loop end address as the loop end address and store it in the loop end address register.

3. The processor instruction fetching system according to claim 2, characterized in that, The bounce detector is used to determine that a new potential instruction loop body has been detected if, when the loop start address is not stored in the loop start address register and the loop end address register is not stored in the loop end address register, the current fetch address is less than the previous fetch address, and the current fetch address is different from the bounce target address in the second register and / or the previous fetch address is different from the bounce address in the third register.

4. The processor instruction fetching system according to claim 2, characterized in that, The bounce detector is used to determine that a new potential instruction loop body has been detected when the loop start address register stores the loop start address and the loop end address register stores the loop end address, and if the current fetch address is less than the previous fetch address, and at least one of the current fetch address or the previous fetch address is not within the range of the loop start address and the loop end address.

5. The processor instruction fetching system according to claim 2, characterized in that, The hit determination module includes a fourth register and a fifth register; The control unit is configured to store at least a portion of the instructions in the instruction loop body into the storage unit when the loop detection unit detects the instruction loop body. The fourth register is used to store the fetch address of the start instruction of at least a portion of the instructions in the instruction loop body as the cache start address; The fifth register is used to store the fetch address of the end instruction in at least a portion of the instructions in the instruction loop body as the cache end address; The hit determination module is used to determine whether the current fetch address sent by the processor core hits the memory unit based on the cache start address and the cache end address.

6. The processor instruction fetching system according to claim 4, characterized in that: The loop detection unit is used to determine whether there is an overlapping address between the first address range corresponding to the at least part of the instructions in the instruction loop body and the second address range corresponding to the new instruction loop body if a new instruction loop body is detected, when at least part of the instructions in the instruction loop body already exist in the storage unit. The control unit is configured to, if the overlapping address exists and the storage unit has free storage space, store at least a portion of the instructions other than the instruction corresponding to the overlapping address in the free storage space, while keeping the instruction corresponding to the overlapping address valid in the storage unit.

7. The processor instruction fetching system according to claim 2, characterized in that, The fetch address is a multiple of 4; The control unit is used to determine the bit value of the fetch address in the target bit position for any fetch address between the loop start address and the loop end address, wherein the target bit position is the (N+1)th to the 2nd bit, and the capacity of the storage unit is 2 to the power of N, where N is a positive integer. The storage location of the instruction corresponding to the fetch address in the memory unit is determined based on the bit value; The instruction at the fetched address is stored in the storage location of the storage unit.

8. The processor instruction fetching system according to any one of claims 1-7, characterized in that, The storage unit includes multiple storage locations and a valid flag bit corresponding to each storage location; The control unit is used for: When a new instruction is written to each storage location, the valid identifier corresponding to that storage location is marked as valid; The cache is located between the processor core and the lower-level cache. When the corresponding instruction stored in the lower-level cache is cleared, the valid flag of the storage location of the corresponding instruction in the storage unit of the cache is invalidated, and / or, when the lower-level cache is invalidated, the valid flag of all storage locations in the storage unit of the cache is invalidated.

9. A method for processing instruction fetch addresses, characterized in that, An instruction fetching system for processors is provided, comprising a processor core, a hit detection module, and a cache, wherein the processor core is connected to the hit detection module and the cache, and the hit detection module is connected to the cache. The instruction fetch address processing method includes: The address bounce is detected based on the fetch address sent by the processor core, and the instruction loop body is determined based on the address bounce result. The instruction loop body represents a set of a certain number of instructions to be executed cyclically. At least a portion of the instructions in the instruction loop body are stored in the storage unit of the cache; When the hit determination module determines that the current fetch address sent by the processor core hits the memory unit, it returns the instruction in the memory unit corresponding to the fetch address to the processor core.

10. The instruction fetch address processing method according to claim 9, characterized in that, The buffer includes a loop detection unit, which includes a first register, a second register, a third register, a loop start address register, a loop end address register, and a back jump detector. The instruction fetch address processing method further includes: The address of the previous instruction fetch sent by the processor core is stored in the first register; When the bounce detector detects a new potential instruction loop body based on the address bounce result, it stores the current instruction fetch address as the bounce target address in the second register; When the bounce detector detects a new potential instruction loop body based on the address bounce result, it stores the previous instruction fetch address as the bounce address in the third register; The bounce detector further includes a counter, and the instruction fetch address processing method further includes: When the bounce detector detects a bounce at the same address, the bounce count of the counter is incremented by one. When a bounce at a different address is detected, the counter is reset. A bounce at the same address means that the current fetch address is the same as the bounce target address and the previous fetch address is the same as the bounce address. When the bounce count of the counter is greater than a preset value, the bounce target address is determined as the loop start address and stored in the loop start address register, and the bounce address is determined as the loop end address and stored in the loop end address register.

11. The instruction fetch address processing method according to claim 10, characterized in that, The instruction fetch address processing method further includes: If the loop start address is not stored in the loop start address register and the loop end address is not stored in the loop end address register, and if the current fetch address is less than the previous fetch address, and the current fetch address is different from the bounce target address in the second register and / or the previous fetch address is different from the bounce address in the third register, then a new potential instruction loop body is determined to be detected.

12. The instruction fetch address processing method according to claim 10, characterized in that, The instruction fetch address processing method further includes: If the loop start address is stored in the loop start address register and the loop end address is stored in the loop end address register, and if the current fetch address is less than the previous fetch address, and at least one of the current fetch address or the previous fetch address is not within the range of the loop start address and the loop end address, then it is determined that a new potential instruction loop body has been detected.

13. The instruction fetch address processing method according to claim 10, characterized in that, The hit detection module includes a fourth register and a fifth register, and the instruction fetch address processing method further includes: When the loop detection unit detects an instruction loop body, at least a portion of the instructions in the instruction loop body is stored in the storage unit; The fetch address of the start instruction in at least a portion of the instructions in the instruction loop body is stored as the cache start address in the fourth register; The fetch address of the end instruction in at least a portion of the instructions in the instruction loop body is stored as the cache end address in the fifth register; Based on the cache start address and the cache end address, determine whether the current fetch address sent by the processor core hits the memory unit.

14. The instruction fetch address processing method according to claim 12, characterized in that, The instruction fetch address processing method further includes: If at least a portion of the instructions in the instruction loop body already exists in the memory cell, and a new instruction loop body is detected, it is determined whether there is an overlapping address between the first address range corresponding to the at least a portion of the instructions in the instruction loop body and the second address range corresponding to the new instruction loop body. If the overlapping address exists and the storage unit has free storage space, then while keeping the instruction corresponding to the overlapping address valid in the storage unit, at least a portion of the instructions in the new instruction loop body, excluding the instruction corresponding to the overlapping address, are stored in the free storage space.

15. The instruction fetch address processing method according to claim 10, characterized in that, The instruction fetch address is a multiple of 4, and the instruction fetch address processing method further includes: For any fetch address between the loop start address and the loop end address, determine the bit value of the fetch address at the target bit position, where the target bit position is the (N+1)th to the 2nd bit, and the capacity of the storage unit is 2 to the power of N, where N is a positive integer. The storage location of the instruction corresponding to the fetch address in the memory unit is determined based on the bit value; The instruction at the fetched address is stored in the storage location of the storage unit.

16. The instruction fetch address processing method according to any one of claims 9-15, characterized in that, The storage unit includes multiple storage locations and a valid flag bit corresponding to each storage location; The instruction fetch address processing method further includes: When a new instruction is written to each storage location, the valid identifier corresponding to that storage location is marked as valid; The cache is located between the processor core and the lower-level cache, and the instruction fetch address processing method further includes: If the corresponding instruction stored in the lower-level cache is cleared, the valid flag of the storage location of the corresponding instruction in the storage unit of the cache is set to invalid, and / or, if the lower-level cache is invalidated, the valid flag of all storage locations in the storage unit of the cache is set to invalid.

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