A cache access method for a gpu primitive assembly stage
By introducing a counter to manage cache lines during the GPU primitive assembly stage, the problem of the inapplicability of existing cache replacement strategies is solved, ensuring that vertex data is acquired quickly and improving primitive assembly efficiency.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- 沐曦科技(成都)有限公司
- Filing Date
- 2026-05-12
- Publication Date
- 2026-06-09
Smart Images
Figure CN122173418A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of chip design technology, and in particular to a cache access method during the GPU primitive assembly stage. Background Technology
[0002] In the 3D graphics rendering pipeline of a GPU, vertex data, as the core input of the primitive assembly unit, is usually stored in a massive amount in the vertex buffer. When the primitive assembly unit performs the assembly operation, it needs to frequently access the vertex data in the vertex buffer. If the vertex buffer is read directly for each access, it will generate a large access latency, which will severely limit the processing throughput of the primitive assembly stage and thus affect the rendering performance of the entire GPU.
[0003] To address the aforementioned vertex data access latency issue, existing technologies typically incorporate a caching module between the primitive assembly unit and the vertex buffer. By temporarily storing frequently accessed vertex data in the cache, subsequent accesses to the same vertex data can be directly retrieved from the cache without repeatedly accessing the vertex buffer, effectively reducing access latency and improving primitive assembly efficiency. However, the cache replacement strategies commonly used in the GPU field are not suitable for this application scenario, impacting the efficiency of the primitive assembly unit in reading vertex data and consequently affecting primitive assembly efficiency. Summary of the Invention
[0004] The purpose of this invention is to provide a cache access method in the GPU primitive assembly stage to improve the efficiency of reading vertex data, thereby improving the processing efficiency of the GPU primitive assembly stage.
[0005] According to the present invention, a cache access method in the GPU primitive assembly stage is provided, the method comprising the following steps: S100: After receiving the vertex data access request sent by the primitive assembly unit, the cache performs a matching and verification between the high-order address of the address in the request and the tag stored in the cache. If they match, proceed to S200; if they do not match, and there is a cache line in the cache with a corresponding counter value of 0, proceed to S300; if they do not match, and there is no cache line in the cache with a corresponding counter value of 0, proceed to S400.
[0006] S200, increment the counter of the cache line corresponding to the matched label by 1, and return the vertex data in the cache line corresponding to the matched label to the primitive assembly unit; and, after the primitive assembly unit completes the processing of the primitive processing request, decrement the counter of the cache line corresponding to the matched label by 1.
[0007] S300, increment the counter of the specified cache line by 1, and return the vertex data corresponding to the mismatched high-order address read from the vertex buffer to the primitive assembly unit via the specified cache line; and, after the primitive assembly unit completes the processing of the primitive processing request, decrement the counter of the specified cache line by 1; the specified cache line is the cache line in the cache that is closest to the pointer of the cache line and whose corresponding counter value is 0.
[0008] S400, wait until there is a cache line in the cache with a corresponding counter value of 0, then execute S300.
[0009] Compared with the prior art, the present invention has at least the following beneficial effects: In this invention, each cache line in the cache has a corresponding counter. If the cache is hit, the counter of the cache line corresponding to the matching tag is incremented by 1, and after the request is processed, the counter of the cache line corresponding to the matching tag is decremented by 1. If the cache is not hit, and there is a cache line in the cache with a corresponding counter value of 0, the counter of the specified cache line is incremented by 1, and after the request is processed, the counter of the specified cache line is decremented by 1. If there is no match, and there is no cache line in the cache with a corresponding counter value of 0, the process waits until a cache line with a corresponding counter value of 0 is found, and then the above steps are executed. Based on this, if vertex data in a cache line is used by the primitive assembly unit, the counter value of that cache line is not 0, and the vertex data in that cache line will not be replaced by other vertex data. Furthermore, when vertex data in that cache line is used simultaneously by two or more requests processed by the primitive assembly unit (adjacent primitives often share some vertex data), the counter value of that cache line equals the number of requests. Only after all requests have been processed does the counter value of that cache line equal 0, and only then can the vertex data in that cache line be replaced. Compared to existing cache replacement strategies, this invention prevents cache lines from being replaced as long as the counter value of a cache line is greater than 0. This fundamentally avoids the problem of cache lines containing currently requested vertex data being mistakenly evicted, ensuring that the primitive assembly unit can continuously and quickly retrieve the required data from the cache, improving the efficiency of vertex data reading, and thus improving the processing efficiency of the GPU primitive assembly stage. Attached Figure Description
[0010] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0011] Figure 1 A flowchart of a cache access method during the GPU primitive assembly stage provided in an embodiment of the present invention; Figure 2 A schematic diagram showing the connection of the primitive assembly unit, buffer, and vertex buffer provided in an embodiment of the present invention; Figure 3 This is a schematic diagram of the graphic elements provided in the embodiments of the present invention. Detailed Implementation
[0012] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0013] According to this embodiment, a cache access method is provided during the GPU primitive assembly stage. The method includes the following steps: Figure 1 As shown: S100: After receiving the vertex data access request sent by the primitive assembly unit, the cache performs a matching and verification between the high-order address of the address in the request and the tag stored in the cache. If they match, proceed to S200; if they do not match, and there is a cache line in the cache with a corresponding counter value of 0, proceed to S300; if they do not match, and there is no cache line in the cache with a corresponding counter value of 0, proceed to S400.
[0014] In this embodiment, the primitive assembly unit is called a Primitive Assembly Unit (PA unit); the cache is dedicated to primitive assembly.
[0015] As a specific implementation, prior to S100, the method further includes: after receiving a primitive processing request carrying a vertex index, the primitive assembly unit obtains the address of the vertex data corresponding to the vertex index according to the vertex index carried in the primitive processing request, and sends a vertex data access request including the address to the cache, such as... Figure 2As shown; the number of vertex indices carried in the primitive processing request is greater than or equal to 1. In one specific implementation, the address = vertex buffer base address + vertex index × single vertex data size. The vertex buffer is a buffer specifically used to store vertex data. For example, the total number of vertices is 64, and the vertex indices are 0-63. Another example is the total number of vertices being 128, with vertex indices ranging from 0-127. In this embodiment, the bit width of the address is the sum of the bit width of the label (i.e., the bit width of the high-order address) and the bit width of the offset address (i.e., the low-order address). The bit width of the offset address is determined based on the number of vertex data that a single cache line can store. In one specific implementation, the bit width of the offset address satisfies 2... m The smallest integer value of m that is greater than or equal to the number of vertex data that a single cache line can store. For example, if a single cache line can store 4 vertex data, then the bit width of the offset address is 2. As another example, if a single cache line can store 8 vertex data, then the bit width of the offset address is 3.
[0016] In one specific implementation, the bit width of the label is determined based on the total number of vertices, the size of the vertex data stored in a single cache line, and the size of a single vertex data. In another specific implementation, the bit width of the label satisfies 2... n The smallest integer value of n that satisfies the condition ≥ total number of vertices / (size of vertex data stored in a single cache line / size of a single vertex data). For example, if the total number of vertices is 64, and a single cache line stores 4 vertex data, the label's bit width is 4. As another example, if the total number of vertices is 128, and a single cache line stores 4 vertex data, the label's bit width is 5.
[0017] It should be understood that the ratio of the size of the vertex data stored in a single cache line to the size of a single vertex data is the number of vertex data that a single cache line can store. For example, if a single cache line can store 4 vertex data, it means that a single cache line stores 4 vertex data. For example, a cache line might store vertex data with indices 0, 1, 2, and 3. Optionally, vertex data includes coordinates, etc. As another example, if a single cache line can store 8 vertex data, it means that a single cache line stores 8 vertex data. For example, a cache line might store vertex data with indices 0, 1, 2, 3, 4, 5, 6, and 7. Optionally, vertex data includes coordinates, etc.
[0018] In one specific implementation, the primitive is a triangle, and the number of vertex indices carried in the primitive processing request is 3. Alternatively, the primitive is a line, and the number of vertex indices carried in the primitive processing request is 2.
[0019] For example, if the primitive is a triangle, and the primitive processing request carries vertex indices 0, 1, and 2, then... Figure 3 As shown. When the total number of vertices is 64 (vertices are indices 0-63), and a single cache line stores 4 vertex data, the cache consists of 8 cache lines (cache line IDs 0-7). If the cache line with ID 0 stores vertex data for vertices 0, 1, 2, and 3, then the tag corresponding to the cache line with ID 0 matches the high-order address in the request, which is 0000. If none of the cache lines with IDs 0-7 store vertex data for vertices 0, 1, 2, and 3, then no cache line matches the high-order address in the request.
[0020] For example, consider a triangle as a primitive, with vertex indices 1, 3, and 4 carried in the primitive processing request. When the total number of vertices is 64 (vertex indices 0-63), and a single cache line stores 4 vertex data, the cache consists of 8 cache lines (cache line IDs 0-7). If cache line ID 0 stores vertex data for vertices 0, 1, 2, and 3, and cache line ID 1 stores vertex data for vertices 4, 5, 6, and 7, then the tag corresponding to cache line ID 0 matches the high-order address of vertices 1 and 3 in the request, both being 0000; the tag corresponding to cache line ID 1 matches the high-order address of vertex 4 in the request, both being 0001. If none of the cache lines IDs 0-7 store vertex data for vertices 4, 5, 6, and 7, then no cache line matches the high-order address of vertex 4 in the request.
[0021] S200, increment the counter of the cache line corresponding to the matched label by 1, and return the vertex data in the cache line corresponding to the matched label to the primitive assembly unit; and, after the primitive assembly unit completes the processing of the primitive processing request, decrement the counter of the cache line corresponding to the matched label by 1.
[0022] It should be understood that if the counter value of the cache line corresponding to the matched tag is 0, then after incrementing the counter by 1, the counter value of the cache line corresponding to the matched tag will be 1. If the counter value of the cache line corresponding to the matched tag is 1, then after incrementing the counter by 1, the counter value of the cache line corresponding to the matched tag will be 2. And so on.
[0023] It should be understood that if the counter value of the cache line corresponding to the matched label is 1, then after decrementing the counter by 1, the counter value of the cache line corresponding to the matched label will be 0. If the counter value of the cache line corresponding to the matched label is 2, then after decrementing the counter by 1, the counter value of the cache line corresponding to the matched label will be 1, which is still not 0. This indicates that in addition to the completed primitive processing request, other primitive processing requests are also using the vertex data in the cache line corresponding to the matched label. For example, if the primitive is a triangle, the primitive assembly unit first receives a primitive processing request carrying vertex indices 0, 1, and 2, and then receives another primitive processing request carrying vertex indices 1, 2, and 3. The high-order bits of the address of the vertex data corresponding to vertices 0, 1, 2, and 3 are 0000, which matches the tag (also 0000) corresponding to the cache line with id 0 in the cache. Then, when neither of the above primitive processing requests is completed, the counter value of the cache line with id 0 in the cache is 2. Even if the primitive assembly unit completes the primitive processing request carrying vertex indices 0, 1, and 2 (but does not complete the primitive processing request carrying vertex indices 1, 2, and 3), the counter value of the cache line with id 0 in the cache is 1, which is still not 0. The vertex data in the cache line with id 0 in the cache is still in a state where it cannot be replaced by other vertex data.
[0024] S300, increment the counter of the specified cache line by 1, and return the vertex data corresponding to the mismatched high-order address read from the vertex buffer to the primitive assembly unit via the specified cache line; and, after the primitive assembly unit completes the processing of the primitive processing request, decrement the counter of the specified cache line by 1; the specified cache line is the cache line in the cache that is closest to the pointer of the cache line and whose corresponding counter value is 0.
[0025] In this embodiment, if the primitive processing request includes two or more vertex indices, then the vertex data access request sent by the primitive assembly unit received by the cache includes two or more addresses. The high-order addresses of these two addresses may be the same or different. If the high-order addresses are different, some high-order addresses may match the tags in the cache, while others may not. In this case, the different high-order addresses are processed separately.
[0026] For example, if a primitive processing request includes 3 vertex indices, then the vertex data access request sent by the primitive assembly unit received by the cache includes 3 addresses. If the high-order addresses of the 3 addresses are all the same, and the high-order address does not match the label in the cache, then the cache needs to send 1 data read request to the vertex buffer.
[0027] For example, if a primitive processing request includes 3 vertex indices, then the vertex data access request sent by the primitive assembly unit received by the cache includes 3 addresses. If only 2 of the 3 addresses have the same high-order address, then these 3 addresses correspond to 2 high-order addresses. If neither of these 2 high-order addresses matches the label in the cache, then the cache needs to send 2 data read requests to the vertex buffer.
[0028] For example, if a primitive processing request includes three vertex indices, then the vertex data access request received by the primitive assembly unit in the cache includes three addresses. If the high-order bits of the three addresses are all different, and none of the three high-order bits match the labels in the cache, then the cache needs to send three data read requests to the vertex buffer. Each data read request retrieves one vertex data with a matching high-order address from the vertex buffer, and then places the retrieved vertex data into one cache line. Specifically, if the counters for three cache lines in the cache are 0, then three data read requests are sent to the vertex buffer, and the vertex data returned by each data read request is placed into one cache line with a counter value of 0. If the counters for only two cache lines in the cache are 0, then two data read requests are sent to the vertex buffer first, and a third data read request is sent only after the counter for another cache line is 0; the vertex data returned by each data read request is placed into one cache line with a counter value of 0. If the counter for only one cache line in the cache is 0, then two data read requests are sent to the vertex buffer first. The remaining data read requests are sent to the vertex buffer only after the counter for another cache line reaches 0. If the counter for no cache line in the cache is 0, then data read requests are sent to the vertex buffer only after the counter for a cache line reaches 0.
[0029] In one specific implementation, the size of a single cache line is equal to the size of a single storage unit in the vertex buffer.
[0030] In one specific implementation, the process of obtaining a specified cache line includes: starting from the current position of the cache line pointer, determining whether the counter value of the cache line pointed to by the pointer is 0. If not, the pointer moves down until the counter value of the cache line pointed to by the pointer is 0, and the cache line pointed to by the pointer is determined as the specified cache line. If, when the pointer moves down to the last cache line, there is still no cache line with a counter value of 0, the determination begins again from the first cache line. If the corresponding counter value is not 0, the pointer moves down until the counter value of the cache line pointed to by the pointer is 0, and the cache line pointed to by the pointer is determined as the specified cache line.
[0031] As a specific implementation, the process of moving the pointer of the cache line includes: S010, when all cache lines of the cache are empty, the pointer points to the first cache line of the cache; if vertex data is stored in the first cache line, the pointer executes the second cache line; and so on, until the pointer points to the last cache line of the cache line and vertex data is also stored in the last cache line, then proceed to S020.
[0032] S020, if the counter value of other cache lines in the cache line is 0, the pointer jumps to the cache line that is closest to the pointer and whose corresponding counter value is 0; otherwise, the pointer does not move.
[0033] In this embodiment, if the counter value of the last cache line becomes 0 before the counters of other cache lines, then the pointer also points to the last cache line.
[0034] In this embodiment, the meaning of "nearest" is already included in the description of the specified cache line, and will not be repeated here.
[0035] Based on S010-S020, precise control of the pointers to cache lines can be achieved.
[0036] In this embodiment, the process of moving the pointer of the cache line further includes: if the counter of the cache line (not limited to the last cache line) pointed to by the pointer is not 0, and there are other cache lines in the cache whose counter values are not 0, then the pointer is moved to the cache line that is closest to the pointer and whose corresponding counter value is 0.
[0037] S400, wait until there is a cache line in the cache with a corresponding counter value of 0, then execute S300.
[0038] In this embodiment, if vertex data in a cache line is used by the primitive assembly unit, the counter value of that cache line is not 0, and the vertex data in that cache line will not be replaced by other vertex data. Furthermore, when vertex data in that cache line is used simultaneously by two or more requests processed by the primitive assembly unit (adjacent primitives often share some vertex data), the counter value of that cache line equals the number of requests. Only after all requests have been processed does the counter value of that cache line equal 0, and only then can the vertex data in that cache line be replaced. Compared to existing cache replacement strategies, this embodiment ensures that as long as the counter value of a cache line is greater than 0, that cache line will not be replaced. This fundamentally avoids the problem of erroneously evicting the cache line containing the vertex data currently being requested, ensuring that the primitive assembly unit can continuously and quickly retrieve the required data from the cache, improving the efficiency of vertex data reading, and thus improving the processing efficiency of the GPU primitive assembly stage.
[0039] While specific embodiments of the invention have been described in detail by way of example, those skilled in the art should understand that the examples are for illustrative purposes only and not intended to limit the scope of the invention. It should also be understood that various modifications can be made to the embodiments without departing from the scope and spirit of the invention. The scope of the invention is defined by the appended claims.
Claims
1. A cache access method during the GPU primitive assembly stage, characterized in that, The method includes the following steps: S100: After receiving the vertex data access request sent by the primitive assembly unit, the cache performs a matching and verification between the high-order address of the address in the request and the tag stored in the cache. If they match, proceed to S200; if they do not match, and there is a cache line in the cache with a corresponding counter value of 0, proceed to S300; if they do not match, and there is no cache line in the cache with a corresponding counter value of 0, proceed to S400. S200, increment the counter of the cache line corresponding to the matched label by 1, and return the vertex data in the cache line corresponding to the matched label to the primitive assembly unit; and, after the primitive assembly unit completes the processing of the primitive processing request, decrement the counter of the cache line corresponding to the matched label by 1. S300, increment the counter of the specified cache line by 1, and return the vertex data corresponding to the mismatched high-order address read from the vertex buffer to the primitive assembly unit via the specified cache line; and, after the primitive assembly unit completes the processing of the primitive processing request, decrement the counter of the specified cache line by 1; the specified cache line is the cache line in the cache that is closest to the pointer of the cache line and whose corresponding counter value is 0; S400, wait until there is a cache line in the cache with a corresponding counter value of 0, then execute S300.
2. The cache access method in the GPU primitive assembly stage according to claim 1, characterized in that, Prior to S100, the method further includes: after receiving a primitive processing request carrying a vertex index, the primitive assembly unit obtains the address of the vertex data corresponding to the vertex index according to the vertex index carried in the primitive processing request, and sends the vertex data access request including the address to the cache; the number of vertex indexes carried in the primitive processing request is greater than or equal to 1.
3. The cache access method in the GPU primitive assembly stage according to claim 2, characterized in that, The primitive is a triangle, and the number of vertex indices carried in the primitive processing request is 3.
4. The cache access method in the GPU primitive assembly stage according to claim 1, characterized in that, The process of moving the pointer to the cache line includes: S010, when all cache lines are empty, the initial value of the counters for all cache lines is 0, and the pointer points to the first cache line; if vertex data is stored in the first cache line, the pointer executes the second cache line; and so on, until the pointer points to the last cache line and vertex data is also stored in the last cache line, then proceed to S020; S020, if the counter value of other cache lines in the cache line is 0, the pointer jumps to the cache line that is closest to the pointer and whose corresponding counter value is 0; otherwise, the pointer does not move.
5. The cache access method in the GPU primitive assembly stage according to claim 1, characterized in that, The bit width of the label is determined based on the total number of vertices, the size of the vertex data stored in a single cache line, and the size of a single vertex data.
6. The cache access method in the GPU primitive assembly stage according to claim 2, characterized in that, Address = Vertex buffer base address + Vertex index × Single vertex data size 7. The cache access method in the GPU primitive assembly stage according to claim 1, characterized in that, The size of a single cache line is equal to the size of a single storage unit in the vertex buffer.
8. The cache access method in the GPU primitive assembly stage according to claim 1, characterized in that, The process of obtaining a specified cache line includes: starting from the current position of the cache line pointer, determining whether the value of the counter of the cache line pointed to by the pointer is 0. If not, the pointer moves down until the value of the counter of the cache line pointed to by the pointer is 0, and the cache line pointed to by the pointer is determined to be the specified cache line.