Direct access memory device and data processing method
By splitting the target matrix into sub-matrices and generating adaptive read/write packet information, the problem that DMA matrix transpose technology cannot handle matrices of arbitrary size is solved, improving hardware resource utilization and data transpose efficiency, and alleviating performance bottlenecks and resource waste.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- 太初(无锡)电子科技有限公司
- Filing Date
- 2026-01-15
- Publication Date
- 2026-06-09
AI Technical Summary
Existing DMA matrix transpose technology cannot handle matrix data of arbitrary size, and there is a trade-off between resource efficiency and performance, resulting in performance bottlenecks and waste of hardware resources in dynamically changing application scenarios.
The descriptor processing module and the transpose processing module are used to split the target matrix into multiple sub-matrices according to the capacity of the transpose unit sub-module, generate read packet information and write packet information, and perform data reading and writing through the maximum bandwidth of the bus to achieve adaptive matrix transpose processing.
It improves hardware resource utilization, reduces the area and power consumption of dedicated transposition hardware, alleviates memory access latency and blocking issues, and enhances bus utilization and data transposition efficiency.
Smart Images
Figure CN122173420A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of direct memory access technology, and more specifically to direct memory access devices and data processing methods. Background Technology
[0002] In modern computing systems, Direct Memory Access (DMA) technology directly transfers data between memory and external devices without continuous CPU intervention, thereby freeing up CPU computing power and improving system energy efficiency. With the rise of artificial intelligence and scientific computing, matrix operations have become a core bottleneck and key to optimization in computing performance. In scenarios involving high-dimensional data reconstruction, such as matrix transposition, DMA technology has evolved from a basic data transporter to an intelligent data reconstruction engine. Its development trajectory is clearly presented: from early dedicated transposition transfers that only supported fixed modes, to later flexible data reconstruction capabilities with configurable and multi-mode features. Currently, cutting-edge research focuses on dynamically adaptive transposition strategies, aiming to optimize data partitioning, access order, and pipeline scheduling based on matrix size and hardware resources. This transforms inefficient, discontinuous access at the macro level into efficient, continuous, parallel operations at the micro level, maximizing the release of memory bandwidth and computing potential.
[0003] In existing technologies, DMA matrix transposition typically employs a block-based general architecture. First, the large matrix is divided into sub-blocks matching the on-chip cache. The DMA controller reads these sub-blocks row by row, rearranges the row and column elements in a dedicated buffer, and finally writes them out column by column. This approach requires the target matrix's dimensions to match the cache sub-blocks. This limitation prevents it from directly processing matrix data of arbitrary sizes. Furthermore, when memory access latency is high and read responses return out of order, this scheme is prone to severe blocking of the entire sub-block transposition processing module due to a few unreturned requests, creating a performance bottleneck. Moreover, in the above approach, the performance of DMA matrix transposition is highly dependent on the sub-block size setting. Sub-blocks that are too small significantly reduce memory access bandwidth efficiency, while sub-blocks that are too large drastically increase the hardware resource overhead and power consumption of the on-chip buffer. This inherent contradiction between resource efficiency and performance makes it difficult for existing solutions to achieve stable and efficient data transposition in dynamically changing application scenarios. Summary of the Invention
[0004] This invention provides a direct memory access device and a data processing method to solve the problem in the prior art that the length and width of the target matrix must match the cache sub-blocks, which makes it impossible to directly process matrix data of arbitrary size.
[0005] In a first aspect, the present invention provides a direct memory access device, including a descriptor processing module and a transpose processing module. The descriptor processing module receives descriptors, splits a target matrix into several sub-matrices based on the descriptor information and the capacity of the transpose unit sub-module, calculates the sub-matrix write packet information for each sub-matrix, and simultaneously extracts multiple read packet information for reading sub-matrix row data according to the maximum bus bandwidth. The read packet information and sub-matrix write packet information are sent to the transpose processing module. When the transpose processing module receives the read response data corresponding to each read packet information, it writes the read response data to the transpose unit sub-module of the transpose processing module for transpose processing to obtain multiple transposed sub-matrices, and extracts the write packet information corresponding to each row according to the sub-matrix write information, and rearranges the transposed sub-matrix data to obtain a write request.
[0006] The apparatus provided in this invention, upon receiving a descriptor, adaptively splits the transpose task of a large target matrix into multiple sub-matrices matching the capacity of the transpose unit sub-module. This achieves the effect of processing arbitrarily large-scale matrix transpose tasks with small-capacity transpose unit sub-modules, reducing the area and power consumption of dedicated transpose hardware while significantly improving hardware resource utilization. Furthermore, in this embodiment, the read packet information is generated based on the maximum bus bandwidth. If the row data of a sub-matrix is less than the maximum bus bandwidth, the same row data from multiple sub-matrices can be merged into a single bus transaction for reading. This combines multiple memory accesses for multiple narrow-width data into a single, efficient full-width access, thereby increasing bus utilization to near its theoretical peak. Moreover, increasing the amount of data acquired in a single transaction effectively alleviates the interruption problem caused by memory access latency and the blocking problem caused by the failure to return data from individual rows of the matrix.
[0007] In one optional implementation, the descriptor processing module includes a descriptor management submodule, a transpose read / split packet submodule, and a read request sending submodule. The descriptor management submodule receives descriptors and sends the transpose information in the descriptors to the transpose read / split packet submodule. The transpose read / split packet submodule splits the target matrix into multiple submatrices according to the capacity of the transpose unit submodule and the transpose information, and calculates the read packet information and write packet information of each submatrix. The read packet information is sent to the transpose processing module and the read request sending submodule, and the submatrix write packet information is sent to the transpose processing module. The read request sending submodule converts the read packet information into read requests that satisfy the interface protocol and sends them sequentially to the data storage system, so that the data storage system returns the corresponding read response data according to the read request information.
[0008] In one optional implementation, the read packet information includes a storage address and a transpose unit storage pointer. The transpose processing module includes a data control submodule, a transpose write / disassemble submodule, a transpose unit submodule, a data storage submodule, a read response processing submodule, and a write request processing submodule. The data control submodule receives the read packet information; the transpose write / disassemble submodule receives the submatrix write packet information; the read response processing submodule receives the read response data and determines the storage address corresponding to the read response data based on the read packet information stored in the data control submodule, and writes the read response data to the data storage submodule according to the storage address; when the transpose unit submodule is idle, the data control submodule extracts data from the data storage submodule according to the read packet information and writes the data to the transpose unit submodule according to the transpose unit storage pointer; the transpose unit submodule transposes the data; the transpose write / disassemble submodule disassembles the submatrix write packet information to obtain the write packet information corresponding to each row, and sends the write packet information to the write request processing submodule; the write request processing submodule rearranges the transposed submatrix data according to the write packet information to obtain a write request that satisfies the interface protocol.
[0009] In one optional implementation, after the data control submodule extracts data from the data storage submodule according to the read packet information and writes the data into the transpose unit submodule according to the transpose unit storage pointer, the read packet is deleted, the corresponding data storage space is released, and the newly extracted read packet information is stored in the released data storage space.
[0010] In one alternative implementation, the transpose unit submodule performs transpose processing on the two submatrices in parallel.
[0011] Secondly, the present invention provides a data processing method for direct memory access, comprising: receiving a descriptor; splitting a target matrix into several sub-matrices based on the descriptor information and the capacity of a transpose unit submodule; calculating submatrix write packet information for each submatrix; and simultaneously extracting multiple read packet information for reading row data of the submatrix according to the maximum bus bandwidth; when receiving read response data corresponding to each read packet information, writing the read response data to the transpose unit submodule for transpose processing according to the read packet information to obtain multiple transposed submatrices; extracting write packet information corresponding to each row according to the submatrix write packet information; and rearranging the transposed submatrix data to obtain a write request that satisfies the interface protocol.
[0012] Thirdly, the present invention provides an electronic device comprising: a memory and a processor, wherein the memory and the processor are communicatively connected to each other, the memory stores computer instructions, and the processor executes the computer instructions to perform the data processing method for direct access to memory described in the second aspect.
[0013] Fourthly, the present invention provides a computer-readable storage medium storing computer instructions for causing a computer to perform the data processing method for direct access to memory described in the second aspect.
[0014] Fifthly, the present invention provides a computer program product, including computer instructions for causing a computer to execute the data processing method for direct access to memory described in the second aspect above. Attached Figure Description
[0015] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.
[0016] Figure 1 This is a first schematic diagram of a direct access memory control device according to an embodiment of the present invention; Figure 2 This is a schematic diagram illustrating the division of a target matrix into multiple sub-matrices according to an embodiment of the present invention; Figure 3 This is a schematic diagram of the transpose unit submodule performing transpose processing on the submatrix according to an embodiment of the present invention; Figure 4 This is a second schematic diagram of a direct access memory control device according to an embodiment of the present invention; Figure 5 This is a flowchart illustrating a data processing method for directly accessing memory according to an embodiment of the present invention; Figure 6 This is a schematic diagram of the hardware structure of an electronic device according to an embodiment of the present invention. Detailed Implementation
[0017] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0018] It is understood that before using the technical solutions disclosed in the various embodiments of the present invention, users should be informed of the types, scope of use, and usage scenarios of the personal information involved in the present invention and their authorization should be obtained in accordance with relevant laws and regulations through appropriate means.
[0019] In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.
[0020] According to embodiments of the present invention, a direct memory access device is provided, such as... Figure 1 As shown, it includes a descriptor processing module and a transpose processing module. The descriptor processing module receives the descriptor, splits the target matrix into several sub-matrices based on the descriptor information and the capacity of the transpose unit sub-module, calculates the sub-matrix write packet information for each sub-matrix, and simultaneously extracts multiple read packet information for reading the row data of the sub-matrix according to the maximum bus bandwidth; and sends the read packet information and sub-matrix write packet information to the transpose processing module.
[0021] In an optional embodiment, the descriptor is initiated by the core. The data granularity of the target matrix, the matrix size, and the step size for reading / writing data in each row of the matrix can be dynamically configured in the descriptor. After receiving the descriptor, the direct access memory control device processes the target matrix according to the descriptor.
[0022] In an optional embodiment, when transposing the target matrix, it is necessary to write the target matrix into the transpose unit submodule for transpose processing. In this embodiment, the target matrix is split into multiple submatrices of a size matching the capacity of the transpose unit submodule, enabling the transpose unit submodule to transpose each submatrix. To transpose multiple submatrices in parallel using the transpose unit submodule, the width of the transpose unit submodule can be set to be the same as the width of the submatrices, and the length of the transpose unit submodule can be set to twice the number of rows in the submatrices to support ping-pong operations and achieve non-blocking continuous read and write of two submatrices.
[0023] In an optional embodiment, after splitting the target matrix into multiple sub-matrices, it is also necessary to form sub-matrix write packet information for each sub-matrix, so that the write packet information of each row can be obtained by decomposing according to the sub-matrix write packet information, and the transposed sub-matrix can be written out row by row. The sub-matrix write packet information includes the starting address of the sub-matrix being written, the row step of the written matrix, the row / column size of the sub-matrix, the transpose granularity, and other information.
[0024] In an optional embodiment, the target matrix needs to be read before it can be transposed. To ensure that the data can be transposed directly after reading the data, the read packet information in this embodiment is constructed based on the sub-matrix obtained by splitting. It includes information such as read request address, read length, data storage address, transpose unit storage pointer, and sub-matrix row size. After reading the data, the transpose unit sub-module can be written according to the read packet information to directly form the transposed sub-matrix.
[0025] While it's possible to read one row of data from each submatrix at a time, obtaining the complete submatrix through multiple reads, this method is slow and wastes bus resources when the bus width exceeds the row length of the submatrix. Therefore, in this embodiment of the invention, a single read packet is used to read row data from multiple submatrixes according to the maximum bus bandwidth. For example, in... Figure 2 In the illustrated embodiment, if the bus length is twice the size of the transposed unit submodule, and the length and width of the target matrix are four times and three times that of the transposed unit submodule, respectively, then each read request generated based on the read packet information can read the row data of two submatrices, thus improving resource utilization.
[0026] When the transpose processing module receives the read response data corresponding to each read packet information, it writes the read response data into the transpose unit submodule of the transpose processing module according to the read packet information to perform transpose processing to obtain multiple transpose submatrices. The submatric write packet information is then split into write packet information for each row of the submatric. The transpose submatrices are rearranged according to the write packet information to obtain the write request.
[0027] In an optional embodiment, since a read request generated by a single read packet can simultaneously retrieve row data from multiple sub-matrices, the data in the read response data includes row data from multiple sub-matrices. For example, in... Figure 3 In the embodiment shown, if a read request can simultaneously obtain row data of two submatrices, then after reading n times, two submatrices with n rows of data can be obtained. The two submatrices are then transposed, and after transposition, each submatric is read out row by row.
[0028] In an optional embodiment, when the DMA receives a transpose task sent by another system and completes the transpose processing of the data, it needs to write the transpose matrix to the destination address indicated by the transpose task. In order to complete the write operation, the transpose processing module needs to extract the write packet information of each row by combining the submatrix write packet information, rearrange the data of each row in the submatrix to obtain the corresponding write request, so that the transpose data can be written to the destination address indicated by the transpose task based on the write request.
[0029] In an optional embodiment, since the submatrix write packet information is the information corresponding to the transposed submatrix, but the tail address of the previous row and the first address of the next row of the same submatrix are not equal, it is necessary to calculate the first address of each row of the submatrix and the storage address in the transposed unit, etc., to facilitate the extraction of data from the transposed unit submodule for rearrangement and generation of write requests.
[0030] In one alternative embodiment, the write request conforms to the interface protocol.
[0031] The apparatus provided in this invention, upon receiving a descriptor, adaptively splits a large target matrix task into multiple sub-matrices matching the capacity of the transpose unit sub-module. This achieves the effect of processing arbitrarily large-scale matrix transpose tasks with small-capacity transpose unit sub-modules, reducing the area and power consumption of dedicated transpose hardware while significantly improving hardware resource utilization. Furthermore, in this embodiment, the read packet information is generated based on the maximum bus bandwidth. If the row data of a sub-matrix is less than the maximum bus bandwidth, the same row data from multiple sub-matrices can be merged into a single bus transaction for reading. This combines multiple memory accesses for multiple narrow-width data into a single, efficient full-width access, thereby increasing bus utilization to near its theoretical peak. Moreover, increasing the amount of data acquired in a single transaction effectively alleviates the interruption problem caused by memory access latency and the blocking problem caused by the failure to return data from individual rows of the matrix.
[0032] In an alternative embodiment, such as Figure 4 As shown, the descriptor processing module includes a descriptor management submodule, a transpose read / disassemble submodule, and a read request sending submodule.
[0033] The descriptor management submodule receives the descriptor and sends the transpose information in the descriptor to the transpose read / disassemble submodule.
[0034] The transpose read / split packet submodule splits the target matrix into multiple submatrices based on the capacity of the transpose unit submodule and the transpose information, and calculates the read packet information and write packet information for each submatrix; it then sends the read packet information to the transpose processing module and the read request sending submodule, and sends the submatrix write packet information to the transpose processing module.
[0035] In one optional embodiment, the read packet information includes information such as read request address, read length, data storage address, and transpose unit storage pointer.
[0036] In an optional embodiment, the read request address in each read packet information refers to the first read request address. The read request address in each read packet information is not the same. It is calculated based on the starting address of the first data in the target matrix, the bus width, the row length of each sub-matrix, and the step size.
[0037] In one optional embodiment, the read length in the read packet information is determined based on the bus width; for example, in... Figure 2 In the embodiment shown, the read length in the read packet information is the bus width.
[0038] In an optional embodiment, the data storage address is used to characterize the location where the data corresponding to the read packet information needs to be stored. The data storage address in each read packet information is not the same and is obtained by polling and arbitrating the available addresses in the data storage submodule, and the storage offset is made according to the address. The data storage submodule includes multiple single-port static random-access memory (SRAM). The above-mentioned method of determining the storage address can reduce read and write conflicts of single-port SRAM and improve performance. Because single-port SRAM has a smaller area than dual-port SRAM, multiple single-port SRAMs can be used to constitute the data storage submodule in this embodiment of the invention.
[0039] In an optional embodiment, the transpose unit stores a pointer to represent the position corresponding to the data corresponding to the read packet information when it is written to the transpose unit submodule.
[0040] The read request sending submodule converts the read packet information into read requests and sends them to the data storage system in succession, so that the data storage system can return the corresponding read response data according to the read request.
[0041] In an optional embodiment, the read request sending submodule converts the read packet information into a read request that meets the interface protocol requirements and sends it sequentially.
[0042] In an alternative embodiment, such as Figure 4 As shown, the transpose processing module includes a data control submodule, a transpose write / disassemble submodule, a transpose unit submodule, a data storage submodule, a read response processing submodule, and a write request processing submodule.
[0043] The data control submodule receives packet reading information.
[0044] The transpose write-and-split-packet submodule receives packet information from the submatrix.
[0045] The read response processing submodule receives the read response data and determines the storage address corresponding to the data in the read response data based on the read packet information stored in the data control submodule. Then, it writes the data in the read response data into the data storage submodule according to the storage address.
[0046] When the transpose unit submodule is idle, the data control submodule extracts data from the data storage module according to the packet reading information and writes the data into the transpose unit submodule according to the transpose unit storage pointer.
[0047] In an optional embodiment, after the data control submodule extracts data from the data storage submodule according to the read packet information and writes the data into the transpose unit submodule according to the transpose unit storage pointer, it deletes the read packet information, releases the corresponding data storage space, and uses the released data storage space to store the newly extracted read packet information.
[0048] The transpose unit submodule performs transpose processing on the data.
[0049] In one optional embodiment, the transpose unit submodule includes multiple SRAMs. The width of the SRAM is the same as the matrix granularity, and the length is twice the number of rows of data in the submatrix, to support ping-pong operations and achieve non-blocking continuous read and write of the two submatrixes. Using multiple SRAMs allows row data to be filled into the transpose unit submodule within one cycle. After all row data of the submatrix has been filled into the transpose unit submodule, data is read out row by row according to the address offset.
[0050] In an optional embodiment, the transpose unit submodule performs transpose processing on the two submatrices in parallel.
[0051] For example, if the transpose cell submodule is a dual-port SRAM with a width of 64B and a depth of 128, and the submatrix size is 64B×64, then the transpose cell submodule supports writing to one submatrix while reading out another submatrix, thus achieving non-blocking continuous read and write of the two submatrixes.
[0052] The transpose write-packet splitting submodule decomposes the write packet information of the submatrix to obtain the write packet information of each row of the submatrix, and sends the write packet information to the write request processing submodule.
[0053] In one optional embodiment, the write packet information includes the address of each row of the transposed submatrix, the data length, and the storage address in the transposed unit submodule.
[0054] In an alternative embodiment, when generating write packet information, the size of the small-capacity transpose unit submodule is matched to write the transpose submatrix line by line, eliminating the need to allocate a large output buffer for the entire large matrix and minimizing matrix caching requirements.
[0055] The write request processing submodule rearranges the transposed submatrix data row by row based on the write packet information to obtain the write request.
[0056] In the apparatus provided in this embodiment of the invention, after the data control submodule extracts data from the data storage submodule according to the read packet information and writes the data to the transpose unit submodule according to the transpose unit storage pointer, the data control submodule deletes the read packet information and releases the corresponding data storage space. After releasing the data storage space, new read packet information can be extracted, ensuring that the number of memory access transactions in the network remains high. Simultaneously, the transpose unit submodule supports parallel transpose of two submatrices. While one submatric is performing transpose, the other submatric can simultaneously perform data write operations, thereby eliminating the idle waiting period between different task stages of the transpose unit submodule and keeping its operating efficiency consistently near its peak.
[0057] This embodiment provides a direct memory access control device, such as... Figure 4 As shown, it includes a descriptor management submodule, a transpose read / disassemble submodule, a read request sending submodule, a data control submodule, a transpose write / disassemble submodule, a transpose unit submodule, a data storage submodule, a read response processing submodule, and a write request processing submodule. Each submodule processes data by executing the following steps: ① The kernel initiates descriptor instructions to DMA. The descriptor can be dynamically configured with the granularity of the data to be transposed, the matrix size, and the step size for reading / writing data in each row of the matrix.
[0058] ② The descriptor management submodule identifies and stores the task type of the descriptor, and parses out the transpose-related information and sends it to the transpose read / disassemble submodule.
[0059] ③ The transpose read / disassemble submodule adaptively extracts read packet information and submatrix write packet information based on the descriptor information. In this example, assuming the bus length is twice the size of the transpose unit submodule, and the original matrix's length and width are 4 times and 3 times that of the transpose unit submodule, respectively, the disassembly process is as follows: Figure 2 As shown.
[0060] To fully utilize bandwidth, the single read packet information extracted by the transpose read / split submodule corresponds to the same row of two sub-matrices. This read packet information includes the read request address, read length, data storage address, and transpose unit pointer, and is sent to the data control submodule and the read request sending submodule. Simultaneously, to conserve hardware resources required by the transpose unit submodule, the DMA will split a large matrix larger than the transpose unit submodule into multiple smaller matrices for transposition, according to the size of the transpose unit submodule. Therefore, the transpose read / split submodule also needs to extract sub-matrix write packet information to indicate the subsequent writing of sub-matrix data. This extracted information includes the starting address of the written sub-matrix, the row stride of the written matrix, the row / column size of the sub-matrix, and the transpose granularity.
[0061] ④ After obtaining the read packet information, the read request sending submodule will convert the read packet information into a read request that meets the interface protocol requirements and send it in sequence.
[0062] ⑤ After receiving the read response data, the read response processing submodule first reads the data storage address corresponding to the data from the data control submodule, and then writes the data into the data storage submodule.
[0063] ⑥ If the transpose unit submodule is idle, the data control submodule extracts data from the data storage submodule based on the read packet information and writes the data to the transpose unit submodule according to the transpose unit storage pointer, while releasing the corresponding data storage space, without waiting for the entire submatrix data to be fully collected. Then, the write request processing submodule reads the submatrix row data and writes it to the specified position in the transpose unit submodule.
[0064] ⑦ The transpose unit submodule implements the matrix transpose operation and allows two submatrices to be transposed in parallel. After all the data of one submatrix is written to the transpose unit submodule, the transposed submatrix data is written out line by line.
[0065] The transpose unit submodule consists of multiple SRAMs with a width equal to the matrix granularity and a length twice the number of rows in the submatrix. Row data can be filled into the transpose unit submodule within one cycle. After all rows of data in the submatrix have been filled into the transpose unit submodule, data is read out row by row according to the address offset (ensuring the data is arranged in 12345). The specific data processing flow is as follows: Figure 3 As shown.
[0066] ⑧ The transpose write-splitting submodule will further decompose the write packet information of the submatrix in sequence, extract the write packet information such as address and data length corresponding to each row of the transposed submatrix, and send it to the write request processing submodule.
[0067] ⑨ The write request processing submodule will rearrange the row data of the transposed submatrix according to the received write packet information, and finally convert it into a write request that meets the interface protocol requirements and send it out.
[0068] This embodiment provides a data processing method that directly accesses memory. Figure 5 This is a flowchart of a data processing method for direct memory access according to an embodiment of the present invention, such as... Figure 5 As shown, the process includes the following steps: Step S501: Receive descriptor, split the target matrix into several sub-matrices based on the descriptor information and the capacity of the transpose unit sub-module, calculate the sub-matrix write packet information of each sub-matrix, and at the same time, extract multiple read packet information for reading sub-matrix row data according to the maximum bus bandwidth.
[0069] Step S502: When the read response data corresponding to each read packet information is received, the read response data is written to the transpose unit submodule according to the read packet information for transpose processing to obtain multiple transposed submatrices.
[0070] Step S503: Extract the write packet information corresponding to each row based on the submatrix write packet information, and rearrange the transposed submatrix data to obtain a write request that satisfies the interface protocol.
[0071] For details, please refer to the description of the direct memory access control device in the above embodiments, which will not be repeated here.
[0072] Figure 6 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present invention.
[0073] The following is a detailed reference. Figure 6 This diagram illustrates a suitable structural design for implementing an electronic device according to embodiments of the present invention. The electronic device may include a processor (e.g., a central processing unit, graphics processor, etc.) 601, which can perform various appropriate actions and processes based on a program stored in read-only memory (ROM) 602 or a program loaded from memory 608 into random access memory (RAM) 603. RAM 603 also stores various programs and data required for the operation of the electronic device. The processor 601, ROM 602, and RAM 603 are interconnected via a bus 604. An input / output (I / O) interface 605 is also connected to the bus 604.
[0074] Typically, the following devices can be connected to I / O interface 605: input devices 606 including, for example, touchscreens, touchpads, keyboards, mice, cameras, microphones, accelerometers, gyroscopes, etc.; output devices 607 including, for example, liquid crystal displays (LCDs), speakers, vibrators, etc.; memory devices 608 including, for example, magnetic tapes, hard disks, etc.; and communication devices 609. Communication device 609 allows electronic devices to communicate wirelessly or wiredly with other devices to exchange data. Although Figure 6 Electronic devices with various devices are shown, but it should be understood that it is not required to implement or have all of the devices shown, and more or fewer devices may be implemented or have instead.
[0075] In particular, according to embodiments of the present invention, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments of the present invention include a computer program product comprising a computer program carried on a non-transitory computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via a communication device 609, or installed from a memory 608, or installed from a ROM 602. When the computer program is executed by the processor 601, it performs the functions defined in the direct memory access data processing method of the embodiments of the present invention.
[0076] Figure 6 The electronic device shown is merely an example and should not be construed as limiting the functionality and scope of use of the embodiments of the present invention.
[0077] This invention also provides a computer-readable storage medium. The methods described above according to embodiments of the invention can be implemented in hardware or firmware, or implemented as computer code that can be recorded on a storage medium, or implemented as computer code downloaded via a network and originally stored on a remote storage medium or a non-transitory machine-readable storage medium and then stored on a local storage medium. Thus, the methods described herein can be processed by software stored on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. The storage medium can be a magnetic disk, optical disk, read-only memory, random access memory, flash memory, hard disk, or solid-state drive, etc.; further, the storage medium can also include combinations of the above types of memory. It is understood that computers, processors, microprocessor controllers, or programmable hardware include storage components capable of storing or receiving software or computer code. When the software or computer code is accessed and executed by the computer, processor, or hardware, the data processing method for direct memory access shown in the above embodiments is implemented.
[0078] A portion of this invention can be applied as a computer program product, such as computer program instructions, which, when executed by a computer, can invoke or provide the methods and / or technical solutions according to the invention through the operation of the computer. Those skilled in the art will understand that the forms in which computer program instructions exist in a computer-readable medium include, but are not limited to, source files, executable files, installation package files, etc. Correspondingly, the ways in which computer program instructions are executed by a computer include, but are not limited to: the computer directly executing the instructions, or the computer compiling the instructions and then executing the corresponding compiled program, or the computer reading and executing the instructions, or the computer reading and installing the instructions and then executing the corresponding installed program. Here, the computer-readable medium can be any available computer-readable storage medium or communication medium accessible to a computer.
[0079] Although embodiments of the invention have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the invention, and such modifications and variations all fall within the scope defined by the appended claims.
Claims
1. A direct memory access device, characterized in that, Includes a descriptor processing module and a transpose processing module. The descriptor processing module receives the descriptor, splits the target matrix into several sub-matrices based on the descriptor information and the capacity of the transpose unit sub-module, calculates the sub-matrix write packet information for each sub-matrix, and simultaneously extracts multiple read packet information for reading the row data of the sub-matrix according to the maximum bus bandwidth. The read packet information and the submatrix write packet information are sent to the transpose processing module; When the transpose processing module receives the read response data corresponding to each read packet information, it writes the read response data to the transpose unit submodule of the transpose processing module according to the read packet information to perform transpose processing to obtain multiple transpose submatrices, and extracts the write packet information corresponding to each row according to the submatric write information, and rearranges the transpose submatric data to obtain the write request.
2. The apparatus according to claim 1, characterized in that, The descriptor processing module includes a descriptor management submodule, a transpose read / disassemble submodule, and a read request sending submodule. The descriptor management submodule receives the descriptor and sends the transpose information in the descriptor to the transpose read / disassemble submodule; The transpose read / split packet submodule splits the target matrix into multiple submatrices based on the capacity and transpose information of the transpose unit submodule, and calculates the read packet information and write packet information of each submatrix. The read packet information is sent to the transpose processing module and the read request sending submodule, and the submatrix write packet information is sent to the transpose processing module; The read request sending submodule converts the read packet information into read requests that satisfy the interface protocol and sends them to the data storage system in succession, so that the data storage system returns the corresponding read response data according to the read request.
3. The apparatus according to claim 1, characterized in that, The read packet information includes a storage address and a pointer to the transpose unit. The transpose processing module includes a data control submodule, a transpose write / disassemble submodule, a transpose unit submodule, a data storage submodule, a read response processing submodule, and a write request processing submodule. The data control submodule receives the packet reading information; The transpose write-and-split submodule receives the submatrix write packet information; The read response processing submodule receives read response data, determines the storage address corresponding to the read response data based on the read packet information corresponding to the read response data stored in the data control submodule, and writes the read response data into the data storage submodule according to the storage address. When the transpose unit submodule is idle, the data control submodule extracts data from the data storage submodule according to the read packet information, and writes the data into the transpose unit submodule according to the transpose unit storage pointer; The transpose unit submodule performs transpose processing on the data; The transpose write-splitting submodule decomposes the write packet information of the submatrix to obtain the write packet information corresponding to each row, and sends the write packet information to the write request processing submodule; The write request processing submodule rearranges the transposed submatrix data according to the write packet information to obtain a write request that satisfies the interface protocol.
4. The apparatus according to claim 3, characterized in that, After the data control submodule extracts data from the data storage submodule according to the read packet information and writes the data into the transpose unit submodule according to the transpose unit storage pointer, the read packet is deleted, the corresponding data storage space is released, and the newly extracted read packet information is stored in the released data storage space.
5. The apparatus according to claim 3, characterized in that, The transpose unit submodule includes multiple dual-port static random access memories. The width of the dual-port static random access memory is the same as the matrix granularity, and its length is twice the number of rows of data in the submatrix.
6. The apparatus according to claim 5, characterized in that, The transpose unit submodule performs transpose processing on the two submatrices in parallel.
7. A data processing method for direct memory access, characterized in that, include: Receive descriptor, split the target matrix into several sub-matrices based on the descriptor information and the capacity of the transpose unit sub-module, calculate the sub-matrix write packet information of each sub-matrix, and at the same time, split multiple read packet information for reading sub-matrix row data according to the maximum bus bandwidth; When the read response data corresponding to each read packet information is received, the read response data is written to the transpose unit submodule according to the read packet information for transpose processing to obtain multiple transposed submatrices; Based on the submatrix write packet information, extract the write packet information corresponding to each row, and rearrange the transposed submatrix data to obtain a write request that satisfies the interface protocol.
8. An electronic device, characterized in that, include: The system includes a memory and a processor, which are communicatively connected to each other. The memory stores computer instructions, and the processor executes the computer instructions to perform the data processing method for direct memory access as described in claim 7.
9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions for causing the computer to perform the data processing method for direct access to memory as described in claim 7.
10. A computer program product, characterized in that, It includes computer instructions for causing a computer to perform the data processing method for direct access to memory as described in claim 7.