Converged terminal display chip dual interface communication system and method

Abstract

The application discloses a kind of fusion terminal display chip double interface communication system and method, it is related to electric information acquisition technical field, fusion terminal display chip double interface communication system includes: main control chip, single GPIO expansion chip and display chip;Main control chip is connected with the chip communication pin of GPIO expansion chip by two-way native GPIO pin, and GPIO expansion chip expands multiple GPIO pins;Main control chip sends control instruction to GPIO expansion chip, controls the level state of GPIO expansion chip, simulates the first serial communication protocol timing to send control instruction to display chip, and simulates the second serial communication protocol timing to receive state data from display chip;Display chip carries out data display according to control instruction, by single GPIO expansion chip, respectively using extended GPIO simulates I2C sending timing and SPI receiving timing, without special interface chip, reduce cost and meet display chip communication demand.

Description

Technical Field

[0001] This application relates to the field of electricity information collection technology, and in particular to a dual-interface communication system and method for a converged terminal display chip. Background Technology

[0002] Currently, converged terminals require a display chip, such as an OLED display module, to display information such as power consumption data and device status. This display chip supports two communication interfaces: receiving control commands via I2C (Inter-Integrated Circuit) with data transmission from the converged terminal to the display chip, and receiving status data via SPI (Serial Peripheral Interface) with data reception from the display chip to the converged terminal. Existing converged terminal main control chips have a limited number of native GPIO (General Purpose Input / Output) pins, and some GPIO pins are already allocated to other external devices, making it impossible to simultaneously meet the I2C and SPI interface requirements of the display chip.

[0003] The current interface design involves adding an additional I2C or SPI expansion chip to achieve data transmission and reception functions. This increases the total production cost, and the expansion chip requires PCB board area, leading to increased PCB design complexity and reduced production yield. Summary of the Invention

[0004] The main purpose of this application is to provide a dual-interface communication system and method for integrated terminal display chips, which aims to solve the technical problem that the number of native GPIOs of the main control chip is insufficient, and that a dedicated interface chip needs to be configured to realize dual-protocol communication of the display chip.

[0005] To achieve the above objectives, this application proposes a dual-interface communication system for a converged terminal display chip. The dual-interface communication system includes: a main control chip, a single GPIO expansion chip, and a display chip. The main control chip is connected to the chip communication pin of the GPIO expansion chip through two native GPIO pins. The GPIO expansion chip expands to multiple GPIO pins, wherein at least two of the expanded first extended GPIO pins are connected to the first communication interface pin of the display chip, and at least three of the expanded second extended GPIO pins are connected to the second communication interface pin of the display chip. The main control chip is used to send control commands to the GPIO expansion chip; The main control chip is also used to simulate the timing of a first serial communication protocol to send control commands to the display chip by controlling the level state of the GPIO expansion chip, and to simulate the timing of a second serial communication protocol to receive status data from the display chip. The display chip is used to display data according to the control instructions.

[0006] In one embodiment, the first extended GPIO is a transmit pin simulating a first serial communication protocol, the second extended GPIO is a receive pin simulating a second serial communication protocol, the first communication interface is a first serial communication protocol interface for receiving control commands, and the second communication interface is a second serial communication protocol interface for outputting status data.

[0007] In one embodiment, the first extended GPIO includes a first serial communication protocol data pin and a first serial communication protocol clock pin, and the second extended GPIO includes a second serial communication protocol clock pin, a second serial communication protocol data input pin, and a second serial communication protocol chip select pin.

[0008] This application proposes one or more technical solutions for a dual-interface communication system for a terminal display chip, comprising: a main control chip, a single GPIO expansion chip, and a display chip. The main control chip is connected to the chip communication pins of the GPIO expansion chip via two native GPIO pins. The GPIO expansion chip extends multiple GPIO pins, wherein at least two first extended GPIO pins are connected to the first communication interface pins of the display chip, and at least three second extended GPIO pins are connected to the second communication interface pins of the display chip. The main control chip is used to send control commands to the GPIO expansion chip. The main control chip is also used to simulate a first serial communication protocol timing to send control commands to the display chip by controlling the level state of the GPIO expansion chip, and to simulate a second serial communication protocol timing to receive status data from the display chip. The display chip is used to display data according to the control commands. By using a single GPIO expansion chip to simulate I2C transmit timing and SPI receive timing respectively, no dedicated interface chip is required, reducing costs and meeting the communication requirements of the display chip. Occupying only two native GPIO channels, the expanded system meets the dual-interface requirements of the display chip while reserving more resources for other peripherals. Furthermore, the software-simulated I2C transmission and SPI reception timings are compatible with the display chip, resulting in high data transmission success rates and compliance with State Grid equipment communication standards. This proposed dual-interface communication system for converged terminal display chips achieves dual-interface simulation through a single GPIO expansion chip. This effectively reduces hardware costs, optimizes main control chip resource usage, and ensures excellent compatibility with the display chip and high data transmission success rates, perfectly meeting the comprehensive requirements of converged terminal products in terms of cost, performance, and standards compliance.

[0009] Furthermore, to achieve the above objectives, this application also proposes a dual-interface communication method for a converged terminal display chip. The dual-interface communication method for a converged terminal display chip is applied to the dual-interface communication system for a converged terminal display chip described above. The dual-interface communication system for a converged terminal display chip includes a main control chip, a single GPIO expansion chip, and a display chip. The GPIO expansion chip expands to multiple GPIO pins, wherein at least two of the expanded first GPIO pins are connected to the first communication interface pins of the display chip, and at least three of the expanded second GPIO pins are connected to the second communication interface pins of the display chip. The dual-interface communication method for the converged terminal display chip includes: Determine the current communication direction of the current instruction or data; Based on the current communication direction, the level states of the first extended GPIO and / or the second extended GPIO are controlled to complete the communication between the main control chip and the display chip.

[0010] In one embodiment, the step of controlling the level of the first extended GPIO and / or the second extended GPIO based on the current communication direction includes: When the current communication direction is for the main control chip to transmit control commands to the display chip, the level state of the first extended GPIO is controlled to simulate the timing of the first serial communication protocol to transmit control commands to the display chip.

[0011] In one embodiment, the at least two extended first extended GPIO pins include: a first serial communication protocol data pin and a first serial communication protocol clock pin; The step of controlling the level state of the first extended GPIO when the current communication direction is when the main control chip transmits control commands to the display chip includes: When the current communication direction is for the main control chip to transmit control commands to the display chip, the level switching time of the first serial communication protocol data pin and the first serial communication protocol clock pin is controlled by a preset level switching time to simulate the timing of the first serial communication protocol in order to transmit control commands to the display chip.

[0012] In one embodiment, the step of controlling the level switching of the first serial communication protocol data pin and the first serial communication protocol clock pin by controlling the level switching time of the first serial communication protocol to simulate the timing of the first serial communication protocol in order to transmit control commands to the display chip when the current communication direction is the main control chip transmitting control commands to the display chip includes: When the current communication direction is for the main control chip to transmit control commands to the display chip, the level of the first serial communication protocol clock pin is set high, and after waiting for a first preset level switching time, the level of the first serial communication protocol data pin is pulled low from high, and after waiting for a first preset level switching time, the start bit transmission is completed. By controlling the level states of the first serial communication protocol data pin and the first serial communication protocol clock pin bit by bit using a preset data format and a first preset level switching time, the data bit transmission is completed. The level of the first serial communication protocol clock pin is set high, and after waiting for a first preset level switching time, the level of the first serial communication protocol data pin is pulled high from low, and after waiting for a first preset level switching time, the stop bit is sent, the simulation of the first serial communication protocol timing is completed, and the control command is sent to the display chip.

[0013] In one embodiment, the step of controlling the level state of the first extended GPIO and / or the second extended GPIO based on the current communication direction includes: When the current communication direction is that the display chip outputs status data to the main control chip, the level state of the second extended GPIO is controlled to simulate the timing of the second serial communication protocol to receive status data.

[0014] In one embodiment, the extended at least three second extended GPIO pins include a second serial communication protocol clock pin, a second serial communication protocol data input pin, and a second serial communication protocol chip select pin; The step of controlling the level state of the second extended GPIO to simulate the timing of the second serial communication protocol to receive status data when the current communication direction is that the display chip outputs status data to the main control chip includes: When the current communication direction is that the display chip outputs status data to the main control chip, the level of the second serial communication protocol clock pin, the second serial communication protocol data input pin, and the second serial communication protocol chip select pin is controlled by the second preset level switching time to simulate the timing of the second serial communication protocol in order to receive the status data output by the display chip.

[0015] In one embodiment, the step of controlling the level switching of the second serial communication protocol clock pin, the second serial communication protocol data input pin, and the second serial communication protocol chip select pin through a second preset level switching time to simulate the timing of the second serial communication protocol in order to receive the status data output by the display chip when the current communication direction is the display chip outputting status data to the main control chip includes: When the current communication direction is that the display chip is outputting status data to the main control chip, the level of the second serial communication protocol chip select pin is pulled low, and the second preset level switching time is waited for to notify the display chip to prepare to send status data; The level of the second serial communication protocol clock pin is pulled high from low and held for a preset duration so that the display chip outputs data to the second serial communication protocol data input pin. Read and store the level of the second serial communication protocol data input pin, pull the level of the second serial communication protocol clock pin low and keep it low for a preset duration, and repeat the step of controlling the level of the second serial communication protocol clock pin to pull it high from low and keep it high for a preset duration a preset number of times until a preset number of bits of status data are collected. Pull the level of the second serial communication protocol chip select pin high and wait for the second preset level switching time to complete the reception of status data.

[0016] This application proposes one or more technical solutions that determine the current communication direction of the current instruction or data; based on the current communication direction, control the level state of the first extended GPIO and / or the second extended GPIO to complete the communication between the main control chip and the display chip. Traditional communication direction control may rely on complex protocol handshakes or multi-line control, increasing communication latency and protocol overhead. This solution directly indicates and switches the communication direction by controlling the GPIO level state. This hardware-level control method has an extremely fast response speed. In terminal products, this means that data interaction between the main control chip and the display chip can be completed more quickly, effectively reducing problems such as screen display latency and operation response lag. Especially for terminal products that require high-speed dynamic screen display or real-time interaction, there is no need to introduce additional dedicated chips, reducing the number of components, simplifying the wiring complexity of the PCB board, and reducing the hardware cost and manufacturing difficulty of the terminal product. Attached Figure Description

[0017] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0018] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a schematic diagram of the structure of a dual-interface communication system for a converged terminal display chip according to an embodiment of this application; Figure 2 A flowchart illustrating an embodiment of a dual-interface communication method for a converged terminal display chip; Figure 3 This is a flowchart illustrating Embodiment 2 of the dual-interface communication method for integrated terminal display chips in this application. Figure 4 This is a flowchart illustrating Embodiment 3 of the dual-interface communication method for integrated terminal display chips in this application; Figure 5 This is a schematic diagram of the extended GPIO simulated I2C transmission process provided in an embodiment of the dual-interface communication method for the integrated terminal display chip of this application.

[0020] Explanation of icon numbers:

[0021] The purpose, features, and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0022] It should be understood that the specific embodiments described herein are merely illustrative of the technical solutions of this application and are not intended to limit this application.

[0023] To better understand the technical solution of this application, a detailed description will be provided below in conjunction with the accompanying drawings and specific implementation methods.

[0024] The main solution of this application embodiment is: a dual-interface communication system for a converged terminal display chip includes: a main control chip, a single GPIO expansion chip, and a display chip; the main control chip is connected to the chip communication pins of the GPIO expansion chip through two native GPIO pins, and the GPIO expansion chip expands to multiple GPIO pins, wherein at least two of the expanded first expanded GPIOs are connected to the first communication interface pins of the display chip, and at least three expanded second expanded GPIOs are connected to the second communication interface pins of the display chip; the main control chip is used to send control commands to the GPIO expansion chip; the main control chip is also used to simulate a first serial communication protocol timing to send control commands to the display chip by controlling the level state of the GPIO expansion chip, and to simulate a second serial communication protocol timing to receive status data from the display chip; the display chip is used to display data according to the control commands.

[0025] Due to the insufficient number of native GPIOs in the main control chip in the existing technology, an additional dedicated interface chip is required to realize dual-protocol communication of the display chip, which leads to technical problems such as increased hardware costs, increased PCB design complexity, and decreased production yield.

[0026] This application provides a solution that simulates the timing of I2C protocol transmission and SPI protocol reception using a single GPIO expansion chip. The main control chip utilizes two native GPIO pins to control the level states of the expansion chip. At least two GPIO pins output by the expansion chip are connected to the I2C interface of the display chip to transmit control commands, and at least three GPIO pins are connected to the SPI interface of the display chip to receive status data. At the communication method level, the system dynamically switches the GPIO pin functions according to the command transmission direction: when the main control chip sends control commands to the display chip, it simulates the start, data, and stop bit timing of the I2C protocol by controlling the toggling of the data and clock pins of the expansion chip; when the display chip sends status data back to the main control chip, it activates the SPI protocol chip select signal, synchronizes the clock, and select pins of the expansion chip by controlling the level changes of these pins. This solution only requires two native GPIO resources from the main control chip and completes the protocol timing simulation through software algorithms. This avoids the increased cost and PCB layout difficulties associated with dedicated interface chips and improves system scalability through hardware pin reuse.

[0027] It should be noted that the executing entity in this embodiment can be a computing service device with data processing, network communication, and program execution functions, such as a tablet computer, personal computer, or mobile phone, or an electronic device or main control chip capable of performing the above functions. The following description uses a main control chip as an example to illustrate this embodiment and the subsequent embodiments.

[0028] Based on this, embodiments of this application provide a dual-interface communication system for a converged terminal display chip, referring to... Figure 1 , Figure 1 This is a schematic diagram of the structure of the first embodiment of the dual-interface communication system for a converged terminal display chip.

[0029] In this embodiment, the dual-interface communication system of the converged terminal display chip includes: a main control chip 10, a single GPIO expansion chip 20, and a display chip 30. The main control chip 10 is connected to the chip communication pin of the GPIO expansion chip 20 through two native GPIO pins. The GPIO expansion chip expands to multiple GPIO pins, wherein at least two of the expanded first expanded GPIO 201A are connected to the first communication interface pin 301 of the display chip 30, and at least three expanded second expanded GPIO 201B are connected to the second communication interface pin 302 of the display chip 30.

[0030] It should be noted that the main control chip 10 has two native GPIO pins, including a first native GPIO pin 101 and a second native GPIO pin 102. The first native GPIO pin 101 is I2C_SDA, i.e., the data line connection pin, and the second native GPIO pin 102 is I2C_SCL, i.e., the clock line connection pin. The expansion chip 20 has chip communication pins corresponding to the I2C interface, including a first chip communication pin 202 and a second chip communication pin 203. The first chip communication pin 202 is the I2C_SDA connection pin, and the second chip communication pin 203 is the I2C_SCL connection pin. The main control chip 10 connects to the I2C interface pins of the GPIO expansion chip 20 through these two native GPIO pins to establish a basic communication link.

[0031] It is understandable that a single GPIO expansion chip 20 is used to expand 16 GPIO channels. Among them, at least two of the expanded first expansion GPIOs 201A are analog first serial communication protocol transmit pins, and at least three expanded second expansion GPIOs 201B are analog second serial communication protocol receive pins. Further, the first expansion GPIO 201A includes a first serial communication protocol data pin 201A1 and a first serial communication protocol clock pin 201A2, which are the data line (SDA_EXT) and clock line (SCL_EXT) required for simulating the I2C protocol. The first serial communication protocol data pin 201A1 = I2C_TX_SDA, and the first serial communication protocol clock pin 201A2 = I2C_TX_SCL, which are respectively connected to the I2C interface data pin 301A and clock pin 301B of the display chip 30.

[0032] At least three second extended GPIOs 201B constitute the SPI protocol receiving channel, including the second serial communication protocol clock pin 201B1, the second serial communication protocol data input pin 201B2, and the second serial communication protocol chip select pin 201B3. It may also include a second serial communication protocol power supply pin (not shown in the figure). The second serial communication protocol clock pin 201B1 = SPI_RX_CLK, the second serial communication protocol data input pin 201B2 = SPI_RX_MISO, the second serial communication protocol chip select pin 201B3 = SPI_RX_CS, and the second serial communication protocol power supply pin = SPI_RX_GND. These pins are connected to the SPI interface clock pin 302A, data output pin 302B, and chip select pin 302C of the display chip 30. Through this pin function allocation, under the control of the main control chip 10, the GPIO expansion chip 20 can send control commands to the display chip 30 through the first extended GPIO 201A simulating I2C protocol timing, and can also receive status data output by the display chip 30 through the second extended GPIO 201B simulating SPI protocol timing, thus realizing dual protocol communication function.

[0033] In this embodiment, the first serial communication protocol data pin 201A1 and the first serial communication protocol clock pin 201A2 are assigned as analog I2C transmit pins, and the second serial communication protocol clock pin 201B1, the second serial communication protocol data input pin 201B2, and the second serial communication protocol chip select pin 201B3 are assigned as analog SPI receive pins, thereby enabling a single chip to expand to dual interface functionality.

[0034] The hardware components of this embodiment include a Rockchip RK3562J main control chip, one GPIO expansion chip, a display chip, and an LCD module. The first native GPIO pin 101 (SDA) and the second native GPIO pin 102 (SCL) of the Rockchip RK3562J are connected to the I2C pins of the GPIO expansion chip. The first serial communication protocol data pin 201A1 (I2C_SDA) and the first serial communication protocol clock pin 201A2GPIO1 (I2C_SCL) of the GPIO expansion chip are connected to the I2C interface of the display chip. The second serial communication protocol clock pin 201B1 (CLK), the second serial communication protocol data input pin 201B2 (MISO), and the second serial communication protocol chip select pin 201B3 (CS) of the GPIO expansion chip are connected to the SPI interface of the display chip. The software environment is: Linux kernel, with the GPIO expansion driver (i2c-dev.ko) loaded, and timing simulation combined with display code compiled into the display driver (lcd.ko).

[0035] In practical implementation, software timing simulation can be used. The main control chip 10 can send control commands to the GPIO expansion chip. The sent control commands can include commands related to the data to be displayed, such as the control command "display power consumption data". At this time, the fusion terminal sends the "display power consumption data" command to the main control chip 10. The data content is 0xAE, 0x00, 0x10, 0xB0, 0xC8. The display chip 10 calls the I2C simulation function i2c_send_data to control the GPIO expansion chip 20 through the I2C bus, thereby causing the I2C timing to flip the level and send the start bit, 5 bytes of data, and stop bit in sequence. Finally, the command is sent to the display chip 30. After receiving the command, the display chip 30 prepares the corresponding status data and waits for SPI transmission. At this time, the main control chip 10 calls the SPI simulation function spi_receive_data to control the GPIO expansion chip 20, thereby causing the SPI timing to flip the level and finally obtain the status data.

[0036] This embodiment integrates a dual-interface communication system for a terminal display chip, comprising: a main control chip, a single GPIO expansion chip, and a display chip. The main control chip is connected to the chip communication pins of the GPIO expansion chip via two native GPIO pins. The GPIO expansion chip extends multiple GPIO pins, wherein at least two of the extended first GPIO pins are connected to the first communication interface pins of the display chip, and at least three extended second GPIO pins are connected to the second communication interface pins of the display chip. The main control chip is used to send control commands to the GPIO expansion chip. The main control chip is also used to simulate a first serial communication protocol timing to send control commands to the display chip by controlling the level state of the GPIO expansion chip, and to simulate a second serial communication protocol timing to receive status data from the display chip. The display chip is used to display data according to the control commands. By using a single GPIO expansion chip to simulate I2C transmit timing and SPI receive timing respectively, no dedicated interface chip is required, reducing costs and meeting the communication requirements of the display chip. Occupying only two native GPIO channels, the expanded system meets the dual-interface requirements of the display chip while reserving more resources for other peripherals. Furthermore, the software-simulated I2C transmission and SPI reception timings are compatible with the display chip, resulting in high data transmission success rates and compliance with State Grid equipment communication standards. This proposed dual-interface communication system for converged terminal display chips achieves dual-interface simulation through a single GPIO expansion chip. This effectively reduces hardware costs, optimizes main control chip resource usage, and ensures excellent compatibility with the display chip and high data transmission success rates, perfectly meeting the comprehensive requirements of converged terminal products in terms of cost, performance, and standards compliance.

[0037] This application also provides a dual-interface communication method for a converged terminal display chip, referring to... Figure 2 , Figure 2 This is a flowchart illustrating the first embodiment of the dual-interface communication method for integrated terminal display chips in this application.

[0038] Based on the first embodiment of the dual-interface communication system for the converged terminal display chip described above, in this embodiment, the dual-interface communication method for the converged terminal display chip includes steps S10 to S40: Step S10: Determine the current communication direction of the current instruction or data.

[0039] It should be noted that in the dual-interface communication system of the converged terminal display chip, the communication direction is divided into two types: sending and receiving. When the main control chip needs to send control commands to the display chip, the communication direction is sending; when the display chip needs to send status data back to the main control chip, the communication direction is receiving. The system determines the subsequent GPIO pin function configuration and timing simulation mode by determining the current communication direction of the command or data.

[0040] Step S20: Control the level state of the first extended GPIO and / or the second extended GPIO based on the current communication direction to complete the communication between the main control chip and the display chip.

[0041] In practice, when the current communication direction is determined to be sending, the main control chip controls the level state of the pins in the first extended GPIO. When the current communication direction is determined to be receiving, the main control chip controls the level state of the pins in the second extended GPIO, thereby completing the communication between the main control chip and the display chip.

[0042] This embodiment provides a dual-interface communication method for a converged terminal display chip, which determines the current communication direction of the current instruction or data; and controls the level state of the first extended GPIO and / or the second extended GPIO based on the current communication direction to complete the communication between the main control chip and the display chip. This method achieves efficient communication between the main control chip and the display chip by dynamically switching the GPIO pin functions.

[0043] Based on the first embodiment of the dual-interface communication method for integrated terminal display chips of this application, in the second embodiment of the same or similar content as the first embodiment of the dual-interface communication method for integrated terminal display chips of this application, please refer to the above description, and it will not be repeated hereafter. Based on this, please refer to... Figure 3 Step S20 includes step S201: Step S201: When the current communication direction is for the main control chip to transmit control commands to the display chip, control the level state of the first extended GPIO to simulate the timing of the first serial communication protocol to transmit control commands to the display chip.

[0044] Understandably, when the main control chip needs to send control commands to the display chip, it first determines the communication direction to be in the transmit state. At this time, the main control chip simulates the start bit, data bit, and stop bit timing of the I2C protocol by controlling the level states of the data pin (I2C_TX_SDA) and clock pin (I2C_TX_SCL) in the first extended GPIO, thus enabling the converged terminal to send control commands to the display chip.

[0045] Control commands can be specific commands that require data to be displayed, such as: display electricity consumption data.

[0046] In one feasible implementation, the extended at least two first extended GPIO pins include: a first serial communication protocol data pin and a first serial communication protocol clock pin; therefore, step S201 may include step A11: when the current communication direction is the main control chip transmitting control instructions to the display chip, the level switching of the first serial communication protocol data pin and the first serial communication protocol clock pin is controlled by a preset level switching time to simulate the first serial communication protocol timing to transmit control instructions to the display chip.

[0047] It is understandable that if the preset level switching time can be set in advance, for example, to 10μs, 5μs, etc., the level state of the first serial communication protocol data pin and the second serial communication protocol clock pin can be controlled by this level switching time, thereby simulating I2C timing and transmitting control commands to the display chip.

[0048] In one feasible implementation, step A11 specifically includes: when the current communication direction is for the main control chip to transmit control commands to the display chip, setting the level of the first serial communication protocol clock pin high, and after waiting for a first preset level switching time, pulling the level of the first serial communication protocol data pin low from high, and waiting for the first preset level switching time to complete the start bit transmission; controlling the level states of the first serial communication protocol data pin and the first serial communication protocol clock pin bit by bit through a preset data format and the first preset level switching time to complete the data bit transmission; setting the level of the first serial communication protocol clock pin high, and after waiting for the first preset level switching time, pulling the level of the first serial communication protocol data pin high from low, and waiting for the first preset level switching time to complete the stop bit transmission, completing the simulation of the first serial communication protocol timing, and sending the control commands to the display chip.

[0049] It should be noted that the first preset level switching time can be set to 10μs. When sending control commands, it is necessary to simulate the timing of the I2C start bit, data bit, and stop bit. Therefore, the start bit is simulated first. Specifically, the level of the first serial communication protocol clock pin is first set high, and after a delay of 10μs, the level of the first serial communication protocol data pin is pulled low, and then delayed for another 10μs to complete the start bit transmission. Subsequently, the data bits need to be transmitted. According to the preset data format and the 10μs level switching time, the level states of the first serial communication protocol data pin and the first serial communication protocol clock pin are adjusted bit by bit to complete the data bit transmission process. The preset data format is 8 data bits + 1 acknowledge bit. Specifically, the level of the SDA (first serial communication protocol data pin) is controlled bit by bit, where high = 1 and low = 0. After each bit is sent, the level of the first serial communication protocol clock pin is pulled high and held for 10μs, then pulled low and held for 10μs, completing the data transmission of one bit. Next, a stop bit simulation is performed. The level of the first serial communication protocol clock pin is again set high, delayed for 10μs, and then the level of the first serial communication protocol data pin is pulled high, waiting for another 10μs to complete the stop bit transmission, ending the I2C command transmission. Thus, the timing of the first serial communication protocol is successfully simulated, accurately sending the control commands to the display chip.

[0050] This embodiment mainly uses a precise delay function, such as usleep(), to control the level switching time, ensuring that the analog timing conforms to the I2C standard, with a rate of 100kHz, and is compatible with the I2C interface of the display chip.

[0051] In this embodiment, when the current communication direction is for the main control chip to transmit control commands to the display chip, the level state of the first extended GPIO is controlled to simulate the timing of the first serial communication protocol to transmit control commands to the display chip. Through the above steps, reliable transmission of control commands is achieved, ensuring that the display chip can correctly parse and execute the corresponding operations.

[0052] Based on the first embodiment of the dual-interface communication method for integrated terminal display chips in this application, in the third embodiment of the same or similar content as the first embodiment of the dual-interface communication method for integrated terminal display chips in this application, please refer to the above description, and it will not be repeated hereafter. Based on this, please refer to... Figure 4 Step S20 includes step S201': Step S201': When the current communication direction is that the display chip outputs status data to the main control chip, control the level state of the second extended GPIO to simulate the timing of the second serial communication protocol to receive status data.

[0053] It should be noted that if the current communication direction is for the display chip to feed back status data to the main control chip, the system needs to switch to receive mode. The main control chip receives the status data output by the display chip by controlling the level states of multiple pins in the second extended GPIO to simulate the timing logic of the SPI protocol.

[0054] In one feasible implementation, the extended at least three second extended GPIO pins include a second serial communication protocol clock pin, a second serial communication protocol data input pin, and a second serial communication protocol chip select pin. Therefore, step S201' may include step B11: when the current communication direction is the display chip outputting status data to the main control chip, the level of the second serial communication protocol clock pin, the second serial communication protocol data input pin, and the second serial communication protocol chip select pin is controlled by a second preset level switching time to simulate the second serial communication protocol timing in order to receive the status data output by the display chip.

[0055] It is understandable that if the second preset level switching time can also be set in advance, for example, to 5μs, 2μs, etc., the level state of the second serial communication protocol clock pin, the second serial communication protocol data input pin, and the second serial communication protocol chip select pin can be controlled by this level switching time, thereby simulating SPI timing and receiving the status data output by the display chip.

[0056] In one feasible implementation, step B11 specifically includes: When the current communication direction is that the display chip is outputting status data to the main control chip, the level of the second serial communication protocol chip select pin is pulled low, and the second preset level switching time is waited for to notify the display chip to prepare to send status data; The level of the second serial communication protocol clock pin is pulled high from low and held for a preset duration so that the display chip outputs data to the second serial communication protocol data input pin. Read and store the level of the second serial communication protocol data input pin, pull the level of the second serial communication protocol clock pin low and keep it low for a preset duration, and repeat the step of controlling the level of the second serial communication protocol clock pin to pull it high from low and keep it high for a preset duration a preset number of times until a preset number of bits of status data are collected. Pull the level of the second serial communication protocol chip select pin high and wait for the second preset level switching time to complete the reception of status data.

[0057] Understandably, if the current communication direction is for the display chip to output corresponding status data to the main control chip, the chip select is enabled first. Specifically, the level of the second serial communication protocol chip select pin is pulled low, and a second preset level switching time is delayed, for example, 5μs, to notify the display chip to prepare to send status data. Next, clock and data acquisition are performed. First, the level of the second serial communication protocol clock pin is pulled high and held for a preset duration, for example, 3μs. At this time, the display chip outputs 1 bit of data to the second serial communication protocol data input pin. By reading the level of the second serial communication protocol data input pin (high level = 1, low level = 0), the read level is stored. Then, the level of the second serial communication protocol clock pin is pulled low and held for 3μs to complete the reception of 1 bit of data. The above clock pin level switching and data reading steps are repeated until a preset number of bits of status data are acquired. The preset number of bits is 8 bits. By continuously acquiring 8 bits of data, 1 byte of status data is formed. Finally, the level of the second serial communication protocol chip select pin is pulled high and waits for 5μs to end SPI reception. This process ensures that the main control chip can accurately and stably receive the status data fed back by the display chip, providing a reliable data source for subsequent data processing and display. By precisely controlling the level states and timing of the GPIO pins, efficient simulation of the SPI protocol is achieved, further improving the system's communication performance and stability.

[0058] The key design feature of this embodiment is to set the second serial communication protocol clock CLK clock frequency to 50kHz to match the SPI output rate of the display chip; and to ensure data synchronization through cyclic acquisition to avoid bit loss or code errors.

[0059] In one feasible implementation, taking display chip data interaction as an example, the first serial communication protocol data pin is GPIO0, the first serial communication protocol clock pin is GPIO1, the second serial communication protocol clock pin is GPIO2, the second serial communication protocol data input pin is GPIO3, and the second serial communication protocol chip select pin is GPIO4. The specific implementation process is as follows: I2C sends control commands: ① The converged terminal needs to send a "display power consumption data" command to the display chip. The data content is: 0xAE, 0x00, 0x10, 0xB0, 0xC8; ② Call the I2C simulation function i2c_send_data (0x3C, data, 5), with parameters: display chip address 0x3C, data array, and data length; ③ The program controls the GPIO expansion chip through the I2C bus, causing GPIO0 (SDA) and GPIO1 (SCL) to toggle their levels according to the I2C timing sequence, and then sends the start bit, 5 bytes of data, and the stop bit in sequence, with a transmission time of about 0.5ms; ④ After the display chip receives the instruction, it prepares the corresponding status data, such as "Data reception successful": 0x01, and waits for SPI transmission.

[0060] SPI receive status data: ⑤ Call the SPI simulation function spi_receive_data (0x01,&recv_data), with parameters: data length 1 byte, receive buffer; ⑥ The program controls the GPIO4 (CS) of the GPIO expansion chip to pull low, and then toggles the GPIO2 (CLK) level at a frequency of 50kHz, synchronously reading the level state of GPIO3 (MISO), continuously acquiring 8 bits of data, and obtaining recv_data=0x01; ⑦ After the data acquisition is complete, GPIO4 (CS) is pulled high, and the SPI reception takes about 0.2ms; Data verification: Compare the sent command with the received status to confirm that the display chip has correctly received the control command; Repeat the above process to continuously send 1000 instructions. The I2C transmission success rate is 100%, the SPI reception success rate is 100%, and there are no lost or incorrect codes.

[0061] like Figure 5 As shown, Figure 5To expand the GPIO-simulated I2C transmission process diagram, taking 10μs as an example, SCL is the clock line, controlled by the master device, used to synchronize the data transmission rhythm; the corresponding hardware pin in the diagram is GPIO1. SDA is the data line, through which the master and slave devices (display chip) transmit data bidirectionally; the corresponding hardware pin in the diagram is GPIO0. All marked delay times in the diagram are 10μs, corresponding to the clock cycle of the standard I2C mode (100kHz). When SCL is held high, SDA is pulled low, generating a falling edge, marking the start of a communication. SCL is first set high and held for 10μs; SDA is pulled low and held for 10μs; the start bit is complete, and the master device begins to send the slave device address and data. Each transmission is 1 byte (8 bits of data), with the most significant bit first; each bit of data transmission corresponds to one SCL clock cycle. When SCL is low, SDA can change its level (set to 0 or 1) to prepare for the next bit of data, lasting 10μs. When SCL goes high, SDA must remain stable, and the slave device reads data from SDA during this phase, lasting 10μs. This process is repeated to complete the transmission of 8 bits of data. When SCL remains high, SDA is pulled high, generating a rising edge, marking the end of one communication cycle. SCL is set high and held for 10μs; SDA is pulled high and held for 10μs; the stop bit is complete, the master device releases the bus, and the slave device returns to the idle state.

[0062] In this embodiment, when the current communication direction is that the display chip outputs status data to the main control chip, the level state of the second extended GPIO is controlled to simulate the timing of the second serial communication protocol to receive status data. Through the above-mentioned fine timing control, the efficient simulation of the SPI protocol on the extended GPIO is achieved.

[0063] It should be noted that the above examples are only for understanding this application and do not constitute a limitation on the dual-interface communication method of the integrated terminal display chip of this application. Any simple modifications based on this technical concept are within the protection scope of this application.

[0064] The above description is only a part of the embodiments of this application and does not limit the patent scope of this application. All equivalent structural transformations made under the technical concept of this application and using the contents of the specification and drawings of this application, or direct / indirect applications in other related technical fields, are included in the patent protection scope of this application.

Claims

1. A dual-interface communication system for a converged terminal display chip, characterized in that, The dual-interface communication system of the converged terminal display chip includes: a main control chip, a single GPIO expansion chip, and a display chip; the main control chip is connected to the chip communication pin of the GPIO expansion chip through two native GPIO pins, and the GPIO expansion chip expands to multiple GPIO pins, wherein at least two of the expanded first extended GPIOs are connected to the first communication interface pin of the display chip, and at least three expanded second extended GPIOs are connected to the second communication interface pin of the display chip; The main control chip is used to send control commands to the GPIO expansion chip; The main control chip is also used to simulate the timing of a first serial communication protocol to send control commands to the display chip by controlling the level state of the GPIO expansion chip, and to simulate the timing of a second serial communication protocol to receive status data from the display chip. The display chip is used to display data according to the control instructions.

2. The dual-interface communication system for a converged terminal display chip as described in claim 1, characterized in that, The first extended GPIO is a transmitting pin that simulates the first serial communication protocol, and the second extended GPIO is a receiving pin that simulates the second serial communication protocol. The first communication interface is a first serial communication protocol interface used to receive control commands; the second communication interface is a second serial communication protocol interface used to output status data.

3. The dual-interface communication system for a converged terminal display chip as described in claim 1, characterized in that, The first extended GPIO includes a first serial communication protocol data pin and a first serial communication protocol clock pin, and the second extended GPIO includes a second serial communication protocol clock pin, a second serial communication protocol data input pin, and a second serial communication protocol chip select pin.

4. A dual-interface communication method for a converged terminal display chip, characterized in that, The dual-interface communication method for the converged terminal display chip is applied to the dual-interface communication system for the converged terminal display chip according to any one of claims 1 to 3. The dual-interface communication for the converged terminal display chip includes a main control chip, a single GPIO expansion chip, and a display chip. The GPIO expansion chip expands to multiple GPIO pins, wherein at least two of the expanded first GPIO pins are connected to the first communication interface pins of the display chip, and at least three of the expanded second GPIO pins are connected to the second communication interface pins of the display chip. The dual-interface communication method for the converged terminal display chip includes: Determine the current communication direction of the current instruction or data; Based on the current communication direction, the level states of the first extended GPIO and / or the second extended GPIO are controlled to complete the communication between the main control chip and the display chip.

5. The dual-interface communication method for a converged terminal display chip as described in claim 4, characterized in that, The step of controlling the level of the first extended GPIO and / or the second extended GPIO based on the current communication direction includes: When the current communication direction is for the main control chip to transmit control commands to the display chip, the level state of the first extended GPIO is controlled to simulate the timing of the first serial communication protocol to transmit control commands to the display chip.

6. The dual-interface communication method for a converged terminal display chip as described in claim 5, characterized in that, The at least two extended first GPIO pins include: a first serial communication protocol data pin and a first serial communication protocol clock pin; The step of controlling the level state of the first extended GPIO when the current communication direction is when the main control chip transmits control commands to the display chip includes: When the current communication direction is for the main control chip to transmit control commands to the display chip, the level switching time of the first serial communication protocol data pin and the first serial communication protocol clock pin is controlled by a preset level switching time to simulate the timing of the first serial communication protocol in order to transmit control commands to the display chip.

7. The dual-interface communication method for a converged terminal display chip as described in claim 6, characterized in that, The step of controlling the level switching of the first serial communication protocol data pin and the first serial communication protocol clock pin by controlling the level switching time of the first serial communication protocol to simulate the timing of the first serial communication protocol in order to transmit control commands to the display chip when the current communication direction is when the main control chip transmits control commands to the display chip includes: When the current communication direction is for the main control chip to transmit control commands to the display chip, the level of the first serial communication protocol clock pin is set high, and after waiting for a first preset level switching time, the level of the first serial communication protocol data pin is pulled low from high, and after waiting for a first preset level switching time, the start bit transmission is completed. By controlling the level states of the first serial communication protocol data pin and the first serial communication protocol clock pin bit by bit using a preset data format and a first preset level switching time, the data bit transmission is completed. The level of the first serial communication protocol clock pin is set high, and after waiting for a first preset level switching time, the level of the first serial communication protocol data pin is pulled high from low, and after waiting for a first preset level switching time, the stop bit is sent, the simulation of the first serial communication protocol timing is completed, and the control command is sent to the display chip.

8. The dual-interface communication method for a converged terminal display chip as described in claim 4, characterized in that, The step of controlling the level state of the first extended GPIO and / or the second extended GPIO based on the current communication direction includes: When the current communication direction is that the display chip outputs status data to the main control chip, the level state of the second extended GPIO is controlled to simulate the timing of the second serial communication protocol to receive status data.

9. The dual-interface communication method for a converged terminal display chip as described in claim 8, characterized in that, The extended at least three second extended GPIOs include a second serial communication protocol clock pin, a second serial communication protocol data input pin, and a second serial communication protocol chip select pin; The step of controlling the level state of the second extended GPIO to simulate the timing of the second serial communication protocol to receive status data when the current communication direction is that the display chip outputs status data to the main control chip includes: When the current communication direction is that the display chip outputs status data to the main control chip, the level of the second serial communication protocol clock pin, the second serial communication protocol data input pin, and the second serial communication protocol chip select pin is controlled by the second preset level switching time to simulate the timing of the second serial communication protocol in order to receive the status data output by the display chip.

10. The dual-interface communication method for a converged terminal display chip as described in claim 9, characterized in that, The step of receiving the status data output by the display chip when the current communication direction is the display chip outputting status data to the main control chip, controlling the level switching of the second serial communication protocol clock pin, the second serial communication protocol data input pin, and the second serial communication protocol chip select pin through a second preset level switching time to simulate the timing of the second serial communication protocol, includes: When the current communication direction is that the display chip is outputting status data to the main control chip, the level of the second serial communication protocol chip select pin is pulled low, and the second preset level switching time is waited for to notify the display chip to prepare to send status data; The level of the second serial communication protocol clock pin is pulled high from low and held for a preset duration so that the display chip outputs data to the second serial communication protocol data input pin. Read and store the level of the second serial communication protocol data input pin, pull the level of the second serial communication protocol clock pin low and keep it low for a preset duration, and repeat the step of controlling the level of the second serial communication protocol clock pin to pull it high from low and keep it high for a preset duration a preset number of times until a preset number of bits of status data are collected. Pull the level of the second serial communication protocol chip select pin high and wait for the second preset level switching time to complete the reception of status data.

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