Code generation method and device, electronic equipment and storage medium

Abstract

The application discloses a code method and device, electronic equipment and storage medium, and relates to the technical field of integrated circuits, and comprises: obtaining a bit sequence signal description file and a configuration file of a target bit sequence signal. According to the bit sequence signal description file and the configuration file of the target bit sequence signal, configuration information of each register is generated, and the type of each register is identified. Taking a first register as an example, a corresponding target code template can be obtained according to the type of the first register. In the case where it is determined that the type of the first register is a first preset type, a first sub-configuration code is generated according to the configuration information of the first register, the configuration file and the target code template. In this way, sub-configuration codes can be obtained by automatically performing corresponding code generation operations according to the type of the register, manual writing of configuration codes by technical personnel can be avoided, the probability of errors can be reduced, and time waste caused by modification and verification operations can be reduced, thereby improving development efficiency.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to code generation methods, apparatus, electronic devices and storage media. Background Technology

[0002] In the field of integrated circuit technology, an electronic fuse (EFUSE) is a programmable non-volatile memory element that can be used to adjust critical parameters of an integrated circuit, such as power supply voltage and clock frequency, or to enable or disable certain functional modules within the integrated circuit through programming. In integrated circuit design, the connection between the EFUSE's bit sequence signal and other functional module signals is crucial, affecting the integrated circuit's configuration, calibration, and security functions. However, when the integrated circuit architecture changes, integrated circuit engineers need to manually adjust and modify the relevant code.

[0003] However, manual modification is prone to errors and inefficient. Summary of the Invention

[0004] This application provides code generation methods, apparatus, electronic devices, storage media, and program products to solve the problems of error-proneness and low efficiency caused by manually modifying code.

[0005] This application provides a code generation method, including:

[0006] Obtain the bit sequence signal description file corresponding to the electronic fuse and the configuration file of the target bit sequence signal; Based on the bit sequence signal description file and configuration file, generate configuration information for at least one register; Based on the configuration information of the first register, determine the type of the first register, wherein the first register is any one of at least one registers; Based on the type of the first register, select a target code template that matches the type of the first register from at least one pre-built code template; When the type of the first register is determined to be the first preset type, the first sub-configuration code is generated according to the configuration information of the first register, the configuration file, and the target code template. The first preset type is used to indicate that the bit sequence signal corresponding to the first register is the target bit sequence signal and that the first register does not have a corresponding backup register. The first sub-configuration code is used to be burned into the electronic fuse so that the electronic fuse can perform register configuration operations according to the first sub-configuration code.

[0007] This application also provides a code generation apparatus, including: The acquisition module is used to acquire the position sequence signal description file corresponding to the electronic fuse and the configuration file of the target position sequence signal; The generation module is used to generate configuration information for at least one register based on the bit sequence signal description file and the configuration file. The determining module is used to determine the type of the first register based on the configuration information of the first register, wherein the first register is any one of at least one registers; A selection module is used to select a target code template that matches the type of the first register from at least one pre-built code template, based on the type of the first register. The generation module is also used to generate a first sub-configuration code based on the configuration information of the first register, the configuration file, and the target code template when the type of the first register is determined to be a first preset type. The first preset type is used to indicate that the bit sequence signal corresponding to the first register is the target bit sequence signal and that the first register does not have a corresponding backup register. The first sub-configuration code is used to be burned into the electronic fuse so that the electronic fuse can perform register configuration operations according to the first sub-configuration code.

[0008] This application also provides an electronic device, including: a memory for storing a computer program; and a processor for implementing the steps of any of the above-described code generation methods when executing the computer program.

[0009] This application also provides a computer-readable storage medium storing a computer program, wherein the computer program, when executed by a processor, implements the steps of any of the above-described code generation methods.

[0010] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of any of the above-described code generation methods.

[0011] This application first obtains a bit sequence signal description file and a target bit sequence signal configuration file. Then, based on these files, configuration information for each register is generated, and the type of each register is identified. Taking the first register as an example, the corresponding target code template can be obtained based on its type. If the first register is determined to be of a first preset type, first sub-configuration code is generated based on its configuration information, the configuration file, and the target code template. This allows for automatic code generation based on the register type, eliminating the need for manual configuration writing by technical personnel, reducing the probability of errors, and consequently minimizing time wasted on modification and verification operations, thus improving development efficiency. Attached Figure Description

[0012] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0013] Figure 1 A flowchart illustrating a code method provided in an embodiment of this application; Figure 2 A flowchart illustrating the parsing of a target bit sequence signal is provided for an embodiment of this application. Figure 3 This application provides a flowchart illustrating the parsing of a bit order signal description file. Figure 4 A flowchart illustrating another code method provided in an embodiment of this application; Figure 5 A flowchart illustrating another code method provided in an embodiment of this application; Figure 6 This is a schematic diagram of the structure of a code generation device provided in an embodiment of this application; Figure 7 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0014] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.

[0015] It should be noted that, in the description of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., in this application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0016] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0017] With the continuous advancement of semiconductor technology, System-on-a-Chip (SoC) has become a core component of electronic products. SoC integrates multiple functional modules such as microprocessors, memory, and peripheral interfaces, greatly improving system performance and integration, reducing product size, and lowering power consumption and cost.

[0018] However, SoCs face numerous challenges in practical applications. On the one hand, unavoidable deviations in integrated circuit manufacturing processes lead to differences in performance parameters within the same batch of SoCs, such as transistor threshold voltage and interconnect resistance and capacitance. These differences affect the overall performance and stability of the integrated circuit. On the other hand, as electronic products become increasingly feature-rich, higher demands are placed on the security and configurability of SoCs. Traditional fixed-function designs struggle to meet diverse market demands, and in today's world where information security is paramount, preventing the illegal copying and tampering of integrated circuits has become a pressing issue. Electronic fuse (EFUSE) technology has emerged to address these challenges. An electronic fuse is a programmable non-volatile memory element that operates based on electromigration and thermal effects. By applying a specific programming current, the fuse can transition from a low-resistance state to a high-resistance state, thus enabling information to be written. This programming process is irreversible; once written, the information is permanently stored and will not be lost even if the integrated circuit is powered off.

[0019] In System-on-a-Chip (SoC), electronic fuses have several important applications. First, they can be used for process compensation in integrated circuits. By programming the electronic fuse after SoC manufacturing, key parameters such as power supply voltage and clock frequency can be adjusted to compensate for performance differences caused by manufacturing process variations, ensuring optimal performance for each SoC. Second, electronic fuses can be used for SoC configuration and personalization. Manufacturers can program electronic fuses to enable or disable certain functional modules according to different customer needs, achieving product differentiation and customization. Furthermore, electronic fuses play a crucial role in SoC security. They can store the SoC's unique identifier (ID) for anti-counterfeiting and traceability, and can also store encryption keys, ensuring secure communication and data storage for SoCs.

[0020] In integrated circuit design, the bit order of electronic fuses and their connections to other design modules are crucial, affecting the configuration, calibration, and security functions of the integrated circuit. However, when the integrated circuit architecture changes or the bit order of the electronic fuse and the signals of the modules it is connected to change, integrated circuit engineers need to manually adjust and modify the relevant code. Relying on manual modification indefinitely has the following drawbacks: First, it is prone to errors. Connecting electronic fuses and other design modules is difficult to do correctly on the first try, requiring repeated modifications, compilation, and debugging of the design code.

[0021] Secondly, it is inefficient, time-consuming and labor-intensive, relying on manual coding by technical personnel, which seriously hinders development efficiency.

[0022] Third, slow updates. When the logic related to the electronic fuse in the SoC integrated circuit architecture changes, technicians need to modify and adapt it again. This is prone to errors and inefficient, which hinders work efficiency and thus the overall development efficiency of the integrated circuit.

[0023] To address the aforementioned problems, embodiments of this application provide a code generation method that can be executed by an electronic device (e.g., a server, computer, etc.), such as... Figure 1 As shown, the specific processing steps of the code generation method may include: Step S101: Obtain the position sequence signal description file and the target position sequence signal configuration file corresponding to the electronic fuse.

[0024] The bit sequence signal description file can be in Excel format. Table entries can include register type (Category), register identification information, bit width, and the bit sequence of the electronic fuse. Register type can be integrated circuit mode, temperature sensor, memory, etc. Integrated circuit mode can be represented as "Chip mode," primarily used to inform the integrated circuit how to start up and what operations to perform after startup. Temperature sensor can be represented as "Tempsensor," mainly used for temperature calibration. Memory can be represented as "memory." Register identification information can include the register name, sequence number, etc. For example, the bit sequence signal description file can be as shown in Table 1.

[0025] Table 1

[0026] The target bit sequence signal is a bit sequence signal of type 'bit sequence signal', which refers to a special bit sequence signal that requires special configuration operations. It can be a selection bit sequence signal. For example, the configuration file for the target bit sequence signal can be written using JavaScript Object Notation (JSON), as shown below: “[ { "register_name":"tref", "condition_signal":"tref_ddelta_sel_i", "select:_signal":"tsensor_tref_i" } { "register_name":"ddelta", "condition_signal":"tref_ddelta_sel_i", "select:_signal":"tsensor_ddelta_i" } ]” Here, "register_name" represents the register identification information, "condition_signal" represents the condition signal identification information, and "select:_signal" represents the selection signal identification information.

[0027] Specifically, technicians can pre-build a position sequence signal description file and a target position sequence signal configuration file, and upload them to the electronic device. In this way, the electronic device can obtain the position sequence signal description file corresponding to the electronic fuse.

[0028] Step S102: Generate configuration information for at least one register based on the bit sequence signal description file and configuration file.

[0029] Specifically, the bit sequence signal description file can include configuration information for each register corresponding to the bit sequence signal of the electronic fuse. The configuration file indicates the relevant configuration information for each target bit sequence signal. Therefore, the electronic device can parse the bit sequence signal description file to obtain the initial configuration information of each register, and then complete the configuration information of the registers using the target bit sequence signals in the configuration file to obtain the configuration information of each register. The configuration information of each register constitutes a register information list.

[0030] Step S103: Determine the type of the first register based on the configuration information of the first register.

[0031] The first register can be any one of at least one register. The type of the first register can be one of a first preset type, a second preset type, a third preset type, etc. The first preset type can be used to indicate that the bit sequence signal corresponding to the first register is the target bit sequence signal, and that the first register does not have a corresponding backup register. The second preset type can be used to indicate that the first register has a corresponding backup register, and that the bit sequence signal corresponding to the first register is not the target bit sequence signal. The third preset type can be used to indicate that the bit sequence signal corresponding to the first register is not the target bit sequence signal, and that the first register does not have a corresponding backup register.

[0032] Specifically, this scheme sets different code templates for different types of registers. The register configuration information indicates the register type. Therefore, to accurately generate configuration code later, the configuration information of each register in the register information list can be traversed. For each register configuration information encountered, the type of each register can be identified based on the encountered register configuration information, and subsequent steps can be executed to generate the corresponding sub-configuration code for each register. Taking the first register as an example, the type of the first register can be identified based on its configuration information.

[0033] Step S104: Select a target code template that matches the type of the first register from at least one pre-built code template, based on the type of the first register.

[0034] The code template can include assignment keywords, separators (e.g., ":"), and fields and operators to be configured corresponding to the type of the first register. For example, the assignment keyword could be "assign". The fields to be configured in the code template of the first preset type include a register name field, a condition signal field, a selection signal field, and a bit order field. Operators include the equals sign and conditional operators (e.g., "?" and ":"). The fields to be configured in the code template of the second preset type include a register name field, a major bit order field, and a minor bit order field. Operators include the equals sign and bit-level logical operators ("|"). The fields to be configured in the code template of the third preset type include a register name field and a bit order field. Operators include the equals sign.

[0035] Specifically, taking the first register as an example, the electronic device can determine a code template that matches the type of the first register from at least one pre-built code template, and determine the matched code template as the target code template.

[0036] Step S105: If the type of the first register is determined to be the first preset type, generate the first sub-configuration code according to the configuration information of the first register, the configuration file, and the target code template.

[0037] The first sub-configuration code is used to program the electronic fuse so that the electronic fuse can perform register configuration operations based on the first sub-configuration code. The register is the same as the register in the other design modules mentioned above.

[0038] Specifically, after determining the type of the first register, the electronic device can select the corresponding building element based on the type of the first register and generate the first sub-configuration code based on the selected building element. Specifically, if the type of the first register is determined to be a first preset type, it means that the bit sequence signal corresponding to the first register is the target bit sequence signal, and the configuration file includes the configuration information of the target bit sequence signal. Therefore, the configuration information of the first register, the configuration file, and the target code template can be used as building elements corresponding to the first preset type. Furthermore, the electronic device can extract the key information required for the target code template from the configuration information of the first register and the configuration file, add it to the corresponding fields in the target code template, and obtain the first sub-configuration code.

[0039] Finally, after the first sub-configuration code is burned into the electronic fuse, the electronic fuse can execute the first sub-configuration code after the integrated circuit is started, and connect the first register with its corresponding bit sequence signal to complete the configuration operation of the first register.

[0040] The code generation method of this application, according to embodiments, firstly obtains a bit sequence signal description file and a target bit sequence signal configuration file. Then, based on the bit sequence signal description file and the target bit sequence signal configuration file, configuration information for each register is generated, and the type of each register is identified. Taking the first register as an example, the corresponding target code template can be obtained based on the type of the first register. If the type of the first register is determined to be a first preset type, first sub-configuration code is generated based on the configuration information of the first register, the configuration file, and the target code template. In this way, the corresponding code generation operation can be automatically executed according to the type of register to obtain the sub-configuration code, eliminating the need for technicians to manually write configuration code, reducing the probability of errors, and thus reducing the time wasted on modification and verification operations, thereby improving development efficiency.

[0041] In some optional implementations, in step S102 above, the electronic device can parse the bit sequence signal description file and the target bit sequence signal configuration file respectively to obtain the configuration information of each register.

[0042] The process of parsing the configuration file of the target bit sequence signal can be referenced as follows: Figure 2 The process is illustrated below. The electronic device can parse the target bit sequence signal configuration file, sequentially obtaining the register names, condition signal identifiers, and selection signal identifiers corresponding to each target bit sequence signal, and storing them sequentially in the target bit sequence signal list. The process ends after traversing all the configuration information of the target bit sequence signals in the configuration file. If the traversal is not complete, it can continue traversing the configuration information of the next target bit sequence signal. This process continues until the final target bit sequence signal list is obtained, which is used to generate sub-configuration code. The relationship between the condition signal and the selection signal is that when the sampled condition signal meets a specified condition (e.g., equal to 0), the value of the selection signal is connected to the corresponding register.

[0043] The process of parsing the configuration file for the bit sequence signal description file can be found in the following example: Figure 3 The process is shown below.

[0044] The aforementioned bit sequence signal description file includes at least one register type and a register list corresponding to each of the at least one register type. The register list includes at least one piece of register information, such as register identification information, bit width, bit sequence, etc.

[0045] Step 1: Obtain the initial data structure.

[0046] The initial data structure may include a register type information field and a register information field. For example, the initial data structure may be in JSON format.

[0047] Specifically, technicians can pre-build an initial data structure for storing register configuration information. The electronic device can then access this initial data structure.

[0048] Step two: Modify the register type information field according to the target register type. Also, modify the register information field according to the target register information.

[0049] The target register type can be any of at least one register type. The target register information is any one of the register information included under the target register type. For example, if the target register type is "Chip mode", the target register information can be the information of "Chip_ID0".

[0050] Specifically, electronic devices can first use a code manipulation library (e.g., the Python Pandas library) to parse the bit order description file, extract the register types including backup markers (e.g., "back up"), and then extract the corresponding register information to construct a backup register list. This way, by adding backup markers to register types, there is no need to add new fields specifically indicating whether it is a backup register type, making it much simpler.

[0051] The electronic device can then iterate through the register types in the bit sequence signal description file. Upon encountering a register type, it can determine whether a corresponding backup register type exists.

[0052] If a corresponding backup register type exists for this register type, all register information under the backup register type can be extracted from the backup register list as backup information, and the register information under this register type can be traversed.

[0053] If there is no corresponding backup register type for this register type, the register information under this register type can be traversed directly.

[0054] Upon traversing each register entry, the electronic device can determine whether it contains a Reserve indicator, i.e., whether the register is a reserved register. If the register contains a Reserve indicator, and there are untraversed register entries of that type, the traversal can continue to the next register entry. If the register does not contain a Reserve indicator, information such as the register identifier, bit width, and bit order can be extracted from the register entry. This information, combined with the target bit order signal list, determines whether the corresponding bit order signal is the target bit order signal. Furthermore, based on the extracted information and the determination result, the initial data structure can be modified to obtain the register's configuration information. If backup information exists, the initial data structure can be modified using the backup information, the extracted information, and the determination result to obtain the register's configuration information.

[0055] If there are still untraversed register entries under this register type, you can continue traversing the next register entry. If there are no untraversed register entries under this register type, and you have not yet traversed all register types, you can continue traversing the next register type. If you have traversed all register entries under all register types, you can stop traversing.

[0056] During the above traversal process, modifying the register type information field according to the target register type may specifically include: The register type information field can include a register type name field, a backup indication field, and an identity field. Accordingly, the electronic device can set these three fields. Specifically, first, the target register type is added to the register type name field. Second, if it is determined that a corresponding backup register type exists for the target register type, the backup indication field is set to a first indication (e.g., True). If it is determined that no corresponding backup register type exists for the target register type, the backup indication field is set to a second indication (e.g., False). Third, if it is determined that the target register type does not include a backup flag but a corresponding backup register type exists, the identity field is set to master register (e.g., "master"). If it is determined that the target register type includes a backup flag, the identity field is set to slave register (e.g., "slave"). If it is determined that no corresponding backup register type exists for the target register type, the identity field is set to no backup register (e.g., "no backup").

[0057] Modifying the register information fields based on the target register information can specifically include: The target register information may include the target register's identification information and bit sequence information. Register information fields may include a register name field, a register index field, a register bit width field, a start index field, an end index field, and a bit sequence field for the electronic fuse. Accordingly, the electronic device may add the target register's name to the register name field, the identification information included in the target register's name to the register index field, the target register's bit width to the bit width field, the start index from the target register's bit sequence information to the start index field, the end index from the target register's bit sequence information to the end index field, and the target register's bit sequence information to the bit sequence field.

[0058] Additionally, the electronic device can determine whether special signal configuration information corresponding to the name of the target register exists in the configuration file. If it is determined that configuration information for the target bit sequence signal corresponding to the name of the target register exists in the target bit sequence signal list, the target bit sequence signal indication field is set to the third indication information (e.g., True). Alternatively, if it is determined that special signal configuration information corresponding to the name of the target register does not exist in the target bit sequence signal list, the target bit sequence signal indication field is set to the fourth indication information (e.g., False).

[0059] After modifying the register type information field and the register information field, an initial configuration information for a bit sequence signal is obtained.

[0060] For example, the configuration information for the "chio_id0" register can be as follows: { "category_name":"Chip_mode", "is_need_backup":True, "register_field_info_list": [ { "register_name":"chio_id0", “register_index”:0, “register_width”:32, “start_index”:0, “end_index”:31, "fuse_bit_order":"31:0", "is_select_register_type":False } ], "master_or_slave_backup_regster":"Master", "master_or_slave_register_index":-1 } Among them, "category_name" represents the register type field, "is_need_backup" represents the backup indication field, "register_field_info_list" represents the register information field, "register_name" represents the register name field, "register_index" represents the register index field, "register_width" represents the register bit width field, "start_index" represents the start index field, "end_index" represents the end index field, "fuse_bit_order" represents the electronic fuse bit order field, "is_select_register_type" represents the target bit order signal indication field, "master_or_slave_backup_register" represents the register identity field, used to indicate the master / slave status of the current register when a backup register exists, and "master_or_slave_register_index" represents the register identity index field, which is generally set to the default value "-1".

[0061] In some optional implementations, the configuration information of the first register includes a backup attribute field and a target bit sequence signal indication field. The backup attribute field can be one of the backup indication field or the identity field described above. Accordingly, in step S103 above, the electronic device can determine the type of the first register using the following specific steps: Step 1: If the target bit sequence signal indication field is determined to be used to indicate that the bit sequence signal corresponding to the first register is the target bit sequence signal, then the type of the first register is determined to be the first preset type.

[0062] Alternatively, in step two, if it is determined that the backup attribute field is used to indicate that a corresponding backup register exists in the first register, the type of the first register is determined to be the second preset type.

[0063] Alternatively, in step three, if the target bit sequence signal indication field is used to indicate that the bit sequence signal corresponding to the first register is not the target bit sequence signal, and the backup attribute field is used to indicate that the first register does not have a corresponding backup register, then the type of the first register is determined to be the third preset type.

[0064] Specifically, the electronic device can extract the field value from the target bit sequence signal indication field of the configuration information of the first register. Then, when the field value is determined to be the third indication information, the type of the first register can be determined to be the first preset type. When the field value is determined to be the fourth indication information, the type of the first register can be determined to be the first preset type.

[0065] Furthermore, the electronic device can extract the field value from the backup attribute field of the configuration information in the first register. When the backup attribute field is the backup indication field mentioned above, if the field value is determined to be the first indication information, then the type of the first register can be determined to be the second preset type; if the field value is determined to be the second indication information, then the type of the first register can be determined to be the second preset type. Alternatively, when the backup attribute field is the identity field mentioned above, if the field value is determined to be either a master register or a slave register, then the type of the first register can be determined to be the second preset type; if the field value is determined to be "no backup register exists," then the type of the first register can be determined to be the second preset type.

[0066] When an electronic device determines that the target bit sequence signal indication field is the fourth indication information and the backup indication field is the second indication information (or the identity field indicates that there is no backup register), it can determine that the type of the first register is the third preset type.

[0067] In this way, by using field values ​​(such as the aforementioned first and second indication information) for binary or enumeration judgment, we can avoid classification errors caused by inconsistent human interpretation. For example, we can prevent ordinary registers from being misjudged as special types, reduce the probability of errors, and improve development efficiency.

[0068] In some alternative implementations, the electronic device may also perform the following specific steps: Step 1: If the type of the first register is determined to be the second preset type, the configuration information of the second register that has a master-slave relationship with the first register is determined from the configuration information of at least one register based on the configuration information of the first register.

[0069] The second preset type is used to indicate that a corresponding backup register exists for the first register. When the first register is the master register, the second register is the slave register, and when the first register is the slave register, the second register is the master register.

[0070] Step 2: Generate the first sub-configuration code based on the configuration information of the first register, the configuration information of the second register, and the target code template.

[0071] Specifically, as stated in step S105, after determining the type of the first register, the electronic device can select the corresponding building element according to the type of the first register and generate the first sub-configuration code based on the selected building element. Specifically, if the type of the first register is determined to be a second preset type, it indicates that the bit sequence signal corresponding to the first register is not the target bit sequence signal, and the first register has a corresponding backup register. Therefore, based on the configuration information of the first register, the configuration information of the second register, which is a backup register of the first register, can be determined from the configuration information of at least one register; that is, the configuration information of the second register that has a master-slave relationship with the first register can be determined. Furthermore, the configuration information of the first register, the configuration information of the second register, and the target code template can be used as building elements corresponding to the second preset type. Furthermore, the electronic device can extract the key information required for the target code template from the configuration information of the first register and the configuration information of the second register, add it to the corresponding fields in the target code template, and obtain the first sub-configuration code.

[0072] Thus, electronic fuses are one-time programmable devices; incorrect programming can render the integrated circuit unusable or degraded. Therefore, a backup mechanism is a critical reliability design element in electronic fuses. Previously, technicians had to manually write the logical relationships between the master and slave registers. This is highly error-prone when there are numerous registers and complex bit sequences. This solution avoids this problem by automatically generating code, ensuring that correct configuration code can still be generated under backup settings.

[0073] In some alternative implementations, the electronic device may also perform the following specific steps: If the type of the first register is determined to be the third preset type, the first sub-configuration code is generated based on the configuration information of the first register and the target code template.

[0074] Specifically, as stated in step S105, after determining the type of the first register, the electronic device can select the corresponding building element according to the type of the first register, and generate the first sub-configuration code based on the selected building element. Specifically, if the type of the first register is determined to be a third preset type, it means that the bit sequence signal corresponding to the first register is not the target bit sequence signal, and the first register does not have a corresponding backup register. Therefore, the configuration information of the first register and the target code template can be directly used as the building element corresponding to the third preset type. Furthermore, the electronic device can extract the key information required for the target code template from the configuration information of the first register according to the target code template, add it to the corresponding field in the target code template, and obtain the first sub-configuration code.

[0075] In this way, for different register types, this solution can select the corresponding building elements according to the register type, eliminating the need for manual judgment to search for relevant information in various files. This can greatly improve the efficiency of writing configuration code and reduce the probability of errors.

[0076] In some optional implementations, during the generation of the first sub-configuration code, the electronic device can identify the fields to be configured (e.g., the content within "{}" in the code template are all fields to be configured) based on the target code template, and identify the field values ​​matching the fields to be configured (i.e., the key information required by the target code template) in the configuration information of the first register, and add the field values ​​to the fields to be configured. Specifically, depending on the type of the first register, this step may include the following three cases: In scenario one, the first register is of a first preset type. The configuration file may include the name of the first register, the identification information of the condition signal, and the identification information of the selection signal. The configuration information of the first register may include the name and bit order information of the first register. Accordingly, in step S105 above, when it is determined that the type of the first register is the first preset type, the electronic device may use the following specific steps to generate the first sub-configuration code based on the configuration information of the first register, the configuration information of the second register, and the target code template: Step 1: Add the name of the first register to the register name field.

[0077] Step 2: Add the identification information of the condition signal to the condition signal field.

[0078] Step 3: Add the identification information of the selection signal to the selection signal field.

[0079] Step 4: Add the positional information to the positional field.

[0080] Step 5: After completing the addition operation, you will obtain the first sub-configuration code.

[0081] The bit sequence field can include a start index field and an end index field, and the bit sequence information can include the start index and the end index. The name of the first register, the identification information of the condition signal, the identification information of the selection signal, and the bit sequence information are the field values ​​to be configured.

[0082] For example, the code template corresponding to the first preset type can be as follows: "assign{register_signal}={condition_signal}?{select:_signal}:efuse_data_r[{start_index}:{end_index}];" Here, {register_signal} represents the register name field, {condition_signal} represents the condition signal field, {select:_signal} represents the select signal field, {start_index} is the start index field, and {end_index} is the end index field.

[0083] For “tref” in Table 1, the electronic device can write “tref” to {register_signal}, write “tref_ddelta_sel_i” to {condition_signal}, write “133” to {start_index}, and write “128” to {end_index}, resulting in the sub-configuration code “assign tref_s=tref_ddelta_sel_i?tsensor_tref_i:efuse_data_r[133:128]”.

[0084] For “ddelta” in Table 1, the electronic device can write “ddelta” to {register_signal}, write “tref_ddelta_sel_i” to {condition_signal}, write “137” to {start_index}, and write “134” to {end_index}, resulting in the sub-configuration code “assign ddelta_s=tref_ddelta_sel_i?tsensor_ddelta_i:efuse_data_r[137:134]”.

[0085] Scenario 2: The first register is of the second preset type. The configuration information of the first register includes its name, first bit sequence information, and first identity information. The configuration information of the first register also includes its name, second bit sequence information, and second identity information. Accordingly, the electronic device can generate the first sub-configuration code based on the configuration information of the first register and the target code template using the following specific steps: Step 1: Add the name of the first register to the register name field.

[0086] Step 2: If it is determined that the first identity information is used to indicate that the first register is the master register, add the first bit sequence information to the master bit sequence field.

[0087] And, in step 3, if it is determined that the second identity information is used to indicate that the second register is a slave register, the second bit sequence information is added to the slave bit sequence field.

[0088] Step 4: After completing the addition operation, you will obtain the first sub-configuration code.

[0089] Both the primary and secondary order fields can include a start index field and an end index field. Both the first and second order information can include a start index and an end index. The name of the first register, the first order information, and the second order information are the values ​​of the fields to be configured. The first identity information can be extracted from the identity field of the configuration information in the first register, and the second identity information can be extracted from the identity field of the configuration information in the second register.

[0090] For example, the code template corresponding to the second preset type can be as follows: "assign{register_signal}=efuse_data_r[{master_start_index}:{master_end_index}]|fuse_data_r[{backup_start_index}:{backup_end_index}];" Where {register_signal} represents the register name field, {master_start_index} represents the starting index field in the master sequence field, {master_end_index} represents the ending index field in the master sequence field, {backup_start_index} represents the starting index field in the backup sequence field, and {backup_end_index} represents the ending index field in the backup sequence field.

[0091] For “Chip_id0” in Table 1, the electronic device can write “Chip_id0” to {register_signal}, write “31” to {master_start_index}, write “0” to {master_end_index}, write “169” to {backup_start_index}, and write “138” to {backup_end_index}, and get the sub-configuration code as assign Chip_id0 = efuse_data_r[31:0]|efuse_data_r[169:138].

[0092] For “Chip_id1” in Table 1, the electronic device can write “Chip_id1” into {register_signal}, write “63” into {master_start_index}, write “32” into {master_end_index}, write “201” into {backup_start_index}, and write “170” into {backup_end_index}, resulting in the sub-configuration code assign Chip_id1=efuse_data_r[63:32]|efuse_data_r[201:170].

[0093] For “Chip_id2” in Table 1, the electronic device can write “Chip_id2” to {register_signal}, write “95” to {master_start_index}, write “64” to {master_end_index}, write “233” to {backup_start_index}, and write “302” to {backup_end_index}, resulting in the sub-configuration code assign Chip_id2=efuse_data_r[95:64]|efuse_data_r[233:202].

[0094] For “Chip_id3” in Table 1, the electronic device can write “Chip_id3” into {register_signal}, write “127” into {master_start_index}, write “96” into {master_end_index}, write “265” into {backup_start_index}, and write “234” into {backup_end_index}, resulting in the sub-configuration code assignChip_id0_s=efuse_data_r[127:96]|efuse_data_r[265:234].

[0095] Scenario 3: The first register is of type 3 (preset type). The configuration information of the first register includes its name and major bit order. Accordingly, the electronic device can generate the first sub-configuration code based on the configuration information of the first register, the configuration information of the second register, and the target code template using the following specific steps: Step 1: Add the name of the first register to the register name field.

[0096] Step 2: Add the positional information to the positional field.

[0097] Step 3: After completing the addition operation, you will obtain the first sub-configuration code.

[0098] For example, the code template corresponding to the third preset type can be as follows: "assign{register_signal}=efuse_data_r[{master_start_index}:{master_end_index}];" The bit order field can include a start index field and an end index field, and the bit order information can include the start index and the end index. The name and bit order information of the first register are the values ​​of the fields to be configured.

[0099] {register_signal} represents the register name field, {master_start_index} represents the start index field in the master sequence field, and {master_end_index} represents the end index field in the master sequence field.

[0100] For “mem_reg1” in Table 1, the electronic device can write “mem_reg1” into {register_signal}, write “281” into {master_start_index}, and write “266” into {master_end_index}, and get the sub-configuration code as assign mem_reg1=efuse_data_r[281:266].

[0101] For “mem_reg2” in Table 1, the electronic device can write “mem_reg2” to {register_signal}, write “297” to {master_start_index}, and write “282” to {master_end_index}, resulting in the sub-configuration code assign mem_reg2=efuse_data_r[297:282].

[0102] In some optional implementations, after step S105, the electronic device can further construct a connection code file for the electronic fuse based on the sub-configuration codes corresponding to at least one generated register, and then program the connection code file into the electronic fuse. Accordingly, the entire process can be as follows: Figure 4 As shown.

[0103] For example, linking code files can be done as follows: “assign Chip_id0_s=efuse_data_r[31:0]|efuse_data_r[169:138]; assign Chip_id1_s=efuse_data_r[63:32]|efuse_data_r[201:170]; assign Chip_id2_s=efuse_data_r[95:64]|efuse_data_r[233:202]; assign Chip_id3_s=efuse_data_r[127:96]|efuse_data_r[265:234]; assign tref_s=tref_ddelta_sel_i?tsensor_tref_i:efuse_data_r[133:128]; assign ddelta_s=tref_ddelta_sel_i?tsensor_ddelta_i:efuse_data_r[137:134]; assign mem_reg1=efuse_data_r[281:266]; assign mem_reg2=efuse_data_r[297:282]” In some optional implementations, the electronic device can acquire a modification instruction, which may include identification information of the register to be modified and modification information. The modification information may include one of the modified bit sequence information, bit width information, etc. When the bit sequence signal corresponding to the register to be modified is the target bit sequence signal, the modification information may also include the identification information of the modified condition signal and the identification information of the selection signal. Accordingly, the electronic device can acquire the sub-configuration code corresponding to the identification information of the register to be modified based on the identification information of the register to be modified. Then, based on the modification information, the sub-configuration code is modified to obtain the modified sub-configuration code.

[0104] In this way, when changes occur to the logic related to the electronic fuse, only the corresponding sub-configuration code needs to be modified, which is simpler and more efficient. Furthermore, it eliminates the need for technicians to re-modify and adapt the circuit, reducing the risk of errors and thus improving the overall development efficiency of the integrated circuit.

[0105] The following example illustrates the process of the code generation method described above. (Refer to...) Figure 5 .

[0106] Electronic devices can traverse the configuration information of registers in the register information list. For the configuration information of the traversed register, it is determined whether the bit sequence signal corresponding to the register is the target bit sequence signal (that is, when the field value of the target bit sequence signal indicator field is determined to be the third indicator information, it is determined to be the target bit sequence signal; otherwise, it is not the target bit sequence signal).

[0107] If the bit sequence signal corresponding to the register is the target bit sequence signal, then the first preset type of code template can be selected. Based on the register configuration information, the first preset type of code template, and the configuration file (or the target bit sequence signal list), sub-configuration code is generated and added to the connection information list.

[0108] If the bit sequence signal corresponding to the register is not the target bit sequence signal, it can be determined whether there is a corresponding backup register based on the configuration information of the traversed registers (judged according to the backup attribute field, see the above description, which will not be repeated here).

[0109] If there is no corresponding backup register for the register, the third preset type of code template can be selected. Based on the register configuration information and the third preset type of code template, sub-configuration code is generated and added to the connection information list.

[0110] If a corresponding backup register exists for the register, then the identity field in the configuration information of the traversed registers can be used to determine whether the register is the master register.

[0111] If the register is not the master register, you can continue to traverse the configuration information of the next register.

[0112] If the register is the master register, the configuration information of the slave registers in the backup register list can be traversed. For each slave register configuration entry encountered, its identifier can be extracted. The master register identifier and slave register identifier are then compared. If they match, the slave register configuration corresponds to the master register; otherwise, the process continues to the next slave register configuration entry until a matching slave register configuration is found. Based on the second preset code template, the master register configuration information, and the slave register configuration information, sub-configuration code can be generated and added to the linker information list.

[0113] After traversing all register information lists, the final connection information list is obtained, and the process ends. The electronic device can then generate a connection code file based on all sub-configuration codes in the final connection information list and burn it into the electronic fuse.

[0114] This solution automates the generation of connection code files for the bit sequence signals of electronic fuses, improving the accuracy of the connection code files, saving technicians' debugging time, and reducing manpower investment in the integrated circuit development process. This significantly improves the efficiency of technicians and reduces the maintenance costs of integrated circuits during development. When the order of the bit sequence signals needs to be adjusted, this solution can quickly adapt and regenerate the connection code file.

[0115] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method.

[0116] Embodiments of this application also provide a code generation apparatus, such as... Figure 6 As shown, it includes: The acquisition module 610 is used to acquire the position sequence signal description file corresponding to the electronic fuse and the configuration file of the target position sequence signal; The generation module 620 is used to generate configuration information for at least one register based on the bit sequence signal description file and the configuration file; The determining module 630 is used to determine the type of the first register based on the configuration information of the first register, wherein the first register is any one of at least one registers; The selection module 640 is used to select a target code template that matches the type of the first register from at least one pre-built code template, based on the type of the first register. The generation module 620 is further configured to generate a first sub-configuration code based on the configuration information of the first register, the configuration file, and the target code template when the type of the first register is determined to be a first preset type. The first preset type is used to indicate that the bit sequence signal corresponding to the first register is the target bit sequence signal and that the first register does not have a corresponding backup register. The first sub-configuration code is used to be burned into the electronic fuse so that the electronic fuse can perform register configuration operations according to the first sub-configuration code.

[0117] In some alternative implementations, the generation module 620 is further configured to: When the type of the first register is determined to be the second preset type, the configuration information of the second register that has a master-slave relationship with the first register is determined from the configuration information of at least one register according to the configuration information of the first register. The second preset type is used to indicate that the first register has a corresponding backup register, and the bit sequence signal corresponding to the first register is not the target bit sequence signal. Based on the configuration information of the first register, the configuration information of the second register, and the target code template, the first sub-configuration code is generated.

[0118] In some alternative implementations, the generation module 620 is further configured to: If the type of the first register is determined to be the third preset type, the first sub-configuration code is generated according to the configuration information of the first register and the target code template. The third preset type is used to indicate that the bit sequence signal corresponding to the first register is not the target bit sequence signal and that the first register does not have a corresponding backup register.

[0119] In some optional implementations, the configuration information of the first register includes a backup attribute field and a target bit sequence signal indication field; the determination module 630 is specifically used for: If it is determined that the target bit sequence signal indication field is used to indicate that the bit sequence signal corresponding to the first register is the target bit sequence signal, the type of the first register is determined to be the first preset type; Alternatively, if it is determined that the backup attribute field is used to indicate that a corresponding backup register exists in the first register, the type of the first register is determined to be the second preset type; Alternatively, if the target bit sequence signal indication field is used to indicate that the bit sequence signal corresponding to the first register is not the target bit sequence signal, and the backup attribute field is used to indicate that the first register does not have a corresponding backup register, then the type of the first register is determined to be the third preset type.

[0120] In some optional implementations, when the type of the first register is a first preset type, the target code template includes a register name field, a condition signal field, a selection signal field, and a bit order field; the configuration file includes the name of the first register, the identification information of the condition signal, the identification information of the selection signal; and the configuration information of the first register includes the name and bit order information of the first register. Module 620 is generated and is specifically used for: Add the name of the first register to the register name field; Add the identification information of the condition signal to the condition signal field; Add the identification information of the selection signal to the selection signal field; Add the ordinal information to the ordinal field; After completing the addition operation, the first sub-configuration code is obtained.

[0121] In some optional implementations, when the type of the first register is a second preset type, the target code template includes a register name field, a major bit order field, and a minor bit order field. The configuration information of the first register includes the name of the first register, the first bit order information, and the first identity information. The configuration information of the first register includes the name of the first register, the second bit order information, and the second identity information. Module 620 is generated and is specifically used for: Add the name of the first register to the register name field; If it is determined that the first identity information is used to indicate that the first register is the master register, the first bit sequence information is added to the master bit sequence field; And, if it is determined that the second identity information is used to indicate that the second register is a slave register, the second bit sequence information is added to the slave bit sequence field; After completing the addition operation, the first sub-configuration code is obtained.

[0122] In some optional implementations, when the type of the first register is a third preset type, the target code template includes a register name field and a bit order field, and the configuration information of the first register includes the name and major bit order information of the first register; Module 620 is generated and is specifically used for: Add the name of the first register to the register name field; Add the ordinal information to the ordinal field; After completing the addition operation, the first sub-configuration code is obtained.

[0123] For a description of the features in the embodiment corresponding to the code generation device, please refer to the relevant description in the embodiment corresponding to the code generation method, which will not be repeated here.

[0124] Embodiments of this application also provide an electronic device, such as... Figure 7 As shown, it includes a memory 10 and a processor 20. The memory 10 stores a computer program, and the processor 20 is configured to run the computer program to perform the steps in any of the code generation method embodiments described above.

[0125] Embodiments of this application also provide a computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps in any of the code generation method embodiments described above at runtime.

[0126] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard disk, magnetic disk, or optical disk.

[0127] Embodiments of this application also provide a computer program product, which includes a computer program that, when executed by a processor, implements the steps in any of the code generation method embodiments described above.

[0128] Embodiments of this application also provide another computer program product, including a non-volatile computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps in any of the code generation method embodiments described above.

[0129] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0130] The foregoing has provided a detailed description of the code generation method, apparatus, electronic device, storage medium, and program product provided in this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are merely for the purpose of helping to understand the method and core ideas of this application. It should be noted that those skilled in the art can make various improvements and modifications to this application without departing from its principles, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. A code generation method, characterized in that, include: Obtain the bit sequence signal description file corresponding to the electronic fuse and the configuration file of the target bit sequence signal; Based on the bit sequence signal description file and the configuration file, generate configuration information for at least one register; Based on the configuration information of the first register, the type of the first register is determined, wherein the first register is any one of at least one of the registers; Based on the type of the first register, a target code template matching the type of the first register is selected from at least one pre-built code template; When the type of the first register is determined to be a first preset type, a first sub-configuration code is generated according to the configuration information of the first register, the configuration file, and the target code template. The first preset type is used to indicate that the bit sequence signal corresponding to the first register is the target bit sequence signal, and the first register does not have a corresponding backup register. The first sub-configuration code is used to be burned into the electronic fuse so that the electronic fuse can perform register configuration operations according to the first sub-configuration code.

2. The code generation method according to claim 1, characterized in that, The method further includes: When it is determined that the type of the first register is the second preset type, the configuration information of the second register that has a master-slave relationship with the first register is determined from the configuration information of at least one of the registers according to the configuration information of the first register. The second preset type is used to indicate that the first register has a corresponding backup register, and the bit sequence signal corresponding to the first register is not the target bit sequence signal. Based on the configuration information of the first register, the configuration information of the second register, and the target code template, the first sub-configuration code is generated.

3. The code generation method according to claim 2, characterized in that, The method further includes: If the type of the first register is determined to be a third preset type, the first sub-configuration code is generated according to the configuration information of the first register and the target code template, wherein the third preset type is used to indicate that the bit sequence signal corresponding to the first register is not the target bit sequence signal, and the first register does not have a corresponding backup register.

4. The code generation method according to claim 3, characterized in that, The configuration information of the first register includes a backup attribute field and a target bit sequence signal indication field; determining the type of the first register based on its configuration information includes: If it is determined that the target bit sequence signal indication field is used to indicate that the bit sequence signal corresponding to the first register is the target bit sequence signal, then the type of the first register is determined to be the first preset type; Alternatively, if it is determined that the backup attribute field is used to indicate that the first register has a corresponding backup register, the type of the first register is determined to be the second preset type; Alternatively, if the target bit sequence signal indication field is used to indicate that the bit sequence signal corresponding to the first register is not the target bit sequence signal, and the backup attribute field is used to indicate that the first register does not have a corresponding backup register, then the type of the first register is determined to be the third preset type.

5. The code generation method according to any one of claims 1 to 4, characterized in that, When the type of the first register is the first preset type, the target code template includes a register name field, a condition signal field, a selection signal field, and a bit order field. The configuration file includes the name of the first register, the identification information of the condition signal, and the identification information of the selection signal. The configuration information of the first register includes the name and bit order information of the first register. When the type of the first register is determined to be a first preset type, the first sub-configuration code is generated based on the configuration information of the first register, the configuration file, and the target code template: Add the name of the first register to the register name field; Add the identification information of the condition signal to the condition signal field; Add the identification information of the selection signal to the selection signal field; Add the bit order information to the bit order field; After completing the addition operation, the first sub-configuration code is obtained.

6. The code generation method according to any one of claims 2 to 4, characterized in that, When the type of the first register is the second preset type, the target code template includes a register name field, a major bit order field, and a minor bit order field. The configuration information of the first register includes the name of the first register, the first bit order information, and the first identity information. The configuration information of the first register includes the name of the first register, the second bit order information, and the second identity information. The step of generating the first sub-configuration code based on the configuration information of the first register, the configuration information of the second register, and the target code template includes: Add the name of the first register to the register name field; If it is determined that the first identity information is used to indicate that the first register is a master register, the first bit sequence information is added to the master bit sequence field; And, if it is determined that the second identity information is used to indicate that the second register is a slave register, the second bit sequence information is added to the slave bit sequence field; After completing the addition operation, the first sub-configuration code is obtained.

7. The code generation method according to claim 3 or 4, characterized in that, When the type of the first register is the third preset type, the target code template includes a register name field and a bit order field, and the configuration information of the first register includes the name and major bit order information of the first register; The step of generating the first sub-configuration code based on the configuration information of the first register, the configuration information of the second register, and the target code template includes: Add the name of the first register to the register name field; Add the bit order information to the bit order field; After completing the addition operation, the first sub-configuration code is obtained.

8. A code generation device, characterized in that, include: The acquisition module is used to acquire the position sequence signal description file corresponding to the electronic fuse and the configuration file of the target position sequence signal; A generation module is used to generate configuration information for at least one register based on the bit sequence signal description file and the configuration file; The determining module is configured to determine the type of the first register based on the configuration information of the first register, wherein the first register is any one of at least one of the registers; A selection module is used to select a target code template that matches the type of the first register from at least one pre-built code template, based on the type of the first register. The generation module is further configured to, when the type of the first register is determined to be a first preset type, generate a first sub-configuration code based on the configuration information of the first register, the configuration file, and the target code template, wherein the first preset type is used to indicate that the bit sequence signal corresponding to the first register is the target bit sequence signal, and the first register does not have a corresponding backup register, and the first sub-configuration code is used to be burned into the electronic fuse so that the electronic fuse performs a register configuration operation based on the first sub-configuration code.

9. An electronic device, characterized in that, include: Memory, used to store computer programs; A processor for implementing the steps of the code generation method as described in any one of claims 1 to 7 when executing the computer program.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, wherein the computer program, when executed by a processor, implements the steps of the code generation method as described in any one of claims 1 to 7.

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