Neuromorphic hardware congestion-aware spiking neural network mapping method and system

Abstract

This invention discloses a spiking neural network (SNN) mapping method and system for congestion awareness on neuromorphic hardware, belonging to the field of neuromorphic computing technology. The method includes: mapping neurons in a spiking neural network model to physical cores of neuromorphic hardware to form an initial mapping scheme; iterating through congestion hotspots and updating the mapping scheme in each iteration to alleviate network communication congestion on the hardware; calculating the distribution of congestion hotspot regions composed of physical cores under the current mapping scheme based on pulse flow evaluation between physical core pairs; for each congestion hotspot region, selecting multiple physical cores with high pulse flow contribution as hub cores to be swapped; determining the optimal swap candidate core for each hub core based on a heuristic swapping decision mechanism; and swapping hub cores with the optimal swap candidate cores to update the mapping scheme. This promotes the efficient deployment of SNNs on neuromorphic hardware and provides key technical support for high-energy-efficiency, low-latency neuromorphic computing.

Description

Technical Field

[0001] This invention belongs to the field of neuromorphic computing technology, specifically relating to a neuromorphic hardware congestion-aware spiking neural network mapping method and system. Background Technology

[0002] Spiking Neural Networks (SNNs) are a novel neural network computing paradigm inspired by the operational mechanisms of biological nervous systems. Unlike traditional Artificial Neural Networks (ANNs), which use continuous-valued activation functions for information transmission, SNNs encode and transmit information through discrete spike events, more faithfully simulating the communication methods between biological neurons. This spike-based information processing mechanism endows SNNs with two significant advantages: first, temporal encoding capability, meaning that information is not only contained in whether a spike is fired, but also encoded in the precise timing of the spike and the temporal pattern of the spike sequence, making it naturally suitable for processing data with temporal dynamic characteristics; second, sparse activation characteristics, meaning that at any given moment, only a small number of neurons in the network are active and firing spikes, while most neurons remain silent. This sparsity directly brings significant energy efficiency advantages. With these unique characteristics, SNNs have shown broad application prospects in many cutting-edge fields such as neuromorphic computing, brain-like artificial intelligence systems, edge intelligent devices, and low-power real-time inference, and are widely regarded as one of the important development directions of next-generation intelligent computing.

[0003] The vast majority of these platforms employ a multi-core design with a Network-on-Chip (NoC) architecture. In this architecture, a large population of neurons is systematically divided and distributed across different neuromorphic cores, each core responsible for simulating the behavior of a certain number of neurons. Spurious data transmission between neurons is achieved through routers and communication links within the network-on-chip, with spurious data being routed and forwarded between cores in the form of data packets. This distributed computing and communication architecture provides the hardware foundation for the efficient execution of large-scale SNNs.

[0004] Deploying SNN models to neuromorphic hardware platforms is not a straightforward process; it typically involves two key steps: partitioning and mapping. In the partitioning phase, all neurons in the SNN are grouped into logical cores according to specific strategies and constraints. The number of neurons in each logical core must meet the resource capacity limitations of the physical cores, while the partitioning strategy must also consider communication overhead and computational load balancing between cores. In the mapping phase, the partitioned logical cores are assigned one by one to the actual physical cores on the neuromorphic hardware platform, determining the specific physical location of each logical core in the on-chip network topology. The quality of the mapping scheme directly determines the physical distance of pulse communication between cores, transmission latency, and network resource utilization efficiency, thus having a crucial impact on the final execution performance of the SNN on hardware. Several SNN mapping methods have been proposed to address this issue, with representative algorithms including SpiNeMap, DFSynthesizer, and FD. These methods share a similar core optimization approach: by analyzing the communication traffic patterns between logical cores, they place core pairs with high communication traffic as close as possible to each other in the physical topology, thereby shortening the average hop count of pulse transmission and achieving the optimization goals of reducing communication energy consumption and transmission latency. However, in pursuing the minimization of local communication distance, these methods generally overlook a key issue: when a large number of high-traffic cores are concentrated in a local area of ​​the physical topology, although the physical distance between core pairs is shortened, the routers and communication links in that area will be subjected to extremely high data transmission pressure, easily forming local communication hotspots and severe communication congestion. This leads to a significant increase in packet queuing time and a significant decrease in network throughput, ultimately causing the overall system performance to decline rather than improve.

[0005] Examining the limitations of existing mapping methods from the perspective of optimization objectives reveals that current mainstream methods primarily focus on two aspects: minimizing total communication energy consumption and minimizing the average or total number of hops. While these metrics can reflect communication efficiency to some extent, they fail to fully capture the impact of network resource competition and congestion on actual performance. In fact, there is a complex negative correlation between network congestion and communication energy consumption—the practice of tightly clustering high-traffic cores to reduce energy consumption often exacerbates congestion in local areas. More importantly, the impact of network congestion on overall communication latency is often far greater than the propagation delay caused by the number of hops themselves, because the queuing delay and retransmission overhead caused by congestion can be several orders of magnitude higher than the increased latency from traversing a few more hops. However, this crucial factor, which has a decisive impact on system performance, has not received the necessary priority and effective optimization in existing mapping methods. While dynamic routing algorithms (such as adaptive routing and load balancing routing) widely used in on-chip networks can dynamically adjust the transmission paths of data packets based on network conditions at runtime, thus distributing traffic and alleviating local congestion to some extent, this passive congestion response strategy has significant limitations: They essentially remedial adjustments based on an already established unreasonable traffic distribution, failing to fundamentally change the traffic distribution pattern determined by the mapping scheme; furthermore, dynamic routing fails to effectively discover and utilize surplus communication path resources in low-load areas of the network, leading to uneven overall network resource utilization. When facing highly uneven and bursty pulse communication patterns generated by actual SNN workloads, the congestion mitigation effect achieved solely by dynamic routing algorithms is very limited, making it difficult to fundamentally solve the congestion problem caused by inappropriate mapping schemes. Therefore, there is an urgent need for a novel SNN mapping method that considers network congestion as a core optimization objective during the mapping phase. By proactively avoiding congestion risks and balancing communication load distribution at the spatial layout level, this method can fundamentally improve the deployment quality and operational performance of SNN models on neuromorphic hardware platforms. Summary of the Invention

[0006] In view of the above, the purpose of this invention is to provide a neuromorphic hardware congestion-aware spiking neural network mapping method and system, which can effectively reduce on-chip network communication congestion, optimize overall time step delay, and avoid a significant increase in energy consumption.

[0007] To achieve the above-mentioned objectives, an embodiment provides a neuromorphic hardware congestion-aware spiking neural network mapping method, comprising the following steps: The neurons in the spiking neural network model are mapped to the physical core of the neuromorphic hardware to form an initial mapping scheme; Each iteration identifies congestion hotspots and updates the mapping scheme to alleviate network communication congestion on the hardware. Specifically, this includes: calculating the distribution of congestion hotspot regions composed of physical cores under the current mapping scheme based on pulse traffic assessment between physical core pairs; for each congestion hotspot region, selecting multiple physical cores with high pulse traffic contribution as hub cores to be swapped; determining the optimal swap candidate core for each hub core based on a heuristic swapping decision mechanism; and updating the mapping scheme by swapping hub cores with the optimal swap candidate cores.

[0008] Preferably, the initial mapping scheme is generated using a constructive method, including at least one of sequential mapping, zigzag mapping, and Hilbert space-filling curve mapping.

[0009] Preferably, the distribution of congestion hotspot regions composed of physical cores under the current mapping scheme is calculated based on the pulse flow assessment between physical core pairs, including: Traverse all physical core pairs in the current mapping scheme, simulate routing paths, and accumulate the number of pulses passed by each physical core on each routing path to obtain the pulse traffic distribution; Based on the pulse flow distribution, the pulse with the largest flow was identified. Each physical core is used as a congestion hotspot region to obtain the distribution of congestion hotspot regions.

[0010] Preferably, for each congestion hotspot area, multiple physical cores with high pulse traffic contribution are selected as hub cores to be swapped, including: Calculate the traffic contribution of all physical cores to the congested hotspot: if the routing path of a physical core pair passes through the congested hotspot, the contribution of the relevant physical cores is accumulated to the corresponding number of pulses. Filter out the top contributors to traffic Each physical core serves as a hub core to be exchanged.

[0011] Preferably, an optimal candidate core for swapping is determined for each hub core based on a heuristic swapping decision mechanism, including: The physical core with the lowest overall score is selected as the optimal candidate core for swapping. The overall score includes traffic score and hop count score. Traffic scoring is used to assess changes in pulse traffic through congestion hotspots after a swap. In specific calculations, only pulse traffic related to the hub's core location that still passes through congestion hotspots after the swap needs to be counted. Hop count score is used to assess the impact of switching on total communication distance, specifically by calculating the change in the sum of Manhattan distances of all connections related to the hub core and physical core before and after the switching.

[0012] Preferably, the method further includes: defining a circular swap window centered on the hub core, and searching only the physical core with the lowest comprehensive score among the physical cores within the window as the optimal swap candidate core.

[0013] Preferably, when updating the mapping scheme, an incremental update strategy is adopted, and only the path traffic affected by the exchange is recalculated.

[0014] Preferably, the method further includes: if the current iteration reaches the maximum number of iterations or the mapping scheme converges, outputting the optimal mapping scheme, wherein the convergence of the mapping scheme is determined based on the key performance indicators continuously tracked during the mapping process, wherein the key performance indicators include network peak congestion and total hop cost.

[0015] To achieve the above-mentioned objectives, an embodiment also provides a neuromorphic hardware congestion-aware spiking neural network mapping system, comprising: The initial mapping module is used to map neurons in the spiking neural network model to the physical core of the neuromorphic hardware, forming an initial mapping scheme. The mapping iteration optimization module is used to find congestion hotspots and update the mapping scheme in each iteration to alleviate network communication congestion on the hardware. Specifically, it includes: calculating the distribution of congestion hotspot areas composed of physical cores under the current mapping scheme based on pulse traffic evaluation between physical core pairs; for each congestion hotspot area, selecting multiple physical cores with high pulse traffic contribution as hub cores to be switched; determining the optimal switching candidate core for each hub core based on a heuristic switching decision mechanism; and updating the mapping scheme by switching hub cores with the optimal switching candidate cores.

[0016] To achieve the above-mentioned objectives, an embodiment also provides a computing device, including a memory and one or more processors, wherein the memory stores executable code, and when the one or more processors execute the executable code, it is used to implement the above-mentioned neuromorphic hardware congestion awareness spiking neural network mapping method.

[0017] To achieve the above-mentioned objectives, the embodiments also provide a computer-readable storage medium storing a program that, when executed by a processor, implements the above-described neuromorphic hardware congestion perception spiking neural network mapping method.

[0018] Compared with the prior art, the beneficial effects of the present invention include at least the following: This invention is the first to take network congestion as the core optimization objective. It effectively alleviates local congestion hotspots and communication congestion through iterative switching strategies. While optimizing congestion, it ensures that energy consumption does not increase significantly through a heuristic switching decision mechanism, achieving a good balance between congestion mitigation and energy consumption control. This provides a reliable technical solution for the efficient deployment of SNNs on neuromorphic hardware. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a flowchart of the neuromorphic hardware congestion awareness spiking neural network mapping method provided in the embodiment; Figure 2 This is a schematic diagram of the mapping process from a spiking neural network to neuromorphic hardware provided in the embodiment; Figure 3 This is a schematic diagram illustrating the overall workflow of finding and mitigating congestion hotspots in the network and updating the mapping scheme in each iteration, as provided in the embodiment. Figure 4 This is a schematic diagram of traffic fraction calculation provided in the embodiment. The gray area represents the hub core to be exchanged. The core scope involved in traffic scores; Figure 5 This is a comparison chart of normalized congestion and overall delay for different mapping methods provided in the embodiments, with the normalization benchmark being the Plain mapping method; Figure 6 This is a comparison chart of normalized energy consumption for different mapping methods provided in the embodiments; Figure 7 This is a comparison chart of the execution times of different iterative optimization mapping methods provided in the embodiments, where the Y-axis uses a logarithmic scale; Figure 8 This is a performance comparison chart of various mapping methods at different scales provided in the embodiments, including normalized congestion, latency, energy consumption, and execution time; Figure 9 , Figure 10 , Figure 11 , Figure 12 The examples provided are respectively top- top- A schematic diagram illustrating the impact of the switching window r and the balance coefficient α on performance and efficiency, including normalized congestion, energy consumption, and execution time; Figure 13 This is a normalized congestion comparison chart of various mapping methods under different partitioning strategies provided in the embodiments; Figure 14 Here is a schematic diagram illustrating the impact of variable inputs on mapping performance provided in the embodiment: (a) the coefficient of variation of the number of pulses under different inputs; (b) the normalized congestion heatmap under different inputs. Detailed Implementation

[0021] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and do not limit the scope of protection of this invention.

[0022] This invention provides a spiking neural network (SNN) mapping scheme that gradually reduces network congestion through iterative swapping operations, thereby optimizing the mapping performance of SNNs on network-on-chip (NoC) based neuromorphic hardware. The core idea is to identify the most congested hotspots in each iteration through statistical analysis, and then swap the cores generating the most communication traffic from these hotspots to alternative locations determined through a heuristic swapping decision process, thus alleviating congestion in these hotspots. This invention demonstrates superior efficiency compared to other iterative optimization methods and exhibits good scalability across different scales. This method promotes the efficient deployment of SNNs on neuromorphic hardware, providing key technical support for energy-efficient, low-latency neuromorphic computing.

[0023] This embodiment provides a neuromorphic hardware congestion-aware spiking neural network mapping method, using an iterative optimization framework based on heuristic search, specifically designed to map LIF neuron-based SNN tasks onto neuromorphic chips. For example... Figure 1 As shown, it includes the following steps: S1 maps neurons in the spiking neural network model to the physical core of the neuromorphic hardware, forming an initial mapping scheme.

[0024] In this embodiment, the spiking neural network model (i.e., the SNN model) is defined as: ,in Let N represent the set of all neurons, and let N represent the number of neurons. The matrix represents the synaptic connections between neurons. In Indicates the existence of from the first i Presynaptic neurons To the j Postsynaptic neuron The connection. The running cycle of the SNN model is... Each time step, all pulse data are used It means that in S Indicates at time step from Send to The pulse.

[0025] Before deploying the SNN model to neuromorphic hardware, the SNN is first divided into several clusters. , Use a 0-1 matrix to represent the number of clusters. This represents the partitioning result. Since each neuron must and can only be assigned to one cluster, and the number of neurons in each cluster is limited by hardware resources (…), this is crucial. That is, it must not exceed the physical core capacity of the hardware and must meet the following constraints:

[0026] Among them, matrix P In Indicates the first i The 1st neuron was assigned to the 1st... k Cluster .

[0027] Total number of pulses between neuron clusters The calculation is as follows:

[0028] in, This represents element-wise multiplication. In Indicates at time step From the k Cluster To the l Cluster The number of pulses.

[0029] This embodiment employs a NoC-based multi-core neuromorphic hardware model, which includes a set of physical cores for computational processing. And a NoC with a 2D Mesh structure. The mapping process aims to establish a one-to-one mapping from logical clusters to physical cores, as follows: Figure 2 As shown, each cluster It will be mapped and placed on a core of the neuromorphic chip. A 0-1 matrix will be used. To represent a mapping scheme, the following must be satisfied:

[0030]

[0031] Among them, matrix In Indicates the first k Cluster Mapped to the l One physical core After mapping is complete, the number of pulses between physical cores It can be obtained through the following formula:

[0032] In this embodiment, to improve efficiency, an initial mapping scheme from the spiking neural network model to the neuromorphic hardware model is first generated. Specifically, constructive methods that preserve spatial locality, such as sequential mapping, Zig-Zag mapping, or Hilbert curve mapping, can be used to generate the initial mapping scheme. The time complexity of these methods is typically O(n log n). .

[0033] Step S1, located in the initialization phase of the method, is responsible for rapidly generating the baseline mapping scheme. Upon receiving the partitioned SNN cluster data, the logical clusters are quickly assigned to the physical cores. This lays a solid topological foundation for subsequent iterative optimization and ensures that the algorithm starts with low initial communication overhead.

[0034] S2, in each iteration, identifies congestion hotspots and updates the mapping scheme to alleviate network communication congestion on the hardware. For example... Figure 3 As shown, the specific steps include: S21, Calculate the distribution of congestion hotspot regions composed of physical cores under the current mapping scheme based on Spike Flow Evaluation between physical core pairs.

[0035] In the initial iteration, the initial mapping scheme is used as the current mapping scheme. In subsequent iterations, the mapping scheme updated in the previous iteration is used as the current mapping scheme. Specifically, all physical core pairs in the current mapping scheme are traversed. Simulate routing paths (such as XY routes) and accumulate the sum of each physical core on each routing path. The number of pulses passed is used to obtain the pulse flow distribution. :

[0036] in, This indicates the total number of pulses from the source address (source) to the destination address (dest). This represents all paths passing through physical core k. Based on pulse flow distribution. Identify the pulse with the largest flow rate. Each physical core is designated as a congestion hotspot region, denoted as a set. This step S21 aims to locate traffic congestion points in the current network.

[0037] Pulse flow assessment is the foundation of congestion awareness in this invention. By simulating hardware routing mechanisms (such as XY routing), path tracing is performed on the entire network's pulse data flow under the current mapping. By traversing the communication requirements between all physical core pairs, the total pulse flow carried on each physical core and routing node is accurately calculated, generating a full hardware chip pulse flow distribution map. This distribution map is the direct basis for identifying network bottlenecks.

[0038] Based on the traffic assessment results, the congested areas in the network are accurately located. Statistical analysis of the pulse traffic distribution map identifies the areas with the highest traffic load. Each physical core is a congestion hotspot region, representing the communication bottleneck in the current mapping scheme and directly determining the system's maximum latency. The accuracy of hotspot identification directly impacts the targeted nature of subsequent optimizations.

[0039] S22: For each congested hotspot area, select multiple physical cores with high pulse traffic contribution as hub cores to be swapped.

[0040] In the embodiment, for a given congestion hotspot area We need to identify which physical core contributed the most to passing through this congested hotspot area. The pulse flow. Specific statistics on all physical cores and their connections to congested hotspot areas. Traffic contribution: If the routing path of the physical core pair passes through the congested hotspot area. The cumulative contribution of the relevant physical cores corresponds to the number of pulses. In the specific implementation, a statistical metric, trace, is defined, where trace[k] represents the pulse originating from or destined for a physical core. And passing through congestion hotspots The number of pulses.

[0041]

[0042] in, Indicates that it is composed of physical core To the physical core The path, Indicates that it is composed of physical core To the physical core The path, As an indicator function, when congested hotspot areas When traversing the path, the value is 1. Representing the physical core To congestion hotspots Congestion hotspots To the physical core The number of pulses.

[0043] Using the trace distribution as the traffic contribution, select the top traces with the largest traffic contribution. Each physical core is designated as a pivot core (Pivot) to be exchanged, denoted as a set. These cores contribute the majority of traffic to hotspot areas. To accelerate computation, routing simulation is unnecessary if the congested hotspot is not within the bounding box formed by the physical core pairs. Selected hub cores are the primary cause of congestion and are the focus of the system's relocation adjustments.

[0044] S23, based on a heuristic exchange decision-making mechanism, determines the optimal exchange candidate core for each hub core.

[0045] Heuristic Swapping Decision, in an effort to alleviate hotspot congestion, attempts to shift the hub core... Other physical cores An exchange is performed. To quantify the effectiveness of the exchange, this invention proposes a comprehensive scoring function. This rating is based on traffic rating. (Flow Score) and jump count score (Hop Score) is composed of.

[0046] Traffic rating This is used to assess changes in pulse traffic through congestion hotspots after a swap. The calculation only needs to count pulse traffic related to the hub core location that still passes through the congestion hotspot after the swap. The specific calculation is based on the hub core. and congestion hotspots The relative position, such as Figure 4 As shown, the traffic is divided into two parts: transmitted traffic and received traffic, and then accumulated in gray areas. For example, if... The ordinate is less than Then the sent traffic will only be counted if the destination core is located in a specific area. The pulse of ) . Considering the limitations of single congestion hotspot optimization, this embodiment adopts a weighted traffic score, comprehensively considering the previous One congestion hotspot area:

[0047] Among them, weight With the k Congestion hotspots The pulse flow rate is directly proportional to the pulse flow rate.

[0048] Jump count score Used to assess the impact of switching on total communication distance (i.e., energy consumption). Calculates the connection between the hub core and the switch before and after switching. and physical core The sum of Manhattan distances of all related connections and Change As a score based on jump count .

[0049]

[0050] This calculation only involves connections related to the swap pairs, and has a complexity of O(n log n). Since congestion and energy consumption are negatively correlated, a comprehensive scoring system is needed to control energy consumption while reducing congestion. Defined as:

[0051] in This indicates a normalization operation. These are parameters that adjust the weights, and they typically take values ​​of... To balance computational efficiency, this embodiment defines a swap window centered on the hub core, with a radius of [missing information]. Only the physical core with the lowest score (optimal) within the window is searched as the optimal swap candidate core.

[0052] The heuristic exchange decision-making mechanism, guided by a heuristic algorithm, searches for the optimal exchange partner within an exchange window surrounding the hub core. It utilizes a weighted comprehensive scoring function. The benefits of each potential exchange are dynamically evaluated by adjusting the weights. It can find the best balance between alleviating congestion and controlling energy consumption, and output the candidate switching core with the lowest score (i.e. the greatest benefit).

[0053] S24, exchange the hub core and the optimal exchange candidate core to update the mapping scheme.

[0054] In this embodiment, the candidate core with the best comprehensive score is selected for exchange with the hub core to generate a new mapping scheme. Then, step S2 is repeated until the maximum number of iterations is reached. If the congestion level no longer decreases significantly (convergence), output the final mapping scheme. .

[0055] The mapping update is primarily responsible for executing changes to physical locations and maintaining system state. Once the optimal swap pair is determined, the mapping table from logical clusters to physical cores is updated. Crucially, to accelerate the next iteration, an incremental update strategy is used, recalculating only the path traffic affected by the swap, rather than rescanning the entire network. This efficient update mechanism enables the system to achieve rapid iteration on large-scale SNN models.

[0056] The method also includes continuously tracking key performance indicators (KPIs) during the mapping process. These KPIs determine whether the optimization has converged and whether to terminate the iteration. Among the various monitored indicators, two are particularly important for evaluating system performance: Peak Congestion, which is the highest traffic value across all cores. Monitoring the downward trend of this Peak Congestion indicator directly reflects the effectiveness of the method in eliminating hotspots.

[0057] Total Hop Cost: This reflects the system's total communication energy consumption. The performance monitor compares the real-time calculated congestion level with the results of the previous iteration. Once it detects that the congestion level no longer decreases significantly or reaches a preset iteration threshold, it triggers the system to output the final mapping scheme. Furthermore, it records the time overhead of the optimization process to ensure the efficiency of the mapping process itself.

[0058] This invention is the first to take network congestion as the core optimization objective. It effectively alleviates local hotspots and communication congestion through iterative switching strategies. While optimizing congestion, it ensures that energy consumption does not increase significantly through balancing coefficients and scoring functions, achieving a good balance between congestion mitigation and energy consumption control. This provides a reliable technical solution for the efficient deployment of SNNs on neuromorphic hardware.

[0059] To verify the effectiveness of the present invention, 14 representative SNN workloads were selected, covering Spiking CNNs (such as VGG19, ResNet-19) for image classification and Spiking Transformers (such as Spikformer, SpikingBERT) for natural language processing and image recognition. The parameters of the experimental workloads are shown in Table 1.

[0060] Table 1

[0061] The baseline methods for comparison include: Plain (sequential mapping), PSO (particle swarm optimization), DFSynthesizer (based on simulated annealing, abbreviated as DFSyn), HSC (Hilbert curve mapping), and FD (force-oriented mapping).

[0062] The hardware platform simulated a to Large-scale Mesh NoCs employ an XY routing mechanism.

[0063] Figure 5 The charts show a statistical comparison of congestion and end-to-end latency for each mapping method under 14 SNN loads. Experimental results demonstrate that the proposed method excels in reducing network congestion. Compared to the Plain baseline, the proposed method reduces network congestion by an average of 56.9%; compared to the state-of-the-art FD method, it reduces it by an average of 43.2%. This congestion reduction directly translates to shorter execution time. Since SNNs are time-step driven, network congestion causes pulse arrival delays. By eliminating congestion hotspots, the proposed method reduces the overall inference latency of the SNN by 41.5% compared to the Plain method and by 38.0% compared to the FD method.

[0064] Figure 6 The graph shows the energy consumption comparison of various mapping methods under 14 SNN loads. Although the primary goal of the method in this invention is to reduce congestion, the introduction of hop count scoring in the switching decision allows the system to effectively control the increase in line length while optimizing congestion. In large models such as Spikformer, the energy consumption of the method in this invention is only slightly higher than that of pure energy-efficient optimization algorithms, but it provides much lower latency, achieving the best trade-off between energy efficiency and performance.

[0065] Figure 7 A statistical comparison of the execution time of each iterative optimization mapping method under 14 SNN loads is presented. The method of this invention exhibits extremely high running efficiency. Thanks to hotspot identification and incremental update strategies, this method avoids blindly searching for all physical core pairs across the entire network. On large-scale grids, the execution time of the method of this invention grows nearly linearly, much faster than the metaheuristic-based PSO and DFSynthesizer (DFSyn) methods (the latter growing exponentially with scale). This demonstrates that the method of this invention has good scalability and is suitable for compilation and mapping tasks of large-scale neuromorphic chips.

[0066] Figure 8 Statistical graphs comparing congestion, latency, energy consumption, and execution time for each mapping method under different SNN workloads. These SNN workloads are mapped to various grid sizes, specifically including... , , , and To obtain the congestion and execution time of different SNN mapping methods under these conditions. Figure 8The left side of the diagram shows the congestion results after normalization relative to the Plain method at different scales. The results show that the method of this invention achieves greater performance improvements in congestion and latency metrics as the scale increases. Although the energy consumption results are not optimal, this is mainly due to the selection of larger weight parameters. This allows for a greater focus on optimizing congestion rather than energy consumption. Furthermore, Figure 8 The right side of the graph displays the time complexity of various methods in a double logarithmic coordinate system (both axes are logarithmic). Execution times are normalized based on the time at the minimum scale. The results show that the method of this invention exhibits near-linear time complexity, with a lower growth rate than other iterative mapping methods.

[0067] Figure 9 To provide the method of the present invention with different parameters top- The diagram illustrates the impact of the settings on performance and efficiency, including normalized congestion, energy consumption, and execution time. Experimental results show that... Increasing the value from 1 to 8 has a negligible impact on network congestion and energy consumption, producing essentially the same optimization results. The main reason for this phenomenon is the highly concentrated distribution of hotspots in the network, meaning that only a very small number of hotspots need to be considered when calculating the scoring function. However, given that execution time increases with... The value increases linearly with increasing efficiency. Considering both computational efficiency and performance, this embodiment determines... These are the optimal configuration parameters.

[0068] Figure 10 To provide the method of the present invention with different parameters top- The diagram illustrates the impact of settings on performance and efficiency, including normalized congestion, energy consumption, and execution time. Experimental results show that larger... A larger value can lead to a faster convergence rate. This is because, during a single iteration, a larger value... Allows multiple swap attempts for the same congested hotspot. (Compared to smaller...) Compared to other methods, this strategy can reuse more intermediate computation results within a single iteration cycle, thus optimizing execution speed to some extent. Therefore, the execution time exhibits a sublinear growth characteristic. Considering the trade-off between convergence speed and computational cost, this embodiment determines... This is the best choice.

[0069] Figure 11 The method of the present invention is used in different parameter time windows The diagram illustrates the impact of settings on performance and efficiency, including normalized congestion, energy consumption, and execution time. Experimental results show that as... As the value increases, network congestion tends to decrease, while system energy consumption tends to increase. This phenomenon occurs because a larger value... The value allows the method of this invention to search for potential candidate cores for swapping over a wider spatial range, thus significantly increasing the chance of finding a globally better solution that can effectively reduce traffic scores (and thus alleviate congestion). However, on the other hand, the expanded search range also increases the possibility of hub cores swapping with distant cores. This long-distance physical location swapping may disrupt the original spatial locality, causing the communication distance between originally physically adjacent core pairs to lengthen, thereby increasing overall communication energy consumption. Furthermore, in terms of computational efficiency, the increased... The value introduces a near-linear performance overhead (i.e., execution time increases with time). (Linear increase). Considering the trade-offs between congestion optimization effect, energy consumption control cost, and computational efficiency, this embodiment determines... The optimal parameter selection.

[0070] Figure 12 The method of this invention has different parameter weighting coefficients. The diagram illustrates the impact of the settings on performance and efficiency, including normalized congestion, energy consumption, and execution time. Weighting parameters are added. The value indicates a greater emphasis on traffic scoring during the optimization process, which aims to alleviate network congestion. Therefore, with With the increase in congestion, the normalized congestion level shows a significant downward trend in the vast majority of SNN workloads. In contrast, larger congestion levels... The value weakens the influence of hop count scoring. The hop count scoring mechanism prioritizes placing clusters with communication relationships in physically proximate locations to minimize data movement. Because the system's priority for minimizing hop count scores is reduced, normalized energy consumption shows an overall upward trend. Based on the above experimental observations of congestion and energy consumption changes, this embodiment determines... The optimal range of parameter selection.

[0071] Figure 13This is a normalized congestion comparison diagram for various mapping methods under different partitioning strategies. To comprehensively evaluate the robustness of the method of this invention, this embodiment extends the experimental analysis to include two distinct SNN partitioning strategies as supplementary verification to the basic partitioning method used in the main evaluation. These two strategies are: a communication optimization-based partitioning strategy (SpiNeCluster), which primarily optimizes for minimizing the total communication volume; and a computational load-based partitioning strategy (Dfsynthesizer), which focuses on evenly balancing the computational load across all computational cores. These partitioning strategies are applicable to different application scenarios. This embodiment aims to verify that the method of this invention can adapt to these different preconditions, thereby demonstrating its effective handling of a wide range of SNN applications. The experiment selected the DFsyn and HSC methods, which performed well in previous tests, as benchmarks for comparison. Experimental results show that regardless of the partitioning method used, the method of this invention consistently outperforms other comparative methods in terms of network congestion, a key indicator. This result strongly demonstrates that the method of this invention has high robustness and maintains its superior mapping performance regardless of the underlying partitioning strategy.

[0072] Figure 14This diagram illustrates the impact of variable inputs on mapping performance. This embodiment also delves into the statistical characteristics of SNN spiking activity under different input conditions to verify the robustness and versatility of the method in the face of input variations. Although the spiking activity of a single neuron in an SNN varies significantly with different input data, from a broader system perspective, the network as a whole exhibits inherent stability. For example, existing research shows that the spiking pattern of a general SNN is stable at the network layer level. To quantify and verify this characteristic, this embodiment measures the coefficient of variation (CV) of the number of spiking events in a single neuron and the entire computational core in response to various inputs (Spikformer, SDT, SpikingBERT, SpikeBERT). Experiments show that at the neuron level, the average CV value is as high as 68.0%. This high value confirms the significant variability and sensitivity of a single neuron's response to different inputs. In stark contrast to the neuron level, at the core level, the CV value drops sharply to 2.7%. This data strongly demonstrates that although the activity of individual neurons within a core fluctuates, the total impulse activity aggregated in each core exhibits high stability. Furthermore, this embodiment further verifies the cross-input adaptability of the mapping scheme. Experimental results show that when the mapping scheme optimized based on a single input sample is tested on other unseen input data, its congestion improvement relative to the baseline method remains highly consistent. The above experimental results reveal a significant advantage of this invention: sampling efficiency. This indicates that statistical information from only a very small number of input samples is sufficient to effectively optimize the entire SNN workload. This characteristic allows the method of this invention to avoid the need for detailed full analysis of massive inputs in practical deployments, thereby significantly reducing the computational overhead of the compilation and mapping process while ensuring optimization effectiveness.

[0073] The embodiment also provides a neuromorphic hardware congestion-aware spiking neural network mapping system, including an initial mapping module and a mapping iteration optimization module. The initial mapping module is used to construct a spiking neural network model and a neuromorphic hardware model. After dividing the spiking neural network into multiple clusters according to hardware limitations, an initial mapping scheme from the spiking neural network model to the neuromorphic hardware model is generated. The mapping iteration optimization module is used to find and alleviate congestion hotspots in the network and update the mapping scheme in each iteration: based on pulse traffic assessment, the statistical distribution of congestion hotspots under the current mapping scheme is calculated. For each congestion hotspot, multiple physical cores with high traffic contribution are selected as hub cores to be swapped. Based on a heuristic swapping decision mechanism, the optimal swapping candidate core is determined for each hub core. The mapping scheme is updated by swapping the hub cores with the optimal swapping candidate cores.

[0074] It should be noted that the neuromorphic hardware congestion-aware spiking neural network mapping system device provided in the above embodiments should be illustrated using the above-described functional module division as an example when performing spiking neural network mapping. The functions described above can be assigned to different functional modules as needed, that is, the internal structure of the terminal or server can be divided into different functional modules to complete all or part of the functions described above. Furthermore, the neuromorphic hardware congestion-aware spiking neural network mapping system and the neuromorphic hardware congestion-aware spiking neural network mapping method embodiments provided in the above embodiments belong to the same concept. For details of its specific implementation process, please refer to the neuromorphic hardware congestion-aware spiking neural network mapping method embodiments, which will not be repeated here.

[0075] The embodiment also provides a computing device, including a memory and one or more processors. The memory stores executable code, and when the one or more processors execute the executable code, it implements the above-described neuromorphic hardware congestion awareness spiking neural network mapping method, specifically including the following steps: S1, mapping neurons in the spiking neural network model to the physical core of the neuromorphic hardware to form an initial mapping scheme; S2, in each iteration, finds congestion hotspots and updates the mapping scheme to alleviate network communication congestion on the hardware.

[0076] The computing device provided in this embodiment, at the hardware level, includes not only a processor and memory, but also internal buses, network interfaces, memory, and other hardware required for business operations. The memory is non-volatile memory. The processor reads the corresponding computer program from the non-volatile memory into memory and then runs it to implement the neuromorphic hardware congestion-aware spiking neural network mapping method described in S1-S2 above. Of course, besides software implementation, this invention does not exclude other implementation methods, such as logic devices or a combination of hardware and software, etc. That is to say, the execution entity of the following processing flow is not limited to individual logic units, but can also be hardware or logic devices.

[0077] The embodiment also provides a computer-readable storage medium having a program stored thereon, which, when executed by a processor, implements the above-described neuromorphic hardware congestion awareness spiking neural network mapping method, specifically including the following steps: S1, mapping neurons in the spiking neural network model to the physical core of the neuromorphic hardware to form an initial mapping scheme; S2, in each iteration, finds congestion hotspots and updates the mapping scheme to alleviate network communication congestion on the hardware.

[0078] In this embodiment, computer-readable media includes both permanent and non-permanent, removable and non-removable media, and information storage can be implemented by any method or technology. Information can be computer-readable instructions, data structures, program modules, or other data. Examples of computer storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, digital versatile optical disc (DVD) or other optical storage, magnetic tape, magnetic magnetic disk storage or other magnetic storage devices, or any other non-transferable medium that can be used to store information accessible by a computing device. As defined herein, computer-readable media does not include transient computer-readable media, such as modulated data signals and carrier waves.

[0079] The specific embodiments described above illustrate the technical solution and beneficial effects of the present invention in detail. It should be understood that the above description is only the most preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, additions, and equivalent substitutions made within the scope of the principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A neuromorphic hardware congestion-aware spiking neural network mapping method, characterized in that, Includes the following steps: The neurons in the spiking neural network model are mapped to the physical core of the neuromorphic hardware to form an initial mapping scheme; Each iteration identifies congestion hotspots and updates the mapping scheme to alleviate network communication congestion on the hardware. Specifically, this includes: calculating the distribution of congestion hotspot regions composed of physical cores under the current mapping scheme based on pulse traffic assessment between physical core pairs; for each congestion hotspot region, selecting multiple physical cores with high pulse traffic contribution as hub cores to be swapped; determining the optimal swap candidate core for each hub core based on a heuristic swapping decision mechanism; and updating the mapping scheme by swapping hub cores with the optimal swap candidate cores.

2. The neuromorphic hardware congestion-aware spiking neural network mapping method according to claim 1, characterized in that, Based on the pulse flow assessment between physical core pairs, the distribution of congestion hotspot regions composed of physical cores under the current mapping scheme is calculated, including: Traverse all physical core pairs in the current mapping scheme, simulate routing paths, and accumulate the number of pulses passed by each physical core on each routing path to obtain the pulse traffic distribution; Based on the pulse flow distribution, the pulse with the largest flow was identified. Each physical core is used as a congestion hotspot region to obtain the distribution of congestion hotspot regions.

3. The neuromorphic hardware congestion-aware spiking neural network mapping method according to claim 1, characterized in that, For each congestion hotspot area, several physical cores with high pulse traffic contribution are selected as hub cores to be swapped, including: Calculate the traffic contribution of all physical cores to the congested hotspot: if the routing path of a physical core pair passes through the congested hotspot, the contribution of the relevant physical cores is accumulated to the corresponding number of pulses. Filter out the top contributors to traffic Each physical core serves as a hub core to be exchanged.

4. The neuromorphic hardware congestion-aware spiking neural network mapping method according to claim 1, characterized in that, The optimal candidate core for swapping is determined for each hub core based on a heuristic swapping decision mechanism, including: The physical core with the lowest overall score is selected as the optimal candidate core for swapping. The overall score includes traffic score and hop count score. Traffic scoring is used to assess changes in pulse traffic through congestion hotspots after a swap. In specific calculations, only pulse traffic related to the hub's core location that still passes through congestion hotspots after the swap needs to be counted. Hop count score is used to assess the impact of switching on total communication distance, specifically by calculating the change in the sum of Manhattan distances of all connections related to the hub core and physical core before and after the switching.

5. The neuromorphic hardware congestion-aware spiking neural network mapping method according to claim 4, characterized in that, The method further includes defining a circular swap window centered on the hub core, and searching only the physical core with the lowest comprehensive score among the physical cores within the window as the optimal swap candidate core.

6. The neuromorphic hardware congestion-aware spiking neural network mapping method according to claim 1, characterized in that, When updating the mapping scheme, an incremental update strategy is adopted, which only recalculates the path traffic affected by the exchange.

7. The neuromorphic hardware congestion-aware spiking neural network mapping method according to claim 1, characterized in that, The method further includes: if the current iteration reaches the maximum number of iterations or the mapping scheme converges, outputting the optimal mapping scheme, wherein the convergence of the mapping scheme is determined based on the key performance indicators continuously tracked during the mapping process, including network peak congestion and total hop cost.

8. A neuromorphic hardware congestion-aware spiking neural network mapping system, characterized in that, include: The initial mapping module is used to map neurons in the spiking neural network model to the physical core of the neuromorphic hardware, forming an initial mapping scheme. The mapping iteration optimization module is used to find congestion hotspots and update the mapping scheme in each iteration to alleviate network communication congestion on the hardware. Specifically, it includes: calculating the distribution of congestion hotspot areas composed of physical cores under the current mapping scheme based on pulse traffic evaluation between physical core pairs; for each congestion hotspot area, selecting multiple physical cores with high pulse traffic contribution as hub cores to be switched; determining the optimal switching candidate core for each hub core based on a heuristic switching decision mechanism; and updating the mapping scheme by switching hub cores with the optimal switching candidate cores.

9. A computing device comprising a memory and one or more processors, wherein the memory stores executable code, characterized in that, When the one or more processors execute the executable code, they are used to implement the neuromorphic hardware congestion awareness spiking neural network mapping method according to any one of claims 1-7.

10. A computer-readable storage medium, characterized in that, It stores a program that, when executed by a processor, implements the neuromorphic hardware congestion-aware spiking neural network mapping method according to any one of claims 1-7.

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