Quantum circuit fidelity optimization method and system, computer device and storage medium

Abstract

This invention relates to the field of quantum computing technology, and particularly to a method, system, computer device, and storage medium for optimizing the fidelity of quantum circuits. The method includes: acquiring the hardware parameters of the quantum circuit to be executed and the quantum processing unit cluster; standardizing the quantum circuit, analyzing the type of quantum gate and its active bits, and standardizing the multi-bit gates; constructing a unified fidelity cost model based on the quantum circuit and hardware parameters, and quantizing the cost into an additive cost; spatially partitioning the quantum circuit based on the coupling relationship between the quantum bits, and temporally partitioning the quantum circuit based on the quantum gate sequence to form a set of spatiotemporal sub-blocks; pre-calculating the partitioning cost for each spatiotemporal sub-block, and determining the candidate execution mode for each spatiotemporal sub-block accordingly; using a multi-objective global optimization algorithm to globally optimize the allocation scheme to obtain a set of optimal cooperative execution schemes; and outputting the quantum circuit mapping results.

Description

Technical Field

[0001] This invention relates to the field of quantum computing technology, and in particular to a method, system, computer device, and storage medium for optimizing the fidelity of quantum circuits. Background Technology

[0002] Current quantum computing is in the era of Noisy Medium-Scale Quantum (NISQ). Commercial quantum processing units (QPUs) are limited by physical technology, generally suffering from problems such as a limited number of qubits per node, short coherence time, and high gate operation noise levels. This makes it difficult to independently support the complete execution of medium-scale quantum algorithms in fields such as quantum chemistry, combinatorial optimization, and quantum machine learning. Distributed quantum computing, through technologies such as quantum teleportation and entanglement distribution, breaks down large-scale quantum circuits into multiple QPU nodes for collaborative execution. This overcomes the limitations of the number of qubits and coherence time of a single QPU and is currently the core technological path for realizing the deployment of medium-scale quantum algorithms.

[0003] Compilation and partitioning of distributed quantum circuits are core components of distributed quantum computing. Their primary objective is to minimize fidelity loss during circuit execution and improve the final success rate of the algorithm while satisfying QPU hardware constraints. Current mainstream solutions in this field generally employ a two-stage architecture that separates partitioning and compilation, which can be categorized into "partitioning before compilation" and "compilation before partitioning." Both approaches suffer from architectural flaws and are difficult to adapt to the actual hardware characteristics of NISQ devices. On one hand, most existing solutions assume a fully connected topology within the QPU, focusing solely on minimizing the number of teleportations across the QPU, completely ignoring the SWAP gate overhead caused by non-fully connected topologies within the QPU. This results in the theoretically optimal partitioning scheme introducing numerous additional gate operations and fidelity losses during actual hardware execution. On the other hand, existing solutions are mostly based on offline static optimization, and the generated execution schemes cannot adapt to real-world scenarios such as dynamic noise fluctuations in NISQ devices, post-measurement branch jumps, and dynamic changes in hardware resources, leading to a significant gap between the actual execution fidelity and theoretical expectations.

[0004] The information disclosed in this background section is intended only to enhance the understanding of the general background of the invention and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Summary of the Invention

[0005] This invention provides a method, system, computer device, and storage medium for optimizing the fidelity of quantum circuits, thereby effectively solving the problems in the background art. To achieve the above objectives, the technical solution adopted by this invention is: a quantum circuit fidelity optimization method, comprising the following steps: Obtain the hardware parameters of the quantum circuit to be executed and the quantum processing unit cluster; The quantum circuit is standardized to determine the type of quantum gate and its active bits, and multi-bit gates are decomposed using standardization. Based on the quantum circuit and hardware parameters, a unified fidelity cost model is constructed, which quantizes the single-qubit gate cost, double-qubit gate cost, swapping gate cost, quantum teleportation cost, and decoherence cost into an additivity cost. The quantum circuit is spatially divided based on the coupling relationship between qubits, and temporally divided based on the quantum gate sequence to form a set of spatiotemporal sub-blocks; For each spatiotemporal sub-block, the compilation cost of executing it on a single quantum processing unit and the partitioning cost of executing it on two quantum processing units are pre-calculated, and the candidate execution methods for each spatiotemporal sub-block are determined accordingly. Based on the candidate execution methods of each spatiotemporal sub-block, a joint cost across the block boundary is constructed. A multi-objective global optimization algorithm is used to globally optimize the quantum processing unit allocation scheme of each spatiotemporal sub-block in order to obtain a set of optimal cooperative execution schemes. The output includes quantum circuit mapping results, swap gate insertion results, cross-quantum processing unit state transfer scheduling results, and performance evaluation results that can be executed on the quantum processing unit cluster.

[0006] Furthermore, the standardization process includes: Extract the gate type, active bit, control bit, and target bit of each quantum gate in the quantum circuit; Multi-bit gates are decomposed using a preset decomposition template, and the equivalent fidelity loss introduced after decomposition is recorded. Construct a qubit coupling matrix to characterize the frequency of co-occurrence of each qubit in a two-qubit gate.

[0007] Furthermore, the spatial segmentation includes: Construct a quantum interaction graph with qubits as vertices and qubit coupling degrees as edge weights; Community detection is performed on the quantum interaction graph to group strongly interacting qubits into the same spatial block; When the number of bits in a certain space block exceeds a preset upper limit, a recursive binary search is performed on that space block until the number of bits in each space block does not exceed the preset upper limit.

[0008] Furthermore, the community detection is achieved through an iterative process of local movement and community aggregation based on modularity gain; The recursive bisection includes: first performing an initial bisection on the spatial block to be divided, and then performing local refinement on the bisection result to minimize the cut edge weights between the bipartite graphs.

[0009] Furthermore, the time blocks include: The quantum gate sequence is divided into multiple consecutive subsequences according to the execution order of the quantum gates; When the length of the last subsequence is less than a preset gate number threshold, the last subsequence is merged into the previous subsequence; By combining spatial blocks with time slices, a set of spatiotemporal sub-blocks is obtained.

[0010] Furthermore, the pre-computation of the compilation cost for each spatiotemporal sub-block to be executed on a single quantum processing unit includes: An initial mapping is generated based on the physical bit coherence time, gate error rate, and internal coupling graph of the quantum processing unit; For cases where the two-bit gate does not satisfy the adjacency constraint, a swap gate is inserted, and the mapping relationship between logical bits and physical bits is updated; The idle time of physical bits is calculated based on the compiled gate execution timing, and the decoherence cost is accumulated.

[0011] Furthermore, it also includes a dynamic recompilation step, which includes: Real-time acquisition of noise parameters and resource status of each quantum processing unit; When a preset trigger condition is detected, the queue of spatiotemporal sub-blocks that have not yet been executed is frozen; The affected spatiotemporal sub-blocks were re-optimized based on the updated noise parameters and resource status; The execution scheme switches to a new one at the natural synchronization point after the current spacetime sub-block finishes execution.

[0012] The present invention also includes a quantum circuit fidelity optimization system using the method described above, the system comprising: The data acquisition module is used to acquire the hardware parameters of the quantum circuit and the quantum processing unit cluster; The preprocessing module is used to standardize quantum circuits and decompose multi-qubit gates; The Unified Fidelity Cost Model module is used to construct unified cost models for single-bit gates, two-bit gates, swapping gates, quantum teleportation, and decoherence. The spatiotemporal joint segmentation module is used to perform spatial and temporal segmentation of quantum circuits to generate a set of spatiotemporal sub-blocks; The block cost pre-computation module is used to pre-compute the execution cost of each spatiotemporal sub-block on a single quantum processing unit and the partitioning cost on two quantum processing units; The cross-block collaborative global optimization module is used to globally optimize the execution scheme of each spatiotemporal sub-block based on the cross-block joint cost; The results output module is used to output quantum circuit mapping results, swap gate insertion results, cross-quantum processing unit state transfer scheduling results, and performance evaluation results.

[0013] The present invention also includes a computer device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor, when executing the computer program, implements the method as described above.

[0014] The present invention also includes a storage medium having a computer program stored thereon, which, when executed by a processor, implements the method as described above.

[0015] The beneficial effects of this invention are as follows: It constructs a technical architecture for joint optimization of segmentation and compilation, breaking the traditional two-stage separation optimization mode. It can simultaneously consider the cross-QPU teleportation cost and the QPU internal compilation cost during the optimization process, resulting in a circuit execution scheme that is more in line with the actual hardware characteristics. It establishes a unified fidelity cost model, which uniformly quantifies the costs of single-bit gates, double-bit gates, SWAP gates, quantum teleportation, and decoherence, providing a multi-dimensional objective standard for optimization decisions. It solves the one-sided problem of traditional methods that only take the number of teleportations as the optimization target, and can minimize the global comprehensive cost of the circuit. By employing a spatiotemporal joint partitioning approach, large-scale quantum circuits are decomposed into multiple small-scale subproblems that can be solved precisely, significantly reducing the computational complexity of global optimization and improving the method's adaptability to medium- and large-scale circuits. An incremental dynamic recompilation mechanism is introduced, which can perform online re-optimization based on the real-time noise parameters of the QPU hardware, the circuit execution status, and resource changes. This allows the method to adapt to real-world scenarios such as dynamic noise fluctuations in NISQ devices and post-measurement branching, narrowing the gap between the actual execution fidelity of the circuit and the theoretical expectation, and improving the hardware robustness of the solution. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a flowchart of the method in Embodiment 1 of the present invention; Figure 2 This is a schematic diagram of the system structure in Embodiment 1 of the present invention; Figure 3 This is a framework diagram of the quantum circuit fidelity optimization system in Embodiment 2 of the present invention; Figure 4This is a schematic diagram of the computer device in Embodiment 3 of the present invention. Detailed Implementation

[0018] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments.

[0019] Example 1; like Figure 1 As shown: A method for optimizing the fidelity of quantum circuits, comprising the following steps: Obtain the hardware parameters of the quantum circuit to be executed and the quantum processing unit cluster. The hardware parameters include at least the physical bit set, internal coupling graph, single-bit gate error rate, double-bit gate error rate, decoherence parameters, and quantum teleportation fidelity and teleportation delay across quantum processing units. The quantum circuits are standardized to determine the types of quantum gates and their active bits, and multi-qubit gates are decomposed using standardization. A unified fidelity cost model is constructed based on quantum circuits and hardware parameters, which quantizes the single-qubit gate cost, double-qubit gate cost, swapping gate cost, quantum teleportation cost, and decoherence cost into an additivity cost. The quantum circuit is spatially divided based on the coupling relationship between qubits, and temporally divided based on the quantum gate sequence to form a set of spatiotemporal sub-blocks; For each spatiotemporal sub-block, the compilation cost of executing it on a single quantum processing unit and the partitioning cost of executing it on two quantum processing units are pre-calculated, and the candidate execution methods for each spatiotemporal sub-block are determined accordingly. Based on the candidate execution methods of each spatiotemporal sub-block, a joint cost across the block boundary is constructed. A multi-objective global optimization algorithm is used to globally optimize the quantum processing unit allocation scheme of each spatiotemporal sub-block in order to obtain a set of cooperative execution schemes that satisfy the optimal fidelity and optimal execution depth. The outputs quantum circuit mapping results, swap gate insertion results, cross-quantum processing unit state transfer scheduling results, and performance evaluation results that can be executed on the quantum processing unit cluster.

[0020] Among them, the unified fidelity cost model adopts the product property of quantum operation fidelity to convert the total fidelity loss after multiple quantum operations are cascaded into the sum of the fidelity losses of each quantum operation.

[0021] In this embodiment, the standardization process includes: Extract the gate type, active bit, control bit, and target bit of each quantum gate in the quantum circuit; Multi-bit gates are decomposed using a preset decomposition template, and the equivalent fidelity loss introduced after decomposition is recorded. Construct a qubit coupling matrix to characterize the frequency of co-occurrence of each qubit in a two-qubit gate.

[0022] Spatial partitioning includes: Construct a quantum interaction graph with qubits as vertices and qubit coupling degrees as edge weights; Community detection is performed on the quantum interaction graph to group strongly interacting qubits into the same spatial block; When the number of bits in a certain space block exceeds the preset upper limit, a recursive binary search is performed on that space block until the number of bits in each space block does not exceed the preset upper limit.

[0023] Community detection is achieved through an iterative process of local movement and community aggregation based on modularity gain.

[0024] Recursive binary search involves: first performing an initial binary search on the spatial blocks to be divided, and then performing local refinement on the binary search results to minimize the cut edge weights between the binary graphs.

[0025] Time blocks include: The quantum gate sequence is divided into multiple consecutive subsequences according to the execution order of the quantum gates; When the length of the last subsequence is less than the preset gate number threshold, the last subsequence is merged into the previous subsequence; By combining spatial blocks with time slices, a set of spatiotemporal sub-blocks is obtained.

[0026] The pre-computation of compilation costs on a single quantum processing unit includes: An initial mapping is generated based on the physical bit coherence time, gate error rate, and internal coupling graph of the quantum processing unit; For cases where the two-bit gate does not satisfy the adjacency constraint, a swap gate is inserted, and the mapping relationship between logical bits and physical bits is updated; The idle time of physical bits is calculated based on the compiled gate execution timing, and the decoherence cost is accumulated.

[0027] The pre-computation of the partition cost, which is performed on two quantum processing units, includes calculating the quantum teleportation cost across the quantum processing units and combining it with the local execution cost of each of the two quantum processing units to form the total partition cost.

[0028] The construction method of cross-block boundary joint cost is as follows: a sliding window is formed by adjacent spatiotemporal sub-blocks, and the local cost and cross-block transfer cost of different sub-blocks within the window are jointly calculated.

[0029] The multi-objective global optimization algorithm adopts a non-dominated sorting evolutionary optimization algorithm, with the optimization objectives of minimizing the total fidelity loss and the shortest total execution depth, and outputs a Pareto optimal solution set.

[0030] This embodiment also includes a dynamic recompilation step, which includes: Real-time acquisition of noise parameters and resource status of each quantum processing unit; When a preset trigger condition is detected, the queue of spatiotemporal sub-blocks that have not yet been executed is frozen; The affected spatiotemporal sub-blocks were re-optimized based on the updated noise parameters and resource status; The execution scheme switches to a new one at the natural synchronization point after the current spacetime sub-block finishes execution.

[0031] like Figure 2 As shown, this embodiment also includes a quantum circuit fidelity optimization system, which uses the method described above. The system includes: The data acquisition module is used to acquire the hardware parameters of the quantum circuit and the quantum processing unit cluster; The preprocessing module is used to standardize quantum circuits and decompose multi-qubit gates; The Unified Fidelity Cost Model module is used to construct unified cost models for single-bit gates, two-bit gates, swapping gates, quantum teleportation, and decoherence. The spatiotemporal joint segmentation module is used to perform spatial and temporal segmentation of quantum circuits to generate a set of spatiotemporal sub-blocks; The block cost pre-computation module is used to pre-compute the execution cost of each spatiotemporal sub-block on a single quantum processing unit and the partitioning cost on two quantum processing units; The cross-block collaborative global optimization module is used to globally optimize the execution scheme of each spatiotemporal sub-block based on the cross-block joint cost; The results output module is used to output quantum circuit mapping results, swap gate insertion results, cross-quantum processing unit state transfer scheduling results, and performance evaluation results.

[0032] Example 2: This embodiment provides a quantum circuit fidelity optimization method based on segmentation-compilation coordination, including the following steps: Step 1: Input preprocessing and construction of a uniform fidelity cost model This step completes the standardization transformation of the original data and the construction of the core cost model, providing a unified quantitative basis for subsequent optimization.

[0033] 1.1 Input Standardization Processing Input: Quantum circuit: The original algorithm circuit, denoted as C=(Q,G), where . is a set of logical qubits. A sequence of quantum gates arranged in the order of execution; QPU Cluster Parameters: Set of Cluster Nodes Each node Include: Physical bit set ,in For nodes Total physical bit capacity; Internal coupling diagram , , represents a physical bit pair that can be directly executed with a two-bit gate; Noise parameter matrix: single-bit gate error rate Double-bit gate error rate Longitudinal relaxation time (i.e., physical bits) From the excited state Relaxation back to ground state The average time, a fundamental parameter for hardware noise modeling, is used to assess the potential fidelity loss of qubits due to energy dissipation, and the lateral relaxation time. (physical bits) The average time for the phase coherence of the superposition state to completely disappear is a core parameter for calculating the decoherence fidelity loss during the idle waiting period of a qubit (used to quantize the impact of line depth on the final execution fidelity). ; Cross-node parameter: any pair of nodes Quantum teleportation fidelity between and transfer delay .

[0034] Output: Standardized line data structure and hardware parameter database.

[0035] Execution flow: Analyze the quantum circuit and extract the type, active bits, and control / target bit information of all quantum gates; Perform multi-bit gate decomposition: Use a preset low-depth decomposition template (e.g., decompose a Tofoli gate into 6 CNOT gates and several single-bit gates), record the equivalent fidelity loss introduced after decomposition, and update the gate sequence. ; Pre-calculated qubit coupling matrix Where C[a][b] represents a qubit. and The number of times they appear together in the same two-bit gate.

[0036] 1.2 Construction of a Unified Fidelity Cost Model Core mathematical principle: The fidelity of quantum operations is multiplicative, meaning the total fidelity of multiple operations cascaded together is equal to the product of the fidelities of each individual operation. Taking its natural logarithm, the total fidelity loss becomes the sum of the fidelity losses of each individual operation, satisfying additivity, making it suitable as a global optimization objective.

[0037] The fidelity loss is defined as: ; Where F represents the fidelity of the quantum operation, and a larger L indicates a lower fidelity. The precise formulas for calculating the fidelity loss of various operations are as follows: Local single-bit gate: A single-bit gate that operates on physical bit v, with a fidelity loss of: ; Local two-bit gate: A two-bit gate operating on physical bits u and v, whose fidelity loss is: ; SWAP gate: In current mainstream QPUs, two-bit gates such as CNOT and CZ are natively supported in hardware and can be directly implemented using a single microwave pulse; however, the SWAP gate has no native hardware implementation and can only be implemented by decomposing it into a combination of multiple native two-bit gates and single-bit gates (such as three CNOT gates). Its error rate is significantly higher than that of the native two-bit gate. Therefore, it must be modeled and its fidelity loss calculated separately as an independent operation. It cannot use the same cost parameter as the native two-bit gate. Its fidelity loss is: Where k is the number of native gates required for decomposition. The additional errors introduced for decomposition (such as intermediate state decoherence) are obtained from the statistical results of actual QPU hardware measurements. Quantum teleportation: from node To the node The fidelity loss of quantum teleportation is: ; Decoherence loss: qubit v in The decoherence loss over time is approximated using a simplified decoherence model, with the fidelity loss being (NISQ device dominant noise): ; Global optimization objective function: ; The constraints are: Where X represents the allocation scheme of qubits to QPU nodes. To be assigned to a node The system allocates one bit for temporary storage to receive quantum teleportation. During quantum teleportation, the system dynamically schedules and temporarily occupies one idle computational bit as an entanglement auxiliary bit, which is released immediately after the teleportation is completed. If all bits of a QPU are occupied in computation and there is no free space, the teleportation operation will be delayed or another QPU will be selected to perform the operation, without the need to permanently reserve a dedicated bit.

[0038] Secondary optimization objective: .in This represents the total execution depth of the line, which is the number of time steps required for all doors to be executed.

[0039] Step 2: Spatiotemporal Joint Blocking This step decomposes the large-scale problem into multiple exact-solvable subproblems of a few bits (with an upper limit of q). This block decomposition method is applicable to the decomposition of large-scale quantum circuits, and all block algorithms have been verified through large-scale benchmark tests.

[0040] 2.1 Spatial Blocking Input: Quantum bit coupling matrix C.

[0041] Output: Set of space blocks ; Execution process: Constructing quantum interaction graphs: undirected weighted graphs The vertices are qubits, and the edges are... The weights are C[a][b]; Louvain Community Detection: This detection algorithm groups strongly interacting qubits into the same module, revealing a hierarchical, modular structure. The algorithm consists of two phases. Local Phase: Each qubit is evaluated based on its immediate neighbors and may be reassigned to a community that maximizes its "interaction benefits." This helps to concentrate two-qubit gates within the same block. Aggregation Phase: Stable communities are merged into "super qubits," generating a simplified graph structure; this graph structure is then recursively processed to form a multi-level hierarchical structure.

[0042] The goal is to maximize the modularity Q of the graph: .in For elements of the adjacency matrix, As vertices i The degree, m The total number of sides, As vertices i The community to which it belongs Let Kronecker function be used.

[0043] Local movement phase: Move each vertex to its adjacent community in turn, selecting the move that maximizes the increase in modularity, until the modularity no longer increases; Community aggregation phase: Aggregate each community into a super vertex, generate a new graph, and repeat the above process until the modularity converges.

[0044] Recursive binary search: For all communities whose size exceeds a predetermined upper limit bit q, perform the following operations: First, perform an initial binary search using the METIS algorithm to make the sizes of the two subgraphs as balanced as possible; then, perform local refinement using the Kernighan-Lin (KL) algorithm to minimize the cut edge weights between the two subgraphs; recursively execute the above steps until the number of bits in all spatial blocks is ≤ q.

[0045] 2.2 Time Blocking Input: Quantum gate sequence G; Output: Set of time slices Each time slice contains a certain number of consecutive gates (with a maximum limit of g). Execution flow: Divide the gate sequence G into consecutive subsequences according to the execution order, with each subsequence having a length of g gates; If the length of the last subsequence is less than g / 3, then merge it into the previous subsequence; Generate a set of spatiotemporal sub-blocks ,in Represents a space block In time slice The purpose of this step is to reduce the impact of decoherence loss on the fidelity of the result.

[0046] Step 3: Pre-calculation of compilation cost within blocks The goal of this step is not to make a final execution decision for each spatiotemporal subblock, but rather to pre-calculate the execution cost of each subblock under various possible QPU allocation schemes, providing input for the global optimization in step 4. Each spatiotemporal subblock The candidate allocation schemes include: executing on any single QPU, or splitting the execution across any two different QPUs.

[0047] 3.1 Pre-calculation of execution cost per QPU Input: Spacetime sub-block QPU node set P.

[0048] Output: The minimum cost of executing this sub-block on all QPUs. and the corresponding optimal QPU node ; Execution flow: The execution cost of each QPU is calculated using the SABRE noise-aware compiler, with the following steps: Initial mapping generation: Prioritize mapping the logical bits of the sub-block to the physical bits in the QPU with the longest coherence time and the lowest gate error rate; Forward routing: Scan in the order of gate execution. If the two physical bits of the current two-bit gate are not adjacent, use the fidelity loss of the SWAP gate as the edge weight, search for the shortest path using Dijkstra's algorithm, insert the SWAP gate sequence and update the mapping. Reverse routing: Scans backwards from the end of the line to optimize the initial mapping and further reduce the number of SWAP gates; Decoherence loss calculation: Based on the compiled gate execution timing, calculate the idle time of each physical bit and accumulate the decoherence loss; Calculate the sub-block in Total cost Take the minimum value among all QPUs. ; 3.2 Pre-calculation of execution cost for dual QPU segmentation Spacetime sub-block QPU node pair set .

[0049] Output: The minimum cost of splitting this sub-block into any two QPUs. and the corresponding optimal QPU node pair

[0050] Execution flow: Divide the quantum circuit into two QPU nodes, and calculate the node pair to which the sub-block is divided. minimum cost Take the minimum value among all node pairs. .

[0051] 3.3 Decision on the optimal execution method for sub-blocks Compare the minimum cost of the two methods, select the execution method with lower total fidelity loss, and record the optimal execution method and corresponding QPU allocation scheme for the sub-block.

[0052] Step 4: Cross-block collaborative global optimization Based on the cost pre-calculated in step 3, this step performs a global optimization of the QPU allocation scheme for all spatiotemporal sub-blocks to solve the boundary consistency problem caused by block division.

[0053] 4.1 Construction of Sliding Window Across Block Boundaries Input: Set of spacetime sub-blocks ; Output: Set of sliding windows ; Execution flow: Traverse all spatiotemporal sub-blocks in chronological and spatial order; for each sub-block... The spatial sub-block adjacent to its right The time sub-block adjacent to the bottom Each window is composed of two adjacent spatiotemporal sub-blocks, covering all cross-block boundaries and cross-block gates.

[0054] 4.2 Window-level Joint Cost Calculation For each window Calculate the total cost of all possible combinations of sub-block allocations: ; in Sub-blocks and QPU allocation scheme, This represents the total cost of cross-block transfer between two sub-blocks.

[0055] 4.3 Global Multi-Objective Optimization Global optimization is implemented based on the NSGA-II framework. With the optimization objectives of minimizing total fidelity loss and shortest path depth, it performs global optimization on the QPU allocation scheme of all spatiotemporal sub-blocks. The decision variable is the allocation scheme for each spatiotemporal sub-block (selected from the candidate allocation set for that sub-block).

[0056] The optimization objective is: ; During the iteration process, the algorithm maintains the Pareto optimal solution set through non-dominated sorting and crowding distance, preserving allocation schemes that balance high fidelity and low latency. To accelerate convergence, the following heuristic is used when initializing the population: each sub-block is preferentially allocated to the sub-block in step 3.1. Minimize the QPU; for adjacent sub-blocks with dense cross-gates, prioritize assigning them to the same QPU to reduce transfer costs. The final output is a set of balanced optimal solutions (Pareto fronts) that can be selected according to requirements.

[0057] Step 5: Output Results After optimization, the following complete solution, which can be executed directly on the QPU cluster, is output: Spatiotemporal sub-block partitioning table: contains the set of qubits, gate sequence, and time interval for each sub-block; Global allocation scheme: the optimal execution method and QPU node number corresponding to each spatiotemporal sub-block; QPU internal execution scheme: logical-physical bit mapping table for each QPU, SWAP gate insertion sequence and gate execution timing; Cross-QPU transfer scheduling plan: source node, target node, transmitted bits, execution time, and global gate list covered for each transfer; Performance Prediction Report: Analysis of expected total fidelity, total number of stealth transfers, total number of SWAP gates, total line depth, and the proportion of cost for each component.

[0058] Step 6: Dynamic Recompilation and Adaptive Adjustment Steps 1-5 above constitute the offline static optimization phase, generating the initial execution plan. During execution, this embodiment introduces a dynamic recompilation mechanism to adapt to noise fluctuations, post-measurement branches, and resource changes in the NISQ device.

[0059] Execution process: Monitoring agent deployment: Deploy a monitoring agent on the classic server to continuously collect real-time calibration data returned by each QPU, including: gate error rate drift of each physical bit, T 1 / T 2. Time variations, fluctuations in the fidelity of invisible transmission, etc.

[0060] Triggering conditions: Recompilation is triggered when any of the following events are detected: the average gate error rate or decoherence time of a QPU changes more than a preset threshold (e.g., 20%) relative to the initial value; the actual fidelity of the currently executing spatiotemporal subblock (through random benchmark testing or periodic verification) is lower than 95% of the expected value; classical branch information after measurement is received, causing the structure of the future to be executed circuit to change (e.g., adaptive quantum circuit); a QPU node goes offline or a new node joins the cluster (resources change dynamically).

[0061] Online recompile: Freeze the queue of spatiotemporal sub-blocks that have not yet started execution; re-optimize from step 2 or step 3 using the latest noise parameters and available resource information (optionally skip unaffected blocks to reduce overhead); generate a new allocation and compilation scheme.

[0062] Hot switching of schemes: The new scheme is dynamically loaded into the execution controller of the QPU cluster, and the new scheme is switched at the next natural synchronization point (when the current sub-block is completed).

[0063] Rollback and safety mechanisms: If recompilation fails or the fidelity of the new scheme decreases instead of increasing, the system retains the original scheme and issues an alarm.

[0064] like Figure 3As shown, this embodiment also includes a noise-aware quantum circuit segmentation and compilation collaborative optimization system, mainly composed of five layers: hardware layer, data layer, model layer, execution layer, and interaction layer. The hardware layer includes a classical control server cluster, a distributed QPU cluster, and a high-speed Ethernet, used for classical computation scheduling, quantum instruction execution, and high-speed cross-node communication. The data layer includes a data acquisition module and a preprocessing module, used to acquire hardware noise parameters in real time and perform analytical standardization on the original quantum circuits. The model layer includes a unified fidelity cost model module, a spatiotemporal joint block model module, a block cost pre-computation model module, and a cross-block collaborative global optimization model module, used to uniformly quantize quantum operation costs, spatiotemporally segment the circuits, pre-compute the execution costs of each sub-block, and perform global multi-objective optimization. The execution layer includes a distributed execution scheduling module and a dynamic recompilation module, used to convert the optimization scheme into executable instructions and support runtime noise adaptive adjustment. The interaction layer includes a system management module, a status monitoring module, and a result display and analysis module, used to provide user management, runtime status visualization, and performance analysis report output.

[0065] 1. Hardware layer: The classical control server cluster is the core control and computing unit of the system, undertaking all classical computing, scheduling, and management tasks. In the offline phase, it performs quantum circuit preprocessing, spatiotemporal joint partitioning, partition cost pre-computation, and cross-block collaborative global optimization. In the online phase, it performs quantum instruction generation, distributed execution timing synchronization, real-time hardware status monitoring, and incremental dynamic recompilation. It is also responsible for the persistent storage of all quantum circuits, compilation results, execution logs, and performance data.

[0066] Distributed QPU cluster: This is the quantum computing execution unit of the system, composed of multiple independent quantum processing unit nodes, supporting the mixed deployment of heterogeneous nodes of different topologies and sizes. Each QPU node independently completes quantum computing operations such as qubit initialization, single-qubit and double-qubit gate execution, and quantum measurement; nodes cooperate through classical communication to complete cross-QPU quantum teleportation, and finally output the measurement results of the quantum circuit, corresponding to the physical execution process of all quantum operations in the method.

[0067] High-speed Ethernet: It is the communication infrastructure between the classical control server cluster and the distributed QPU cluster, realizing the classical information exchange required for classical command issuance, measurement result feedback, hardware status feedback and cross-QPU teleportation, and meeting the timing synchronization requirements of quantum computing.

[0068] 2. Data Layer: Data acquisition module: Establishes continuous communication with the distributed QPU cluster, collects single-bit gate error rate, double-bit gate error rate, longitudinal relaxation time T1, lateral relaxation time T2, cross-node quantum teleportation fidelity, and information such as temperature, load, and online status of QPU nodes for each physical bit; when a hardware parameter mutation is detected to exceed a preset threshold, the abnormal data is pushed to the dynamic recompilation module in real time.

[0069] Preprocessing module: Receives quantum circuit files and QPU cluster hardware configuration files uploaded by users, performs quantum circuit analysis, multi-qubit gate normalization decomposition, and pre-calculation of the quantum bit coupling matrix. At the same time, it standardizes the hardware static parameters and dynamically acquired real-time parameters to build a unified fidelity cost model and outputs a structured data format that is universally applicable within the system, providing input for the upper model layer.

[0070] 3. Model layer: Unified Fidelity Cost Model Module: Based on the multiplicative principle of quantum operation fidelity, an additivity fidelity loss model is constructed to unify and quantify the costs of single-qubit gates, two-qubit gates, SWAP gates, quantum teleportation, and decoherence into directly comparable values, providing an objective quantitative standard for all optimization decisions.

[0071] The spatiotemporal joint block model module implements the weighted Louvain community detection algorithm and recursive binary search method to decompose large-scale quantum circuits into multiple strongly interactive spatial blocks according to the spatial dimension, and then divides them into multiple time slices according to the temporal dimension to generate a set of spatiotemporal sub-blocks with a bit count not exceeding a preset threshold.

[0072] Block cost pre-computation model module: Integrates a noise-aware compiler and a genetic algorithm based on bit rearrangement and fixed segmentation coding to pre-compute the total fidelity loss of each spatiotemporal sub-block when executed on any single QPU and when divided into any two QPUs, generating a complete sub-block-allocation scheme cost matrix.

[0073] Cross-block collaborative global optimization model module: Constructs a sliding window covering all spatiotemporal sub-block boundaries, calculates the joint cost of different allocation combinations of adjacent sub-blocks, performs global optimization based on the NSGA-II multi-objective evolutionary algorithm with the goal of minimizing total fidelity loss and shortest total path depth, incorporates a heuristic population initialization strategy to accelerate convergence, and outputs the Pareto optimal solution set.

[0074] 4. Execution layer: Distributed execution scheduling module: It transforms the globally optimal allocation scheme generated by the model layer into an executable instruction sequence for each QPU node. It adopts a time-triggered global synchronous execution mechanism to precisely control the instruction issuance timing of each node and the time synchronization of cross-node quantum teleportation. It supports batch instruction preloading and asynchronous collection of execution results, and finally summarizes the measurement results of all nodes.

[0075] Dynamic recompiling module: Receives hardware status data from the data acquisition module in real time. When the preset recompiling trigger conditions are met (hardware parameter drift exceeds the threshold, actual fidelity is lower than expected, post-measurement branch, resource changes), the queue of spatiotemporal sub-blocks that have not yet started execution is frozen. An incremental recompiling strategy is adopted, only recalculating the execution cost of the affected sub-blocks and their adjacent sub-blocks, generating updated global allocation and execution instructions, and completing the scheme switch at the next natural synchronization point.

[0076] 5. Interaction Layer: System Management Module: Provides user management, access control, hardware resource management and system configuration functions, allowing administrators to configure QPU cluster parameters, optimize algorithm parameters and recompile trigger thresholds, ensuring system security and configurability.

[0077] Results Display and Analysis Module: After the quantum circuit is executed, a detailed performance analysis report is automatically generated, displaying the spatiotemporal sub-block partitioning results, global allocation scheme, expected and actual execution fidelity, total number of teleportation times, total number of SWAP gates, total circuit depth, and the proportion of cost for each part; it supports the export and visualization of result data, providing users with comprehensive performance evaluation basis.

[0078] Through the above technical solution, this embodiment achieves the following beneficial effects: A technical architecture for joint optimization of segmentation and compilation was constructed, breaking the traditional two-stage separation optimization mode. It can simultaneously take into account the cross-QPU invisible transfer cost and the QPU internal compilation cost during the optimization process, resulting in a circuit execution scheme that is more in line with the actual characteristics of the hardware. A unified fidelity cost model was established, which quantifies the costs of single-bit gates, double-bit gates, SWAP gates, quantum teleportation, and decoherence. This provides a multi-dimensional objective standard for optimization decisions and solves the one-sided problem of traditional methods that only use the number of teleportations as the optimization objective. It can minimize the overall global cost of the circuit.

[0079] By adopting a spatiotemporal joint block approach, large-scale quantum circuits are decomposed into multiple small-scale subproblems that can be solved exactly, which significantly reduces the computational complexity of global optimization and improves the adaptability of the method to medium- and large-scale circuits. Introducing an incremental dynamic recompilation mechanism enables online re-optimization based on real-time noise parameters, line execution status, and resource changes in the QPU hardware. This adapts to real-world scenarios such as dynamic noise fluctuations in NISQ devices and post-measurement branching, narrowing the gap between actual line execution fidelity and theoretical expectations, and improving the hardware robustness of the solution.

[0080] Example 3: Please see Figure 4 The diagram shows a structural schematic of a computer device provided in an embodiment of this application. An embodiment of this application provides a computer device 400, including a processor 410 and a memory 420. The memory 420 stores a computer program executable by the processor 410. When the computer program is executed by the processor 410, it performs the method described above.

[0081] This application embodiment also provides a storage medium 430, on which a computer program is stored, and the computer program is executed by a processor 410 to perform the above method.

[0082] The storage medium 430 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as Static Random Access Memory (SRAM), Electrically Erasable Programmable Read-Only Memory (EEPROM), Erasable Programmable Read Only Memory (EPROM), Programmable Red-Only Memory (PROM), Read-Only Memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk.

[0083] In the description of this invention, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. "A plurality of" means two or more, unless otherwise explicitly specified.

[0084] In this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0085] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Furthermore, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0086] Any process or method description in the flowchart or otherwise herein can be understood as representing a module, segment, or portion of code comprising one or more executable instructions for implementing a particular logical function or process, and the scope of the preferred embodiments of the invention includes additional implementations in which functions may be performed not in the order shown or discussed, including substantially simultaneously or in reverse order depending on the functions involved, as will be understood by those skilled in the art to which embodiments of the invention pertain.

[0087] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a ordered list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (such as a computer-based system, a processor-included system, or other system that can fetch and execute instructions from, an instruction execution system, apparatus, or device). For the purposes of this specification, "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transmit programs for use by, or in conjunction with, an instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of computer-readable media include: an electrical connection having one or more wires (electronic device), a portable computer disk drive (magnetic device), random access memory (RAM), read-only memory (ROM), erasable and editable read-only memory (EPROM or flash memory), fiber optic devices, and portable optical disc read-only memory (CDROM). Alternatively, the computer-readable medium may be paper or other suitable media on which the program can be printed, since the program can be obtained electronically, for example, by optically scanning the paper or other medium, followed by editing, interpreting, or otherwise processing as necessary, and then stored in a computer memory.

[0088] It should be understood that various parts of the present invention can be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented in software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, it can be implemented using any one or a combination of the following techniques known in the art: discrete logic circuits having logic gates for implementing logical functions on data signals, application-specific integrated circuits (ASICs) having suitable combinational logic gates, programmable gate arrays (PGAs), field-programmable gate arrays (FPGAs), etc.

[0089] Those skilled in the art will understand that all or part of the steps of the methods in the above embodiments can be implemented by a program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, the program includes one or a combination of the steps of the method embodiments.

[0090] The storage medium mentioned above can be a read-only memory, a disk, or an optical disk, etc. Although embodiments of the present invention have been shown and described above, it is to be understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of the present invention.

Claims

1. A method for optimizing the fidelity of quantum circuits, characterized in that, Includes the following steps: Obtain the hardware parameters of the quantum circuit to be executed and the quantum processing unit cluster; The quantum circuit is standardized to determine the type of quantum gate and its active bits, and multi-bit gates are decomposed using standardization. Based on the quantum circuit and hardware parameters, a unified fidelity cost model is constructed, which quantizes the single-qubit gate cost, double-qubit gate cost, swapping gate cost, quantum teleportation cost, and decoherence cost into an additivity cost. The quantum circuit is spatially divided based on the coupling relationship between qubits, and temporally divided based on the quantum gate sequence to form a set of spatiotemporal sub-blocks; For each spatiotemporal sub-block, the compilation cost of executing it on a single quantum processing unit and the partitioning cost of executing it on two quantum processing units are pre-calculated, and the candidate execution methods for each spatiotemporal sub-block are determined accordingly. Based on the candidate execution methods of each spatiotemporal sub-block, a joint cost across the block boundary is constructed. A multi-objective global optimization algorithm is used to globally optimize the quantum processing unit allocation scheme of each spatiotemporal sub-block in order to obtain a set of optimal cooperative execution schemes. The output includes quantum circuit mapping results, swap gate insertion results, cross-quantum processing unit state transfer scheduling results, and performance evaluation results that can be executed on the quantum processing unit cluster.

2. The quantum circuit fidelity optimization method according to claim 1, characterized in that, The standardization process includes: Extract the gate type, active bit, control bit, and target bit of each quantum gate in the quantum circuit; Multi-bit gates are decomposed using a preset decomposition template, and the equivalent fidelity loss introduced after decomposition is recorded. Construct a qubit coupling matrix to characterize the frequency of co-occurrence of each qubit in a two-qubit gate.

3. The quantum circuit fidelity optimization method according to claim 1, characterized in that, The spatial partitioning includes: Construct a quantum interaction graph with qubits as vertices and qubit coupling degrees as edge weights; Community detection is performed on the quantum interaction graph to group strongly interacting qubits into the same spatial block; When the number of bits in a certain space block exceeds a preset upper limit, a recursive binary search is performed on that space block until the number of bits in each space block does not exceed the preset upper limit.

4. The quantum circuit fidelity optimization method according to claim 3, characterized in that, The community detection is achieved through an iterative process of local movement and community aggregation based on modularity gain; The recursive bisection includes: first performing an initial bisection on the spatial block to be divided, and then performing local refinement on the bisection result to minimize the cut edge weights between the bipartite graphs.

5. The quantum circuit fidelity optimization method according to claim 1, characterized in that, The time blocks include: The quantum gate sequence is divided into multiple consecutive subsequences according to the execution order of the quantum gates; When the length of the last subsequence is less than a preset gate number threshold, the last subsequence is merged into the previous subsequence; By combining spatial blocks with time slices, a set of spatiotemporal sub-blocks is obtained.

6. The quantum circuit fidelity optimization method according to claim 1, characterized in that, The pre-calculation of the compilation cost for each spatiotemporal sub-block on a single quantum processing unit includes: An initial mapping is generated based on the physical bit coherence time, gate error rate, and internal coupling graph of the quantum processing unit; For cases where the two-bit gate does not satisfy the adjacency constraint, a swap gate is inserted, and the mapping relationship between logical bits and physical bits is updated; The idle time of physical bits is calculated based on the compiled gate execution timing, and the decoherence cost is accumulated.

7. The quantum circuit fidelity optimization method according to any one of claims 1 to 6, characterized in that, It also includes a dynamic recompiling step, which includes: Real-time acquisition of noise parameters and resource status of each quantum processing unit; When a preset trigger condition is detected, the queue of spatiotemporal sub-blocks that have not yet been executed is frozen; The affected spatiotemporal sub-blocks were re-optimized based on the updated noise parameters and resource status; The execution scheme switches to a new one at the natural synchronization point after the current spacetime sub-block finishes execution.

8. A quantum circuit fidelity optimization system, characterized in that, Using the method of any one of claims 1 to 7, the system comprises: The data acquisition module is used to acquire the hardware parameters of the quantum circuit and the quantum processing unit cluster; The preprocessing module is used to standardize quantum circuits and decompose multi-qubit gates; The Unified Fidelity Cost Model module is used to construct unified cost models for single-bit gates, two-bit gates, swapping gates, quantum teleportation, and decoherence. The spatiotemporal joint segmentation module is used to perform spatial and temporal segmentation of quantum circuits to generate a set of spatiotemporal sub-blocks; The block cost pre-computation module is used to pre-compute the execution cost of each spatiotemporal sub-block on a single quantum processing unit and the partitioning cost on two quantum processing units; The cross-block collaborative global optimization module is used to globally optimize the execution scheme of each spatiotemporal sub-block based on the cross-block joint cost; The results output module is used to output quantum circuit mapping results, swap gate insertion results, cross-quantum processing unit state transfer scheduling results, and performance evaluation results.

9. A computer device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the method as described in any one of claims 1-7.

10. A storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the method as described in any one of claims 1-7.

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