A signal readout method and apparatus for a lateral resistance based hall device array
By changing the free magnetic layer flip angle of the Hall effect device through spin orbital moment and setting the Hall resistance value, and by summing the voltage or current through series or parallel Hall signal terminals, the problem of complex current source matching and high power consumption in high-density, low-power memory calculation of traditional Hall effect device arrays is solved, and the effect of simplifying the control circuit and reducing the circuit area is achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- THE HONG KONG UNIV OF SCI & TECH
- Filing Date
- 2026-01-16
- Publication Date
- 2026-06-09
AI Technical Summary
Traditional Hall effect device arrays suffer from complex current source matching and high power consumption in high-density, low-power in-memory computing, resulting in complex and costly control circuits.
By changing the free magnetic layer flip angle of the Hall effect device through spin orbital moment, the Hall resistance value is set, and voltage or current summation is achieved through series or parallel connection of Hall signal terminals, simplifying the control circuit design.
It achieves current-induced magnetization reversal under shunt conditions, reduces circuit area, simplifies circuit design of multi-Hall effect devices, and supports high-density, low-power in-memory computing.
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Figure CN122177174A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of circuit technology, and in particular to a signal readout method and apparatus based on a Hall effect device array with lateral resistance. Background Technology
[0002] Hall effect electronic devices are based on the Hall effect (which has lateral resistance). R xy A Hall resistor (also known as a transverse Hall voltage) can generate a transverse Hall voltage under an external magnetic field and has transverse resistance. R xy Therefore, they are widely used in sensing, measurement, and other fields. However, traditional devices... R xy The smaller size results in a low readout signal amplitude, making it unsuitable for direct use in high-density, low-power in-memory computing. In recent years, research into new materials has significantly improved... R xy This makes Hall effect-based device arrays feasible in the field of computing.
[0003] When using Hall effect device arrays to perform multiply-accumulate calculations, an intuitive approach is to sum the Hall voltages of multiple devices in series. However, the inventors of this application recognize a significant technical drawback in this voltage-based summation scheme. To ensure the lateral voltage of each Hall effect device... V xy_i = R xy_i · I x_i For the input current to be accurately and linearly summed, it must be guaranteed that the input current flowing through each device is constant. I x_i It is strictly controlled. This typically requires equipping each device in the array with an independent, precisely matched current source. In large-scale arrays requiring high-density integration, providing a large number of matched current sources makes the peripheral control circuitry extremely complex, power-consuming, and costly, thus severely hindering the practical application of this technology. Summary of the Invention
[0004] The main objective of this application is to propose a signal readout method, apparatus, electronic device, and storage medium based on a Hall effect device array with lateral resistance, so as to simplify the circuit of the multi-Hall effect device and provide a corresponding signal readout scheme.
[0005] To achieve the above objectives, one aspect of this application proposes a signal readout method based on a Hall device array with lateral resistance. The Hall device array includes a plurality of Hall effect devices. Each Hall effect device has two power supply terminals along the x-direction for supplying electrical energy to the Hall effect region, and at least one Hall signal terminal along the y-direction for outputting a Hall signal. The x-direction and y-direction are perpendicular to each other. Each Hall effect device has a free magnetic layer with perpendicular magnetic anisotropy. The method includes the following steps: By using spin orbital moment to change the flip angle of the free magnetic layer of at least one of the Hall effect devices, the Hall resistance value of the corresponding Hall effect device is set to the desired target value; Connect the Hall signal terminals of several Hall effect devices in series and read the summed voltage; The Hall signal terminals of several Hall effect devices are connected in parallel, and the summed current is read.
[0006] In some embodiments, changing the flip angle of the free magnetic layer of at least one Hall effect device using spin orbital moments includes the following steps: The magnetization direction of the free magnetic layer of at least one Hall effect device is non-volatilely programmed using spin orbital moments to change the flip angle of the free magnetic layer.
[0007] In some embodiments, connecting the Hall signal terminals of a plurality of Hall effect devices in series and reading the summed voltage includes the following steps: Along the x-direction, let the input current of each of the Hall effect devices be... The two ends of the input are equal in size but opposite in direction; The Hall effect devices are connected in series along the y-direction, and the total Hall voltage obtained by summing them is then read. V xy_total = ; in, R xy，i It is the current Hall resistance value of the i-th Hall effect device.
[0008] In some embodiments, the method further includes the following steps: Utilizing longitudinal input current and horizontal output voltage V xy_total Implement matrix multiplication and addition in a neural network; The expression for the multiplication-addition method is: Y= ; Where Y is the result of the multiplication-addition method. G These are the weights of each neuron in the neural network, and each weight corresponds to a Hall resistance value. ; X It is the input to the neural network.
[0009] In some embodiments, connecting the Hall signal terminals of a plurality of Hall effect devices in parallel and reading the summed current includes the following steps: An equal positive and negative voltage ±½ is applied along the x-direction to the power supply terminal of the Hall effect device. V in_i ; The relationship between the current and the input voltage, which determines the input direction, is as follows: V in_i ; The Hall effect devices are connected in parallel along the y-direction, and the total Hall current obtained by measuring any of the Hall signal terminals and summing the readings is: I xy_total = ; in, I xy_total The total Hall current is... The weights of each neuron in the neural network are... Let be the input voltage of the i-th Hall effect device. The current Hall resistance value of the i-th Hall effect device. Let be the resistance across the i-th Hall effect device in the x-direction. Let be the resistance at both ends of the i-th Hall effect device in the y-direction; When a clamping voltage is applied to the Hall signal terminal V c If it is determined that the Hall signal terminal being measured is not ground, then I xy_total = ;in, The clamping voltage of the i-th Hall effect device is given.
[0010] In some embodiments, the method further includes the following steps: The total Hall current is used to perform matrix multiplication and addition operations in the neural network.
[0011] In some embodiments, the free magnetic layer is any one of a heavy metal layer, a ferromagnetic layer, or a magnetic topological insulator.
[0012] To achieve the above objectives, another aspect of this application proposes a signal readout device based on a Hall device array with lateral resistance. The Hall device array includes a plurality of Hall effect devices. Each Hall effect device has two power supply terminals along the x-direction for supplying electrical energy to the Hall effect region, and at least one Hall signal terminal along the y-direction for outputting a Hall signal. The x-direction and y-direction are perpendicular to each other. Each Hall effect device has a free magnetic layer with perpendicular magnetic anisotropy. The device includes: A resistance setting unit is used to change the flip angle of the free magnetic layer of at least one of the Hall effect devices by using spin orbital moment, thereby setting the Hall resistance value of the corresponding Hall effect device to the desired target value. A voltage reading unit is used to connect the Hall signal terminals of several Hall effect devices in series and read the summed voltage. A current reading unit is used to connect the Hall signal terminals of several Hall effect devices in parallel and read the summed current.
[0013] To achieve the above objectives, another aspect of this application provides an electronic device, which includes a memory and a processor. The memory stores a computer program, and the processor executes the computer program to implement the above-described method.
[0014] To achieve the above objectives, another aspect of the embodiments of this application proposes a computer-readable storage medium storing a computer program that, when executed by a processor, implements the above-described method.
[0015] To achieve the above objectives, another aspect of this application provides a computer program product, including a computer program that, when executed by a processor, implements the above-described method.
[0016] The embodiments of this application include at least the following beneficial effects: This application provides a signal readout method, apparatus, electronic device, and storage medium based on a Hall effect device array with lateral resistance. This application utilizes a spin orbital moment to change the flip angle of the free magnetic layer of at least one Hall effect device, thereby setting the Hall resistance value of the corresponding Hall effect device to a desired target value. The Hall signal terminals of several Hall effect devices are connected in series to read the summed voltage; the Hall signal terminals of several Hall effect devices are connected in parallel to read the summed current. The Hall effect device of this application can achieve current-induced out-of-plane magnetization reversal under shunt conditions. This reversal can be achieved not only when the lateral terminals are suspended but also when current flow is allowed at the lateral terminals (shunt). This reversal can be achieved through a spin orbital moment (SOT), and the flip angle can change the resistance value, thereby reducing the need for Hall effect devices with different resistance values, i.e., reducing the circuit area. Furthermore, this application also implements series connection of the Hall signal terminals of multiple Hall effect devices to achieve voltage summation, or parallel connection to achieve current summation, thereby realizing matrix multiplication and addition operations in the Hall effect device array. Attached Figure Description
[0017] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0018] Figure 1 A schematic flowchart illustrating a signal readout method based on a Hall effect device array with lateral resistance, provided in an embodiment of this application; Figure 2 This is a schematic diagram of the out-of-plane magnetization reversal of the power supply terminal when current is allowed to flow, provided in an embodiment of this application. Figure 3 A schematic diagram of the transverse current in the Hall effect device provided in the embodiments of this application; Figure 4 A schematic diagram showing the connection of multiple Hall effect devices connected in series to achieve voltage summation in an embodiment of this application; Figure 5 This application provides a schematic diagram of a connection for summing currents by connecting the Hall signal terminals of multiple Hall effect devices in parallel, as shown in the embodiment of the present application. Figure 6 A schematic diagram showing another connection of multiple Hall effect devices connected in parallel to achieve current summation, provided in an embodiment of this application; Figure 7 A schematic diagram of a signal readout device based on a Hall effect device array with lateral resistance, provided for an embodiment of this application; Figure 8 This is a schematic diagram of the hardware structure of an electronic device provided in an embodiment of this application. Detailed Implementation
[0019] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit it. In the following description, when referring to the accompanying drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with those of this application; they are merely examples of apparatuses and methods consistent with some aspects of the embodiments of this application as detailed in the appended claims.
[0020] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit this application.
[0021] Before providing a detailed description of the embodiments of this application, some related technologies involved in the embodiments of this application will be described first, as follows: In in-memory computing applications such as neural networks, large-scale vector-matrix multiplication (MVM) operations are often required. One implementation uses an array of adjustable resistive, memory-enabled devices (memristor arrays), where the conductance (or resistance) of the devices represents the weights of the matrix. Multiplication and accumulation operations can be achieved by applying an input voltage (representing the input vector) to a row of the array and measuring the column currents, which are naturally summed according to Kirchhoff's laws. Current memristor arrays mainly include resistive switching memristors, phase-change memristors, ferroelectric memristors, and magnetoresistive memristors. While resistive switching and phase-change memristors can provide multiple resistance states, their stability is poor and there are significant differences between devices due to the resistance mechanisms of charged ion drift or phase changes. Ferroelectric memristors can operate as independent capacitors or in conjunction with the gate oxide layer of field-effect transistors, but their power consumption still needs optimization. In contrast, magnetic devices offer significant advantages in write and read speeds, non-volatility and long-term stability, and cycle life, making them highly promising for energy-efficient in-memory computing.
[0022] The embodiments of this application aim to solve the feasible circuit design of multiply-add operations based on Hall effect devices, simplify the control circuit of multiply-add operations of multi-device matrix, and provide a multi-device signal summation scheme that can be read from both voltage and current. Simultaneously, it provides a device structure that can still achieve SOT magnetization reversal under lateral terminal shunt conditions.
[0023] Reference Figure 1 This application provides a signal readout method based on a Hall device array with lateral resistance. The Hall device array includes several Hall effect devices. Each Hall effect device has two power supply terminals along the x-direction for supplying power to the Hall effect region and at least one Hall signal terminal along the y-direction for outputting Hall signals. The x-direction and y-direction are perpendicular to each other. Each Hall effect device has a free magnetic layer with perpendicular magnetic anisotropy. This method may include, but is not limited to, S100 to S120, as follows: S100: By using spin orbital moment to change the flip angle of the free magnetic layer of at least one of the Hall effect devices, the Hall resistance value of the corresponding Hall effect device is set to the desired target value. S110: Connect the Hall signal terminals of several Hall effect devices in series and read the summed voltage; S120: Connect the Hall signal terminals of several Hall effect devices in parallel and read the summation current.
[0024] Specifically, embodiments of this application relate to a method having a non-zero lateral resistance ( R xy or R yx This invention relates to a multi-port device and a readout method for predictable signal summation in a multi-device array. The device includes two power supply terminals for supplying power to the Hall effect region; and at least one Hall signal terminal for outputting a Hall signal. "Hall effect" is a broad concept here, including but not limited to physical effects that cause non-zero transverse resistance, such as the ordinary Hall effect, anomalous Hall effect, topological Hall effect, quantum Hall effect, and quantum anomalous Hall effect. The Hall signal terminal can receive or output voltage or current signals.
[0025] In one aspect, the device in this application supports current-induced out-of-plane magnetization reversal, which can be achieved not only when the lateral terminals are suspended, but also when current flow (shunting) is permitted at the lateral terminals. This reversal can be achieved through spin-orbit moment (SOT) and is applicable to material systems such as heavy metal / ferromagnetic layer structures and magnetic topological insulators.
[0026] On the other hand, the readout method of this application supports connecting multiple device Hall signal terminals in series to achieve voltage summation, or connecting them in parallel to achieve current summation, thereby realizing matrix multiplication and addition operations in the array. When using the current readout mode, it is only necessary to apply equal positive and negative voltages to the power supply terminal of each device to ensure that there is no potential difference at the center of the device, avoid parasitic currents between devices, and ensure the correctness of multiplication and addition operations.
[0027] Optionally, the step of changing the flip angle of the free magnetic layer of at least one of the Hall effect devices using spin orbital moments includes the following steps: The magnetization direction of the free magnetic layer of at least one Hall effect device is non-volatilely programmed using spin orbital moments to change the flip angle of the free magnetic layer.
[0028] For example, the spin orbital moment generated by SOT is used to non-volatilely program the magnetization direction of the ferromagnetic layer of each Hall effect device, directly changing its resistance. Set to the desired synaptic weight G By eliminating the floating restriction of lateral terminals in the traditional structure (allowing lateral current shunting), the signal terminals (y-direction) of all devices can be integrated into a simple row / column drive circuit, thereby simplifying the overall array control circuit design (from requiring 3 transistors to control the x and y direction terminals to only needing one x-direction transistor to select the device), and improving the array density and scalability.
[0029] Optionally, the step of connecting the Hall signal terminals of several Hall effect devices in series and reading the summed voltage includes the following steps: Along the x-direction, let the input current of each of the Hall effect devices be... The two ends of the input are equal in size but opposite in direction; The Hall effect devices are connected in series along the y-direction, and the total Hall voltage obtained by summing them is then read. V xy_total = ; in, R xy，i It is the current Hall resistance value of the i-th Hall effect device.
[0030] Optionally, the method further includes the following steps: Utilizing longitudinal input current and horizontal output voltage V xy_total Implement matrix multiplication and addition in a neural network; The expression for the multiplication-addition method is: Y= ; Where Y is the result of the multiplication-addition method. G These are the weights of each neuron in the neural network, and each weight corresponds to a Hall resistance value. ; X It is the input to the neural network.
[0031] Optionally, the step of connecting the Hall signal terminals of several Hall effect devices in parallel and reading the summed current includes the following steps: An equal positive and negative voltage ±½ is applied along the x-direction to the power supply terminal of the Hall effect device. V in_i ; The relationship between the current and the input voltage, which determines the input direction, is as follows: V in_i ; The Hall effect devices are connected in parallel along the y-direction, and the total Hall current obtained by measuring any of the Hall signal terminals and summing the readings is: I xy_total = ; in, I xy_total The total Hall current is... The weights of each neuron in the neural network are... Let be the input voltage of the i-th Hall effect device. The current Hall resistance value of the i-th Hall effect device. Let be the resistance across the i-th Hall effect device in the x-direction. Let be the resistance at both ends of the i-th Hall effect device in the y-direction; When a clamping voltage is applied to the Hall signal terminal V c If it is determined that the Hall signal terminal being measured is not ground, then I xy_total = ;in, The clamping voltage of the i-th Hall effect device is given.
[0032] Optionally, the method further includes the following steps: The total Hall current is used to perform matrix multiplication and addition operations in the neural network.
[0033] Optionally, the free magnetic layer may be any one of a heavy metal layer, a ferromagnetic layer, or a magnetic topological insulator.
[0034] It is understandable that the SOT shunt switching unit in a Hall effect device, as an independent magnetic programming unit, can be extracted and applied separately to other memory or logic circuits requiring non-volatile, high-speed, and low-power magnetization switching, thus expanding the technical applicability of the embodiments of this application. Furthermore, the material system of the embodiments of this application is flexible, not limited to specific heavy metal / ferromagnetic multilayer films, but also adaptable to materials with stronger spin-orbit coupling effects, such as magnetic topological insulators. This reserves space for future material upgrades to further reduce switching current density and improve device performance.
[0035] The following sections will provide a detailed description and explanation of some optional embodiments of this application, using specific application examples.
[0036] 1. Readout method for generalized Hall effect devices.
[0037] Basic components: equipped with lateral resistance R xy Devices.
[0038] like Figure 2 As shown, there are two power supply terminals along the x-direction for supplying electrical energy to the Hall effect region. Input voltage or current can be applied. The resistance between the terminals in this direction is... R x There is at least one lateral Hall signal terminal along the y-direction for outputting a Hall signal, and the resistance at both ends in this direction is... R y .
[0039] In a Hall effect device with non-zero lateral resistance, the center potential is V c A schematic diagram of the transverse current at that time is shown below. Figure 3 As shown.
[0040] Hall signal terminals can output voltage ( V xy ) or current ( I xy Hall signal terminals of multiple devices can be connected in series to achieve voltage summation, or in parallel to achieve current summation.
[0041] Voltage( V xy In readout mode: Along the x-direction, it is necessary to ensure the input current of each device. The two ends of the input are equal in magnitude but opposite in direction, for example, through a separate current source loop for each device.
[0042] like Figure 4 As shown, the total Hall voltage obtained by connecting Hall effect devices in series along the y-direction is... V xy_total= .in R xy_i This is the current Hall resistance value of each Hall device. Thus, the vertical input and horizontal output ( V xy_total This implements matrix multiplication and addition (Y= Where G is the weight of each neuron and X is the input to the neural network.
[0043] Current ( I xy In readout mode: Apply equal positive and negative voltages (±½) to the power supply terminals of each device along the x-direction. V in_i Correspondingly, the relationship between the current and the input voltage in the input direction is as follows: V in_i .
[0044] like Figure 5 As shown, the total Hall current can be obtained by connecting multiple Hall effect devices in parallel along the y-direction. I xy_total = The current measured through a signal terminal ( I xy_total This allows for the summation of the total current of multiple devices and matrix multiplication and addition operations. If the current measurement port is not grounded, i.e., a clamping voltage is applied... V c ,but I xy_total = .
[0045] Figure 6 Summation of parallel currents and Figure 5 The difference is that the directional upper and lower signal terminals are connected together, and the total current is the same. xy_total ,because Figure 5 Along the y-direction, the upper ammeter and the lower ammeter and Figure 6 The ammeters all measured the same current, I. xy_total .
[0046] 2. A SOT flip device under shunt conditions, comprising a free magnetic layer with perpendicular magnetic anisotropy; Adjacent spin-orbit moment source layers (such as heavy metal layers, magnetic topological insulators, etc.); still refer to Figure 2Input voltage or current is applied to the two power supply terminals along the x-direction; at least one signal terminal along the y-direction can be shunt to an external circuit, the shunt path has finite impedance, allowing the input current to flow out along the y-direction during the SOT current-induced reversal; under shunt conditions, controllable reversal of out-of-plane magnetization can still be achieved through the SOT.
[0047] The embodiments of this application are based on the mechanism of SOT-induced magnetic reversal caused by current generation, which can regulate R xy The size of R, for example, any value between plus or minus 600 ohms (different sizes of R will be obtained depending on the angle of flipping). xy Thus R xy This allows for different weights to be represented, enabling matrix multiplication and addition in neural networks. Traditional methods measure Hall voltage along the y-direction, thus avoiding current shunting. This application's embodiment utilizes the principle of current shunting along the y-direction to achieve current-induced magnetization reversal.
[0048] In summary, the embodiments of this application include the following key technical solutions: (1) A series readout scheme based on voltage summation, where each device is equipped with an independent, matched current source or other methods are used to insulate the ports of each transversely connected device. They came to seek peace.
[0049] (2) Parallel readout scheme for current summation: By applying a symmetrical voltage input (e.g., +V / -V), the output current is directly summed. To implement vector-matrix multiplication and addition.
[0050] (3) The device that enables magnetic reversal by current can be realized under shunt conditions.
[0051] The embodiments of this application include at least the following beneficial effects: The Hall effect device array of this application is particularly suitable for implementing synaptic layers in neural networks, enabling high-energy-efficiency in-memory computation (computation is performed within memory). Specific implementation methods and their effects are as follows: (1) In terms of weight programming and storage: the spin orbital moment generated by SOT is used to non-volatilely program the magnetization direction of the ferromagnetic layer of each Hall effect device, and the resistance is directly set. Set to the desired synaptic weight G By eliminating the floating restriction of lateral terminals in the traditional structure (allowing lateral current shunting), the signal terminals (y-direction) of all devices can be integrated into a simple row / column drive circuit, thereby simplifying the overall array control circuit design (from requiring 3 transistors to control the x and y direction terminals to only needing one x-direction transistor to select the device), and improving the array density and scalability.
[0052] (2) In terms of inference computation (signal readout): During the inference process, the input vector represents... Vi The analog voltage signal is synchronously applied to the corresponding row line of the array. Each synaptic unit will generate a signal corresponding to the input voltage of that row. Vi and its storage conductivity Gi Proportional transverse Hall current Iij=Vi×Gij Thanks to the voltage input-current summation readout mode supported by this application embodiment, the currents of all cells in the same column are naturally summed at the end of the column lines, directly yielding the corresponding output current for that column. Ij=Σ(Vi×Gij) This process directly and efficiently performs vector-matrix multiplication, and the summation result is deterministic, avoiding errors and power consumption caused by digital conversion, and realizing predictable low-power analog computing.
[0053] (3) Regarding the flexibility of devices and systems: The core of this application's embodiments, namely the SOT shunt switching unit, can be separated as an independent magnetic programming unit and applied separately to other memory or logic circuits that require non-volatile, high-speed, and low-power magnetization switching, thus expanding the technical applicability of this application's embodiments. Simultaneously, the material system of this application's embodiments is flexible, not limited to specific heavy metal / ferromagnetic multilayer films, but also adaptable to materials with stronger spin-orbit coupling effects, such as magnetic topological insulators. This reserves material upgrade space for future further reductions in switching current density and improvements in device performance.
[0054] In summary, the embodiments of this application efficiently integrate the storage of synaptic weights of neural networks with simulated multiply-accumulate operations at the physical level through the above specific methods, providing a practical hardware solution for realizing a high-density, low-power in-memory computing architecture.
[0055] Reference Figure 7 This application also provides a signal readout device based on a Hall effect device array with lateral resistance, which can realize the above-mentioned signal readout method based on a Hall effect device array with lateral resistance. The device includes: The Hall device array includes several Hall effect devices. Each Hall effect device has two power supply terminals along the x-direction for supplying electrical energy to the Hall effect region, and at least one Hall signal terminal along the y-direction for outputting Hall signals. The x-direction and y-direction are perpendicular to each other. Each Hall effect device has a free magnetic layer with perpendicular magnetic anisotropy. The device includes: A resistance setting unit is used to change the flip angle of the free magnetic layer of at least one of the Hall effect devices by using spin orbital moment, thereby setting the Hall resistance value of the corresponding Hall effect device to the desired target value. A voltage reading unit is used to connect the Hall signal terminals of several Hall effect devices in series and read the summed voltage. A current reading unit is used to connect the Hall signal terminals of several Hall effect devices in parallel and read the summed current.
[0056] It is understood that the content of the above method embodiments is applicable to the present device embodiments. The specific functions implemented by the present device embodiments are the same as those of the above method embodiments, and the beneficial effects achieved are also the same as those achieved by the above method embodiments.
[0057] This application also provides an electronic device, which includes a memory and a processor. The memory stores a computer program, and the processor executes the computer program to implement the method of this application. This electronic device can be any smart terminal, including tablet computers, in-vehicle computers, etc.
[0058] It is understood that the content of the above method embodiments is applicable to the device embodiments. The specific functions implemented by the device embodiments are the same as those of the methods of this application, and the beneficial effects achieved are the same as those achieved by the methods of this application.
[0059] Figure 8 The hardware structure of an electronic device according to another embodiment is illustrated. The electronic device includes: The processor 101 can be implemented using a general-purpose CPU (Central Processing Unit), microprocessor, application-specific integrated circuit (ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the technical solutions provided in the embodiments of this application. The memory 102 can be implemented as a read-only memory (ROM), static storage device, dynamic storage device, or random access memory (RAM). The memory 102 can store the operating system and other applications. When the technical solutions provided in the embodiments of this specification are implemented through software or firmware, the relevant program code is stored in the memory 102 and is called and executed by the processor 101. Input / output interface 103 is used to implement information input and output; The communication interface 104 is used to enable communication and interaction between this device and other devices. Communication can be achieved through wired means (such as USB, network cable, etc.) or wireless means (such as mobile network, WIFI, Bluetooth, etc.). Bus 105 transmits information between various components of the device (e.g., processor 101, memory 102, input / output interface 103, and communication interface 104); The processor 101, memory 102, input / output interface 103 and communication interface 104 are connected to each other within the device via bus 105.
[0060] This application also provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the method of this application.
[0061] It is understood that the content of the above method embodiments is applicable to this storage medium embodiment. The specific functions implemented in this storage medium embodiment are the same as those in the above method embodiments, and the beneficial effects achieved are also the same as those achieved in the above method embodiments.
[0062] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the above-described method.
[0063] Memory, as a non-transitory computer-readable storage medium, can be used to store non-transitory software programs and non-transitory computer-executable programs. Furthermore, memory may include high-speed random access memory, and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some embodiments, memory may optionally include memory remotely located relative to the processor, and these remote memories can be connected to the processor via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.
[0064] The embodiments described in this application are for the purpose of more clearly illustrating the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided by the embodiments of this application. As those skilled in the art will know, with the evolution of technology and the emergence of new application scenarios, the technical solutions provided by the embodiments of this application are also applicable to similar technical problems.
[0065] Those skilled in the art will understand that the technical solutions shown in the figures do not constitute a limitation on the embodiments of this application, and may include more or fewer steps than shown, or combine certain steps, or different steps.
[0066] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.
[0067] Those skilled in the art will understand that all or some of the steps in the methods disclosed above, as well as the functional modules / units in the systems and devices, can be implemented as software, firmware, hardware, or suitable combinations thereof.
[0068] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.
[0069] It should be understood that in this application, "at least one (item)" means one or more, and "more than" means two or more. "And / or" is used to describe the relationship between related objects, indicating that three relationships can exist. For example, "A and / or B" can represent three cases: only A exists, only B exists, and both A and B exist simultaneously, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one (item) of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one (item) of a, b, or c can represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, and c can be single or multiple.
[0070] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of the units described above is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.
[0071] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.
[0072] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.
[0073] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes multiple instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned storage medium includes various media capable of storing programs, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.
[0074] The preferred embodiments of the present application have been described above with reference to the accompanying drawings, but this does not limit the scope of the claims of the present application. Any modifications, equivalent substitutions, and improvements made by those skilled in the art without departing from the scope and substance of the embodiments of the present application shall be within the scope of the claims of the present application.
Claims
1. A signal readout method based on a Hall effect device array with lateral resistance, characterized in that, The Hall device array includes several Hall effect devices. Each Hall effect device has two power supply terminals along the x-direction for supplying electrical energy to the Hall effect region, and at least one Hall signal terminal along the y-direction for outputting Hall signals. The x-direction and y-direction are perpendicular to each other. Each Hall effect device has a free magnetic layer with perpendicular magnetic anisotropy. The method includes the following steps: By using spin orbital moment to change the flip angle of the free magnetic layer of at least one of the Hall effect devices, the Hall resistance value of the corresponding Hall effect device is set to the desired target value; Connect the Hall signal terminals of several Hall effect devices in series and read the summed voltage; The Hall signal terminals of several Hall effect devices are connected in parallel, and the summed current is read.
2. The signal readout method based on a Hall effect device array with lateral resistance according to claim 1, characterized in that, The method of changing the flip angle of the free magnetic layer of at least one Hall effect device using spin orbital moment includes the following steps: The magnetization direction of the free magnetic layer of at least one Hall effect device is non-volatilely programmed using spin orbital moments to change the flip angle of the free magnetic layer.
3. The signal readout method based on a Hall effect device array with lateral resistance according to claim 1, characterized in that, The step of connecting the Hall signal terminals of several Hall effect devices in series and reading the summed voltage includes the following steps: Along the x-direction, let the input current of each of the Hall effect devices be... The two ends of the input are equal in size but opposite in direction; The Hall effect devices are connected in series along the y-direction, and the total Hall voltage obtained by summing them is then read. V xy_total = ; in, R xy，i It is the current Hall resistance value of the i-th Hall effect device.
4. The signal readout method based on a Hall effect device array with lateral resistance according to claim 3, characterized in that, The method further includes the following steps: Utilizing longitudinal input current and horizontal output voltage V xy_total Implement matrix multiplication and addition in a neural network; The expression for the multiplication-addition method is: Y= ； Where Y is the result of the multiplication-addition method. G These are the weights of each neuron in the neural network, and each weight corresponds to a Hall resistance value. ; X It is the input to the neural network.
5. The signal readout method based on a Hall effect device array with lateral resistance according to claim 1, characterized in that, The method of connecting the Hall signal terminals of several Hall effect devices in parallel and reading the summed current includes the following steps: An equal positive and negative voltage ±½ is applied along the x-direction to the power supply terminal of the Hall effect device. V in_i ; The relationship between the current and the input voltage, which determines the input direction, is as follows: V in_i ; The Hall effect devices are connected in parallel along the y-direction, and the total Hall current obtained by measuring any of the Hall signal terminals and summing the readings is: I xy_total = ； in, I xy_total The total Hall current is... The weights of each neuron in the neural network are... Let be the input voltage of the i-th Hall effect device. The current Hall resistance value of the i-th Hall effect device. Let be the resistance across the i-th Hall effect device in the x-direction. Let be the resistance at both ends of the i-th Hall effect device in the y-direction; When a clamping voltage is applied to the Hall signal terminal V c If it is determined that the Hall signal terminal being measured is not ground, then I xy_total = ;in, The clamping voltage of the i-th Hall effect device is given.
6. The signal readout method based on a Hall effect device array with lateral resistance according to claim 5, characterized in that, The method further includes the following steps: The total Hall current is used to perform matrix multiplication and addition operations in the neural network.
7. A signal readout method for a Hall effect device array based on lateral resistance according to any one of claims 1 to 6, characterized in that, The free magnetic layer can be any one of a heavy metal layer, a ferromagnetic layer, or a magnetic topological insulator.
8. A signal readout device based on a Hall effect device array with lateral resistance, characterized in that, The Hall device array includes several Hall effect devices. Each Hall effect device has two power supply terminals along the x-direction for supplying electrical energy to the Hall effect region, and at least one Hall signal terminal along the y-direction for outputting Hall signals. The x-direction and y-direction are perpendicular to each other. Each Hall effect device has a free magnetic layer with perpendicular magnetic anisotropy. The device includes: A resistance setting unit is used to change the flip angle of the free magnetic layer of at least one of the Hall effect devices by using spin orbital moment, thereby setting the Hall resistance value of the corresponding Hall effect device to the desired target value. A voltage reading unit is used to connect the Hall signal terminals of several Hall effect devices in series and read the summed voltage. A current reading unit is used to connect the Hall signal terminals of several Hall effect devices in parallel and read the summed current.
9. An electronic device, characterized in that, The electronic device includes a memory and a processor, the memory storing a computer program, and the processor executing the computer program to implement the method as described in any one of claims 1 to 7.
10. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by a processor, it implements the method as described in any one of claims 1 to 7.