Current-sharing calibration method, current-sharing calibration circuit, and electronic device

Abstract

This application discloses a current sharing calibration method, a current sharing calibration circuit, and an electronic device. The current sharing calibration method includes: obtaining a zero-point calibration duty cycle using a first current sharing test voltage of the current sharing bus under no-load conditions and an initial zero-point calibration duty cycle to generate a first pulse width signal; adjusting the reference output voltage of the power supply regulation circuit using the first pulse width signal and the initial proportional calibration pulse width signal to obtain a first current sharing bus voltage; obtaining a proportional calibration duty cycle using a second current sharing test voltage of the current sharing bus under full-load conditions, the maximum target output current, the maximum current sharing bus voltage, and the initial proportional calibration duty cycle to generate a second pulse width signal; and adjusting the reference output voltage using the first pulse width signal and the second pulse width signal to obtain a second current sharing bus voltage. Through the above methods, the current sharing calibration method of this application can effectively balance the accuracy of the current sharing bus under both light and full load conditions.

Description

Technical Field

[0001] This application relates to the field of circuit control technology, and in particular to a current sharing calibration method, a current sharing calibration circuit, and an electronic device. Background Technology

[0002] Nowadays, with the increasing abundance of electronic devices, various industries have higher and higher requirements for the power supply performance of electronic devices, especially in power supply scenarios with high power levels such as AI (Artificial Intelligence) servers, data centers, and 5G (5th Generation Mobile Communication Technology) equipment. As the power level increases, the number of power conditioning circuits that need to be connected in parallel also increases, which in turn increases the requirements for the current sharing of each power conditioning circuit in parallel.

[0003] However, the methods used in related technologies to achieve parallel current sharing control usually employ B-value (zero point) calibration or K-value (proportional) calibration, which both suffer from insufficient calibration accuracy under light load and large deviations between the single-unit bus voltage and the target value, resulting in poor parallel current sharing performance. Summary of the Invention

[0004] The main technical problem addressed by this application is to provide a current sharing calibration method, a current sharing calibration circuit, and an electronic device, which can solve the problems of insufficient calibration accuracy under light load and large deviation between the single-machine bus voltage and the target value in the current sharing calibration method of related technologies, thus leading to poor parallel current sharing.

[0005] To solve the above-mentioned technical problems, one technical solution adopted in this application is: providing a current sharing calibration method applied to the current sharing calibration of a power supply conditioning circuit. The power supply conditioning circuit is coupled to an output bus and used to couple with a current sharing calibration circuit. The current sharing calibration circuit is coupled to a current sharing bus, and the output bus is used to couple with a load operating circuit. The current sharing calibration method includes: the current sharing calibration circuit acquiring a reference output voltage of the power supply conditioning circuit and a first current sharing test voltage on the output bus under no-load conditions; obtaining a zero-point calibration duty cycle using the first current sharing test voltage and an initial zero-point calibration duty cycle; and generating a first pulse using the zero-point calibration duty cycle. A wide-range signal is generated; the reference output voltage is adjusted using the first pulse width signal and the initial proportional calibration pulse width signal to obtain the first current sharing bus voltage; the first current sharing bus voltage is output to the current sharing bus; the second current sharing test voltage on the current sharing bus under full load is obtained; the proportional calibration duty cycle is obtained using the second current sharing test voltage, the maximum target output current, the maximum current sharing bus voltage, and the initial proportional calibration duty cycle; the second pulse width signal is generated using the proportional calibration duty cycle; the reference output voltage is adjusted using the first pulse width signal and the second pulse width signal to obtain the second current sharing bus voltage; the second current sharing bus voltage is output to the current sharing bus.

[0006] The steps of obtaining the reference output voltage of the power supply regulation circuit by the current sharing calibration circuit include: obtaining the output current of the power supply regulation circuit; multiplying the output current by a linear scaling factor and adding a linear bias factor to obtain the reference output voltage.

[0007] Before the step of obtaining the first current sharing test voltage under no-load conditions of the current sharing bus, the method further includes: obtaining an initial proportional calibration duty cycle and an initial zero-point calibration duty cycle using the maximum target output current and the maximum current sharing bus voltage; generating an initial proportional calibration pulse width signal using the initial proportional calibration duty cycle; generating an initial zero-point calibration pulse width signal using the initial zero-point calibration duty cycle; adjusting the reference output voltage using the initial proportional calibration pulse width signal and the initial zero-point calibration pulse width signal to obtain a third current sharing bus voltage; and outputting the third current sharing bus voltage to the current sharing bus.

[0008] The steps of obtaining the initial proportional calibration duty cycle and the initial zero-point calibration duty cycle using the maximum target output current and the maximum current sharing bus voltage include: obtaining the initial proportional calibration duty cycle using the maximum target output current, the maximum current sharing bus voltage, and the linear proportional coefficient; and obtaining the initial zero-point calibration duty cycle using the initial proportional calibration duty cycle, the set voltage amplitude, and the linear bias coefficient.

[0009] The step of obtaining the initial proportional calibration duty cycle using the maximum target output current, the maximum current-sharing bus voltage, and the linear scaling factor includes: processing the maximum target output current, the maximum current-sharing bus voltage, and the linear scaling factor using a first calculation function to obtain the initial proportional calibration duty cycle; wherein the formula for the first calculation function is:

[0010] Where D1 is the initial proportional calibration duty cycle, I out-max V is the maximum target output current. Ishare-max Where is the maximum current-sharing bus voltage, B is the linear proportional coefficient, K1 is the first adjustment coefficient, and K2 is the second adjustment coefficient.

[0011] The step of obtaining the initial zero-point calibration duty cycle using the initial proportional calibration duty cycle, the set voltage amplitude, and the linear bias coefficient includes: processing the initial proportional calibration duty cycle, the set voltage amplitude, and the linear bias coefficient using a second operation function to obtain the initial zero-point calibration duty cycle; wherein the formula for the second operation function is:

[0012] Wherein, the set voltage amplitude is the amplitude of the first pulse width signal, D2 is the initial zero-point calibration duty cycle, and U f The set voltage amplitude is defined as follows: A is the linear bias coefficient, K3 is the third adjustment coefficient, K4 is the fourth adjustment coefficient, and K5 is the fifth adjustment coefficient.

[0013] The step of obtaining the zero-point calibration duty cycle using the first current-sharing test voltage and the initial zero-point calibration duty cycle includes: using a third calculation function to process the first current-sharing test voltage, the initial zero-point calibration duty cycle, and the set voltage amplitude to obtain the zero-point calibration duty cycle; wherein the formula of the third calculation function is:

[0014] Among them, D 2x For the zero-point calibration duty cycle, V Ishare-test1 K is the first current sharing test voltage, and K6 is the sixth adjustment coefficient.

[0015] The step of obtaining the proportional calibration duty cycle using the second current sharing test voltage, the maximum target output current, the maximum current sharing bus voltage, and the initial proportional calibration duty cycle includes: using a fourth operation function to process the maximum target output current, the maximum current sharing bus voltage, the second current sharing test voltage, and the initial proportional calibration duty cycle to obtain the proportional calibration duty cycle; wherein, the formula of the fourth operation function is:

[0016] Among them, D 1x For the proportional calibration duty cycle, V Ishare-test2 K is the second current sharing test voltage, and K7 is the seventh adjustment coefficient.

[0017] The current sharing calibration method involves calibrating the power supply regulation circuit using a current sharing calibration circuit. This circuit includes a main control circuit, a zero-point calibration circuit, a proportional calibration circuit, and an operational amplifier circuit. The proportional calibration circuit includes a calibration switch, a fifth resistor, a second resistor, and a first capacitor. The operational amplifier circuit includes a third resistor, a fourth resistor, and an operational amplifier. The main control circuit is coupled to the zero-point calibration circuit, the control terminal of the calibration switch, and the non-inverting input terminal of the operational amplifier, and is also used to couple with the power supply regulation circuit. The first terminal of the calibration switch is coupled to the first terminal of the fifth resistor, and the second terminal of the calibration switch is coupled to the second terminal of the first capacitor and grounded. The second terminal of the fifth resistor is coupled to the first terminal of the second resistor. The first terminal of the first capacitor and the second terminal of the second resistor are coupled to the zero-point calibration circuit, the first terminal of the third resistor, the first terminal of the fourth resistor, and the inverting input terminal of the operational amplifier. The second terminal of the third resistor is grounded, and the second terminal of the fourth resistor is coupled to the output terminal of the operational amplifier and used for coupling with the current sharing bus. The steps for obtaining the initial proportional calibration duty cycle using the maximum target output current, the maximum current sharing bus voltage, and the linear proportional coefficient include: the main control circuit uses the fifth operation function to process the maximum target output current, the maximum current sharing bus voltage, the linear proportional coefficient, the second resistance value, the third resistance value, the fourth resistance value, and the fifth resistance value to obtain the initial proportional calibration duty cycle; wherein, the formula of the fifth operation function is:

[0018] Wherein, the second resistance value, the third resistance value, the fourth resistance value, and the fifth resistance value are the resistance values ​​of the second resistor, the third resistor, the fourth resistor, and the fifth resistor, respectively; D1 is the initial proportional calibration duty cycle, I out-max V is the maximum target output current. Ishare-max R1 is the maximum current-sharing bus voltage, B is the linear proportional coefficient, R2 is the second resistance value, R3 is the third resistance value, R4 is the fourth resistance value, and R5 is the fifth resistance value.

[0019] The zero-point calibration circuit includes a sixth resistor, a first resistor, and a second capacitor. The first terminal of the sixth resistor is coupled to the main control circuit. The second terminal of the sixth resistor is coupled to the first terminal of the second capacitor and the first terminal of the first resistor. The second terminal of the first resistor is coupled to the second terminal of the second resistor, the first terminal of the third resistor, the first terminal of the fourth resistor, and the inverting input terminal. The step of obtaining the initial zero-point calibration duty cycle using the initial proportional calibration duty cycle, the set voltage amplitude, and the linear bias coefficient includes: the main control circuit uses a sixth operation function to process the initial proportional calibration duty cycle, the set voltage amplitude, the linear bias coefficient, the first resistance value, the second resistance value, the third resistance value, the fourth resistance value, the fifth resistance value, and the sixth resistance value to obtain the initial zero-point calibration duty cycle; the formula for the sixth operation function is:

[0020] Wherein, the set voltage amplitude is the amplitude of the initial proportional calibration pulse width signal, the first resistance value and the sixth resistance value are the resistance values ​​of the first resistor and the sixth resistor, respectively; D2 is the initial zero-point calibration duty cycle, U f The set voltage amplitude is A, the linear bias coefficient is R1, the first resistance value is R6, and the sixth resistance value is R6.

[0021] The step of obtaining the zero-point calibration duty cycle using the first current sharing test voltage and the initial zero-point calibration duty cycle includes: the main control circuit uses a seventh operation function to process the first current sharing test voltage, the initial zero-point calibration duty cycle, the set voltage amplitude, the first resistance value, the fourth resistance value, and the sixth resistance value to obtain the zero-point calibration duty cycle; wherein, the formula of the seventh operation function is:

[0022] Among them, D 2x For the zero-point calibration duty cycle, V Ishare-test1 The voltage is the first current sharing test voltage.

[0023] The step of obtaining the proportional calibration duty cycle using the maximum target output current, the maximum current sharing bus voltage, the second current sharing test voltage, and the initial proportional calibration duty cycle includes: the main control circuit uses the eighth operation function to process the maximum target output current, the maximum current sharing bus voltage, the second current sharing test voltage, the initial proportional calibration duty cycle, the second resistance value, the third resistance value, the fourth resistance value, and the fifth resistance value to obtain the proportional calibration duty cycle; wherein, the formula of the eighth operation function is:

[0024] Among them, D 1x For the proportional calibration duty cycle, V Ishare-test2 This is the second current sharing test voltage.

[0025] The steps of the current sharing calibration circuit to obtain the reference output voltage of the power supply regulation circuit and the first current sharing test voltage of the current sharing bus under no-load conditions include: obtaining the first current sharing test voltage of the current sharing bus under no-load conditions at intervals of a first set time or a first set number of signal cycles.

[0026] The step of obtaining the second current sharing test voltage under full load condition of the current sharing bus includes: obtaining the second current sharing test voltage under full load condition of the current sharing bus at intervals of a second set time or a second set number of signal cycles.

[0027] To solve the above-mentioned technical problems, another technical solution adopted in this application is: to provide a current sharing calibration circuit, wherein the current sharing calibration circuit is coupled to the current sharing bus and is used to couple with the power supply regulation circuit; wherein the current sharing calibration circuit uses the current sharing calibration method described in any of the above claims to perform current sharing calibration on the power supply regulation circuit.

[0028] To solve the above-mentioned technical problems, another technical solution adopted in this application is: to provide an electronic device, wherein the electronic device includes a housing and a current sharing calibration circuit connected to the housing; wherein the current sharing calibration circuit is the current sharing calibration circuit as described above.

[0029] The beneficial effects of this application are as follows: Unlike the prior art, the current sharing calibration method provided in this application obtains the first current sharing test voltage of the current sharing bus under no-load conditions of the transfer bus, uses the first current sharing test voltage and the initial zero-point calibration duty cycle to obtain the zero-point calibration duty cycle, generates a first pulse width signal, and then uses the first pulse width signal and the initial proportional calibration pulse width signal to adjust the reference output voltage of the power supply regulation circuit to obtain the first current sharing bus voltage, and outputs it to the current sharing bus. Thus, by performing zero-point calibration under no-load conditions, the calibration accuracy can be effectively improved, and the deviation between the single-machine current sharing bus voltage and the target value can be reduced, so as to ensure the accuracy of the current sharing bus under light load conditions. Furthermore, by acquiring the second current sharing test voltage of the current sharing bus under full load conditions of the transfer bus, the proportional calibration duty cycle is obtained using the second current sharing test voltage, the maximum target output current, the maximum current sharing bus voltage, and the initial proportional calibration duty cycle. This generates a second pulse width signal, and the reference output voltage is adjusted using the first and second pulse width signals to obtain the second current sharing bus voltage. Thus, based on the no-load zero-point calibration, proportional calibration is further performed under full load to effectively ensure the accuracy of the current sharing bus under full load, thereby effectively balancing the accuracy of the current sharing bus under both light load and full load conditions, and improving the overall parallel current sharing efficiency. Attached Figure Description

[0030] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort, wherein: Figure 1 This is a flowchart illustrating the first embodiment of the current sharing calibration method of this application; Figure 2 This is a schematic diagram of the structure of the first embodiment of the current sharing calibration circuit and power supply regulation circuit of this application; Figure 3 This is a flowchart illustrating the second embodiment of the current sharing calibration method of this application; Figure 4 This is a schematic diagram of the structure of the current sharing calibration circuit and power supply regulation circuit of the second embodiment of this application; Figure 5 yes Figure 4 A schematic diagram of an embodiment of the current sharing calibration circuit in the diagram; Figure 6 yes Figure 3 A flowchart illustrating an embodiment of S23; Figure 7 These are schematic diagrams of the simulated waveforms of various signals corresponding to the zero-point calibration of the relevant current sharing bus; Figure 8 These are schematic diagrams of the simulated waveforms of various signals corresponding to the proportional calibration of the relevant current sharing bus; Figure 9 yes Figure 3 The simulation waveform diagrams of each signal corresponding to the current sharing calibration method in the diagram; Figure 10 This is a schematic diagram of one embodiment of the electronic device of this application. Detailed Implementation

[0031] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0032] The terms "first," "second," and "third" in this application are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first," "second," or "third" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified. All directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of this application are only used to explain the relative positional relationships and movements between components in a specific orientation (as shown in the figures). If the specific orientation changes, the directional indications also change accordingly. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or devices.

[0033] In this document, the term "implementation" means that a specific feature, structure, or characteristic described in connection with an implementation may be included in at least one implementation of this application. The appearance of this phrase in various places in the specification does not necessarily refer to the same implementation, nor is it a separate or alternative implementation mutually exclusive with other implementations. It will be explicitly and implicitly understood by those skilled in the art that the implementations described herein can be combined with other implementations.

[0034] The present application will now be described in detail with reference to the accompanying drawings and embodiments.

[0035] Please refer to the following: Figure 1 and Figure 2 ,in, Figure 1 This is a flowchart illustrating the first embodiment of the current sharing calibration method of this application. Figure 2 This is a schematic diagram of the first embodiment of the current sharing calibration circuit of this application. Specifically, it may include the following steps: S11: The current sharing calibration circuit obtains the reference output voltage of the power supply regulation circuit and the first current sharing test voltage on the current sharing bus under no-load conditions.

[0036] It is understood that the current sharing calibration method in this embodiment is specifically applied to, for example... Figure 2The first power supply regulation circuit 40 is shown to perform current sharing calibration; wherein, the first current sharing calibration circuit 30 is used to couple with the first power supply regulation circuit 40 and the first current sharing bus 401, the first power supply regulation circuit 40 is coupled to the first output bus 402, and the first output bus 402 is used to couple with the first load working circuit 403; the first current sharing calibration circuit 30 performs current sharing calibration on the first power supply regulation circuit 40 using any of the current sharing calibration methods described herein.

[0037] It is worth noting that the term "coupled" in this article refers to any direct or indirect connection. Therefore, if the article describes a first circuit coupled to a second circuit, it means that the first circuit can be directly connected to the second circuit via electrical connection or signal connection methods such as wireless transmission or optical transmission, or indirectly connected to the second circuit via other circuits or connection methods via electrical connection or signal connection.

[0038] In some embodiments, the first power supply regulation circuit 40 may be one or more of any reasonable independent power supply or energy storage circuit, such as AC power supply, DC power supply, or energy storage auxiliary power supply. It may also be one or more of the functional circuits that regulate, convert, and process signals of independent power supply or energy storage circuit. This embodiment does not limit this.

[0039] In some embodiments, the first power regulation circuit 40 may specifically include a bridge inverter circuit, a bridge rectifier circuit, a buck circuit, a boost circuit, a buck-boost circuit, or any other reasonable circuit topology, and this embodiment does not limit it in this way.

[0040] In some embodiments, the first current sharing calibration circuit 30 may specifically include any reasonable circuit unit with signal processing function, such as a control chip, a DSP (Digital Signal Processing) chip, an MCU (Micro Controller Unit) circuit, a CPU (Central Processing Unit), a microcontroller, a field-programmable gate array, a programmable logic device, discrete gate or transistor logic devices, or discrete hardware. This application does not limit this.

[0041] Specifically, the first current sharing calibration circuit 30 samples the reference output voltage from the first power supply regulation circuit 40 in real time, and samples the first current sharing test voltage from the first current sharing bus 401 when it is determined that the first output bus 402 is not under load, that is, the first load working circuit 403 is not connected to the first output bus 402, or the first load working circuit 403 is adjusted to an unloaded state.

[0042] In some embodiments, the sampling and acquisition of the first current sharing test voltage by the first current sharing calibration circuit 30 can be a constant voltage value measured from the first current sharing bus 401 by any reasonable voltage detection device such as a multimeter or voltmeter when the first bus 402 is not under load during the production line testing stage or the product trial operation stage. This application does not limit this.

[0043] In other embodiments, the sampling of the first current sharing test voltage by the first current sharing calibration circuit 30 can be achieved through one or more of any reasonable voltage sampling methods, such as voltage sensors, sampling resistors, Hall sensors, or circuit model estimation, during product operation. This can be done in response to the power-on of the first current sharing calibration circuit 30 and the first power supply regulation circuit 40, during a set period when the first output bus 402 is not under load, or in response to the absence of a load command from the host computer, or when the output current or output voltage of the first power supply regulation circuit 40 is detected to be no greater than a set threshold. The sampling can be performed in real time from the first current sharing bus 401, or the dynamic voltage value can be obtained at set intervals of a set duration or a set number of signal cycles. This is to facilitate subsequent dynamic current sharing calibration and achieve better current sharing. This application does not limit this method.

[0044] In some embodiments, the first load working circuit 403 may be a functional circuit in any reasonable power-consuming device with high requirements for current sharing accuracy, such as a server, communication equipment, or battery management system. This application does not limit this.

[0045] It's worth noting that the load states of electronic circuits typically include: no-load, light-load, full-load, and overload, each corresponding to different load rates. Load rate refers to the ratio between the actual load carried by an electrical device or system and its rated capacity, usually expressed as a percentage. Its definition and optimization range differ depending on the application scenario. Load factor = Actual load / Rated load * 100%, used to measure equipment utilization. Too low a load factor results in wasted capacity, while too high a load factor exacerbates wear and shortens lifespan. No-load refers to an actual load of 0; full load, also known as full load, corresponds to a load factor of 100%.

[0046] In addition, the host computer typically refers to a computer system with powerful computing and data processing capabilities. It is responsible for monitoring the entire control system, issuing commands, acquiring data, processing and analyzing data, and facilitating user interaction. As the "brain" of the system, the host computer can handle complex algorithms, store long-term data, and provide a graphical user interface for operation.

[0047] A lower-level machine refers to a device or controller / control circuit that is directly connected to hardware such as sensors and actuators in a control system. It is responsible for executing specific control commands issued by the upper-level machine, such as outputting switch signals, adjusting analog quantities, and acquiring data. Lower-level machines typically perform simple logical judgments and real-time control tasks.

[0048] S12: Obtain the zero-point calibration duty cycle using the first current sharing test voltage and the initial zero-point calibration duty cycle.

[0049] Understandably, in order to ensure the overall current sharing of the power supply output of each first power supply regulation circuit 40, the initial zero-point calibration duty cycle set during the power-on and startup phase of the first current sharing calibration circuit 30 and the first power supply regulation circuit 40 is obtained by fitting characteristic data obtained from simulation experiments or production line tests, or the initial zero-point calibration duty cycle is calculated by relevant circuit parameters in the first current sharing calibration circuit 30.

[0050] The zero-point calibration duty cycle is obtained by processing the initial zero-point calibration duty cycle and the currently acquired first current sharing test voltage using a preset calculation function or rule program.

[0051] S13: Generate the first pulse width signal by calibrating the duty cycle using the zero point.

[0052] Understandably, the duty cycle refers to the ratio of the duration of the high level in a pulse signal to the total cycle time. Once the zero-point calibration duty cycle is obtained, the first pulse width signal can be generated by modulating it using the corresponding signal modulation rules.

[0053] In some embodiments, the first pulse width signal and other pulse width signals herein may be one or more of any reasonable control signals such as PWM (Pulse Width Modulation) signal or PFM (Pulse Frequency Modulation) signal, and this application does not limit them.

[0054] S14: The reference output voltage of the power supply regulation circuit is adjusted using the first pulse width signal and the initial proportional calibration pulse width signal to obtain the first current sharing bus voltage.

[0055] Similarly, to ensure the overall current sharing of the power supply output of each first power supply regulation circuit 40, the initial proportional calibration duty cycle set during the power-on and startup phase of the first current sharing calibration circuit 30 and the first power supply regulation circuit 40 is obtained by fitting characteristic data obtained from simulation experiments or production line tests, or the initial proportional calibration duty cycle is calculated by relevant circuit parameters in the first current sharing calibration circuit 30, and then the initial proportional calibration pulse width signal is modulated using the initial proportional calibration duty cycle.

[0056] Furthermore, the first current sharing calibration circuit 30 samples and acquires the reference output voltage of the first power supply regulation circuit 40 in real time, or the output current or output voltage of the first power supply regulation circuit 40, so as to adjust the output current or output voltage to obtain the reference output voltage. Then, the initial proportional calibration pulse width signal and the currently modulated first pulse width signal are used to adjust one or more of any reasonable parameters such as amplitude, phase, and zero crossing point of the reference output voltage to obtain the first current sharing bus voltage.

[0057] S15: Output the voltage of the first current sharing bus to the current sharing bus.

[0058] The first current sharing calibration circuit 30 outputs the first current sharing bus voltage to the first current sharing bus 401, so as to achieve zero-point calibration through the first current sharing bus 401.

[0059] S16: Obtain the second current sharing test voltage on the current sharing bus under full load conditions.

[0060] Furthermore, when the first current sharing calibration circuit 30 determines that the first current sharing bus 401 is fully loaded, that is, when the first load working circuit 403 is connected to the first output bus 402, or when the first load working circuit 403 is adjusted to a full load state, the first current sharing calibration circuit 30 samples and obtains the second current sharing test voltage from the first current sharing bus 401.

[0061] Similarly, the sampling and acquisition of the second current sharing test voltage by the first current sharing calibration circuit 30 can be specifically a constant voltage value measured from the first current sharing bus 401 when the first output bus 402 is under load, obtained by any reasonable voltage detection device such as a multimeter or voltmeter during the production line testing stage or the product trial operation stage. Alternatively, it can be one or more of any reasonable voltage sampling methods such as voltage sensor, sampling resistor, Hall sensor or circuit model estimation during the product operation stage. In response to the power-on set time of the first current sharing calibration circuit 30 and the first power conditioning circuit 40, or in response to the load command sent by the host computer, or when the output current or output voltage of the first power conditioning circuit 40 is detected to be greater than the set threshold, the sampling and acquisition can be carried out in real time, or the dynamic voltage value can be acquired at set intervals or a set number of signal cycles, so as to facilitate subsequent dynamic current sharing calibration and achieve better current sharing. This application does not limit this.

[0062] S17: The proportional calibration duty cycle is obtained using the second current sharing test voltage, the maximum target output current, the maximum current sharing bus voltage, and the initial proportional calibration duty cycle.

[0063] Understandably, in order to meet the operating requirements of the first load operating circuit 403, the output voltage provided to the first load operating circuit 403 needs to be within a specific voltage range, thereby setting the maximum target output current and the maximum current sharing bus voltage.

[0064] Specifically, the first current sharing calibration circuit 30 uses a preset operation function or rule program to process the preset maximum target output current, maximum current sharing bus voltage, initial proportional calibration duty cycle, and the currently sampled second current sharing test voltage to obtain the proportional calibration duty cycle.

[0065] It is worth noting that when the second current sharing test voltage is a constant voltage value, the proportional calibration duty cycle also corresponds to a constant value; while when the second current sharing test voltage is a dynamic voltage value, the proportional calibration duty cycle is a dynamically adjustable value, so that dynamic proportional calibration can be performed more effectively by dynamically adjusting the proportional calibration duty cycle, thereby achieving better current sharing.

[0066] S18: Generate a second pulse width signal by calibrating the duty cycle using a proportional method.

[0067] When the proportional calibration duty cycle is obtained, the second pulse width signal is generated by modulating the signal using the set signal modulation rules.

[0068] S19: The reference output voltage is adjusted using the first pulse width signal and the second pulse width signal to obtain the second current sharing bus voltage.

[0069] The initial proportional calibration pulse width signal is replaced with a second pulse width signal to adjust one or more of the following reasonable parameters, such as amplitude, phase, and zero crossing point, of the reference output voltage of the first power supply regulation circuit 40, in conjunction with the first pulse width signal, so as to obtain the second current sharing bus voltage.

[0070] S110: Output the second current sharing bus voltage to the current sharing bus.

[0071] The first current sharing calibration circuit 30 outputs the second current sharing bus voltage to the first current sharing bus 401, so as to further achieve proportional calibration through the first current sharing bus 401.

[0072] It is worth noting that this current sharing calibration refers to the process of adjusting the output of each parallel unit in a power electronic system operating in parallel, so as to make its current or power distribution as uniform as possible.

[0073] Specifically, there are at least two first power supply regulation circuits 40, and each first power supply regulation circuit 40 is equipped with a first current sharing calibration circuit 30, so that each first current sharing calibration circuit 30 independently performs current sharing calibration on the power supply output of the corresponding first power supply regulation circuit 40 to obtain a first pulse width signal and a second pulse width signal.

[0074] Therefore, when each of the first power supply regulation circuits 40 operates in parallel to supply power to the first load working circuit 403, each of the first current sharing calibration circuits 30 can respectively use the corresponding calibrated first pulse width signal and second pulse width signal to adjust the reference output voltage of each of the corresponding first power supply regulation circuits 40, so as to obtain each of the second current sharing bus voltages, and respectively output each of the second current sharing bus voltages to the first current sharing bus 401 to achieve current sharing.

[0075] At the same time, the bus output current or power obtained by each first power supply regulation circuit 40 after current sharing calibration will be uniformly provided to the first load working circuit 403 to drive the first load working circuit 403 to work.

[0076] The above scheme effectively improves calibration accuracy and reduces the deviation between the single-unit current sharing bus voltage and the target value by performing zero-point calibration under no-load conditions, thus ensuring the accuracy of the current sharing bus under light load conditions. Furthermore, by acquiring the second current sharing test voltage on the first current sharing bus 401 under full-load conditions of the first output bus 402, a proportional calibration duty cycle is obtained using this second current sharing test voltage, the maximum target output current, the maximum current sharing bus voltage, and the initial proportional calibration duty cycle. This generates a second pulse width signal, which is then used to adjust the reference output voltage to obtain the current sharing bus voltage. This allows for further proportional calibration under full load conditions on top of no-load zero-point calibration, effectively ensuring the accuracy of the current sharing bus under full load conditions. This effectively balances the accuracy of the current sharing bus under both light and full load conditions, thereby improving the overall parallel current sharing efficiency. Through a two-stage closed-loop regulation mechanism of no-load zero-point calibration and full-load proportional calibration, high-precision compensation of the output characteristics of the first power supply regulation circuit 40 is achieved, which effectively solves the problem of insufficient calibration accuracy of the current sharing bus under light load, and is of great significance for multiple parallel current sharing applications.

[0077] Furthermore, in some embodiments, S12 may specifically include: multiplying the output current by a linear scaling factor and adding a linear bias factor to obtain a reference output voltage.

[0078] Understandably, this reference output voltage With output current The relationship is usually linear. When its coefficients are set as a linear proportionality coefficient A and a linear bias coefficient B, then: .

[0079] Please see Figure 3 and Figure 4 ,in, Figure 3 This is a flowchart illustrating the second embodiment of the current sharing calibration method of this application. Figure 4This is a schematic diagram of the structure of the current sharing calibration circuit and power supply regulation circuit of the second embodiment of this application. The current sharing calibration method of this embodiment is... Figure 1 A detailed implementation flowchart of the current sharing calibration method is shown, which specifically includes the following steps: S21: Obtain the output current of the power supply regulation circuit.

[0080] It is understood that, in this embodiment, the current sharing calibration method may specifically be a second current sharing calibration circuit 50, such as... Figure 4 The second power supply regulation circuit 60 shown implements current sharing calibration. The second power supply regulation circuit 60 includes an energy storage sub-circuit 62 coupled to each other and at least two voltage conversion sub-circuits 61. The energy storage sub-circuit 62 includes at least two supercapacitors Cs connected in parallel and a bridging capacitor ECap. The voltage conversion sub-circuit 61 includes an upper switch Qs, a lower switch Qx and an energy storage inductor Lx.

[0081] In this configuration, the first terminals of each supercapacitor Cs are mutually coupled and connected to the first terminals of each energy storage inductor Lx and the first terminal of the bridging capacitor ECap. The second terminals of each supercapacitor Cs are mutually coupled and connected to the first terminals of each lower-side switching transistor Qx, and are used for coupling with the second output bus 602. The second terminal of each energy storage inductor Lx is coupled to the first terminals of its corresponding upper-side switching transistor Qs and the second terminals of the lower-side switching transistor Qx. The second terminal of each upper-side switching transistor Qs is coupled to the second terminal of the bridging capacitor ECap and the first terminal of each lower-side switching transistor Qx. The first terminal of each second current sharing calibration circuit 50 is used to be coupled to the second output bus 602. The second terminal of each second current sharing calibration circuit 50 is used to be coupled to the second current sharing bus 601. The second output bus 602 is coupled to the second load working circuit 603. The control terminal of each upper switch Qs and the control terminal of each lower switch Qx are used to be coupled to the drive control circuit (not shown in the figure) so as to be controlled by the drive control signal sent by the drive control circuit to turn on or off the connection between its first terminal and the second terminal.

[0082] In some embodiments, the upper switch Qs, the lower switch Qx, and other switches mentioned herein may specifically be one of a MOSFET (Metal-Oxide-Semiconductor-Field Effect-Transistor), a transistor, a thin-film transistor, a field-effect transistor, or any other reasonable switch, and this application does not limit this.

[0083] In other embodiments, the voltage conversion sub-circuit 61 may be a bridge inverter circuit, a bridge rectifier circuit, a half-bridge buck-boost circuit, a full-bridge buck-boost circuit, or any other reasonable circuit topology. This embodiment does not limit this.

[0084] Specifically, the second current sharing calibration circuit 50 is used to sample and obtain the output current I from the second power supply regulation circuit 60, such as the second terminal of the corresponding upper-mounted switch Qs. out .

[0085] S22: Multiply the output current by the linear scaling factor and add the linear bias factor to obtain the reference output voltage.

[0086] Understandably, the reference output voltage V Iout With output current I out The relationship is usually linear. When its coefficients are set as a linear proportionality coefficient B and a linear bias coefficient A, then: .

[0087] S23: Obtain the initial proportional calibration duty cycle and the initial zero-point calibration duty cycle using the maximum target output current and the maximum current sharing bus voltage.

[0088] Understandably, in order to meet the operating requirements of the second load operating circuit 603, the output voltage supplied to the second load operating circuit 603 needs to be within a specific voltage range, and the maximum target output current I is thus determined. out-max Maximum current-sharing bus voltage V Ishare-max For example, when the target output current of the second power supply regulation circuit 60 is 0-Imax, the corresponding target current sharing bus voltage is 0-Vmax.

[0089] The second current sharing calibration circuit 50 uses a preset operation function or rule procedure to calculate the preset maximum target output current I. out-max and the maximum current-sharing bus voltage V Ishare-max The initial proportional calibration duty cycle is obtained through calculation. And the initial zero-point calibration duty cycle D2.

[0090] It is worth noting that this initial proportional calibration duty cycle The duty cycle D2 of the initial zero-point calibration actually corresponds to the initial setting value of the second current sharing calibration circuit 50 and the second power supply regulation circuit 60 when the second outgoing bus 602 is unloaded during the power-on and start-up phase.

[0091] S24: Generate the initial proportional calibration pulse width signal using the initial proportional calibration duty cycle.

[0092] After obtaining the initial proportional calibration duty cycle At that time, the initial proportional calibration pulse width signal is generated by modulating the signal using the set signal modulation rules.

[0093] S25: Generate the initial zero-point calibration pulse width signal using the initial zero-point calibration duty cycle.

[0094] When the initial zero-point calibration duty cycle D2 is obtained, the initial zero-point calibration pulse width signal is generated by modulating the signal using the set signal modulation rules.

[0095] S26: The reference output voltage is adjusted using the initial proportional calibration pulse width signal and the initial zero-point calibration pulse width signal to obtain the third current sharing bus voltage.

[0096] The reference output voltage V of the currently acquired second power supply regulation circuit 60 is obtained by using the initial proportional calibration pulse width signal and the initial zero-point calibration pulse width signal. Iout One or more of any reasonable parameters, such as amplitude, phase, and zero-crossing point, can be adjusted to obtain the third current-sharing bus voltage V. Ishare3 .

[0097] S27: Output the third current sharing bus voltage to the current sharing bus.

[0098] The voltage V of the third current-equalizing bus Ishare3 It is sent to the second current sharing bus 601 to achieve initial current sharing calibration.

[0099] S28: Obtain the first current sharing test voltage on the current sharing bus under no-load conditions.

[0100] S29: Obtain the zero-point calibration duty cycle using the first current sharing test voltage and the initial zero-point calibration duty cycle.

[0101] S210: Generate the first pulse width signal by calibrating the duty cycle using the zero point.

[0102] S211: The reference output voltage of the power supply regulation circuit is adjusted using the first pulse width signal and the initial proportional calibration pulse width signal to obtain the first current sharing bus voltage.

[0103] S212: Output the voltage of the first current sharing bus to the current sharing bus.

[0104] S213: Obtain the second current sharing test voltage on the current sharing bus under full load conditions.

[0105] S214: The proportional calibration duty cycle is obtained using the second current sharing test voltage, the maximum target output current, the maximum current sharing bus voltage, and the initial proportional calibration duty cycle.

[0106] S215: Generate a second pulse width signal by calibrating the duty cycle using a proportional method.

[0107] S216: The reference output voltage is adjusted using the first pulse width signal and the second pulse width signal to obtain the second current sharing bus voltage.

[0108] S217: Output the second current sharing bus voltage to the current sharing bus.

[0109] Among them, S28, S29, S210, S211, S212, S213, S214, S215, S216 and S217 and Figure 1 S11, S12, S13, S14, S15, S16, S17, S18 and S19 are the same. For details, please refer to S11, S12, S13, S14, S15, S16, S17, S18, S19 and S110 and their related textual descriptions, which will not be repeated here.

[0110] It is worth noting that the second current sharing calibration circuit 50 will adjust the current sharing bus voltage V. Ishare The output is sent to the second current sharing bus 601 to achieve current sharing. At the same time, each second power supply regulation circuit 60 is also used to provide its output voltage / output current after current sharing calibration and adjustment to the second load working circuit 603 via the second output bus 602.

[0111] Please continue reading. Figure 6 , Figure 6 yes Figure 3 A flowchart illustrating an embodiment of S23 is provided. In one embodiment, the current sharing calibration method of this application, in addition to the above-described S21-S215, further includes some more specific steps. Specifically, S23 may further include the following steps: S231: The initial proportional calibration duty cycle is obtained using the maximum target output current, the maximum current sharing bus voltage, and the linear proportional coefficient.

[0112] Specifically, the second current sharing calibration circuit 50 uses a preset operation function or rule procedure to measure the preset maximum target output current I. out-max Maximum current-sharing bus voltage V Ishare-max The initial proportional calibration duty cycle is obtained by performing calculations on the linear scaling factor B. .

[0113] S232: The initial zero-point calibration duty cycle is obtained by using the initial proportional calibration duty cycle, the set voltage amplitude, and the linear bias coefficient.

[0114] The duty cycle is calibrated using a preset calculation function or rule-based procedure to set the initial ratio. The initial zero-point calibration duty cycle D2 is obtained by setting the voltage amplitude Uf and the linear bias coefficient A.

[0115] It is worth noting that the set voltage amplitude U fSpecifically, these are the amplitudes of the initial proportional calibration pulse width signal, the initial zero-point calibration pulse width signal, the first pulse width signal, and the second pulse width signal, i.e., the set voltage amplitude U of the high level of each pulse width signal. f .

[0116] Furthermore, in some embodiments, the above-mentioned S231 may specifically include: using a first operation function to calculate the maximum target output current I. out-max Maximum current-sharing bus voltage V Ishare-max The initial proportional calibration duty cycle is obtained by performing calculations on the linear scaling factor B. ; The formula for the first operational function is:

[0117] Where D1 is the initial proportional calibration duty cycle, I out-max For the maximum target output current, V Ishare-max Where is the maximum current-sharing bus voltage, B is the linear proportional coefficient, K1 is the first adjustment coefficient, and K2 is the second adjustment coefficient.

[0118] It is worth noting that the first adjustment coefficient K1 and the second adjustment coefficient K2 can be specifically obtained by fitting the characteristic data obtained from simulation experiments or production line tests, and can actually correspond to the program settings of the MCU circuit.

[0119] Furthermore, in some embodiments, the above-mentioned S232 may specifically include: using a second operation function to adjust the initial proportional calibration duty cycle D1 and set the voltage amplitude U. f The initial zero-point calibration duty cycle D2 is obtained by performing calculations on the linear bias coefficient A. The formula for the second operational function is as follows:

[0120] Wherein, the voltage amplitude is set to the amplitude of the first pulse width signal, D2 is the initial zero-point calibration duty cycle, and U f To set the voltage amplitude, A is the linear bias coefficient, K3 is the third adjustment coefficient, K4 is the fourth adjustment coefficient, and K5 is the fifth adjustment coefficient.

[0121] Similarly, the third adjustment coefficient K3, the fourth adjustment coefficient K4, and the fifth adjustment coefficient K5 can also correspond to the program setting values ​​obtained by fitting the feature data obtained in simulation experiments or production line tests.

[0122] Furthermore, in some embodiments, S28 may specifically include: using a third operation function to measure the first current sharing test voltage V. Ishare-test1 Initial zero-point calibration duty cycle D2 and set voltage amplitude U fThe zero-point calibration duty cycle D is obtained through calculation. 2x ; The formula for the third operation function is:

[0123] Among them, D 2x For zero-point calibration of the duty cycle, V Ishare-test1 K is the first current sharing test voltage, and K6 is the sixth adjustment coefficient.

[0124] Similarly, the sixth adjustment coefficient K6 can also correspond to the program setting value obtained by fitting the feature data obtained in simulation experiments or production line tests.

[0125] Furthermore, in some embodiments, S213 may specifically include: using a fourth operation function to calculate the maximum target output current I. out-max Maximum current-sharing bus voltage V Ishare-max Second current sharing test voltage V Ishare-test2 The initial proportional calibration duty cycle D1 is processed to obtain the proportional calibration duty cycle D. 1x ; The formula for the fourth operation function is:

[0126] Among them, D 1x To proportionally calibrate the duty cycle, V Ishare-test2 K7 is the second current sharing test voltage, and K7 is the seventh adjustment coefficient.

[0127] Similarly, the seventh adjustment coefficient K7 can also correspond to the program setting value obtained by fitting the feature data obtained in simulation experiments or production line tests.

[0128] Please continue reading. Figure 5 , Figure 5 yes Figure 4 A schematic diagram of one embodiment of the current sharing calibration circuit.

[0129] In some embodiments, the current sharing calibration method specifically involves calibrating the second power supply regulation circuit 60 using a second current sharing calibration circuit 50. The second current sharing calibration circuit 50 includes a main control circuit 51, a zero-point calibration circuit 52, a proportional calibration circuit 53, and an operational amplifier circuit 54. The proportional calibration circuit 53 includes a calibration switch Qj, a fifth resistor Rz5, a second resistor Rz2, and a first capacitor C1. The operational amplifier circuit 54 includes a third resistor Rz3, a fourth resistor Rz4, and an operational amplifier U1. The main control circuit 51 is coupled to the zero-point calibration circuit 52, the control terminal of the calibration switch Qj, and the non-inverting input terminal of the operational amplifier U1, and is used to couple with the second power supply regulation circuit 60 to calibrate the current sharing of the second power supply regulation circuit 60. The first terminal is coupled to the first terminal of the fifth resistor Rz5. The second terminal of the calibration switch Qj is coupled to the second terminal of the first capacitor C1 and grounded. The second terminal of the fifth resistor Rz5 is coupled to the first terminal of the second resistor Rz2 and the first terminal of the first capacitor C1. The second terminal of the second resistor Rz2 is coupled to the zero-point calibration circuit 52, the first terminal of the third resistor Rz3, the first terminal of the fourth resistor Rz4, and the inverting input terminal of the operational amplifier U1. The second terminal of the third resistor Rz3 is grounded. The second terminal of the fourth resistor Rz4 is coupled to the output terminal of the operational amplifier U1 and is used to couple with the second current sharing bus 601.

[0130] Specifically, S231 may also include: the main control circuit 51 uses a fifth operation function to determine the maximum target output current I. out-max Maximum current-sharing bus voltage V Ishare-max The initial proportional calibration duty cycle D1 is obtained by processing the linear proportional coefficient B, the second resistance value R2, the third resistance value R3, the fourth resistance value R4, and the fifth resistance value R5. The formula for the fifth operation function is:

[0131] Wherein, the second resistance value R2, the third resistance value R3, the fourth resistance value R4, and the fifth resistance value R5 are the resistance values ​​of the second resistor Rz2, the third resistor Rz3, the fourth resistor Rz4, and the fifth resistor Rz5, respectively; D1 is the initial proportional calibration duty cycle, I out-max For the maximum target output current, V Ishare-max R1 is the maximum current-sharing bus voltage, B is the linear proportional coefficient, R2 is the second resistance value, R3 is the third resistance value, R4 is the fourth resistance value, and R5 is the fifth resistance value.

[0132] It is worth noting that the calculation process for the initial proportional calibration duty cycle D1 is as follows: Assuming the zero point has been calibrated, when the initial proportional calibration pulse width signal is low, i.e., the calibration switch Qj is off:

[0133] When the initial proportional calibration pulse width signal is high, i.e., when the calibration switch Qj is closed:

[0134] in, This refers to the current-sharing bus voltage when the calibrator switch Qj is closed; Therefore, the voltage of the current-sharing bus can be obtained. for:

[0135] make , The initial proportional calibration duty cycle is calculated by reverse calculation. We can then obtain:

[0136] Therefore, based on the current-sharing bus voltage V Ishare When the resistance values ​​of the first resistor Rz1, the second resistor Rz2, the third resistor Rz3, the fourth resistor Rz4, the fifth resistor Rz5, and the sixth resistor Rz6 are determined according to the requirements, and the second current sharing calibration circuit 50 is configured according to the resistance values, the initial proportional calibration duty cycle D1 can be obtained by performing corresponding calculations on the resistance values.

[0137] In other embodiments, this resistance parameter can be further modified by the main control circuit 51 according to a program setting, replacing the first resistor Rz1, the second resistor Rz2, the third resistor Rz3, the fourth resistor Rz4, the fifth resistor Rz5, and the sixth resistor Rz6. This directly outputs a corresponding pulse width signal to the inverting input of the operational amplifier U1 to adjust the amplitude amplification ratio of the operational amplifier U1, thereby achieving corresponding zero-point calibration and proportional calibration, i.e., setting the first adjustment coefficient K1 = Let the second adjustment coefficient K2 = .

[0138] In addition, the main control circuit 51 is specifically used to sample and acquire the output current I of the second power regulation circuit 60 in real time. out To control the output current I out The reference output voltage V is obtained through calculation and processing. Iout The initial proportional calibration duty cycle D1, initial zero-point calibration duty cycle D2, and zero-point calibration duty cycle D are calculated using the above-mentioned function formulas and other function formulas in this paper, respectively. 2x Proportional calibration duty cycle D 1x At different stages, corresponding pulse width signals are generated sequentially, so as to affect the reference output voltage V. Iout The signal is amplified or reduced by an appropriate ratio to obtain the current-sharing bus voltage V. Ishare .

[0139] Furthermore, in some embodiments, the zero-point calibration circuit 52 includes a sixth resistor Rz6, a first resistor Rz1, and a second capacitor C2. The first end of the sixth resistor Rz6 is coupled to the main control circuit 51, and the second end of the sixth resistor Rz6 is coupled to the first end of the second capacitor C2 and the first end of the first resistor Rz1. The second end of the first resistor Rz1 is coupled to the second end of the second resistor Rz2, the first end of the third resistor Rz3, the first end of the fourth resistor Rz4, and the inverting input terminal.

[0140] Specifically, S232 may further include: the main control circuit 51 uses a sixth operation function to set the initial proportional calibration duty cycle D1 and the voltage amplitude U. f The initial zero-point calibration duty cycle D2 is obtained by processing the linear bias coefficient A, the first resistance value R1, the second resistance value R2, the third resistance value R3, the fourth resistance value R4, the fifth resistance value R5, and the sixth resistance value R6. The formula for the sixth operation function is:

[0141] Among them, the voltage amplitude U is set. f The amplitude of the initial proportional calibration pulse width signal is set, with the first resistance R1 and the sixth resistance R6 being the resistance values ​​of the first resistor Rz1 and the sixth resistor Rz6, respectively; D2 is the initial zero-point calibration duty cycle, U f To set the voltage amplitude, A is the linear bias coefficient, R1 is the first resistance value, and R6 is the sixth resistance value.

[0142] It is worth noting that the calculation process for the initial zero-point calibration duty cycle D2 is as follows: Given the initial proportional calibration duty cycle D1, and the calibration zero point... , When the initial proportional calibration pulse width signal is low, i.e., when the calibration switch Qj is off:

[0143] When the initial proportional calibration pulse width signal is high, i.e., when the calibration switch Qj is closed:

[0144] When the output current hour, The theoretical value is also 0, so we can conclude that:

[0145] Therefore, it can be deduced that:

[0146] Similarly, based on the current-sharing bus voltage VIshare By determining the resistance values ​​of the first resistor Rz1, the second resistor Rz2, the third resistor Rz3, the fourth resistor Rz4, the fifth resistor Rz5, and the sixth resistor Rz6, the initial zero-point calibration duty cycle D2 can be obtained by calculating the corresponding resistance values.

[0147] Furthermore, let the third adjustment coefficient K3 = The fourth adjustment coefficient K4 = This allows for zero-point calibration to be effectively achieved by replacing individual resistor configurations according to the program settings, thus saving circuit costs.

[0148] In some embodiments, the main control circuit 51 further includes a current sampling sub-circuit (not shown) and a control sub-circuit (not shown). The current sampling sub-circuit is coupled to the second power regulation circuit 60 and the non-inverting input of the operational amplifier U1 to sample and acquire the output current in the second power regulation circuit 60. To output the current Multiply by the linear scaling factor B and add the linear bias factor A to obtain the reference output voltage. This will then adjust the reference output voltage. The signal is sent to the non-inverting input of the operational amplifier U1. This control sub-circuit is coupled to the control terminal of the calibration switch Qj and the first terminal of the sixth resistor Rz6, so as to send the initial proportional calibration pulse width signal and the initial zero-point calibration pulse width signal to the control terminal of the calibration switch Qj and the first terminal of the sixth resistor Rz6, respectively, so as to be used for zero-point calibration and proportional calibration, respectively.

[0149] The initial proportional calibration pulse width signal corresponds to a signal with an amplitude of the set voltage amplitude U. f A PWM wave with a duty cycle of D1 is used to adjust the amplification ratio of operational amplifier U1 by controlling the on / off state of calibration switch Qj, thereby performing proportional calibration. This initial zero-point calibration pulse width signal corresponds to a signal with an amplitude of the set voltage amplitude U. f A PWM wave with a duty cycle of D2 can eliminate circuit zero-point error.

[0150] Furthermore, in some embodiments, the above-mentioned S28 may further include: the main control circuit 51 using a seventh operation function to measure the first current sharing test voltage V. Ishare-test1 Initial zero-point calibration duty cycle D2, set voltage amplitude U f The zero-point calibration duty cycle D is obtained by processing the first resistance value R1, the fourth resistance value R4, and the sixth resistance value R6. 2x ; The formula for the seventh operation function is:

[0151] Among them, D2x For zero-point calibration of the duty cycle, V Ishare-test1 This is the first current sharing test voltage.

[0152] It is worth noting that the zero-point calibration duty cycle D 2x The calculation process is as follows:

[0153]

[0154] Among these steps, zero-point calibration is performed on the second outgoing bus 602 when it is unloaded, and the first current sharing test voltage under no-load conditions is sampled and obtained. Let the zero-point calibration duty cycle after calibration be... Then we have the formula:

[0155]

[0156] achievable Calibration formula:

[0157] Furthermore, in some embodiments, the above-described S213 may further include: the main control circuit 51 employs an eighth operation function to determine the maximum target output current I. out-max Maximum current-sharing bus voltage V Ishare-max Second current sharing test voltage V Ishare-test2 The initial proportional calibration duty cycle D1, the second resistance value R2, the third resistance value R3, the fourth resistance value R4, and the fifth resistance value R5 are used to calculate and obtain the proportional calibration duty cycle. ; The formula for the eighth operation function is:

[0158] Among them, D 1x To proportionally calibrate the duty cycle, V Ishare-test2 This is the second current sharing test voltage.

[0159] It is worth noting that the proportional calibration duty cycle D 1x The calculation process is as follows:

[0160] ; Among these measures, zero-point calibration is performed when the second outgoing bus 602 is fully loaded, and the second current sharing test voltage under full load is sampled and obtained. Let the zero-point calibration duty cycle after calibration be... Then we have the formula:

[0161] ;

[0162] ; Therefore, we get:

[0163] Furthermore, in some embodiments, S27 may specifically include: acquiring the first current sharing test voltage V on the second current sharing bus 601 under the no-load state of the second transfer bus 602 at intervals of a first set time period or a first set number of signal cycles. Ishare-test1 .

[0164] Understandably, in order to achieve better current sharing, the zero-point current sharing calibration performed by the second current sharing calibration circuit 50 can be a dynamic current sharing calibration, which is performed once every first set time interval or a first set number of signal cycles, so that each current sharing calibration is closer to the ideal state.

[0165] In some embodiments, the first set duration can be 10ms to 20ms; the number of first settings can be 5 to 20, and this application does not limit this.

[0166] Furthermore, in some embodiments, the above-mentioned S212 may specifically include: acquiring the second current sharing test voltage V on the second current sharing bus 601 under the full load state of the second output bus 602 at intervals of a second predetermined time period or a second predetermined number of signal cycles. Ishare-test2 .

[0167] Understandably, in order to achieve better current sharing, the proportional current sharing calibration performed by the second current sharing calibration circuit 50 can also be a dynamic current sharing calibration, which is performed once every second set time interval or second set number of signal cycles, so that each current sharing calibration is closer to the ideal state.

[0168] In some embodiments, the second set duration can be specifically 10ms (milliseconds) to 20ms; the number of second settings can be specifically 5 to 20, and this application does not limit this.

[0169] Please continue reading. Figures 7-9 ,in, Figure 7 These are schematic diagrams of the simulated waveforms of various signals corresponding to the zero-point calibration of the relevant current-sharing bus. Figure 8 These are schematic diagrams of the simulated waveforms of various signals corresponding to the proportional calibration of the relevant current sharing bus. Figure 9 yes Figure 3 The simulation waveform diagrams of each signal corresponding to the current sharing calibration method are shown in the figure.

[0170] Understandably, such as Figure 7 and Figure 8 The calibration results show that both methods have a problem with the current-sharing bus voltage V under light load. Ishare The problem is low accuracy. And such as... Figure 9 As shown, the calibration method in this application has higher calibration accuracy under light load compared to the previous two calibration methods, and can effectively avoid the problem of poor flow sharing under light load or multiple parallel operation conditions, which is of great significance for multiple parallel operation flow sharing.

[0171] This application also provides an electronic device, please refer to... Figure 10 , Figure 10 This is a schematic diagram of one embodiment of the electronic device of this application. In this embodiment, the electronic device 70 includes a housing 71 and a third current sharing calibration circuit 72 connected to the housing 71.

[0172] It should be noted that the third current sharing calibration circuit 72 described in this embodiment is either the first current sharing calibration circuit 30 or the second current sharing calibration circuit 50 described in any of the above embodiments. Please refer to [link / reference] for details. Figures 1-9 The relevant textual content will not be elaborated upon here.

[0173] The beneficial effects of this application are as follows: Unlike the prior art, the current sharing calibration method provided in this application obtains the first current sharing test voltage of the current sharing bus under no-load conditions of the transfer bus, uses the first current sharing test voltage and the initial zero-point calibration duty cycle to obtain the zero-point calibration duty cycle, generates a first pulse width signal, and then uses the first pulse width signal and the initial proportional calibration pulse width signal to adjust the reference output voltage of the power supply regulation circuit to obtain the first current sharing bus voltage, and outputs it to the current sharing bus. Thus, by performing zero-point calibration under no-load conditions, the calibration accuracy can be effectively improved, and the deviation between the single-machine current sharing bus voltage and the target value can be reduced, so as to ensure the accuracy of the current sharing bus under light load conditions. Furthermore, by acquiring the second current sharing test voltage of the current sharing bus under full load conditions of the transfer bus, the proportional calibration duty cycle is obtained using the second current sharing test voltage, the maximum target output current, the maximum current sharing bus voltage, and the initial proportional calibration duty cycle. This generates a second pulse width signal, and the reference output voltage is adjusted using the first and second pulse width signals to obtain the second current sharing bus voltage. Thus, based on the no-load zero-point calibration, proportional calibration is further performed under full load to effectively ensure the accuracy of the current sharing bus under full load, thereby effectively balancing the accuracy of the current sharing bus under both light load and full load conditions, and improving the overall parallel current sharing efficiency.

[0174] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A current sharing calibration method, applied to the current sharing calibration of a power supply regulating circuit, wherein the power supply regulating circuit is coupled to an output bus and is used to couple with a current sharing calibration circuit, the current sharing calibration circuit is coupled to a current sharing bus, and the output bus is used to couple with a load operating circuit, characterized in that, The current sharing calibration method includes: The current sharing calibration circuit acquires the reference output voltage of the power supply regulation circuit and the first current sharing test voltage on the current sharing bus when the output bus is in an unloaded state. The zero-point calibration duty cycle is obtained using the first current-sharing test voltage and the initial zero-point calibration duty cycle; The first pulse width signal is generated using the zero-point calibration duty cycle. The first current-sharing bus voltage is obtained by adjusting the reference output voltage using the first pulse width signal and the initial proportional calibration pulse width signal. The voltage of the first current-equalizing bus is output to the current-equalizing bus; Obtain the second current sharing test voltage on the current sharing bus under full load conditions of the outgoing bus; The proportional calibration duty cycle is obtained using the second current sharing test voltage, the maximum target output current, the maximum current sharing bus voltage, and the initial proportional calibration duty cycle. The duty cycle is calibrated using the aforementioned ratio to generate a second pulse width signal; The second current-sharing bus voltage is obtained by adjusting the reference output voltage using the first pulse width signal and the second pulse width signal; The second current-equalizing bus voltage is output to the current-equalizing bus.

2. The current sharing calibration method according to claim 1, characterized in that, The step of the current sharing calibration circuit obtaining the reference output voltage of the power supply regulation circuit includes: Obtain the output current of the power regulation circuit; The reference output voltage is obtained by multiplying the output current by the linear scaling factor and adding the linear bias factor.

3. The current sharing calibration method according to claim 2, characterized in that, Before the step of obtaining the first current sharing test voltage on the current sharing bus under no-load conditions of the outgoing bus, the method further includes: The initial proportional calibration duty cycle and the initial zero-point calibration duty cycle are obtained using the maximum target output current and the maximum current sharing bus voltage; The initial proportional calibration duty cycle is used to generate the initial proportional calibration pulse width signal; The initial zero-point calibration duty cycle is used to generate the initial zero-point calibration pulse width signal; The reference output voltage is adjusted using the initial proportional calibration pulse width signal and the initial zero-point calibration pulse width signal to obtain the third current-sharing bus voltage; The voltage of the third current-equalizing bus is output to the current-equalizing bus.

4. The current sharing calibration method according to claim 3, characterized in that, The steps of obtaining the initial proportional calibration duty cycle and the initial zero-point calibration duty cycle using the maximum target output current and the maximum current-sharing bus voltage include: The initial proportional calibration duty cycle is obtained using the maximum target output current, the maximum current sharing bus voltage, and the linear proportional coefficient. The initial zero-point calibration duty cycle is obtained using the initial proportional calibration duty cycle, the set voltage amplitude, and the linear bias coefficient.

5. The current sharing calibration method according to claim 4, characterized in that, The step of obtaining the initial proportional calibration duty cycle using the maximum target output current, the maximum current-sharing bus voltage, and the linear scaling factor includes: The initial proportional calibration duty cycle is obtained by performing calculations on the maximum target output current, the maximum current sharing bus voltage, and the linear proportional coefficient using a first calculation function. The formula for the first operational function is: Where D1 is the initial proportional calibration duty cycle, I out-max V is the maximum target output current. Ishare-max Where is the maximum current-sharing bus voltage, B is the linear proportional coefficient, K1 is the first adjustment coefficient, and K2 is the second adjustment coefficient.

6. The current sharing calibration method according to claim 5, characterized in that, The step of obtaining the initial zero-point calibration duty cycle using the initial proportional calibration duty cycle, the set voltage amplitude, and the linear bias coefficient includes: The initial zero-point calibration duty cycle is obtained by performing calculations on the initial proportional calibration duty cycle, the set voltage amplitude, and the linear bias coefficient using a second calculation function. The formula for the second operation function is: Wherein, the set voltage amplitude is the amplitude of the first pulse width signal, D2 is the initial zero-point calibration duty cycle, and U f The set voltage amplitude is defined as follows: A is the linear bias coefficient, K3 is the third adjustment coefficient, K4 is the fourth adjustment coefficient, and K5 is the fifth adjustment coefficient.

7. The current sharing calibration method according to claim 6, characterized in that, The step of obtaining the zero-point calibration duty cycle using the first current sharing test voltage and the initial zero-point calibration duty cycle includes: The zero-point calibration duty cycle is obtained by performing calculations on the first current sharing test voltage, the initial zero-point calibration duty cycle, and the set voltage amplitude using a third calculation function. The formula for the third operation function is as follows: Among them, D 2x For the zero-point calibration duty cycle, V Ishare-test1 K is the first current sharing test voltage, and K6 is the sixth adjustment coefficient.

8. The current sharing calibration method according to claim 7, characterized in that, The step of obtaining the proportional calibration duty cycle using the second current sharing test voltage, the maximum target output current, the maximum current sharing bus voltage, and the initial proportional calibration duty cycle includes: The proportional calibration duty cycle is obtained by performing calculations on the maximum target output current, the maximum current sharing bus voltage, the second current sharing test voltage, and the initial proportional calibration duty cycle using a fourth calculation function. The formula for the fourth operation function is as follows: Among them, D 1x For the proportional calibration duty cycle, V Ishare-test2 K is the second current sharing test voltage, and K7 is the seventh adjustment coefficient.

9. The current sharing calibration method according to claim 4, characterized in that, The current sharing calibration circuit includes a main control circuit, a zero-point calibration circuit, a proportional calibration circuit, and an operational amplifier circuit. The proportional calibration circuit includes a calibration switch, a fifth resistor, a second resistor, and a first capacitor. The operational amplifier circuit includes a third resistor, a fourth resistor, and an operational amplifier. The main control circuit is coupled to the zero-point calibration circuit, the control terminal of the calibration switch, and the non-inverting input terminal of the operational amplifier, and is also used to couple with the power supply regulation circuit. The first terminal of the calibration switch is coupled to the first terminal of the fifth resistor, the second terminal of the calibration switch is coupled to the second terminal of the first capacitor and grounded, the second terminal of the fifth resistor is coupled to the first terminal of the second resistor and the first terminal of the first capacitor, the second terminal of the second resistor is coupled to the zero-point calibration circuit, the first terminal of the third resistor, the first terminal of the fourth resistor, and the inverting input terminal of the operational amplifier, the second terminal of the third resistor is grounded, and the second terminal of the fourth resistor is coupled to the output terminal of the operational amplifier and is also used to couple with the current sharing bus. The step of obtaining the initial proportional calibration duty cycle using the maximum target output current, the maximum current sharing bus voltage, and the linear proportional coefficient includes: The main control circuit uses a fifth operation function to process the maximum target output current, the maximum current sharing bus voltage, the linear proportional coefficient, the second resistance value, the third resistance value, the fourth resistance value, and the fifth resistance value to obtain the initial proportional calibration duty cycle. The formula for the fifth operational function is as follows: Wherein, the second resistance value, the third resistance value, the fourth resistance value, and the fifth resistance value are the resistance values ​​of the second resistor, the third resistor, the fourth resistor, and the fifth resistor, respectively; D1 is the initial proportional calibration duty cycle, I out-max V is the maximum target output current. Ishare-max R1 is the maximum current-sharing bus voltage, B is the linear proportional coefficient, R2 is the second resistance value, R3 is the third resistance value, R4 is the fourth resistance value, and R5 is the fifth resistance value.

10. The current sharing calibration method according to claim 9, characterized in that, The zero-point calibration circuit includes a sixth resistor, a first resistor, and a second capacitor. The first end of the sixth resistor is coupled to the main control circuit. The second end of the sixth resistor is coupled to the first end of the second capacitor and the first end of the first resistor. The second end of the first resistor is coupled to the second end of the second resistor, the first end of the third resistor, the first end of the fourth resistor, and the inverting input terminal. The step of obtaining the initial zero-point calibration duty cycle using the initial proportional calibration duty cycle, the set voltage amplitude, and the linear bias coefficient includes: The main control circuit uses a sixth operation function to process the initial proportional calibration duty cycle, the set voltage amplitude, the linear bias coefficient, the first resistance value, the second resistance value, the third resistance value, the fourth resistance value, the fifth resistance value, and the sixth resistance value to obtain the initial zero-point calibration duty cycle. The formula for the sixth operational function is as follows: Wherein, the set voltage amplitude is the amplitude of the initial proportional calibration pulse width signal, the first resistance value and the sixth resistance value are the resistance values ​​of the first resistor and the sixth resistor, respectively; D2 is the initial zero-point calibration duty cycle, U f The set voltage amplitude is A, the linear bias coefficient is R1, the first resistance value is R6, and the sixth resistance value is R6.

11. The current sharing calibration method according to claim 10, characterized in that, The step of obtaining the zero-point calibration duty cycle using the first current sharing test voltage and the initial zero-point calibration duty cycle includes: The main control circuit uses a seventh operation function to process the first current sharing test voltage, the initial zero-point calibration duty cycle, the set voltage amplitude, the first resistance value, the fourth resistance value, and the sixth resistance value to obtain the zero-point calibration duty cycle; The formula for the seventh operation function is as follows: Among them, D 2x For the zero-point calibration duty cycle, V Ishare-test1 The voltage is the first current sharing test voltage.

12. The current sharing calibration method according to claim 11, characterized in that, The step of obtaining the proportional calibration duty cycle using the maximum target output current, the maximum current sharing bus voltage, the second current sharing test voltage, and the initial proportional calibration duty cycle includes: The main control circuit uses an eighth operation function to process the maximum target output current, the maximum current sharing bus voltage, the second current sharing test voltage, the initial proportional calibration duty cycle, the second resistance value, the third resistance value, the fourth resistance value, and the fifth resistance value to obtain the proportional calibration duty cycle; The formula for the eighth operation function is as follows: Among them, D 1x For the proportional calibration duty cycle, V Ishare-test2 This is the second current sharing test voltage.

13. The current sharing calibration method according to any one of claims 1-12, characterized in that, The steps of the current sharing calibration circuit to obtain the reference output voltage of the power supply regulation circuit and the first current sharing test voltage on the current sharing bus under no-load conditions include: The first current sharing test voltage of the current sharing bus under no-load condition is acquired at intervals of a first set time period or a first set number of signal cycles.

14. The current sharing calibration method according to any one of claims 1-12, characterized in that, The step of obtaining the second current sharing test voltage on the current sharing bus under full load conditions of the outgoing bus includes: The second current sharing test voltage of the current sharing bus under full load condition is obtained at intervals of a second set time period or a second set number of signal cycles.

15. A current sharing calibration circuit, characterized in that, The current sharing calibration circuit is coupled to the current sharing bus and is used to couple with the power supply regulation circuit. The current sharing calibration circuit uses the current sharing calibration method as described in any one of claims 1-14 to perform current sharing calibration on the power supply regulation circuit.

16. An electronic device, characterized in that, The electronic device includes a housing and a current equalization calibration circuit connected to the housing; The current sharing calibration circuit is the current sharing calibration circuit as described in claim 15.

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