Negative voltage charge pump circuit and switched power converter

Abstract

This application relates to the field of switching power supply converter technology, and provides a negative voltage charge pump circuit and a switching power supply converter. The negative voltage charge pump circuit adds a clock modulation module, a reference voltage generation module, a comparator module, a fourth driver module, and a fifth, sixth, and seventh power transistor to an existing charge pump. When the negative voltage charge pump circuit enters a light-load condition, by shutting down the large-size power transistor and its driver module, only the small-size power transistor remains operational. The small-size power transistor automatically determines whether to operate based on the absolute value of the output voltage, significantly reducing the operating current of the negative voltage charge pump circuit and improving its conversion efficiency under light load. Simultaneously, by using a narrow pulse modulation unit in the clock modulation module to perform pulse width modulation processing, the clock signal driving the small-size power transistor is optimized, further reducing circuit power consumption under light load.

Description

Technical Field

[0001] This application belongs to the field of switching power supply converter technology, and particularly relates to a negative voltage charge pump circuit and a switching power supply converter. Background Technology

[0002] Switched-capacitor charge pumps are widely used in low-power power supply scenarios such as portable electronic devices due to their advantages of small size, low quiescent current, and low electromagnetic interference. Conversion efficiency is their core performance indicator. To ensure load-carrying capacity and conversion efficiency under heavy-load conditions, traditional negative-voltage charge pumps typically use large-size power switching transistors paired with matching drive modules with high drive capability to reduce the on-resistance of the power transistors and lower conduction losses. In actual operation, charge pumps operate under light-load or even zero-load conditions. When the output load current is extremely small, the operating current of the charge pump is mainly consumed in the periodic driving process of the power transistors, and the periodic switching of the power switching transistors is necessary to maintain stable output voltage. This results in the charge pump generating a large operating current even with a small output load, especially under zero-load conditions, leading to extremely poor conversion efficiency. Summary of the Invention

[0003] This application provides a negative voltage charge pump circuit and a switching power supply converter, which can solve the problem that current negative voltage charge pump circuits still generate a large operating current and have extremely poor conversion efficiency when the output load is small, especially in the zero-load state.

[0004] In a first aspect, embodiments of this application provide a negative voltage charge pump circuit, including a first power transistor, a second power transistor, a third power transistor, a fourth power transistor, an output capacitor, an output resistor, a first resistor, a second resistor, a flying capacitor, a first switch, an error amplifier, a first driving module, a second driving module, and a third driving module. The source of the first power transistor receives an input voltage, the gate of the first power transistor is connected to a first terminal of the first switch, the second terminal of the first switch is connected to the output terminal of the error amplifier, the control terminal of the first switch receives a first clock signal, the drain of the first power transistor is connected to the drain of the second power transistor and the first terminal of the flying capacitor, and the gate of the second power transistor is connected to the first... A driving module is connected. The sources of the second power transistor and the third power transistor are both grounded. The gate of the third power transistor is connected to the second driving module. The drain of the third power transistor is connected to the drain of the fourth power transistor and the second terminal of the flying capacitor. The gate of the fourth power transistor is connected to the third driving module. The source of the fourth power transistor is connected to the first terminal of the output capacitor, the first terminal of the output resistor, and the first terminal of the second resistor. The second terminal of the second resistor is connected to the first terminal of the first resistor and the first input terminal of the error amplifier. The second terminal of the first resistor receives a first reference voltage, and the second input terminal of the error amplifier receives a second reference voltage. The negative voltage charge pump circuit further includes a clock modulation module, a reference voltage generation module, a comparison module, a fourth drive module, a fifth power transistor, a sixth power transistor, and a seventh power transistor. The fifth power transistor is smaller than the second power transistor and they are of the same type. The sixth power transistor is smaller than the third power transistor and they are of the same type. The seventh power transistor is smaller than the fourth power transistor and they are of the same type. The comparison module is connected to the reference voltage generation module, the output of the error amplifier, the clock modulation module, and the fourth drive module. The fourth drive module is connected to the... The clock modulation module, the first driving module, the second driving module, the third driving module, the gate of the fifth power transistor, the gate of the sixth power transistor, and the gate of the seventh power transistor are connected. The drain of the fifth power transistor is connected to the drain of the second power transistor, and the source of the fifth power transistor is connected to the source of the second power transistor. The drain of the sixth power transistor is connected to the source of the third power transistor, and the source of the sixth power transistor is connected to the drain of the third power transistor. The drain of the seventh power transistor is connected to the drain of the fourth power transistor, and the source of the seventh power transistor is connected to the source of the fourth power transistor. The reference voltage generation module is used to generate a third reference voltage based on a first current, wherein the first current is proportional to the current flowing through the first power transistor; the comparison module is used to compare the error voltage output by the error amplifier with the third reference voltage, and output a first comparison signal when the error voltage is greater than the third reference voltage; The clock modulation module is used to output a first clock signal, a second clock signal, a third clock signal, and a fourth clock signal based on the first comparison signal and the base clock signal. The clock modulation module is configured with a narrow pulse modulation unit; the narrow pulse modulation unit is used to reduce the pulse width of the second clock signal and the fourth clock signal. The fourth driving module is used to output a first driving signal, a second driving signal, and a third driving signal according to the second clock signal, the third clock signal, and the fourth clock signal, respectively, to drive the fifth power transistor, the sixth power transistor, and the seventh power transistor. The fourth driving module also outputs a first control signal, a second control signal, and a third control signal according to the first comparison signal, the second clock signal, the third clock signal, and the fourth clock signal, respectively, to turn off the first driving module, the second driving module, and the third driving module, thereby turning off the second power transistor, the third power transistor, and the fourth power transistor.

[0005] In one possible implementation of the first aspect, the comparison module is further configured to output a second comparison signal when the error voltage is less than the third reference voltage; the fourth driving module is further configured to output a fourth control signal, a fifth control signal, and a sixth control signal according to the second comparison signal, the second clock signal, the third clock signal, and the fourth clock signal, respectively for controlling the first driving module to drive the second power transistor, the second driving module to drive the third power transistor, and the third driving module to drive the fourth power transistor.

[0006] In one possible implementation of the first aspect, the narrow pulse modulation unit includes a pulse width extension unit, a logic unit, a first non-overlapping clock generation unit, a narrow pulse generation unit, a second switch, a third switch, a second non-overlapping clock generation unit, and a third non-overlapping clock generation unit. The pulse width extension unit and the logic unit are both connected to the comparison module. The pulse width extension unit is connected to the control terminals of the second switch and the third switch, respectively. The first non-overlapping clock generation unit is connected to the logic unit, the narrow pulse generation unit, the first terminal of the second switch, and the third non-overlapping clock generation unit, respectively. The first terminal of the third switch is connected to the narrow pulse generation unit. The second terminals of the third switch and the second switches are both connected to the second non-overlapping clock generation unit. The second non-overlapping clock generation unit and the third non-overlapping clock generation unit are both connected to the fourth driving module. The third non-overlapping clock generation unit is connected to the control terminal of the first switch. The pulse width extension unit is used to output a first pulse width extension signal and a second pulse width extension signal according to the first comparison signal and the base clock signal, wherein the second pulse width extension signal is the inverted signal of the first pulse width extension signal; the second switch is used to turn on or off according to the second pulse width extension signal, and the third switch is used to turn on or off according to the first pulse width extension signal; the logic unit is used to output a logic signal according to the first comparison signal and the base clock signal; the first non-overlapping clock generation unit is used to output a first signal and a second signal according to the logic signal; the narrow pulse generation unit is used to generate a narrow pulse signal from the first signal; the second non-overlapping clock generation unit is used to output the second clock signal and the fourth clock signal according to the narrow pulse signal when the third switch is turned on; the third non-overlapping clock generation unit is used to output the first clock signal and the third clock signal according to the second signal.

[0007] In one possible implementation of the first aspect, the pulse width extension unit includes a first driver, a first inverter, a second inverter, a third inverter, a fourth inverter, a first OR gate, a first flip-flop, a second flip-flop, a third flip-flop, and a fourth flip-flop. The first terminal of the first driver and the first input terminal of the first OR gate are both connected to the comparison module. The second terminal of the first driver is connected to the input terminal of the first inverter and the reset terminal of the fourth flip-flop, respectively. The input terminal of the first flip-flop is connected to the output terminal of the first inverter. The clock terminals of the first flip-flop and the third flip-flop are both connected to the output terminal of the fourth inverter and the input terminal of the third inverter, respectively. The output terminal of the first flip-flop is connected to the input terminal of the second flip-flop. The reset terminals of the first, second, and third flip-flops are all connected to the output of the first OR gate. The clock terminal of the second flip-flop is connected to the output of the third inverter. The output of the second flip-flop is connected to the input of the third flip-flop. The clock terminal of the fourth flip-flop is connected to the output of the third flip-flop. The input of the fourth flip-flop receives a preset voltage. The output of the fourth flip-flop is connected to the second input of the first OR gate. The NOT output of the fourth flip-flop is connected to the input of the second inverter and the control terminal of the third switch. The output of the second inverter is connected to the control terminal of the second switch. The input of the fourth inverter receives the basic clock signal.

[0008] In one possible implementation of the first aspect, the logic unit includes a fifth inverter and a first NOR gate, the input of the fifth inverter receives the base clock signal, the output of the fifth inverter is connected to the first input of the first NOR gate, the second input of the first NOR gate is connected to the comparison module, and the output of the first NOR gate is connected to the first non-overlapping clock generation unit.

[0009] In one possible implementation of the first aspect, the reference voltage generation module includes an eighth power transistor and a current source. The drain of the eighth power transistor receives the input voltage, and the gate of the eighth power transistor is connected to the source of the eighth power transistor, a first terminal of the current source, and the comparison module, respectively. The second terminal of the current source is grounded. The eighth power transistor and the first power transistor are power transistors of the same type and have the same size.

[0010] In one possible implementation of the first aspect, the comparison module includes a comparator and a sixth inverter, the first input terminal of the comparator is connected to the reference voltage generation module, the second input terminal of the comparator is connected to the output terminal of the error amplifier, the output terminal of the comparator is connected to the input terminal of the sixth inverter, and the output terminal of the sixth inverter is connected to the fourth drive module.

[0011] In one possible implementation of the first aspect, the fourth driving module includes a first driving unit, a second driving unit, and a third driving unit. The first driving unit is connected to the gates of the comparison module, the clock modulation module, the first driving module, and the fifth power transistor, respectively. The second driving unit is connected to the gates of the comparison module, the clock modulation module, the second driving module, and the sixth power transistor, respectively. The third driving unit is connected to the gates of the comparison module, the clock modulation module, the third driving module, and the seventh power transistor, respectively. The first driving unit is configured to output the first driving signal according to the second clock signal to drive the fifth power transistor, and also to output the first control signal according to the second clock signal and the first comparison signal to turn off the first driving module and thus turn off the second power transistor. The second driving unit is used to output the second driving signal according to the third clock signal to drive the sixth power transistor, and also to output the second control signal according to the third clock signal and the first comparison signal to turn off the second driving module and thus turn off the third power transistor. The third driving unit is used to output the third driving signal according to the fourth clock signal to drive the seventh power transistor, and also to output the third control signal according to the fourth clock signal and the first comparison signal to turn off the third driving module and thus turn off the fourth power transistor.

[0012] In one possible implementation of the first aspect, the first driving unit includes a first AND gate and a first driving subunit. The first input terminal of the first AND gate is connected to the comparison module, the output terminal of the first AND gate is connected to the first driving module, the output terminal of the first driving subunit is connected to the gate of the fifth power transistor, and the second input terminal of the first AND gate and the input terminal of the first driving subunit both receive the second clock signal. The second driving unit includes a second AND gate and a second driving subunit. The first input terminal of the second AND gate is connected to the comparison module, the output terminal of the second AND gate is connected to the second driving module, and the output terminal of the second driving subunit is connected to the gate of the sixth power transistor. The second input terminal of the second AND gate and the input terminal of the second driving subunit both receive the third clock signal. The third driving unit includes a third AND gate and a third driving subunit. The first input terminal of the third AND gate is connected to the comparison module, the output terminal of the third AND gate is connected to the third driving module, and the output terminal of the third driving subunit is connected to the gate of the seventh power transistor. The second input terminal of the third AND gate and the input terminal of the third driving subunit both receive the fourth clock signal.

[0013] Secondly, embodiments of this application provide a switching power supply converter, including the negative voltage charge pump circuit described in any one of the first aspects.

[0014] The beneficial effects of the embodiments in this application compared with the prior art are: This application provides a negative voltage charge pump circuit, including a first power transistor, a second power transistor, a third power transistor, a fourth power transistor, an output capacitor, an output resistor, a first resistor, a second resistor, a flying capacitor, a first switch, an error amplifier, a first driving module, a second driving module, and a third driving module. It also includes a clock modulation module, a reference voltage generation module, a comparator module, a fourth driving module, a fifth power transistor, a sixth power transistor, and a seventh power transistor. The fifth power transistor is smaller than the second power transistor and they are of the same type; the sixth power transistor is smaller than the third power transistor and they are of the same type; and the seventh power transistor is smaller than the fourth power transistor and they are of the same type.

[0015] The reference voltage generation module generates a third reference voltage based on a first current. The first current is proportional to the current flowing through the first power transistor. Since the current flowing through the first power transistor represents the load current, the first current reflects changes in the load current. The third reference voltage generated by the reference voltage generation module based on the first current can serve as the threshold voltage for the negative charge pump circuit to enter a light-load condition. The comparison module compares the error voltage output by the error amplifier with the third reference voltage. When the error voltage is greater than the third reference voltage, it indicates that the negative charge pump circuit has entered a light-load condition, and the comparison module outputs a first comparison signal. The clock modulation module outputs a first clock signal, a second clock signal, a third clock signal, and a fourth clock signal based on the first comparison signal and the base clock signal. The fourth drive module is used to output a first drive signal, a second drive signal, and a third drive signal according to the second clock signal, the third clock signal, and the fourth clock signal, respectively, to drive the fifth power transistor, the sixth power transistor, and the seventh power transistor; at the same time, it also outputs a first control signal, a second control signal, and a third control signal according to the four clock signals and the first comparison signal, respectively, to turn off the first drive module, the second drive module, and the third drive module, thereby turning off the second power transistor, the third power transistor, and the fourth power transistor.

[0016] Therefore, when the negative voltage charge pump circuit enters a light load condition, the large-size power transistor and its driving module are turned off, and only the small-size power transistor works. The small-size power transistor automatically determines whether to work based on the absolute value of the output voltage. This can maintain the normal switching cycle of the negative voltage charge pump circuit, ensure the stability of the output voltage, and significantly reduce the operating current under light load conditions without affecting other circuit performance, thus effectively improving the conversion efficiency of the negative voltage charge pump circuit under light load conditions.

[0017] In addition, the clock modulation module in this application is equipped with a narrow pulse modulation unit, which is used to reduce the pulse width of the second clock signal and the fourth clock signal, shorten the conduction time of the small-size power transistor, reduce the energy transfer from the flying capacitor to the output terminal, and further reduce the power consumption of the drive circuit. Compared with the conduction and energy transfer of normal width pulses, narrow pulses can reduce the output voltage ripple.

[0018] In summary, this application generates a third reference voltage through a reference voltage generation module, and then a comparison module compares the third reference voltage with the error voltage output by the error amplifier to determine whether the negative charge pump circuit has entered a light-load condition. When the negative charge pump circuit enters a light-load condition, by shutting down the large-size power transistor and its driver module, only the small-size power transistor is kept operating. The small-size power transistor automatically determines whether to operate based on the absolute value of its output voltage, significantly reducing the operating current of the negative charge pump circuit and improving its conversion efficiency under light load. Simultaneously, the clock signal driving the small-size power transistor is optimized using a narrow-pulse modulation unit in the clock modulation module, further reducing circuit power consumption under light load. This achieves a dual reduction in power consumption under light load, allowing the circuit to maintain high conversion efficiency across the entire load range.

[0019] It is understandable that the beneficial effects of the second aspect mentioned above can be found in the relevant descriptions in the first aspect mentioned above, and will not be repeated here. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 This is a schematic diagram of the circuit connection of an existing charge pump; Figure 2 This is the timing diagram of an existing charge pump. Figure 3 This is a schematic block diagram of a negative pressure charge pump circuit provided in an embodiment of this application; Figure 4 This is a circuit diagram of a negative pressure charge pump circuit provided in an embodiment of this application; Figure 5 This is a schematic block diagram of a narrow pulse modulation unit provided in an embodiment of this application; Figure 6 This is a circuit diagram of a narrow pulse modulation unit provided in an embodiment of this application; Figure 7 This is a timing diagram for burst mode control of a negative pressure charge pump circuit provided in an embodiment of this application.

[0022] In the diagram: 101, Clock modulation module; 1011, Pulse width extension unit; 1012, Logic unit; 1013, First non-overlapping clock generation unit; 1014, Narrow pulse generation unit; 1015, Second non-overlapping clock generation unit; 1016, Third non-overlapping clock generation unit; 102, Reference voltage generation module; 103, Comparison module; 104, Fourth drive module; 1041, First drive unit; 1042, Second drive unit; 1043, Third drive unit. Detailed Implementation

[0023] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application may also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods have been omitted so as not to obscure the description of this application with unnecessary detail.

[0024] It should be understood that, when used in this application specification and the appended claims, the term "comprising" indicates the presence of the described features, integrals, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or a collection thereof.

[0025] It should also be understood that the term “and / or” as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0026] As used in this application specification and the appended claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrase "if determined" or "if [the described condition or event] is detected" may be interpreted, depending on the context, as "once determined," "in response to determination," "once [the described condition or event] is detected," or "in response to detection of [the described condition or event]."

[0027] Furthermore, in the description of this application and the appended claims, the terms "first," "second," "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0028] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0029] Figure 1 A schematic diagram of the circuit connection of an existing charge pump is shown, such as... Figure 1 As shown, the existing charge pump includes a first power transistor M1, a second power transistor M2, a third power transistor M3, a fourth power transistor M4, an output capacitor Cout, an output resistor Rout, a first resistor R1, a second resistor R2, a flying capacitor Cfly, a first switch SW1, an error amplifier EA, a first driver module DRV1, a second driver module DRV2, and a third driver module DRV3. The source of the first power transistor M1 receives the input voltage VIN. The gate of the first power transistor M1 is connected to the first terminal of the first switch SW1. The second terminal of the first switch SW1 is connected to the output terminal of the error amplifier EA. The control terminal of the first switch SW1 receives the first clock signal clk_mp1. The drain of the first power transistor M1 is connected to the drain of the second power transistor M2 and the first terminal of the flying capacitor Cfly. The gate of the second power transistor M2 is connected to... The first driver module DRV1 is connected. The sources of the second power transistor M2 and the third power transistor M3 are both grounded. The gate of the third power transistor M3 is connected to the second driver module DRV2. The drain of the third power transistor M3 is connected to the drain of the fourth power transistor M4 and the second terminal of the flying capacitor Cfly. The gate of the fourth power transistor M4 is connected to the third driver module DRV3. The source of the fourth power transistor M4 is connected to the first terminal of the output capacitor Cout, the first terminal of the output resistor Rout, and the first terminal of the second resistor R2. The second terminal of the second resistor R2 is connected to the first terminal of the first resistor R1 and the first input terminal (inverting input terminal) of the error amplifier EA. The second terminal of the first resistor R1 receives the first reference voltage VREF1, and the second input terminal (non-inverting input terminal) of the error amplifier EA receives the second reference voltage VREF2. The first driver module DRV1 receives the second clock signal clk_mn1, the second driver module DRV2 receives the third clock signal clk_mp2, and the third driver module DRV3 receives the fourth clock signal clk_mn2. The first power transistor M1 and the third power transistor M3 are both PMOS power transistors, while the second power transistor M2 and the fourth power transistor M4 are both NMOS power transistors.

[0030] The first drive module DRV1, the second drive module DRV2, and the third drive module DRV3 are the drive modules for the second power transistor M2, the third power transistor M3, and the fourth power transistor M4, respectively, and are used to output VGMN1, VGMIP2, and VGMN2. The first power transistor M1 is driven by the error amplifier EA, and a first switch SW1 controlled by the first clock signal clk_mp1 is positioned between the error voltage VC and VGMP1. When the first clock signal clk_mp1 is low, the first switch SW1 is on, and the voltage of VGMP1 equals the error voltage VC. When the first clock signal clk_mp1 is high, the first switch SW1 is off, and VGMP1 is high. The first resistor R1 and the second resistor R2 form a voltage divider series. The feedback voltage generated is compared with the second reference voltage VREF2, adjusting the magnitude of the error voltage VC, thereby adjusting the gate-source voltage VGS of the first power transistor M1. This changes the on-resistance of the first power transistor M1, causing a change in the output voltage VOUT, thus forming a feedback system that makes the output voltage VOUT controllable.

[0031] When the first clock signal clk_mp1 is low, the first power transistor M1 and the third power transistor M3 are turned on, while the second power transistor M2 and the fourth power transistor M4 are turned off. The first terminal of the flying capacitor Cfly is connected to the input voltage VIN through the first power transistor M1, and the second terminal of the flying capacitor Cfly is connected to ground through the third power transistor M3. The input voltage VIN charges the flying capacitor Cfly, storing energy. When the first clock signal clk_mp1 is high, the second power transistor M2 and the fourth power transistor M4 are turned on, while the first power transistor M1 and the third power transistor M3 are turned off. The first terminal of the flying capacitor Cfly is connected to ground through the second power transistor M2, and the second terminal of the flying capacitor Cfly is connected to the output capacitor Cout through the fourth power transistor M4. The flying capacitor Cfly charges the output capacitor Cout, transferring energy to it. During discharge, the direction of the flying capacitor Cfly is reversed, so the resulting output voltage VOUT is negative. Ignoring the on-resistance of the power transistor, the existing charge pump can generate a maximum output voltage VOUT of -VIN, which can also be set by the first reference voltage VREF1.

[0032] Figure 2The diagram illustrates the operating timing of an existing charge pump. As the load current Iload decreases, the ripple of the output voltage VOUT decreases each clock cycle. When the load current Iload decreases, if the first power transistor M1 maintains its previous conduction level, the charge replenished by the output voltage VOUT each clock cycle will be greater than the charge consumed, causing the output voltage VOUT to increase. In effect, the first resistor R1 and the second resistor R2 act as feedback units. If the output voltage VOUT decreases (i.e., its absolute value increases), the feedback voltage is sent to the inverting input of the error amplifier EA, resulting in a higher error voltage VC generated by the error amplifier EA. The first power transistor M1 reduces its conduction level when the first clock signal clk_mp1 is low, increasing its on-resistance. This reduces the energy transferred to the flying capacitor Cfly each clock cycle, as well as the energy transferred from the flying capacitor Cfly to the output capacitor Cout. The feedback mechanism causes the error voltage VC to increase as the load current Iload decreases. When the first clock signal clk_mp1 is low, the first switch SW1 is turned on, and the voltage of VGMP1 is equal to the error voltage VCVC. The low potential of VGMP1, like the error voltage VC, rises as the load current Iload decreases. VGMP1, VGMN1, VGMP2, and VGMN2 are all in phase with the clock signal clk. Regardless of the load size, each clock cycle controls the on / off state of the first power transistor M1, the second power transistor M2, the third power transistor M3, and the fourth power transistor M4. In practical designs, to reduce the voltage drop between the absolute values ​​of the output voltage VOUT and the input voltage VIN, and to improve the conversion efficiency of the charge pump under heavy loads, considering that the on-resistance of the power transistors is a major influencing factor, the four power transistors are usually made of larger sizes, resulting in lower on-resistance. However, in actual operation, the charge pump mostly operates under light load or even zero load conditions. When the output load current is extremely small, the operating current of the charge pump is mainly consumed in the periodic driving process of the power transistors, and the periodic on / off operation of the power switches is necessary to maintain the stability of the output voltage VOUT. This results in the charge pump still generating a large operating current when the output load is small, especially under zero load conditions, and the conversion efficiency is extremely poor.

[0033] To address the aforementioned problems, this application provides a negative pressure charge pump circuit, such as... Figure 3As shown, the negative voltage charge pump circuit adds a clock modulation module 101, a reference voltage generation module 102, a comparison module 103, a fourth drive module 104, a fifth power transistor M5, a sixth power transistor M6, and a seventh power transistor M7 to the existing charge pump. Specifically, the fifth power transistor M5 is smaller than the second power transistor M2 and they are of the same type; the sixth power transistor M6 is smaller than the third power transistor M3 and they are of the same type; and the seventh power transistor M7 is smaller than the fourth power transistor M4 and they are of the same type. The comparison module 103 is connected to the reference voltage generation module 102, the output of the error amplifier EA, the clock modulation module 101, and the fourth drive module 104. The fourth drive module 104 is connected to the clock modulation module 101, the first drive module DRV1, the second drive module DRV2, the third drive module DRV3, the gate of the fifth power transistor M5, the gate of the sixth power transistor M6, and the gate of the seventh power transistor M7. The drain of the fifth power transistor M5 is connected to the drain of the second power transistor M2, and the source of the fifth power transistor M5 is connected to the source of the second power transistor M2. The drain of the sixth power transistor M6 is connected to the source of the third power transistor M3, and the source of the sixth power transistor M6 is connected to the drain of the third power transistor M3. The drain of the seventh power transistor M7 is connected to the drain of the fourth power transistor M4, and the source of the seventh power transistor M7 is connected to the source of the fourth power transistor M4.

[0034] Specifically, the reference voltage generation module 102 generates a third reference voltage VREF3 based on the first current. The first current is proportional to the current flowing through the first power transistor M1. Since the current flowing through the first power transistor M1 represents the magnitude of the load current, the first current can reflect changes in the load current. The third reference voltage VREF3 generated by the reference voltage generation module 102 based on the first current can serve as the threshold voltage for the negative charge pump circuit to enter a light-load condition. The comparison module 103 compares the error voltage VC output by the error amplifier EA with the third reference voltage VREF3. When the error voltage VC is greater than the third reference voltage VREF3, it indicates that the negative charge pump circuit has entered a light-load condition, and at this time, the comparison module 103 outputs a first comparison signal. The clock modulation module 101 outputs a first clock signal clk_mp1, a second clock signal clk_mn1, a third clock signal clk_mp2, and a fourth clock signal clk_mn2 based on the first comparison signal and the base clock signal clk. The fourth drive module 104 is used to output a first drive signal VGMN1W, a second drive signal VGMP2W, and a third drive signal VGMN2W according to the second clock signal clk_mn1, the third clock signal clk_mp2, and the fourth clock signal clk_mn2, respectively, to drive the fifth power transistor M5, the sixth power transistor M6, and the seventh power transistor M7; at the same time, it also outputs a first control signal, a second control signal, and a third control signal according to the four clock signals and the first comparison signal, respectively, to turn off the first drive module DRV1, the second drive module DRV2, and the third drive module DRV3, thereby turning off the second power transistor M2, the third power transistor M3, and the fourth power transistor M4.

[0035] Therefore, when the negative voltage charge pump circuit enters a light load condition, the large-size power transistor and its driving module are turned off, and only the small-size power transistor works. The small-size power transistor automatically determines whether to work based on the absolute value of the output voltage VOUT. This can maintain the normal switching cycle of the negative voltage charge pump circuit, ensure the stability of the output voltage VOUT, and significantly reduce the operating current under light load conditions without affecting other circuit performance, thus effectively improving the conversion efficiency of the negative voltage charge pump circuit under light load conditions.

[0036] In addition, the clock modulation module 101 in this application is equipped with a narrow pulse modulation unit. The narrow pulse modulation unit is used to reduce the pulse width of the second clock signal clk_mn1 and the fourth clock signal clk_mn2, shorten the conduction time of the small-size power transistor, reduce the energy transfer from the flying capacitor Cfly to the output terminal, and further reduce the power consumption of the drive circuit. Compared with the conduction and energy transfer of normal width pulses, narrow pulses can reduce the output voltage ripple.

[0037] In summary, this application generates a third reference voltage VREF3 through the reference voltage generation module 102, and then the comparison module 103 compares the third reference voltage VREF3 with the error voltage VC output by the error amplifier EA to determine whether the negative charge pump circuit has entered a light-load condition. When the negative charge pump circuit enters a light-load condition, by turning off the large-size power transistor and its driving module, only the small-size power transistor is kept working. The small-size power transistor automatically determines whether to work based on the absolute value of its output voltage VOUT, significantly reducing the operating current of the negative charge pump circuit and improving its conversion efficiency under light load. At the same time, the narrow pulse modulation unit in the clock modulation module 101 performs pulse width modulation processing to optimize the clock signal driving the small-size power transistor, further reducing the circuit power consumption under light load. This achieves a double reduction in the power consumption of the negative charge pump circuit under light load, allowing the circuit to maintain high conversion efficiency across the entire load range.

[0038] It should be noted that the first comparison signal includes SAVE_POWER and SAVE_POWER_B. SAVE_POWER is transmitted to the clock modulation module 101, and SAVE_POWER_B is transmitted to the fourth drive module 104. SAVE_POWER_B is the inverted signal of SAVE_POWER.

[0039] In some embodiments, the comparison module 103 is further configured to characterize the negative voltage charge pump circuit entering a heavy-load condition when the error voltage VC is less than the third reference voltage VREF3, at which time the comparison module 103 outputs a second comparison signal. When the negative voltage charge pump circuit enters a heavy-load condition, the fourth drive module 104 is further configured to output a fourth control signal, a fifth control signal, and a sixth control signal according to the second comparison signal, the second clock signal clk_mn1, the third clock signal clk_mp2, and the fourth clock signal clk_mn2, respectively, to control the first drive module DRV1 to drive the second power transistor M2, the second drive module DRV2 to drive the third power transistor M3, and the third drive module DRV3 to drive the fourth power transistor M4. It should be noted that the fifth power transistor M5, the sixth power transistor M6, and the seventh power transistor M7 are still in operation at this time, and their drive signals are not affected by the comparison signal. Thus, it can be seen that when the negative voltage charge pump circuit enters a heavy-load condition, the large-size power transistor and the small-size power transistor work together, and the large-size power transistor can maintain the high conversion efficiency of the negative voltage charge pump circuit under heavy load.

[0040] It should be noted that the second comparison signal is out of phase with the first comparison signal. If SAVE_POWER in the first comparison signal is high, then SAVE_POWER in the second comparison signal is low.

[0041] The following is combinedFigure 4 The circuit structure shown describes the principles of the reference voltage generation module 102, the comparison module 103, and the fourth drive module 104.

[0042] In some embodiments, such as Figure 4 As shown, the reference voltage generation module 102 includes an eighth power transistor M8 and a current source. The drain of the eighth power transistor M8 receives the input voltage VIN. The gate of the eighth power transistor M8 is connected to the source of the eighth power transistor M8, the first terminal of the current source, and the comparator module 103, respectively. The second terminal of the current source is grounded. The eighth power transistor M8 and the first power transistor M1 are power transistors of the same type and have the same size.

[0043] Specifically, the first current IREF1 generated by the current source passes through the eighth power transistor M8 to generate the third reference voltage VREF3. Since the eighth power transistor M8 and the first power transistor M1 are of the same type and are matched, the first current IREF1 is proportional to the current flowing through the first power transistor M1. The current flowing through the first power transistor M1 represents the load current Iload. Therefore, the third reference voltage VREF3 generated based on the first current IREF1 can serve as the threshold voltage for the negative charge pump circuit to enter a light load condition. When the error voltage VC is greater than the third reference voltage VREF3, it indicates that the negative charge pump circuit has entered a light load condition. When the error voltage VC is less than the third reference voltage VREF3, it indicates that the negative charge pump circuit has entered a heavy load condition. It should be noted that since the eighth power transistor M8 and the first power transistor M1 are of the same type and are matched, the third reference voltage VREF3 will adapt to different process angles (i.e., production deviations), thus making the range of load current threshold variation when switching power transistor sizes smaller.

[0044] In some embodiments, such as Figure 4 As shown, the comparison module 103 includes a comparator COMP1 and a sixth inverter INV6. The first input terminal of the comparator COMP1 is connected to the reference voltage generation module 102, the second input terminal of the comparator COMP1 is connected to the output terminal of the error amplifier EA, the output terminal of the comparator COMP1 is connected to the input terminal of the sixth inverter INV6, and the output terminal of the sixth inverter INV6 is connected to the fourth drive module 104.

[0045] Specifically, comparator COMP1 compares the error voltage VC output by error amplifier EA with the third reference voltage VREF3. When the error voltage VC is greater than the third reference voltage VREF3, the output SAVE_POWER flips to a high level. After being inverted by the sixth inverter INV6, the output SAVE_POWER_B becomes a low level.

[0046] When the error voltage VC is less than the third reference voltage VREF3, the output SAVE_POWER flips to a low level. After being inverted by the sixth inverter INV6, the output SAVE_POWER_B becomes a high level.

[0047] In some embodiments, such as Figure 4 As shown, the fourth driving module 104 includes a first driving unit 1041, a second driving unit 1042, and a third driving unit 1043. The first driving unit 1041 is connected to the gates of the comparison module 103, the clock modulation module 101, the first driving module DRV1, and the fifth power transistor M5, respectively. The second driving unit 1042 is connected to the gates of the comparison module 103, the clock modulation module 101, the second driving module DRV2, and the sixth power transistor M6, respectively. The third driving unit 1043 is connected to the gates of the comparison module 103, the clock modulation module 101, the third driving module DRV3, and the seventh power transistor M7, respectively.

[0048] The first driving unit 1041 is used to output a first driving signal VGMN1W according to the second clock signal clk_mn1 to drive the fifth power transistor M5, and also outputs a first control signal according to the second clock signal clk_mn1 and the first comparison signal to turn off the first driving module DRV1, thereby turning off the second power transistor M2; the second driving unit 1042 is used to output a second driving signal VGMP2W according to the third clock signal clk_mp2 to drive the sixth power transistor M6, and also outputs a second control signal according to the third clock signal clk_mp2 and the first comparison signal to turn off the second driving module DRV2, thereby turning off the third power transistor M3; the third driving unit 1043 is used to output a third driving signal VGMN2W according to the fourth clock signal clk_mn2 to drive the seventh power transistor M7, and also outputs a third control signal according to the fourth clock signal clk_mn2 and the first comparison signal to turn off the third driving module DRV3, thereby turning off the fourth power transistor M4. Therefore, when the negative voltage charge pump circuit enters a light load condition, the large-size power transistor and its driving module are turned off, and only the small-size power transistor works. This can maintain the normal switching cycle of the negative voltage charge pump circuit, ensure the stability of the output voltage VOUT, and significantly reduce the operating current under light load conditions without affecting other circuit performance, thus effectively improving the conversion efficiency of the negative voltage charge pump circuit under light load conditions.

[0049] It should be noted that the first driving unit 1041 is also used to output a fourth control signal based on the second comparison signal and the second clock signal clk_mn1, a fifth control signal based on the second comparison signal and the third clock signal clk_mp2, and a sixth control signal based on the second comparison signal and the fourth clock signal clk_mn2. These signals are used to control the first driving module DRV1 to drive the second power transistor M2, the second driving module DRV2 to drive the third power transistor M3, and the third driving module DRV3 to drive the fourth power transistor M4, respectively. Therefore, when the negative voltage charge pump circuit enters a heavy load condition, both the large-size and small-size power transistors work together, and the large-size power transistor can maintain the high conversion efficiency of the negative voltage charge pump circuit under heavy load.

[0050] It should be noted that, as Figure 4 As shown, the first driving unit 1041 includes a first AND gate AND1 and a first driving subunit DRV_MN1W. The first input terminal of the first AND gate AND1 is connected to the comparator module 103, and the output terminal of the first AND gate AND1 is connected to the first driving module DRV1. The output terminal of the first driving subunit DRV_MN1W is connected to the gate of the fifth power transistor M5. The second input terminal of the first AND gate AND1 and the input terminal of the first driving subunit DRV_MN1W both receive the second clock signal clk_mn1. Similarly, the second driving unit 1042 includes a second AND gate AND2 and a second driving subunit DRV_MP2W. The first input terminal of the second AND gate AND2 is connected to the comparator module 103, and the output terminal of the second AND gate AND2 is connected to the second driving module DRV_MP2W. RV2 is connected, the output of the second driving sub-unit DRV_MP2W is connected to the gate of the sixth power transistor M6, the second input of the second AND gate AND2 and the input of the second driving sub-unit DRV_MP2W both receive the third clock signal clk_mp2; the third driving unit 1043 includes a third AND gate AND3 and a third driving sub-unit DRV_MN2W, the first input of the third AND gate AND3 is connected to the comparator module 103, the output of the third AND gate AND3 is connected to the third driving module DRV3, the output of the third driving sub-unit DRV_MN2W is connected to the gate of the seventh power transistor M7, the second input of the third AND gate AND3 and the input of the third driving sub-unit DRV_MN2W both receive the fourth clock signal clk_mn2.

[0051] Specifically, when the error voltage VC is greater than the third reference voltage VREF3, the SAVE_POWER_B output by the comparator module 103 is low. Since SAVE_POWER_B is low, the first control signal output by the first AND gate AND1 is low, used to turn off the first drive module DRV1, thereby turning off the second power transistor M2. Similarly, the second control signal output by the second AND gate AND2 is low, used to turn off the second drive module DRV2, thereby turning off the third power transistor M3; the third control signal output by the third AND gate AND3 is low, used to turn off the third drive module DRV3, thereby turning off the fourth power transistor M4. This achieves the goal of turning off three large-sized power transistors under light load conditions.

[0052] When the error voltage VC is less than the third reference voltage VREF3, the SAVE_POWER_B output by the comparator module 103 is high. Since SAVE_POWER_B is high, the fourth control signal output by the first AND gate AND1 is in phase with the second clock signal clk_mn1, and is used to control the first driver module DRV1 to drive the second power transistor M2. Similarly, the fifth control signal output by the second AND gate AND2 is in phase with the third clock signal clk_mp2, and is used to control the second driver module DRV2 to drive the third power transistor M3; the sixth control signal output by the third AND gate AND3 is in phase with the fourth clock signal clk_mn2, and is used to control the third driver module DRV3 to drive the fourth power transistor M4. This allows three large-sized power transistors to operate under heavy load conditions.

[0053] It should be noted that the first driving subunit DRV_MN1W is only controlled by the second clock signal clk_mn1, the second driving subunit DRV_MP2W is only controlled by the third clock signal clk_mp2, and the third driving subunit DRV_MN2W is only controlled by the fourth clock signal clk_mn2. Therefore, regardless of the operating condition of the negative voltage charge pump circuit, the first driving subunit DRV_MN1W always outputs the first driving signal VGMN1W according to the second clock signal clk_mn1 to drive the fifth power transistor M5, the second driving subunit DRV_MP2W always outputs the second driving signal VGMP2W according to the third clock signal clk_mp2 to drive the sixth power transistor M6, and the third driving subunit DRV_MN2W always outputs the third driving signal VGMN2W according to the fourth clock signal clk_mn2 to drive the seventh power transistor M7.

[0054] To further reduce the operating current under light load conditions, the negative voltage charge pump circuit of this application also includes a clock modulation module 101, which is described below in conjunction with... Figure 5 to Figure 7 The circuit diagram and timing diagram shown illustrate the principle of the clock modulation module 101.

[0055] In one embodiment of this application, such as Figure 5 As shown, the narrow pulse modulation unit includes a pulse width extension unit 1011, a logic unit 1012, a first non-overlapping clock generation unit 1013, a narrow pulse generation unit 1014, a second switch SW2, a third switch SW3, a second non-overlapping clock generation unit 1015, and a third non-overlapping clock generation unit 1016. The pulse width extension unit 1011 and the logic unit 1012 are both connected to the comparison module 103. The pulse width extension unit 1011 is connected to the control terminals of the second switch SW2 and the third switch SW3, respectively. The first non-overlapping clock generation unit 1015 is connected to the control terminals of the second switch SW2 and the third switch SW3, respectively. The first terminal of the second switch SW2 and the third non-overlapping clock generation unit 1016 are connected to the logic unit 1012, the narrow pulse generation unit 1014, the first terminal of the second switch SW2, and the third non-overlapping clock generation unit 1016. The first terminal of the third switch SW3 is connected to the narrow pulse generation unit 1014. The second terminal of the third switch SW3 and the second terminal of the second switch SW2 are both connected to the second non-overlapping clock generation unit 1015. The second non-overlapping clock generation unit 1015 and the third non-overlapping clock generation unit 1016 are both connected to the fourth drive module 104. The third non-overlapping clock generation unit 1016 is connected to the control terminal of the first switch SW1.

[0056] Specifically, the pulse width extension unit 1011 is used to output a first pulse width extension signal POWER_SAVE_EXT_B and a second pulse width extension signal POWER_SAVE_EXT based on the first comparison signal and the base clock signal clk. The second pulse width extension signal POWER_SAVE_EXT is the inverted signal of the first pulse width extension signal POWER_SAVE_EXT_B, and is used to control the on / off state of the second switch SW2 and the third switch SW3, respectively. The logic unit 1012 is used to output a logic signal based on the first comparison signal and the base clock signal clk. The first non-overlapping clock generation unit 1013 is used to output a first signal clk_mn and a second signal clk_mp based on the logic signal. The narrow pulse generation unit 1014 is used to generate a narrow pulse signal from the first signal clk_mn. When the second switch SW2 is on and the third switch SW3 is off, the first signal clk_mn can be directly transmitted to the second non-overlapping clock generation unit 1015 through the second switch SW2. When the second switch SW2 is off and the third switch SW3 is on (light load condition), the first signal clk_mn is converted into a narrow pulse signal by the narrow pulse generation unit 1014, and the narrow pulse signal can be transmitted to the second non-overlapping clock generation unit 1015 through the third switch SW3. The second non-overlapping clock generation unit 1015 outputs a second clock signal clk_mn1 and a fourth clock signal clk_mn2 with normal pulse width (the pulse width corresponding to the pulse width of the base clock signal clk) based on the first signal clk_mn, and also outputs a second clock signal clk_mn1 and a fourth clock signal clk_mn2 with narrower pulse width based on the narrow pulse signal. The third non-overlapping clock generation unit 1016 directly receives the second signal clk_mp and outputs the first clock signal clk_mp1 and the third clock signal clk_mp2 according to the second signal clk_mp, indicating that the pulse widths of the first clock signal clk_mp1 and the third clock signal clk_mp2 maintain normal pulse widths.

[0057] In one embodiment of this application, such as Figure 6As shown, the pulse width extension unit 1011 includes a first driver BUF1, a first inverter INV1, a second inverter INV2, a third inverter INV3, a fourth inverter INV4, a first OR gate OR1, a first flip-flop D1, a second flip-flop D2, a third flip-flop D3, and a fourth flip-flop D4. The first terminal of the first driver BUF1 and the first input terminal of the first OR gate OR1 are both connected to the comparator module 103. The second terminal of the first driver BUF1 is connected to the input terminal of the first inverter INV1 and the reset terminal (Reset terminal) of the fourth flip-flop D4, respectively. The input terminal (D terminal) of the first flip-flop D1 is connected to the output terminal of the first inverter INV1. The clock terminals (Clk terminals) of the first flip-flop D1 and the clock terminals of the third flip-flop D3 are both connected to the output terminal of the fourth inverter INV4 and the input terminal of the third inverter INV3, respectively. The output terminal (Q terminal) is connected to the input terminal of the second flip-flop D2. The reset terminals of the first flip-flop D1, the second flip-flop D2, and the third flip-flop D3 are all connected to the output terminal of the first OR gate OR1. The clock terminal of the second flip-flop D2 is connected to the output terminal of the third inverter INV3. The output terminal of the second flip-flop D2 is connected to the input terminal of the third flip-flop D3. The clock terminal of the fourth flip-flop D4 is connected to the output terminal of the third flip-flop D3. The input terminal of the fourth flip-flop D4 receives a preset voltage. The output terminal of the fourth flip-flop D4 is connected to the second input terminal of the first OR gate OR1. The NOT output terminal (Q NOT terminal) of the fourth flip-flop D4 is connected to the input terminal of the second inverter INV2 and the control terminal of the third switch SW3, respectively. The output terminal of the second inverter INV2 is connected to the control terminal of the second switch SW2. The input terminal of the fourth inverter INV4 receives the basic clock signal clk.

[0058] Specifically, the four flip-flops (D flip-flops) of the pulse width extension unit 1011 work together to form the core counting unit. They also work with the reset and trigger logic of the SAVE_POWER signal to realize the pulse width extension function. The three D flip-flops, the first flip-flop D1, the second flip-flop D2, and the third flip-flop D3, sequentially detect the falling edge, rising edge, and falling edge of the basic clock signal clk, respectively, to complete the clock edge counting trigger. After the SAVE_POWER signal changes from low to high, the three flip-flops sequentially detect the corresponding clock edge trigger transmission, which finally makes the Q2 signal output by the third flip-flop D3 go high and the Q-not output of the fourth flip-flop D4 go low, that is, POWER_SAVE_EXT goes low, and the pulse width extension time ends. Simultaneously, when the SAVE_POWER signal goes high, or when the Q signal output by the fourth flip-flop D4 goes high (i.e., the timing ends), combined with the operation logic of the first OR gate OR1, the output of the first OR gate OR1 outputs a high level. This synchronously resets the first flip-flop D1, the second flip-flop D2, and the third flip-flop D3, restoring them to their initial states to trigger the next pulse width extension timing. Each D flip-flop works together to complete the pulse width extension and shutdown control of the POWER_SAVE_EXT signal. The first inverter INV1, the second inverter INV2, the third inverter INV3, and the fourth inverter INV4 are all used to invert the input signal, and the first driver BUF1 is used to improve the driving capability.

[0059] In one embodiment of this application, such as Figure 6 As shown, the logic unit 1012 includes a fifth inverter INV5 and a first NOR gate NOR1. The input of the fifth inverter INV5 receives the base clock signal clk. The output of the fifth inverter INV5 is connected to the first input of the first NOR gate NOR1. The second input of the first NOR gate NOR1 is connected to the comparison module 103. The output of the first NOR gate NOR1 is connected to the first non-overlapping clock generation unit 1013.

[0060] Specifically, combining the operational logic of the fifth inverter INV5 and the first NOR gate NOR1, it can be seen that when the SAVE_POWER signal goes high (light load condition), the first NOR gate NOR1 outputs a low level; when the SAVE_POWER signal goes low (heavy load condition) and the base clock signal clk is high, the first NOR gate NOR1 outputs a high level. Finally, the processed logic signal is output to the first non-overlapping clock generation unit 1013, providing the basic logic trigger signal for the modulation of the subsequent clock signal.

[0061] like Figure 7 As shown, Figure 6The timing diagram of the control circuit is shown. During actual operation, the load of the charge pump changes dynamically, therefore the duration of the high level of the light load indicator signal SAVE_POWER also varies. Under light load, the SAVE_POWER signal goes high, and all power transistor drive circuits stop working. Because the load is very small, the absolute value of the output voltage VOUT can be maintained. When the light load duration causes the absolute value of the output voltage VOUT to decrease, the SAVE_POWER signal goes low, discharging to the output capacitor Cout, causing the absolute value of the output voltage VOUT to rise slightly. After the absolute value of the output voltage VOUT rises, the SAVE_POWER signal goes high again. Because the switching action is stopped during the period when the SAVE_POWER signal is high, the average switching frequency is significantly reduced, thus reducing switching losses. Figure 7 The two high-active-pulse falling edges of the SAVE_POWER signal occur during the low and high levels of the base clock signal clk, respectively. During the first high-pulse phase of the SAVE_POWER signal, after its falling edge arrives, the output Q0 of the first flip-flop D1 goes high when triggered by the falling edge of the base clock signal clk. Immediately following, the rising edge of the base clock signal clk triggers the output Q1 of the second flip-flop D2 to go high, and then the falling edge of the base clock signal clk triggers the output Q2 of the third flip-flop D3 to go high. When the rising edge of Q2 arrives, the fourth flip-flop D4 is triggered, causing the POWER_SAVE_EXT signal to go low. Define the time from when the SAVE_POWER signal goes high to when the POWER_SAVE_EXT signal goes low as t1. During this t1 period, clk_mn1 and clk_mn2 are both narrow pulses, with the pulse width of clk_mn2 being t2. This corresponds to a shortened time for the flying capacitor Cfly to transfer energy to the output, while clk_mp1 and clk_mp2 maintain their normal pulse widths to ensure the normal charging process of the flying capacitor Cfly. If the SAVE_POWER signal remains low after going low, and the t1 period ends, clk_mp1, clk_mp2, clk_mn1, and clk_mn2 all return to their normal pulse widths. At this time, the charge pump circuit switches to heavy-load operation. During the second high pulse phase of the SAVE_POWER signal, after its falling edge arrives, the falling edge of the base clock clk triggers faster, and the output Q0 of the first flip-flop D1 goes high earlier, causing a corresponding change in the duration of t1. The timing logic of the remaining signals remains consistent with the first high pulse phase. During the few cycles after the SAVE_POWER signal ends at its high level, only a short pulse discharges to the output capacitor Cout, so the absolute value of the output voltage VOUT changes little, and the output voltage VOUT ripple will be even smaller when operating under light load and skip cycle conditions.

[0062] This application also provides a switching power supply converter, including the aforementioned negative charge pump circuit. The switching power supply converter employing the aforementioned negative charge pump circuit can automatically shut down large-size power transistors and perform narrow-pulse modulation of the clock signal under light load conditions, significantly reducing operating current and drive losses under light loads, effectively improving conversion efficiency across the entire load range, while ensuring load-carrying capacity and output stability under heavy load conditions. It also features low power consumption and high adaptability, better meeting the needs of various electronic devices for efficient, stable, and energy-saving power supply systems.

[0063] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0064] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A negative voltage charge pump circuit, comprising a first power transistor, a second power transistor, a third power transistor, a fourth power transistor, an output capacitor, an output resistor, a first resistor, a second resistor, a flying capacitor, a first switch, an error amplifier, a first driving module, a second driving module, and a third driving module. The source of the first power transistor receives an input voltage, the gate of the first power transistor is connected to a first terminal of the first switch, the second terminal of the first switch is connected to the output terminal of the error amplifier, the control terminal of the first switch receives a first clock signal, the drain of the first power transistor is connected to the drain of the second power transistor and the first terminal of the flying capacitor, and the gate of the second power transistor is connected to the first driving module. The sources of the second power transistor and the third power transistor are both grounded. The gate of the third power transistor is connected to the second driving module. The drain of the third power transistor is connected to the drain of the fourth power transistor and the second terminal of the flying capacitor. The gate of the fourth power transistor is connected to the third driving module. The source of the fourth power transistor is connected to the first terminal of the output capacitor, the first terminal of the output resistor, and the first terminal of the second resistor. The second terminal of the second resistor is connected to the first terminal of the first resistor and the first input terminal of the error amplifier. The second terminal of the first resistor receives a first reference voltage, and the second input terminal of the error amplifier receives a second reference voltage. Its features are, The negative voltage charge pump circuit further includes a clock modulation module, a reference voltage generation module, a comparison module, a fourth drive module, a fifth power transistor, a sixth power transistor, and a seventh power transistor. The fifth power transistor is smaller than the second power transistor and they are of the same type. The sixth power transistor is smaller than the third power transistor and they are of the same type. The seventh power transistor is smaller than the fourth power transistor and they are of the same type. The comparison module is connected to the reference voltage generation module, the output of the error amplifier, the clock modulation module, and the fourth drive module. The fourth drive module is connected to the... The clock modulation module, the first driving module, the second driving module, the third driving module, the gate of the fifth power transistor, the gate of the sixth power transistor, and the gate of the seventh power transistor are connected. The drain of the fifth power transistor is connected to the drain of the second power transistor, and the source of the fifth power transistor is connected to the source of the second power transistor. The drain of the sixth power transistor is connected to the source of the third power transistor, and the source of the sixth power transistor is connected to the drain of the third power transistor. The drain of the seventh power transistor is connected to the drain of the fourth power transistor, and the source of the seventh power transistor is connected to the source of the fourth power transistor. The reference voltage generation module is used to generate a third reference voltage based on a first current, wherein the first current is proportional to the current flowing through the first power transistor. The comparison module is used to compare the error voltage output by the error amplifier with the third reference voltage, and outputs a first comparison signal when the error voltage is greater than the third reference voltage; The clock modulation module is used to output a first clock signal, a second clock signal, a third clock signal, and a fourth clock signal according to the first comparison signal and the base clock signal. The clock modulation module is configured with a narrow pulse modulation unit. The narrow pulse modulation unit is used to reduce the pulse width of the second clock signal and the fourth clock signal; The fourth driving module is used to output a first driving signal, a second driving signal, and a third driving signal according to the second clock signal, the third clock signal, and the fourth clock signal, respectively, to drive the fifth power transistor, the sixth power transistor, and the seventh power transistor. The fourth driving module also outputs a first control signal, a second control signal, and a third control signal according to the first comparison signal, the second clock signal, the third clock signal, and the fourth clock signal, respectively, to turn off the first driving module, the second driving module, and the third driving module, thereby turning off the second power transistor, the third power transistor, and the fourth power transistor.

2. The negative pressure charge pump circuit according to claim 1, characterized in that, The comparison module is further configured to output a second comparison signal when the error voltage is less than the third reference voltage; the fourth driving module is further configured to output a fourth control signal, a fifth control signal, and a sixth control signal according to the second comparison signal, the second clock signal, the third clock signal, and the fourth clock signal, respectively, to control the first driving module to drive the second power transistor, the second driving module to drive the third power transistor, and the third driving module to drive the fourth power transistor.

3. The negative pressure charge pump circuit according to claim 1, characterized in that, The narrow pulse modulation unit includes a pulse width extension unit, a logic unit, a first non-overlapping clock generation unit, a narrow pulse generation unit, a second switch, a third switch, a second non-overlapping clock generation unit, and a third non-overlapping clock generation unit. The pulse width extension unit and the logic unit are both connected to the comparison module. The pulse width extension unit is connected to the control terminals of the second switch and the third switch, respectively. The first non-overlapping clock generation unit is connected to the logic unit, the narrow pulse generation unit, the first terminal of the second switch, and the third non-overlapping clock generation unit, respectively. The first terminal of the third switch is connected to the narrow pulse generation unit. The second terminals of both the third switch and the second switch are connected to the second non-overlapping clock generation unit. The second and third non-overlapping clock generation units are both connected to the fourth driving module. The third non-overlapping clock generation unit is connected to the control terminal of the first switch. The pulse width extension unit is used to output a first pulse width extension signal and a second pulse width extension signal according to the first comparison signal and the base clock signal, wherein the second pulse width extension signal is the inverted signal of the first pulse width extension signal; the second switch is used to turn on or off according to the second pulse width extension signal, and the third switch is used to turn on or off according to the first pulse width extension signal; the logic unit is used to output a logic signal according to the first comparison signal and the base clock signal; the first non-overlapping clock generation unit is used to output a first signal and a second signal according to the logic signal; the narrow pulse generation unit is used to generate a narrow pulse signal from the first signal; the second non-overlapping clock generation unit is used to output the second clock signal and the fourth clock signal according to the narrow pulse signal when the third switch is turned on; the third non-overlapping clock generation unit is used to output the first clock signal and the third clock signal according to the second signal.

4. The negative pressure charge pump circuit according to claim 3, characterized in that, The pulse width extension unit includes a first driver, a first inverter, a second inverter, a third inverter, a fourth inverter, a first OR gate, a first flip-flop, a second flip-flop, a third flip-flop, and a fourth flip-flop. The first terminal of the first driver and the first input terminal of the first OR gate are both connected to the comparison module. The second terminal of the first driver is connected to the input terminal of the first inverter and the reset terminal of the fourth flip-flop, respectively. The input terminal of the first flip-flop is connected to the output terminal of the first inverter. The clock terminals of the first and third flip-flops are connected to the output terminal of the fourth inverter and the input terminal of the third inverter, respectively. The output terminal of the first flip-flop is connected to the input terminal of the second flip-flop. The reset terminals of the first, second, and third flip-flops are all connected to the output of the first OR gate. The clock terminal of the second flip-flop is connected to the output of the third inverter. The output of the second flip-flop is connected to the input of the third flip-flop. The clock terminal of the fourth flip-flop is connected to the output of the third flip-flop. The input of the fourth flip-flop receives a preset voltage. The output of the fourth flip-flop is connected to the second input of the first OR gate. The NOT output of the fourth flip-flop is connected to the input of the second inverter and the control terminal of the third switch. The output of the second inverter is connected to the control terminal of the second switch. The input of the fourth inverter receives the base clock signal.

5. The negative pressure charge pump circuit according to claim 3, characterized in that, The logic unit includes a fifth inverter and a first NOR gate. The input of the fifth inverter receives the base clock signal, the output of the fifth inverter is connected to the first input of the first NOR gate, the second input of the first NOR gate is connected to the comparison module, and the output of the first NOR gate is connected to the first non-overlapping clock generation unit.

6. The negative voltage charge pump circuit according to claim 1, characterized in that, The reference voltage generation module includes an eighth power transistor and a current source. The drain of the eighth power transistor receives the input voltage. The gate of the eighth power transistor is connected to the source of the eighth power transistor, the first terminal of the current source, and the comparison module. The second terminal of the current source is grounded. The eighth power transistor and the first power transistor are the same type of power transistor and have the same size.

7. The negative voltage charge pump circuit according to claim 1, characterized in that, The comparison module includes a comparator and a sixth inverter. The first input terminal of the comparator is connected to the reference voltage generation module, the second input terminal of the comparator is connected to the output terminal of the error amplifier, the output terminal of the comparator is connected to the input terminal of the sixth inverter, and the output terminal of the sixth inverter is connected to the fourth drive module.

8. The negative pressure charge pump circuit according to claim 1, characterized in that, The fourth driving module includes a first driving unit, a second driving unit, and a third driving unit. The first driving unit is connected to the gate of the comparison module, the clock modulation module, the first driving module, and the fifth power transistor, respectively. The second driving unit is connected to the gate of the comparison module, the clock modulation module, the second driving module, and the sixth power transistor, respectively. The third driving unit is connected to the gate of the comparison module, the clock modulation module, the third driving module, and the seventh power transistor, respectively. The first driving unit is configured to output the first driving signal according to the second clock signal to drive the fifth power transistor, and also to output the first control signal according to the second clock signal and the first comparison signal to turn off the first driving module and thus turn off the second power transistor. The second driving unit is used to output the second driving signal according to the third clock signal to drive the sixth power transistor, and also to output the second control signal according to the third clock signal and the first comparison signal to turn off the second driving module and thus turn off the third power transistor. The third driving unit is used to output the third driving signal according to the fourth clock signal to drive the seventh power transistor, and also to output the third control signal according to the fourth clock signal and the first comparison signal to turn off the third driving module and thus turn off the fourth power transistor.

9. The negative pressure charge pump circuit according to claim 8, characterized in that, The first driving unit includes a first AND gate and a first driving subunit. The first input terminal of the first AND gate is connected to the comparison module, the output terminal of the first AND gate is connected to the first driving module, the output terminal of the first driving subunit is connected to the gate of the fifth power transistor, and the second input terminal of the first AND gate and the input terminal of the first driving subunit both receive the second clock signal. The second driving unit includes a second AND gate and a second driving subunit. The first input terminal of the second AND gate is connected to the comparison module, the output terminal of the second AND gate is connected to the second driving module, and the output terminal of the second driving subunit is connected to the gate of the sixth power transistor. The second input terminal of the second AND gate and the input terminal of the second driving subunit both receive the third clock signal. The third driving unit includes a third AND gate and a third driving subunit. The first input terminal of the third AND gate is connected to the comparison module, the output terminal of the third AND gate is connected to the third driving module, and the output terminal of the third driving subunit is connected to the gate of the seventh power transistor. The second input terminal of the third AND gate and the input terminal of the third driving subunit both receive the fourth clock signal.

10. A switching power supply converter, characterized in that, Includes the negative pressure charge pump circuit according to any one of claims 1-9.

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