Dynamic comparator for successive approximation analog-to-digital converter

Abstract

This invention discloses a dynamic comparator for a successive approximation analog-to-digital converter (ADC), relating to the field of comparator technology. The dynamic comparator includes: a cascaded pre-amplifier circuit and a latch circuit; the pre-amplifier circuit includes at least a differential input pair of transistors, a positive feedback loop, and a first tail current source; the differential input pair is used to receive external differential input signals; the positive feedback loop and the first tail current source are both connected to the differential input pair; the first tail current source includes three NMOS transistors connected in parallel; the three NMOS transistors connected in parallel are used to dynamically bias the differential input pair; the positive feedback loop is connected between the two signal output nodes of the pre-amplifier circuit; the positive feedback loop is used to increase the gain of the pre-amplifier circuit. This invention addresses the problems of large footprint and difficult offset calibration in existing successive approximation ADCs.

Description

Technical Field

[0001] This invention relates to the field of comparator technology, and more particularly to a dynamic comparator for successive approximation analog-to-digital converters. Background Technology

[0002] Successive approximation analog-to-digital converters (SAR ADCs), widely used in medium-to-high precision and medium-speed scenarios, rely heavily on comparators as their core functional module. The performance of the comparator directly determines the overall signal conversion quality and reliability of the SAR ADC. The core working principle of a SAR ADC is based on a successive approximation binary search logic, gradually narrowing down the possible range of the analog signal to ultimately convert the input continuous analog signal into a discrete digital signal. In this process, the comparator needs to perform bit-by-bit comparisons from the most significant bit (MSB) to the least significant bit (LSB). Due to the fundamental differences in the comparison logic and signal characteristics of different bits, the performance requirements for the comparator exhibit significant stage-specific variations: during the MSB comparison stage, the output step size of the SAR ADC is relatively large, corresponding to a higher amplitude of the output analog signal. At this time, the signal strength itself is much greater than the strength of noise interference, and the impact of noise on the comparison result is almost negligible. The core objective of this stage is to shorten the time required for a single comparison. Therefore, the comparator needs to have a high-speed response capability to accelerate the iterative process of successive approximation, thereby improving the overall conversion speed of SARADC.

[0003] In the LSB comparison stage, as the successive approximation process progresses, the output step size of the digital-to-analog converter gradually decreases, and the amplitude variation of the output signal becomes extremely weak. At this point, the object of comparison is a weak signal approaching the quantization limit. The requirement for comparison speed is greatly reduced, but the impact of noise is significantly amplified. Weak signals are highly susceptible to noise interference, leading to deviations in the comparison results and consequently affecting the final conversion accuracy. Therefore, the core requirement for this stage is that the comparator possesses low-noise characteristics. By suppressing noise interference, accurate judgment of weak signals is ensured, guaranteeing the conversion accuracy of the SAR ADC.

[0004] In analog integrated circuit design, high speed and low noise are mutually exclusive and contradictory characteristics. This is because increasing speed usually leads to increased noise, while reducing noise may sacrifice speed. To balance the different requirements of the MSB and LSB comparison stages, existing technologies mostly adopt dual comparator or dual-mode comparator schemes.

[0005] The dual comparator scheme designs two independent comparators with different performance characteristics. One comparator focuses on high-speed response and is adapted for MSB comparison, while the other focuses on low noise and is adapted for LSB comparison. The two comparators are dynamically switched according to the needs of different comparison stages.

[0006] The dual-mode comparator approach adjusts the operating mode of a single comparator, such as by changing parameters like bias current and load resistance, to switch between high-speed and low-noise modes to adapt to different needs. Both approaches attempt to find a trade-off between speed and noise, but both have significant, unavoidable drawbacks.

[0007] For the dual comparator scheme, an additional complete comparator structure needs to be designed, which will significantly increase the chip area and is not conducive to the miniaturization design of integrated circuits. More importantly, the device characteristics of the two independent comparators, such as threshold voltage and size deviation, have inherent differences, which makes it difficult to keep their offset voltages consistent. The inconsistency of offset voltage will directly affect the accuracy of the comparison results, and complex calibration algorithms are needed to compensate for this difference, which greatly increases the calibration difficulty and cost.

[0008] While dual-mode comparator schemes do not require additional comparator structures, the circuit topology, such as bias current paths and load resistor connections, changes during mode switching, leading to dynamic fluctuations in offset voltage. These fluctuations further increase calibration complexity, requiring separate calibration for each mode and compensation for offset bias caused by mode switching. Furthermore, these fluctuations may affect conversion accuracy due to incomplete calibration of offset fluctuations, making it difficult to meet the stringent application requirements of high-precision SAR ADCs. Summary of the Invention

[0009] The purpose of this invention is to provide a dynamic comparator for successive approximation analog-to-digital converters (ADCs) to solve the problems of large area occupation and difficult offset calibration in existing successive approximation ADCs, while taking into account the high speed of MSB comparison and the low noise requirement of LSB comparison.

[0010] To achieve the above objectives, the present invention provides the following technical solution: In a first aspect, the present invention provides a dynamic comparator for a successive approximation analog-to-digital converter, comprising: Cascaded preamplifier circuit and latch circuit; The pre-amplifier circuit includes at least a differential input pair of transistors, a positive feedback loop, and a first tail current source; the differential input pair of transistors is used to receive external differential input signals; the positive feedback loop and the first tail current source are both connected to the differential input pair of transistors; The first tail current source includes three NMOS transistors connected in parallel; the three NMOS transistors connected in parallel are used to dynamically bias the differential input pair transistors. The positive feedback loop is connected between the two signal output nodes of the pre-amplifier circuit; the positive feedback loop is used to increase the gain of the pre-amplifier circuit.

[0011] Optionally, the three NMOS transistors connected in parallel include a first NMOS transistor, a second NMOS transistor, and a third NMOS transistor; The first and second NMOS transistors are controlled to conduct by the two signal output nodes of the pre-amplifier circuit, respectively; the third NMOS transistor is controlled to conduct by the first clock signal.

[0012] Optionally, the total width-to-length ratio of the three NMOS transistors connected in parallel is a preset value.

[0013] Optionally, the pre-amplifier circuit may also include a pull-up transistor; The pull-up transistor is connected to the differential input pair.

[0014] Optionally, the two signal output nodes of the pre-amplifier circuit are the first signal output node and the second signal output node, respectively. The differential input pair includes a fourth NMOS transistor and a fifth NMOS transistor; the pull-up transistors include a first PMOS transistor and a second PMOS transistor. The drains of the first PMOS transistor and the fourth NMOS transistor are both connected to the first signal output node. The drains of the second PMOS transistor and the fifth NMOS transistor are both connected to the second signal output node; The source of the fourth NMOS transistor is connected to the source of the fifth NMOS transistor; the drains of the three NMOS transistors connected in parallel are all connected to the source of the fourth NMOS transistor.

[0015] Optionally, the positive feedback loop includes a third PMOS transistor and a fourth PMOS transistor; The gate of the third PMOS transistor and the drain of the fourth PMOS transistor are both connected to the first signal output node. The gate of the fourth PMOS transistor and the drain of the third PMOS transistor are both connected to the second signal output node.

[0016] Optionally, the latching circuit includes a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, and a ninth NMOS transistor; the fifth PMOS transistor is the second tail current source; and the gate of the fifth PMOS transistor is connected to a second clock signal.

[0017] Optionally, the three NMOS transistors connected in parallel are dynamically turned on during the regeneration phase according to the voltage changes of the first signal output node and the second signal output node, adjusting the overdrive voltage of the differential input pair transistors. The overdrive voltage decreases synchronously with the voltage of the first signal output node and the second signal output node, thereby reducing the equivalent input noise.

[0018] Optionally, in the later stage of the regeneration phase, the voltages of the first signal output node and the second signal output node both decrease and form a differential voltage, the currents of the first NMOS transistor and the second NMOS transistor both decrease and the rate of decrease differs, the third NMOS transistor remains in the conducting state, and the total tail current of the first tail current source decreases.

[0019] Optionally, the positive feedback loop increases the output resistance of the pre-amplifier circuit, increases the gain of the pre-amplifier circuit, and reduces the noise of the latch circuit equivalent to the input of the pre-amplifier circuit.

[0020] Compared with existing technologies, this invention solves the problems of large chip area and difficult offset calibration in existing technologies through a single-structure design, while simultaneously meeting the requirements of high-speed MSB comparison and low-noise LSB comparison. Specifically, a positive feedback loop is added to the pre-amplifier circuit, and the traditional single tail current source is replaced with a first tail current source composed of three parallel NMOS transistors, forming an integrated optimized structure: the first tail current source composed of three parallel NMOS transistors dynamically biases the differential input pair transistors, which can optimize the circuit power consumption and noise characteristics; the positive feedback loop is connected between the two output nodes of the pre-amplifier circuit, and by increasing the output resistance and amplification factor, it can improve the signal processing speed to meet the high-speed requirements of MSB comparison, while ensuring the signal processing accuracy to meet the low-noise requirements of LSB comparison. This design does not require an additional comparator main structure, and achieves synergistic optimization of high speed and low noise within a single comparator, fundamentally overcoming the inherent defects of dual comparators and dual-mode comparators. Attached Figure Description

[0021] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings: Figure 1 A schematic diagram of the circuit structure of a dynamic comparator for a successive approximation analog-to-digital converter provided as an embodiment of the present invention; Figure 2 A schematic diagram of the circuit structure of a latch circuit provided in one embodiment of the present invention; Figure 3 A schematic diagram of the state of a dynamic comparator during the regeneration phase, provided as an embodiment of the present invention; Figure 4 A test diagram provided for one embodiment of the present invention.

[0022] Figure labels: 1-Pre-amplifier circuit; 2-Latch circuit; 10-Differential input pair; 11-Positive feedback loop; 12-First tail current source; 13-Pull-up transistor. Detailed Implementation

[0023] To facilitate a clear description of the technical solutions in the embodiments of the present invention, the terms "first" and "second" are used to distinguish identical or similar items with essentially the same function and effect. For example, the first threshold and the second threshold are merely used to distinguish different thresholds and do not limit their order. Those skilled in the art will understand that the terms "first" and "second" do not limit the quantity or execution order, and that the terms "first" and "second" are not necessarily different.

[0024] It should be noted that in this invention, the terms "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in this invention should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of terms such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0025] In this invention, "at least one" means one or more, and "more than one" means two or more. "And / or" describes the relationship between the associated objects, indicating that three relationships can exist.

[0026] like Figure 1 As shown, this embodiment of the invention provides a dynamic comparator for a successive approximation analog-to-digital converter, which may include: a cascaded preamplifier circuit 1 and a latch circuit 2; The pre-amplifier circuit 1 includes at least a differential input pair transistor 10, a positive feedback loop 11, and a first tail current source 12; the differential input pair transistors are used to receive external differential input signals; the positive feedback loop 11 and the first tail current source 12 are both connected to the differential input pair transistor 10; The first tail current source 12 includes three NMOS transistors connected in parallel; the three NMOS transistors connected in parallel are used to dynamically bias the differential input pair transistor 10. The positive feedback loop 11 is connected between the two signal output nodes of the pre-amplifier circuit 1; the positive feedback loop 11 is used to increase the output resistance and amplification factor of the pre-amplifier circuit 1.

[0027] It should be noted that the traditional dynamic comparators in existing SAR ADCs typically include cascaded pre-amplifier and latch circuits. However, the tail current source of the pre-amplifier circuit is usually composed of a single MOSFET and lacks the positive feedback loop described in this invention. Existing comparators have significant drawbacks: firstly, a single tail current source cannot flexibly adjust the bias state, making it difficult to simultaneously meet the high-speed requirements of MSB comparison and the low-noise requirements of LSB comparison. Designing a larger tail current for high speed would significantly increase noise and power consumption; conversely, reducing the tail current to lower noise would sacrifice comparison speed. Secondly, the pre-amplifier circuit lacks a positive feedback enhancement mechanism, resulting in limited output resistance and amplification factor. This not only leads to slow signal establishment but also fails to effectively attenuate the noise equivalent to the input from the latch circuit, affecting comparison accuracy. To address these contradictions, existing technologies often employ dual comparators or dual-mode comparators. However, such solutions require additional circuit modules, significantly increasing chip area. Furthermore, the introduction of multiple modules increases the complexity of offset calibration and reduces circuit stability.

[0028] The beneficial effects of this embodiment: This embodiment of the invention proposes a single-structure, multi-functional dynamic comparator design. The core improvements are in two aspects: first, a positive feedback loop is added to the pre-amplification circuit of a single comparator; second, the single tail current source MOS transistor in the traditional pre-amplification stage is replaced with three NMOS transistors connected in parallel, forming a simplified structure that integrates dynamic bias and positive feedback enhancement. Through the above structural improvements, without adding an additional comparator main structure, high-speed comparison and low-noise performance can be simultaneously optimized within a single comparator. It can meet the high-speed requirements of MSB comparison and the accuracy requirements of LSB comparison, fundamentally overcoming the inherent defects of existing dual comparators and dual-mode comparators, such as large area occupation and difficulty in offset calibration, while also optimizing dynamic power consumption characteristics.

[0029] See Figure 1 It can be seen that the pre-amplifier circuit also includes pull-up transistor 13; pull-up transistor 13 is connected to the differential input pair transistor 10.

[0030] like Figure 1 As shown, the two signal output nodes of the pre-amplifier circuit are the first signal output node. Second signal output node .

[0031] The differential input pair 10 includes a fourth NMOS transistor MN4 and a fifth NMOS transistor MN5. The gate of the fourth NMOS transistor MN4 is connected to the first differential input signal in the external differential input signal. The gate of the fifth NMOS transistor MN5 is connected to the second differential input signal in the external differential input signal. The source of the fourth NMOS transistor MN4 is connected to the source of the fifth NMOS transistor MN5. The drains of the three NMOS transistors connected in parallel are all connected to the source of the fourth NMOS transistor MN4.

[0032] The pull-up transistors include a first PMOS transistor MP1 and a second PMOS transistor MP2. The source of the first PMOS transistor MP1 and the source of the second PMOS transistor MP2 are connected to the power supply VDD. The gate of the first PMOS transistor MP1 and the gate of the second PMOS transistor MP2 are connected to the first clock signal CLK1.

[0033] The drains of the first PMOS transistor MP1 and the fourth NMOS transistor MN4 are both connected to the first signal output node. Connected. The drains of the second PMOS transistor MP2 and the fifth NMOS transistor MN5 are both connected to the second signal output node. Connected.

[0034] like Figure 1 As shown, the three NMOS transistors connected in parallel include the first NMOS transistor MN1, the second NMOS transistor MN2, and the third NMOS transistor MN3.

[0035] The first NMOS transistor MN1 and the second NMOS transistor MN2 are controlled to conduct by the two signal output nodes of the pre-amplifier circuit, respectively; the third NMOS transistor MN3 is controlled to conduct by the first clock signal CLK1. For example, the gate of the first NMOS transistor MN1 is connected to the first signal output node. Connected to the first signal output node The output signal, and the gate of the second NMOS transistor MN2 is connected to the second signal output node. Connect to access the second signal output node The output signal is CLK1. The gate of the third NMOS transistor MN3 is connected to the first clock signal CLK1.

[0036] like Figure 1 As shown, the positive feedback loop 11 includes a third PMOS transistor MP3 and a fourth PMOS transistor MP4. The sources of both the third PMOS transistor MP3 and the fourth PMOS transistor MP4 are connected to the power supply VDD.

[0037] The gate of the third PMOS transistor MP3 and the drain of the fourth PMOS transistor MP4 are both connected to the first signal output node. Connected; the gate of the fourth PMOS transistor MP4 and the drain of the third PMOS transistor MP3 are both connected to the second signal output node. Connected.

[0038] like Figure 2As shown, the latching circuit includes a fifth PMOS transistor MP5, a sixth PMOS transistor MP6, a seventh PMOS transistor MP7, a sixth NMOS transistor MN6, a seventh NMOS transistor MN7, an eighth NMOS transistor MN8, and a ninth NMOS transistor MN9; the fifth PMOS transistor MP5 is the second tail current source; the gate of the fifth PMOS transistor MP5 is connected to the second clock signal. The source of the fifth PMOS transistor MP5 is connected to the power supply VDD.

[0039] Specifically, the sources of the sixth PMOS transistor MP6 and the seventh PMOS transistor MP7 are both connected to the drain of the fifth PMOS transistor. The gates of the sixth PMOS transistor MP6 and the seventh NMOS transistor MN7 are connected to the first node A. The drains of the sixth PMOS transistor MP6, the sixth NMOS transistor MN6, and the seventh NMOS transistor MN7 are connected to the third signal output node of the latch circuit. The gate of the seventh PMOS transistor MP7 and the gate of the eighth NMOS transistor MN8 are connected to the second node B. The drains of the seventh PMOS transistor MP7, the eighth NMOS transistor MN8, and the ninth NMOS transistor MN9 are connected to the fourth signal output node of the latch circuit. First node A and fourth signal output node Connected; the second node B and the third signal output node Connected. The gate of the sixth NMOS transistor MN6 receives signals from the first signal output node. The gate of the ninth NMOS transistor MN9 receives the signal from the second signal output node. The signal.

[0040] Based on the circuit structure described above, the complete operating cycle (reset phase and regeneration phase) of the dynamic comparator in the embodiment of the present invention will be explained below.

[0041] I. Reset Phase (CLK=0, CLKN=1).

[0042] When the first clock signal CLK1=0 and the second clock signal CLK2=1 in the clock signal, the dynamic comparator of the present invention enters the reset phase.

[0043] In the pre-amplification circuit, the first clock signal CLK1 is low, turning on the first PMOS transistor MP1 and the second PMOS transistor MP2, thus turning on the first signal output node. Second signal output node Pull up to the power supply voltage VDD.

[0044] The third NMOS transistor MN3 of the first tail current source is also controlled by CLK1 and is in the off state at this time. The fourth NMOS transistor MN4 and the fifth NMOS transistor MN5 of the preamplifier stage have no bias current and stop signal processing.

[0045] In the latch circuit, when the second clock signal is high, the fifth PMOS transistor MP5 of the second tail current source is turned off, and the third signal output node of the latch circuit... and the fourth signal output node It is pulled down to a low level, completing the reset preparation.

[0046] The core function of the reset phase is to clear the signal residue from the previous cycle, providing an initial state for accurate comparison in the subsequent regeneration phase. Noise in this phase will not affect the subsequent comparison results.

[0047] II. Regeneration stage (CLK=1, CLKN=0).

[0048] When the clock signal switches to the first clock signal CLK1=1 and the second clock signal CLK2=0, the comparator enters the core regeneration phase.

[0049] (1) After the reset phase ends, the regeneration phase is in the initial state. , The node remains at a high level during the reset phase, causing the first NMOS transistor MN1 and the second NMOS transistor MN2 in the first tail current source to conduct. Since CLK=1, the third NMOS transistor MN3 also conducts. Therefore, all three NMOS transistors connected in parallel are conducting. At this time, the total tail current of the first tail current source can be consistent with the tail current of a traditional dynamic comparator, ensuring that the differential input pair transistors MN4 and MN5 can obtain sufficient initial current, guaranteeing the high-speed response capability required for MSB comparison.

[0050] (2) External differential input signal and The gates of differential input transistors MN4 and MN5 are connected respectively, converting the differential signal into a differential current. , The node discharges, and the discharge process causes the first signal output node to discharge. Second signal output node The output voltage gradually decreases.

[0051] Because the gate of MN1 is Connected, the gate of MN2 is connected to Therefore, in the later stage of the regeneration phase, the first signal output node is connected. Second signal output node The voltage decreases, causing the gate-source voltage of the first NMOS transistor MN1 and the second NMOS transistor MN2 to decrease and their on-current to decrease. Therefore, the total tail current in the first tail current source decreases synchronously, avoiding... , The parasitic capacitance of the node discharges to the ground terminal, reducing dynamic power consumption.

[0052] The current of the differential input pair transistors MN4 and MN5 is provided by the first tail current source. As the total tail current of the first tail current source gradually decreases, the current of MN4 and MN5 also decreases synchronously, and the rate of decrease is faster than that of a traditional comparator, resulting in a gradual decrease in the overdrive voltage corresponding to MN4 and MN5.

[0053] Specifically, according to the equivalent input noise formula derived by Lazavi: (1); It is evident that reducing the overdrive voltage directly and significantly reduces the equivalent input noise of the comparator, achieving the low-noise performance required for LSB comparison. Specifically, This is the equivalent input noise; This represents the overdrive voltage of each differential input pair transistor. Since MN4 and MN5 are symmetrical differential pairs, their overdrive voltages are equal, so they are represented by the same symbol. The same applies to other transistor parameters. for and Parasitic capacitance of nodes; Boltzmann's constant; Absolute temperature; The noise figures of MOS transistors MN4 and MN5 are given. For the threshold voltages of MN4 and MN5; MN4 and MN5 are the gate-source voltages.

[0054] In summary, the three NMOS transistors MN1, MN2, and MN3 connected in parallel output nodes during the regeneration phase according to the first signal. Second signal output node The voltage change dynamically activates the differential input pair transistors MN4 and MN5, adjusting their overdrive voltages. The overdrive voltages follow the first signal output node. Second signal output node The voltage decreases synchronously, reducing the equivalent input noise.

[0055] (3) The present invention introduces a positive feedback loop composed of the third PMOS transistor MP3 and the fourth PMOS transistor MP4 in the pre-amplifier circuit. The positive feedback loop plays a continuous role in the signal establishment process during the regeneration stage. The positive feedback loop increases the output resistance of the pre-amplifier circuit, increases the gain of the pre-amplifier circuit, i.e. the voltage amplification factor, and reduces the noise of the latch circuit equivalent to the input terminal of the pre-amplifier circuit (i.e., the differential input transistor pair).

[0056] Specifically, according to the core formula for the voltage amplification factor of the pre-amplification stage: (2); The gain of the pre-amplifier circuit can be calculated; where, This represents the gain of the pre-amplifier circuit. Transconductance of the differential input pair transistor; The output resistance of the pre-amplifier circuit is given by formula (2). Since the positive feedback loop can increase the output resistance of the pre-amplifier circuit, the output resistance can be increased. The increase directly improves the gain of the pre-amplifier circuit. . ; Electron mobility; For gate oxide capacitance; This represents the width-to-length ratio of the MOSFET. "||" indicates parallel connection; The output resistance of the first tail current source; This refers to the output resistance of the differential input pair transistors (MN4 and MN5). That is, the value of Rout is determined by the impedance of MN4 / MN5 and the impedance of the first tail current source. The positive feedback loop indirectly improves the overall efficiency by suppressing current shunting in these two impedance branches. .

[0057] Based on the topology of the positive feedback loop in this invention, the principle of increasing the output resistance Rout can be broken down into "dynamic current compensation" and "impedance parallel suppression", which is fully adapted to the signal change process in the regeneration stage.

[0058] First, positive feedback suppresses current loss at the output node through "dynamic current compensation".

[0059] During the regeneration phase, the differential input signal will cause , A differential voltage difference is generated between the two output nodes (e.g.) > At this time, the drain currents of MN4 and MN5 will differ. ),lead to Excessive current loss at nodes and rapid voltage drop will cause the output resistance ro2 of the differential input pair transistors to decrease implicitly due to increased current fluctuations if this current loss is not suppressed, thus violating the impedance stability of ro2.

[0060] The positive feedback loop compensates for the current and stabilizes the output resistance ro2 in the following way, thereby improving Rout: when > hour: The high voltage will cause the gate voltage of the positive feedback transistor MP4 to... Increased power level → Reduced conduction capability of MP4 (PMOS transistor characteristic: The closer to 0, the smaller the conduction current. →MP4 direction The pull-up current of the node (flowing from VDD to...) ) decrease; at the same time, The low voltage will cause the gate voltage of the positive feedback transistor MP3 to... Reduce → Enhance MP3's conductivity → MP3 to The pull-up current of the node (flowing from VDD to) Increase; final, The node's additional pull-up current due to MP3 suppresses current loss; The reduced pull-up current of the node due to MP4 prevents excessive current compensation, effectively reducing the current change at the output node. Macroscopically, this manifests as... The impedance increases because current changes are suppressed, and the voltage's ability to impede current becomes stronger.

[0061] Secondly, positive feedback reduces tail current shunting and increases the output resistance of the first tail current. The equivalent impedance.

[0062] The output resistance of the first tail current source Essentially, it is the total impedance of MN1, MN2, and MN3 connected in parallel. If the current from the tail current source is additionally shunted, it will lead to... The impedance decreases because current shunting is equivalent to adding parallel branches, thus reducing the total impedance.

[0063] The positive feedback loop suppresses the shunting of the tail current through signal linkage, indirectly improving... : Late regeneration phase, first signal output node With the second signal output node The voltages of both NMOS transistors decrease and form a stable differential voltage. The currents of the first NMOS transistor MN1 and the second NMOS transistor MN2 decrease, but at different rates. The third NMOS transistor MN3 remains on, and its current is unaffected. and Due to voltage changes, the total tail current of the first tail current source decreases synchronously.

[0064] Positive feedback loop will drive , The differential signal is established quickly, specifically in two scenarios: Scenario 1, if the initial differential signal... > =The current in MN1 decreases faster than that in MN2, and more of the total current from the tail current source flows to MN2; Scenario 2, if the initial differential signal is > In this scenario, the current in MN2 decreases faster than that in MN1, and more of the total current from the tail current source flows to MN1. Both scenarios reduce the current shunting in one branch, causing the total tail current of the first tail current source to decrease synchronously.

[0065] The suppression of tail current shunting means that the current output of the tail current source is more stable, and its equivalent output resistance ro1 is increased due to the reduction of parallel shunting (the smaller the current in the parallel branch, the closer the total impedance is to the impedance of a single branch).

[0066] And a positive feedback loop can drive , The principle of rapid differential signal establishment can be analyzed from two aspects: "positive feedback effect of signal amplification" and "discharge difference due to increased output resistance". Firstly, there is the positive feedback signal amplification effect.

[0067] The gates of MP3 and MP4 in the positive feedback loop are respectively connected to and Node, when , A tiny voltage difference (e.g., V) is generated due to differential current discharge. >V )hour: High voltage will increase the gate voltage of the MP4, weakening its conduction capability and causing the drain (connection point) of the MP4 to... The pull-up current decreases, further accelerating Discharge; at the same time The low voltage will reduce the gate voltage of the MP3 player, enhance its conduction capability, and increase the drain voltage (connected to the MP3 player). The pull-up current increases, slowing down The discharge; the above positive feedback process will amplify and The voltage difference between them allows the differential signal to quickly transform from a small difference to a significant difference, shortening the signal settling time.

[0068] Secondly, the increased output resistance leads to a greater discharge difference.

[0069] The positive feedback loop increases the output resistance of the pre-amplifier circuit. ,and , The discharge rate is determined by "differential current × output resistance" (V = I × R). When When the value increases, under the same differential current, and The voltage difference will be more significant, further accelerating the establishment of the differential signal.

[0070] In summary, on the one hand, when the noise of the latch circuit is equivalent to the input of the preamplifier circuit, it needs to be divided by a higher Au, which will result in more significant noise attenuation and reduce the contribution of the latch circuit to the equivalent input noise. The logic is: latch circuit noise → reverse transmission to the input of the preamplifier → divided by Au → the larger the Au, the smaller the equivalent noise.

[0071] On the other hand, the positive feedback loop will accelerate the first signal output node. Second signal output node The establishment speed of the differential signal further improves the comparator's response speed, achieving a synergistic optimization of high speed and low noise.

[0072] (4) With the pre-amplifier circuit , Once the differential signal of the node is established, the latch circuit enters the working state.

[0073] Because the second clock signal CLK2=0, the fifth PMOS transistor MP5 of the second tail current source of the latch circuit is turned on, affecting the third signal output node. Fourth signal output node Charge it so that , The voltage gradually increases; simultaneously, the pre-amplifier circuit... , The node signal is connected to the gates of the sixth NMOS transistor MN6 and the ninth NMOS transistor MN9 in the latch circuit, because , There is a voltage difference (e.g., V) >V The conduction current of MN6 is greater than that of MN9, resulting in The discharge rate is slower than Ultimately, this led to V >V .

[0074] when , When the voltage difference is large enough, the positive feedback mechanism of the latch circuit is activated, rapidly amplifying the differential signal and completing the final comparison result latching.

[0075] Understandably, as the currents of MN1 and MN2 decrease, the total tail current of the first tail current source decreases synchronously, causing the drain discharge current of the differential input pair transistors MN4 and MN5 to decrease accordingly, thereby leading to a decrease in the first signal output node. Second signal output node The discharge rate is slowed down and the depth of discharge is reduced (i.e., the node voltage does not drop to ground GND, but remains in the preset medium-high level range). This characteristic avoids the parasitic capacitance from being completely discharged to GND and ensures the effectiveness of signal establishment. Especially in ultra-high speed comparator applications, it can significantly reduce the energy loss of capacitor charging and discharging, and significantly reduce dynamic power consumption.

[0076] The novel low-noise dynamic comparator of the present invention addresses the core defects of existing solutions through targeted structural improvements.

[0077] I. Solve the problem of traditional dual comparators occupying a large chip area.

[0078] This invention optimizes the tail current source of the pre-amplification stage based on the traditional comparator, splitting it into MN1, MN2 and MN3, and adding a positive feedback loop. There is no additional complete comparator, and the area is close to that of the traditional comparator, avoiding the large area waste of adding an extra comparator in the dual comparator.

[0079] II. Addressing the shortcomings of poor consistency in dual comparator offset and instability in dual-mode comparator offset. This invention employs a single comparator structure, eliminating the need to switch devices or modes: through dynamic adjustment of the tail current and a positive feedback loop, the requirements for high MSB speed and low LSB noise are simultaneously met within the same comparator. This eliminates the problem of offset differences between the two devices in a dual comparator and avoids the cause of offset fluctuations due to mode switching in a dual-mode comparator, ensuring the consistency and stability of offset characteristics.

[0080] Third, it addresses the shortcomings of traditional comparators in terms of noise performance.

[0081] Dynamic adjustment of tail current to reduce noise: Tail current decreases in the later stage of regeneration → differential input pair overdrive voltage decreases → according to formula (1), equivalent input noise is reduced.

[0082] Noise suppression via positive feedback loop: The positive feedback loop increases the gain of the pre-amplifier stage, which means that the noise from the latch circuit is attenuated more significantly when it is equivalent to the input, thus further reducing the overall noise.

[0083] Fourth, it addresses the drawback of high dynamic power consumption in traditional comparators.

[0084] In the later stage of regeneration, the tail current decreases, which reduces the discharge depth of the first and second signal output nodes, preventing the capacitor from being completely discharged to GND and reducing the energy loss of capacitor charging and discharging. This is especially suitable for ultra-high-speed scenarios.

[0085] It should be noted that the total width-to-length ratio of the three NMOS transistors connected in parallel is a preset value, and this total width-to-length ratio can be consistent with the width-to-length ratio of a single tail current source MOS transistor in a traditional dynamic comparator. The ratio of the width-to-length ratios among the three NMOS transistors connected in parallel can be set according to requirements. Alternatively, it can be said that the three NMOS transistors MN1, MN2, and MN3 connected in parallel in this embodiment are obtained by splitting a single tail current source MOS transistor in a traditional dynamic comparator. The total width-to-length ratio of the three is a preset value, and this preset value is the same as the width-to-length ratio of a single tail current source MOS transistor in a traditional dynamic comparator. The ratio of the width-to-length ratios among MN1, MN2, and MN3 can be set according to actual requirements.

[0086] To verify the low-noise performance of this invention, simulation tests were conducted on the designed dynamic comparator. Using a 28nm process, while ensuring that the dimensions of the differential input pair transistors MN4 and MN5 and other components remained unchanged, the single tail current MOS transistor of the traditional dynamic comparator was split into three parallel NMOS transistors (MN1, MN2, and MN3), and MN1, MN2, and MN3 were configured with different aspect ratios for comparison. To maintain the preset ratio, the overall width-to-length ratio of the three components is consistent with the width-to-length ratio of a single tail current source MOSFET in a traditional comparator. The simulation uses the Pss+Pac+Pnoise method, integrating noise over a frequency range of 1MHz to half the clock frequency. The test results are as follows... Figure 4 And the data shown in Table 1 below.

[0087] Table 1: Test data of three NMOS transistors connected in parallel Figure 4 The dynamic trend of the tail current during the regeneration stage is intuitively presented: the first tail current source of the comparator in this invention is affected by MN1 and MN2. , Dynamic control of node voltage causes the total tail current to decrease rapidly from its initial value, with a significantly greater rate of decrease than that of a traditional single tail current source. This characteristic directly leads to a rapid reduction in the overdrive voltage of the differential input pair transistors. According to the equivalent input noise formula, the reduction in overdrive voltage is positively correlated with noise suppression, ultimately achieving lower noise performance.

[0088] Table 1, through comparison of multiple sets of variables, further verifies the technological innovation of this invention in reducing input noise: 1) Comparing "1:0:0 (no positive feedback loop)" and "1:0:0 (with positive feedback loop)," it can be seen that simply adding a positive feedback loop can reduce the noise from 0.568mV to 0.563mV, proving the progress of positive feedback in improving gain and suppressing noise; 2) As the ratio of MN1 and MN2 increases (from 2:1:1 to 2:3:3 and then to 0:1:1), the noise continues to decrease, verifying the synergistic optimization advantages of the dynamic bias tail current source and the positive feedback loop. By splitting the tail current source and dynamically adjusting the conduction state, combined with the enhancement of positive feedback gain, a stepwise reduction in noise is achieved. Compared with the traditional solution, the maximum noise reduction is more than 10%, fully demonstrating the technological breakthrough of this invention in low-noise design.

[0089] It is important to note that the size of MN3 is not absolutely zero in practical applications, but rather needs to be set to an extremely small preset size. The core purpose of this design is to provide an initial conduction path using MN3 at the beginning of the regeneration phase, ensuring that the tail current source quickly enters the working state and guarantees the high-speed response capability required for MSB comparison; as the regeneration phase progresses, , As the node voltage decreases, MN1 and MN2 gradually dominate the dynamic adjustment of the tail current. The extremely small size of MN3 will not affect the core characteristic of the tail current changing with the signal. This avoids the speed loss caused by the tail current start-up delay in the early stage of regeneration, and maximizes the dynamic biasing effect of MN1 and MN2 to achieve low noise performance.

[0090] For high-precision comparators (the total size of the first tail current source is usually larger), the noise reduction effect of the present invention will be more prominent, further verifying the effectiveness of the above working principle.

[0091] Although the invention has been described herein in conjunction with various embodiments, those skilled in the art will understand and implement other variations of the disclosed embodiments by reviewing the accompanying drawings, the disclosure, and the appended claims in carrying out the claimed invention. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality.

[0092] Although the invention has been described in conjunction with specific features and embodiments, it is obvious that various modifications and combinations can be made therein without departing from the spirit and scope of the invention. Accordingly, this specification and drawings are merely exemplary descriptions of the invention as defined by the appended claims, and are considered to cover any and all modifications, variations, combinations, or equivalents within the scope of the invention. Clearly, those skilled in the art can make various alterations and modifications to the invention without departing from its spirit and scope. Thus, if such modifications and modifications of the invention fall within the scope of the claims and their equivalents, the invention is also intended to include such modifications and modifications.

Claims

1. A dynamic comparator for a successive approximation analog-to-digital converter, characterized in that, include: Cascaded preamplifier circuit and latch circuit; The pre-amplifier circuit includes at least a differential input pair of transistors, a positive feedback loop, and a first tail current source; The differential input pair is used to receive external differential input signals; the positive feedback loop and the first tail current source are both connected to the differential input pair. The first tail current source includes three NMOS transistors connected in parallel; the three NMOS transistors connected in parallel are used to dynamically bias the differential input pair transistors. The positive feedback loop is connected between the two signal output nodes of the pre-amplifier circuit; the positive feedback loop is used to increase the gain of the pre-amplifier circuit.

2. The dynamic comparator for a successive approximation analog-to-digital converter according to claim 1, characterized in that, The three NMOS transistors connected in parallel include a first NMOS transistor, a second NMOS transistor, and a third NMOS transistor; The first NMOS transistor and the second NMOS transistor are respectively controlled to be turned on by the two signal output nodes of the pre-amplifier circuit; the third NMOS transistor is controlled to be turned on by the first clock signal.

3. The dynamic comparator for a successive approximation analog-to-digital converter according to claim 1, characterized in that, The total width-to-length ratio of the three NMOS transistors connected in parallel is a preset value.

4. The dynamic comparator for a successive approximation analog-to-digital converter according to claim 1, characterized in that, The pre-amplification circuit also includes a pull-up transistor; The pull-up transistor is connected to the differential input pair.

5. The dynamic comparator for a successive approximation analog-to-digital converter according to claim 4, characterized in that, The two signal output nodes of the pre-amplifier circuit are the first signal output node and the second signal output node, respectively. The differential input pair includes a fourth NMOS transistor and a fifth NMOS transistor; the pull-up transistor includes a first PMOS transistor and a second PMOS transistor; The drain of the first PMOS transistor and the drain of the fourth NMOS transistor are both connected to the first signal output node; The drains of the second PMOS transistor and the fifth NMOS transistor are both connected to the second signal output node; The source of the fourth NMOS transistor is connected to the source of the fifth NMOS transistor; the drains of the three NMOS transistors connected in parallel are all connected to the source of the fourth NMOS transistor.

6. The dynamic comparator for a successive approximation analog-to-digital converter according to claim 5, characterized in that, The positive feedback loop includes a third PMOS transistor and a fourth PMOS transistor; The gate of the third PMOS transistor and the drain of the fourth PMOS transistor are both connected to the first signal output node. The gate of the fourth PMOS transistor and the drain of the third PMOS transistor are both connected to the second signal output node.

7. The dynamic comparator for a successive approximation analog-to-digital converter according to claim 5, characterized in that, The latching circuit includes a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, and a ninth NMOS transistor; the fifth PMOS transistor is the second tail current source; the gate of the fifth PMOS transistor is connected to a second clock signal.

8. The dynamic comparator for a successive approximation analog-to-digital converter according to claim 5, characterized in that, The three NMOS transistors connected in parallel are dynamically turned on during the regeneration phase according to the voltage changes of the first signal output node and the second signal output node, adjusting the overdrive voltage of the differential input pair transistors. The overdrive voltage decreases synchronously with the voltage of the first signal output node and the second signal output node, thereby reducing the equivalent input noise.

9. The dynamic comparator for a successive approximation analog-to-digital converter according to claim 7, characterized in that, In the later stage of regeneration, the voltages of the first signal output node and the second signal output node both decrease and form a differential voltage. The currents of the first NMOS transistor and the second NMOS transistor both decrease, but the rate of decrease differs. The third NMOS transistor remains in the on state, and the total tail current of the first tail current source decreases.

10. The dynamic comparator for a successive approximation analog-to-digital converter according to claim 1, characterized in that, The positive feedback loop increases the output resistance of the pre-amplifier circuit, increases the gain of the pre-amplifier circuit, and reduces the noise of the latch circuit equivalent to the input of the pre-amplifier circuit.

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