An enhanced PWM chopper circuit and method

Abstract

The application discloses an enhanced PWM chopper circuit and method, and belongs to the technical field of internal PWM peripherals of a DSP chip.The circuit of the application is integrated in the internal part of the DSP chip, and is composed of a low-frequency pulse generation module, a chopping clock generation module and a pulse modulation and synthesis unit in cascade.The original PWM square wave is reconstructed into a composite signal with a low-frequency energy envelope and a high-frequency fine chopping through hardware logic;the corresponding method realizes the frequency and duty cycle adjustment of the low-frequency pulse width and the high-frequency chopping clock through programmable configuration, and simultaneously designs an edge synchronization, boundary protection and timing optimization mechanism to ensure that the composite signal has no burr and the pulse is complete.The application does not occupy CPU resources, realizes the hardware programmable generation of a complex PWM chopping waveform, reduces switching loss, improves waveform quality and system integration, and can be widely applied to scenes such as precision driving, audio synthesis and high-power power electronic control.

Description

Technical Field

[0001] This invention relates to the field of PWM peripheral technology for DSP chips, specifically to an enhanced PWM chopper circuit and method, which is suitable for secondary modulation of PWM signals in DSP chips. It can generate a composite PWM chopper signal of low-frequency long pulse envelope + high-frequency chopper pulse in hardware, and is widely used in precision motor drive, audio synthesis, high-power power electronic control, electromagnetic compatibility optimization and other scenarios. Background Technology

[0002] The PWM (Pulse Width Modulation) module is one of the core peripherals of a DSP chip. It achieves functions such as energy regulation and waveform generation by outputting alternating high and low level square wave signals, and is widely used in industrial control, consumer electronics, and power electronics. Traditional PWM modules within DSP chips have relatively basic functions, only able to output standard square waves with fixed frequency and duty cycle. This presents significant technical limitations in applications requiring complex waveform modulation.

[0003] Limited functionality and reliance on CPU software simulation: Traditional PWM cannot directly generate composite waveforms such as frequency dithering, specific harmonic elimination, and low-frequency long pulse + high-frequency chopping. To achieve such complex modulation, it is necessary to simulate through CPU software interrupts or timers. This method will consume a lot of CPU resources, resulting in a decrease in the real-time response speed of the DSP system and difficulty in generating high-frequency, high-precision composite modulation signals.

[0004] Poor flexibility and low system integration: For special applications such as precision driving and audio synthesis that require "low-frequency long pulse envelope to achieve energy transmission + internal high-frequency chopping to achieve fine adjustment", existing PWM modules cannot be directly configured in hardware and often require external dedicated PWM chopping chips, which not only increases hardware costs but also increases circuit complexity and reduces system integration and reliability.

[0005] Waveform quality and switching losses are difficult to balance: When traditional PWM square waves are directly used for high-power switching control, the fixed switching frequency leads to high switching losses and high harmonic content. Additional filtering circuits are required to meet application requirements, which further increases the system cost.

[0006] To address the aforementioned issues, some existing solutions attempt to achieve simple frequency adjustment by expanding the register configuration of the PWM module, but still cannot achieve composite modulation of low-frequency envelope and high-frequency chopping; other solutions achieve composite waveform generation through external chopping circuits, but do not solve the problems of low system integration and high cost. Summary of the Invention

[0007] This invention addresses the shortcomings of traditional DSP chip PWM modules, such as limited functionality, reliance on CPU software to simulate complex waveforms, and inability to implement low-frequency envelope and high-frequency chopping composite modulation in hardware. It provides an enhanced PWM chopping circuit and method. The invention integrates the circuit within the DSP chip, consisting of three cascaded functional modules forming a pure hardware modulation architecture. Programmable registers allow for flexible adjustment of the low-frequency pulse width, high-frequency chopping clock frequency, and duty cycle. Edge synchronization, boundary protection, and timing optimization mechanisms are designed to ensure the composite chopping signal is glitch-free and pulses are complete. The corresponding method performs signal modulation, synthesis, and optimization through hardware logic, requiring no CPU software intervention throughout. This invention achieves hardware-based generation of complex PWM chopping waveforms, reducing switching losses, improving waveform quality and system integration, while freeing up CPU resources and enhancing the real-time response capability of the DSP system.

[0008] To solve the above-mentioned technical problems, the present invention provides the following technical solution:

[0009] An enhanced PWM chopper circuit is integrated inside a DSP chip and connected to an external system clock SysClk and a raw PWM square wave signal. It includes a low-frequency pulse generation module, a chopper clock generation module, and a pulse modulation and synthesis unit. The three modules are cascaded in sequence. The pulse modulation and synthesis unit interacts bidirectionally with the low-frequency pulse generation module and the chopper clock generation module, respectively, and finally outputs a hybrid modulation chopper signal ChopOut.

[0010] The low-frequency pulse generation module has a built-in configurable register. It uses 8 system clock cycles as a standard time unit Tunit and generates a low-frequency long pulse signal P_low with a width of N×8×Tsys based on the rising edge trigger count of the original PWM square wave, where N = configurable register + 1 and Tsys is the system clock cycle.

[0011] The chopper clock generation module has a built-in frequency division configuration register and a duty cycle configuration register [2:0]. It uses SysClk / 8 as the highest chopper frequency reference to generate a high-frequency chopper clock signal with a frequency of fmax_chop / M and a duty cycle of 12.5%~87.5% that is adjustable in seven levels, where M = frequency division configuration register + 1.

[0012] The pulse modulation and synthesis unit is the core processing module, including a timing register submodule, a boundary alignment submodule, a boundary protection submodule, and a signal synthesis submodule. It realizes chopping region definition, edge synchronization, pulse integrity protection, timing optimization, and final signal synthesis, and outputs a glitch-free, pulse-complete composite chopping signal.

[0013] As a further technical solution of the present invention: In the chopper clock generation module, the upper limit of the high-level duration count value of the high-frequency chopper clock is Counthigh=(frequency division configuration register+1)×8×(register+1). When the chopper clock counter value ≤ Counthigh, the chopper clock signal outputs a high level, and vice versa.

[0014] As a further technical solution of the present invention: the timing register submodule of the pulse modulation and synthesis unit adopts a two-stage D flip-flop to continuously register the initial chopping region signal for two cycles in the system clock domain, thereby eliminating metastability risks and logic competition, and outputting a stable original chopping region signal.

[0015] As a further technical solution of the present invention: the boundary alignment submodule of the pulse modulation and synthesis unit includes a front-end boundary alignment submodule, which synchronously samples the original chopping region signal under the chopping clock signal, performs a logical AND operation between the sampled signal and the original chopping region signal to obtain chopping region signal 1, so that the starting boundary of the chopping region is strictly aligned to the rising edge of the chopping clock signal.

[0016] As a further technical solution of the present invention: the boundary protection submodule of the pulse modulation and synthesis unit monitors the falling edge of the original PWM square wave in real time. If the chopping clock signal is high when the falling edge is detected, it is determined that there is an incomplete chopping pulse. The chopping region signal 2 is immediately set high and extended to the next falling edge of the chopping clock signal to ensure the integrity of the chopping pulse.

[0017] As a further technical solution of the present invention: the pulse modulation and synthesis unit has a built-in timing optimization circuit and adopts a dual trigger synchronization and delay chain matching design to prevent glitches from occurring during the switching of the gate signal and ensure that the output waveform edges are clean.

[0018] An enhanced PWM chopping method based on the above circuit, which realizes composite modulation of the original PWM square wave through hardware logic without CPU software intervention, includes the following steps:

[0019] S1: Generate a low-frequency long pulse signal P_low: Responding to the rising edge of the original PWM square wave, the low-frequency pulse generation module starts counting with the system clock SysClk as the beat. The counting threshold is configured by the configurable register. When the count value is ≤ N, P_low remains high, N = configurable register + 1. If it exceeds, it is pulled low. When the next rising edge of the PWM arrives, the counter is reset, generating a low-frequency long pulse with a width of N×8×Tsys.

[0020] S2: Generate high-frequency chopper clock signal: After the chopper function is enabled, the chopper clock generation module uses SysClk / 8 as the highest reference frequency, configures the division coefficient M through the division configuration register to generate an adjustable frequency chopper clock signal, and then configures the Counthigh value through the register to realize the generation of a high-frequency chopper clock with seven duty cycles.

[0021] S3: Define the chopping region and eliminate metastability: Invert P_low and perform a logical AND operation with the original PWM square wave to generate a preliminary chopping region signal. After passing through the timing registers of two-stage D flip-flops, a stable original chopping region signal OriginChopzone is output.

[0022] S4: Front-end boundary alignment: The OriginChopzone is sampled synchronously under the chopper clock signal. The sampled signal is ANDed with the OriginChopzone to obtain chopper region signal 1, so that the starting boundary of the chopper region is strictly aligned with the rising edge of the chopper clock signal.

[0023] S5: End boundary protection and pulse integrity guarantee: Real-time monitoring of the falling edge of the original PWM square wave. If the chopper clock signal is high when the falling edge arrives, the boundary protection mechanism is triggered to set the chopper region signal 2 high until the chopper clock signal is pulled low after the next falling edge.

[0024] S6: Synthesize the final chop signal: Perform a logical OR operation on chop region signal 1 and chop region signal 2 to generate the global chop region signal ChopZone; during the effective period of ChopZone, perform a logical AND operation on the chop clock signal and the original PWM square wave to generate a high-frequency modulation signal, and then perform a logical AND operation on the signal and P_low to output the final hybrid modulation chop signal ChopOut.

[0025] As a further technical solution of the present invention: In step S2, the chopper clock frequency fchop is calculated by the formula fchop=(SysClk / 8) / M, where M=frequency division configuration register+1, so as to realize the programmable adjustment of the chopper clock frequency.

[0026] As a further technical solution of the present invention: In step S6, during the entire signal synthesis process, the timing optimization mechanism of dual trigger synchronization and delay chain matching is used to suppress the glitches at the moment of gating signal switching and ensure the edge integrity of the output ChopOut.

[0027] As a further technical solution of the present invention: all modulation, synthesis and timing optimization operations of the method are completed by hardware logic without the participation of CPU software, and do not occupy the CPU resources of the DSP chip, thereby realizing the real-time generation of composite chopper signals.

[0028] One or more technical solutions provided in the embodiments of this application have at least the following technical effects or advantages:

[0029] 1. Pure hardware implementation, freeing up CPU resources: This invention integrates all modulation, synthesis, and timing optimization operations into the hardware circuitry inside the DSP chip, without the need for CPU software simulation or interrupt intervention, thus completely freeing up the DSP's CPU resources and improving the system's real-time response speed and multi-tasking capabilities.

[0030] 2. Feature-rich and supports programmable composite modulation: By configuring different register parameters, the width of the low-frequency long pulse, the frequency and duty cycle of the high-frequency chopper clock can be flexibly adjusted to realize the generation of composite waveforms of low-frequency long pulse envelope + high-frequency chopper pulse, which can meet the complex waveform requirements of different application scenarios such as precision driving, audio synthesis, and high-power control.

[0031] 3. Reduce switching losses and improve system efficiency: Low-frequency long pulses extend the conduction time of power devices, reduce the switching frequency per unit time, and significantly reduce the switching losses of power devices; at the same time, the switching characteristics of power devices can be optimized by adjusting the duty cycle of high-frequency chopper, further improving the energy transmission efficiency of the system.

[0032] 4. Improve waveform quality and reduce filtering costs: Through fine modulation by high-frequency chopping, the ideal waveform can be flexibly approximated, reducing the harmonic content of the output signal and improving waveform quality; the excellent waveform characteristics reduce the design requirements of subsequent filtering circuits, reduce the use of filtering components, and reduce system hardware costs.

[0033] 5. High integration and high reliability: The circuit is directly integrated into the DSP chip, eliminating the need for an external dedicated chopper chip, which greatly improves the system integration and simplifies the design of peripheral circuits; at the same time, the pure hardware logic design eliminates software operation failures, and combined with metastability elimination, glitch suppression, and pulse integrity protection mechanisms, it improves the system's operational reliability.

[0034] 6. Strong compatibility and easy implementation: The circuit of this invention can be seamlessly integrated with the PWM peripherals and system clock of existing DSP chips without modifying the core architecture of the DSP chip. Only a small number of hardware registers and logic circuits need to be added, resulting in low hardware implementation cost and easy integration into the design flow of existing DSP chips. Attached Figure Description

[0035] Figure 1 This is a schematic diagram of the overall module connection of the enhanced PWM chopper circuit of the present invention;

[0036] Figure 2 This is a diagram showing the structure and timing of the low-frequency pulse generation module of the present invention.

[0037] Figure 3 This is a schematic diagram of the structure and duty cycle adjustment of the chopper clock generation module of the present invention;

[0038] Figure 4 This is a schematic diagram showing the internal sub-module connections of the pulse modulation and synthesis unit of the present invention;

[0039] Figure 5 This is a flowchart illustrating the enhanced PWM chopping method of the present invention;

[0040] Figure 6 This is an overview diagram of the waveform of the composite modulation chopper signal of the present invention. Detailed Implementation

[0041] The technical solutions in the embodiments of the present invention will be clearly and completely described below. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0042] like Figures 1-6 As shown, this invention provides an integrated hybrid modulation chopper circuit. This circuit reconstructs a single PWM square wave into a composite signal consisting of a "low-frequency long pulse envelope" and a "high-frequency chopper pulse" through hardware logic. Its core architecture includes three cascaded modules: a low-frequency pulse generation module, a chopper clock generation module, and a pulse modulation and synthesis unit. The structure is shown in the figure below.

[0043] The circuit is connected to the external system clock (SysClk) and the original PWM square wave signal, ultimately outputting a modulated chopper signal with specific harmonic characteristics. The specific structure and working principle of each module are as follows:

[0044] (1) Low-FreqPulseGenerator

[0045] This module is used to generate a "long pulse" signal that controls the main cycle of energy transfer.

[0046] Configuration logic: The module has a built-in configurable register (configurable register) that supports programming settings for any multiple of the base time unit.

[0047] Reference Time Unit Definition: Eight system clock cycles (8Tsys) are defined as one standard time unit (Tunit). Therefore, the width Tlong of the low-frequency pulse can be expressed as: Tlong = N × 8 × Tsys, where N is configurable. Timing: When the circuit detects the rising edge (or enable signal) of the input raw PWM square wave, the internal counter starts. The counter accumulates in increments of the system clock. When the count reaches the preset configuration value N, the counter resets and stops. This process generates a low-frequency pulse signal with a high-level width of N × 8 × Tsys.

[0048] (2) Chopper clock generation module (chopper clock signal generator)

[0049] This module generates a high-frequency chopper clock for fine-tuning.

[0050] Clock Source and Frequency Division: The highest chopping frequency reference (fmax_chop) is 8 times the system clock (SysClk / 8). Programmable frequency division with any level can be achieved by configuring the frequency division configuration register. Frequency Configuration Range: The chopping clock frequency fchop can be calculated using the formula fchop = fmax_chop / M, where the division factor M = frequency division configuration register + 1, supporting multiple configuration levels. The corresponding actual division ratio is 8 * M times the system clock.

[0051] Duty cycle adjustment: The duty cycle of the chopper clock can be precisely adjusted in 7 levels via the duty cycle configuration register (registers [2:0]): 12.5%, 25%, 37.5%, 50%, 62.5%, 75%, and 87.5%. This design allows users to optimize the balance between switching losses and drive capability based on load characteristics.

[0052] (3) Pulse Modulation Unit

[0053] This module is the core processing unit of the circuit, responsible for logically synthesizing low-frequency long pulses with high-frequency chopper clocks to eliminate timing conflicts.

[0054] Edge detection and alignment: The circuit first performs edge detection on the input raw PWM square wave to capture its precise transition moments. Then, the phase of the high-frequency chopper clock is synchronized and aligned with the raw PWM signal to ensure that the chopper clock is in a known initial phase at the instant the long pulse window opens.

[0055] Logic synthesis and timing optimization: The input PWM square wave signal, low-frequency long pulse, and high-frequency chopper clock are logically processed to obtain a gate signal (ChopZone). This gate signal is then ANDed with the high-frequency chopper clock to obtain the high-frequency chopper portion signal. Finally, it is ORed with the low-frequency long pulse to obtain the final output signal. To prevent glitch at the moment of gate signal switching, a dedicated timing optimization circuit (dual flip-flop synchronization and delay chain matching) is designed inside this unit to ensure clean, glitch-free edges on the output waveform.

[0056] Output signal: The final output signal exhibits a fine pulse width characteristic determined by the high-frequency chopping clock within the effective chopping range; while in the low-frequency pulse range, it outputs a continuous pulse.

[0057] Specific work steps:

[0058] The specific workflow of this invention is described in detail below. When the hybrid modulation chopper circuit described in this invention is operating, it strictly follows the logical timing sequence of the following steps to achieve accurate synthesis of the low-frequency energy envelope and the high-frequency fine-chopped signal:

[0059] Step S101: Generation of low-frequency long pulse P_low (energy main cycle control)

[0060] When the circuit receives the original PWM square wave signal from the external input, the low-frequency pulse counter starts to accumulate count under the drive of the system clock (SysClk).

[0061] Threshold Configuration: The upper threshold of the counter is set by a configurable register, which offers various configuration options. The counting threshold N = configurable register + 1, corresponding to a low-frequency pulse width of N × 8 system clock cycles (Tsys).

[0062] Pulse generation logic: During the effective period of each original square wave pulse (typically within the rising edge-triggered enable window), the low-frequency pulse output signal P_low remains active (high level) as long as the current value of the counter is less than or equal to the preset threshold N. When the count value exceeds N, P_low is pulled low. When the next original square wave pulse arrives, the counter is reset and a new round of counting begins. This mechanism ensures that the output signal has a low-frequency energy main cycle with controllable width.

[0063] Step S102: Generation of high-frequency chopper clock signal (fine modulation wave)

[0064] When the chopping function is enabled, the chopping clock counter starts.

[0065] Frequency Configuration: The counter's cycle period (i.e., clock cycle) is controlled by the register divider configuration register, and the configuration value range is adjustable. This value defines the division factor M (M=Config_Value+1) relative to the system clock's 8-division reference, so the chopper clock frequency can be programmably adjusted between M*8 divisions of the system clock.

[0066] Duty cycle generation: The duty cycle is set by a register (value 0 to 7). Based on the frequency configuration described above, the hardware logic automatically calculates the upper limit of the high-level duration count.

[0067] Counthigh = (Preset Configuration Register + 1) × 8 × (Register + 1)

[0068] When the value of the chopper clock counter is less than or equal to Counthigh, the chopper clock signal outputs a high level; otherwise, it outputs a low level. This logic can generate seven high-frequency chopper waveforms with duty cycles precisely distributed between 12.5% ​​and 87.5%.

[0069] Step S103: Defining the chopping region and synchronizing its edges (anti-overlap processing)

[0070] To avoid timing conflicts or glitches between low-frequency pulses and high-frequency chopper signals, a safe "chopper region" needs to be defined.

[0071] Preliminary Region Generation: First, the low-frequency pulse signal P_low is inverted and then ANDed with the original square wave input signal to generate a preliminary "original chopping region" signal. This signal identifies the precise time window that allows high-frequency chopping to occur.

[0072] Timing register (stepping): To completely eliminate metastability risks and ensure timing convergence, the above-mentioned "original chop zone" signal is continuously registered for two steps in the system clock domain (two-stage D flip-flops), resulting in a stable "original chop zone" signal (OriginChopzone). This operation effectively avoids logic races during the switching of high and low frequency signals.

[0073] Step S104: Front Edge Alignment

[0074] Considering that the original chopping region signal may suddenly end while the chopping clock is still at a high level (falling edge arrives), directly truncating it will result in the first chopping pulse being incomplete.

[0075] Boundary alignment: The original chopper region signal is synchronously sampled under the chopper clock signal. The sampled signal is then ANDed with the original chopper region signal to obtain "chopper region signal 1 (chopper region signal 1)". Thus, the chopper clock signal period that overlaps with the low-frequency pulse signal P_low is not used, and the starting boundary of the chopper region is strictly aligned to the rising edge of the chopper clock.

[0076] Step S105: End boundary alignment and pulse integrity protection (anti-truncation processing)

[0077] Considering that the original square wave input signal may suddenly end while the chopping clock is still at a high level (falling edge arrives), directly truncating it will result in the last chopping pulse being incomplete.

[0078] Boundary detection: The circuit monitors the falling edge of the original square wave input signal in real time. If a falling edge is detected while the chopper clock signal is still high, it is determined that there is an incomplete chopper pulse.

[0079] Pulse Extension: Once the boundary protection mechanism is triggered, the circuit immediately sets "Chopzone2" to a high level, forcibly extending the chopping window. This signal remains high until the chopping clock signal experiences a subsequent falling edge, after which it is pulled low. This mechanism ensures the integrity of each high-frequency chopping pulse and guarantees the reliability of energy transfer.

[0080] Step S106: Final signal synthesis and output

[0081] Region merging: The timing-optimized "Chop Zone Signal 1" and the "Chop Zone Signal 2" used for boundary protection are logically ORed to merge them into the final "Global Chop Zone" signal.

[0082] Signal Modulation: During the effective period of the "global chopping region" signal, the high-frequency chopping clock signal is logically ANDed with the original square wave input signal to generate a modulated signal with high-frequency details.

[0083] Output synthesis: Finally, the modulated signal is ANDed with the "low-frequency pulse signal" that represents the main energy period to generate the final hybrid modulated chopper output signal.

[0084] Through the above hardware logic processing, this invention achieves seamless connection and precise coordination between low-frequency large pulses and high-frequency small pulses on the time axis, and outputs a high-quality chopper waveform with both high energy transmission efficiency and excellent electromagnetic compatibility characteristics without occupying any CPU resources.

[0085] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from the spirit or essential characteristics of the invention. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, it is intended that all variations falling within the meaning and scope of equivalents of the claims be included within the present invention.

[0086] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This way of describing the specification is only for clarity. Those skilled in the art should regard the specification as a whole, and the technical solutions in each embodiment have been appropriately combined to form other embodiments that are easy for those skilled in the art to understand.

Claims

1. An enhanced PWM chopper circuit, characterized in that, Integrated within the DSP chip, it is connected to the external system clock SysClk and the original PWM square wave signal. It includes a low-frequency pulse generation module, a chopper clock generation module, and a pulse modulation and synthesis unit. The three modules are cascaded in sequence. The pulse modulation and synthesis unit interacts bidirectionally with the low-frequency pulse generation module and the chopper clock generation module, and finally outputs a hybrid modulation chopper signal ChopOut. The low-frequency pulse generation module has a built-in configurable register. It uses 8 system clock cycles as a standard time unit Tunit and generates a low-frequency long pulse signal P_low with a width of N×8×Tsys based on the rising edge trigger count of the original PWM square wave, where N = configurable register + 1 and Tsys is the system clock cycle. The chopper clock generation module has a built-in frequency division configuration register and a duty cycle configuration register [2:0]. It uses SysClk / 8 as the highest chopper frequency reference to generate a high-frequency chopper clock signal with a frequency of fmax_chop / M and a duty cycle of 12.5%~87.5% that is adjustable in seven levels, where M = frequency division configuration register + 1. The pulse modulation and synthesis unit is the core processing module, including a timing register submodule, a boundary alignment submodule, a boundary protection submodule, and a signal synthesis submodule. It realizes chopping region definition, edge synchronization, pulse integrity protection, timing optimization, and final signal synthesis, and outputs a glitch-free, pulse-complete composite chopping signal.

2. The enhanced PWM chopper circuit according to claim 1, characterized in that, In the chopper clock generation module, the upper limit of the high-level duration count value of the high-frequency chopper clock is Counthigh = (frequency division configuration register + 1) × 8 × (register + 1). When the chopper clock counter value is ≤ Counthigh, the chopper clock signal outputs a high level; otherwise, it outputs a low level.

3. The enhanced PWM chopper circuit according to claim 1, characterized in that, The timing register submodule of the pulse modulation and synthesis unit uses a two-stage D flip-flop to continuously register the initial chopping region signal for two clock cycles in the system clock domain, eliminating metastability risks and logic races, and outputting a stable original chopping region signal.

4. The enhanced PWM chopper circuit according to claim 1, characterized in that, The boundary alignment submodule of the pulse modulation and synthesis unit includes a front-end boundary alignment submodule, which synchronously samples the original chopper region signal under the chopper clock signal, performs a logical AND operation between the sampled signal and the original chopper region signal to obtain chopper region signal 1, so that the starting boundary of the chopper region is strictly aligned to the rising edge of the chopper clock signal.

5. The enhanced PWM chopper circuit according to claim 1, characterized in that, The boundary protection submodule of the pulse modulation and synthesis unit monitors the falling edge of the original PWM square wave in real time. If the chopping clock signal is high when the falling edge is detected, it is determined that there is an incomplete chopping pulse. The chopping region signal 2 is immediately set high and extended to the next falling edge of the chopping clock signal to ensure the integrity of the chopping pulse.

6. The enhanced PWM chopper circuit according to claim 1, characterized in that, The pulse modulation and synthesis unit has a built-in timing optimization circuit and adopts a dual-flip-flop synchronization and delay chain matching design to prevent glitches from occurring during gating signal switching and ensure clean edges of the output waveform.

7. An enhanced PWM chopping method based on the circuit described in any one of claims 1-6, characterized in that, The composite modulation of the original PWM square wave is achieved through hardware logic without CPU software intervention, including the following steps: S1: Generate a low-frequency long pulse signal P_low: Responding to the rising edge of the original PWM square wave, the low-frequency pulse generation module starts counting with the system clock SysClk as the beat. The counting threshold is configured by the configurable register. When the count value is ≤ N, P_low remains high, N = configurable register + 1. If it exceeds, it is pulled low. When the next rising edge of the PWM arrives, the counter is reset, generating a low-frequency long pulse with a width of N×8×Tsys. S2: Generate high-frequency chopper clock signal: After the chopper function is enabled, the chopper clock generation module uses SysClk / 8 as the highest reference frequency, configures the division coefficient M through the division configuration register to generate an adjustable frequency chopper clock signal, and then configures the Counthigh value through the register to realize the generation of a high-frequency chopper clock with seven duty cycles. S3: Define the chopping region and eliminate metastability: Invert P_low and perform a logical AND operation with the original PWM square wave to generate a preliminary chopping region signal. After passing through the timing registers of two-stage D flip-flops, a stable original chopping region signal OriginChopzone is output. S4: Front-end boundary alignment: The OriginChopzone is sampled synchronously under the chopper clock signal. The sampled signal is ANDed with the OriginChopzone to obtain chopper region signal 1, so that the starting boundary of the chopper region is strictly aligned with the rising edge of the chopper clock signal. S5: End boundary protection and pulse integrity guarantee: Real-time monitoring of the falling edge of the original PWM square wave. If the chopper clock signal is high when the falling edge arrives, the boundary protection mechanism is triggered to set the chopper region signal 2 high until the chopper clock signal is pulled low after the next falling edge. S6: Synthesize the final chop signal: Perform a logical OR operation on chop region signal 1 and chop region signal 2 to generate the global chop region signal ChopZone; during the effective period of ChopZone, perform a logical AND operation on the chop clock signal and the original PWM square wave to generate a high-frequency modulation signal, and then perform a logical AND operation on the signal and P_low to output the final hybrid modulation chop signal ChopOut.

8. The enhanced PWM chopping method according to claim 7, characterized in that, In step S2, the chopper clock frequency fchop is calculated using the formula fchop=(SysClk / 8) / M, where M=frequency divider configuration register+1, thus enabling programmable adjustment of the chopper clock frequency.

9. The enhanced PWM chopping method according to claim 7, characterized in that, In step S6, during the entire signal synthesis process, the timing optimization mechanism of dual trigger synchronization and delay chain matching is used to suppress glitches at the moment of gating signal switching and ensure the edge integrity of the output ChopOut.

10. The enhanced PWM chopping method according to any one of claims 7-9, characterized in that, All modulation, synthesis, and timing optimization operations in the method are performed by hardware logic without CPU software involvement, thus not occupying the CPU resources of the DSP chip and realizing the real-time generation of composite chopper signals.

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