A virtual slave station and incremental monitoring method and system based on an FPGA-based EtherCAT bus protocol

Abstract

The application discloses a kind of virtual slave station and incremental monitoring method and system of EtherCAT bus protocol based on FPGA, it is related to industrial control technical field, the prestorage mechanism of FPGA hardware level parallel processing and shadow configuration register group, the communication continuity and system robustness of EtherCAT bus under the scene of slave station abnormal offline are significantly improved, offline detection and virtual replacement response delay can be compressed to microsecond level, WKC deviation accumulation and main station alarm shutdown caused by link interruption in traditional scheme are completely avoided;At the same time, based on the real-time comparison and deviation number statistics of WKC incremental expected value, communication abnormal node can be accurately positioned and fault early warning is realized, and artificial diagnosis and maintenance cost are greatly reduced.

Description

Technical Field

[0001] This invention relates to the field of industrial control technology, and in particular to a virtual slave station and incremental monitoring method and system based on the EtherCAT bus protocol of FPGA. Background Technology

[0002] EtherCAT (Ethernet Control Automation Technology) has become one of the core protocols of industrial real-time Ethernet due to its real-time processing mechanism, high bandwidth utilization, and nanosecond-level clock synchronization accuracy. In a typical EtherCAT network, the message frames sent by the master station sequentially traverse each slave station. Each slave station completes the mapping and interaction of process data objects (PDOs) with the synchronization manager (Sm) through the fieldbus memory management unit (FMMU). An embedded work counter (WKC) is used within the frame. Each time a correctly processed message passes through a slave station, the WKC increments according to a predetermined rule. The master station verifies the integrity of the communication link by comparing the WKC increment with the expected value. With the increasing demands for communication continuity in industrial settings, fault-tolerant handling of abnormal operating conditions such as slave station offline and link intermittent interruptions has gradually become a research hotspot.

[0003] Existing solutions largely rely on heartbeat detection and network reconfiguration at the master station's application layer: the master station periodically reads the slave station's status register, and upon detecting offline status, software initiates reconfiguration and state machine reset. This method typically has millisecond-level detection latency, which cannot meet the microsecond-level response requirements of motion control. Furthermore, data frames lost during offline periods can cause accumulated WKC (Warranty Control Center) deviations, triggering master station error alarms or even system shutdowns. In recent years, Field-Programmable Gate Arrays (FPGAs) have been widely used for hardware offloading of the EtherCAT protocol stack due to their parallel processing architecture and extremely low data path latency. However, existing FPGA implementations mainly focus on protocol acceleration under normal operating conditions, lacking systematic research on virtual replacement and seamless recovery mechanisms when slave stations are offline.

[0004] For example, CN107707447B discloses a slave system and control method based on EtherCAT. The core architecture includes a slave data exchange module, an ARM core MCU slave controller, an encoder acquisition module, a digital / analog I / O module, and a bus protocol conversion module. This system achieves communication between the data exchange module and the MCU via a high-speed SPI bus, utilizes an ASIC chip for link-layer data parsing, and ports the EtherCAT protocol to the μcosII real-time kernel. It also implements multi-protocol input / output conversion through priority task scheduling. However, this technical solution has the following significant shortcomings: First, the slave controller uses an ARM core MCU, which requires software protocol stack parsing when processing EtherCAT frames. This results in multiple memory copies and task scheduling delays in the data path, making it difficult to fully utilize the hardware parallelism of the FPGA. Second, when the slave is offline, the system can only rely on the master station application layer software to detect and trigger network reconstruction. There is a lack of a hardware-level virtual slave replacement mechanism between the ASIC and the MCU. During offline periods, messages sent by the master station cannot receive effective simulated responses, leading to WKC incremental interruptions and forced termination of bus communication. Third, this solution does not involve real-time monitoring and deviation statistics of WKC increments. The master station cannot accurately locate abnormal slaves on the communication link, and fault diagnosis relies on application layer logs, resulting in delayed responses. Therefore, the solution proposed in CN107707447B has significant technical deficiencies in offline fault tolerance and real-time monitoring.

[0005] CN116736766A discloses a high-dynamic positioning compact EtherCAT slave-type drive and control system. Based on CN107707447B, it adds a description of the EtherCAT data frame traversal process and WKC update mechanism: the master station sends a downlink data frame, and after the slave station analyzes and addresses the message, it extracts or inserts data within the frame according to commands and updates the WKC to indicate successful access. This system also uses an ARM core MCU as the slave controller and stores basic ESC configuration information in an external EEPROM. Although the role of WKC as a successful access indicator is clarified, no technical means are provided to maintain the continuity of WKC increments when a slave station is offline. Specifically, when a slave station goes offline due to a link failure or power outage, subsequent slave stations cannot receive data frames forwarded from the previous station, the entire bus topology is disrupted, and the master station will detect a WKC increment that is significantly different from the expected value, thus triggering error handling. It also fails to provide any insights into using FPGA to implement a virtual slave engine to replace offline slave responses, nor does it address hardware-level monitoring and rapid recovery mechanisms such as shadow configuration register groups, PDO mapping template pre-storage, and WKC incremental expectation value comparison. Therefore, the system disclosed in CN116736766A still suffers from significant problems such as high communication interruption risk and long recovery time when facing abnormal operating conditions such as slave momentary outages in actual industrial environments. Summary of the Invention

[0006] The purpose of this section is to outline some aspects of the embodiments of the present invention and to briefly introduce some preferred embodiments. Some simplifications or omissions may be made in this section, as well as in the abstract and title of the present application, to avoid obscuring the purpose of this section, the abstract and title of the invention. Such simplifications or omissions shall not be used to limit the scope of the present invention.

[0007] In view of the aforementioned existing problems, the present invention is proposed.

[0008] Therefore, the purpose of this invention is to solve the technical problems of bus interruption, WKC deviation accumulation, and large recovery delay caused by slave station offline in the prior art.

[0009] To address the aforementioned technical problems, this invention provides the following technical solution: a virtual slave station and incremental monitoring method based on the EtherCAT bus protocol using FPGA, comprising: pre-storing a shadow configuration register group for each port corresponding to the slave station, recording the slave station's PDO mapping template and WKC incremental expected value; continuously monitoring the link signal loss flag of each port by the port state machine; when the flag indicates that the corresponding slave station is online normally: receiving a data frame, dividing the data frame into multiple segmented data blocks for parallel verification, and simultaneously buffering the data frame; if the verification passes, extracting the actual WKC increment from the sub-message of each slave station in the buffer, comparing it with the pre-stored WKC incremental expected value, and recording the number of deviations; if the verification fails, discarding the data frame and not performing WKC comparison; when the flag indicates that the corresponding slave station is offline: immediately switching to the shadow configuration register group of the port to construct a virtual loopback channel, with the virtual slave station engine generating a response data frame to reply to the master station; after the slave station comes back online, directly restoring the slave station's data exchange according to the PDO mapping template in the shadow configuration register group.

[0010] As a preferred embodiment of the present invention, the shadow configuration register group further stores: a distributed clock timestamp before offline, a deep cache queue, an alternative response data template required by the virtual slave engine, and a configuration command record area; wherein: the deep cache queue is used to store all process data write operation sub-messages sent by the master station to the corresponding port during offline, stored in first-in-first-out order; the alternative response data template is derived from the PDO mapping template: for each input data entry in the PDO mapping template, the default response is all zeros; for the status bit field, the online status of the controlled slave is set to zero and the slave offline warning flag is set at the same time; the derivation rules are fixed in the FPGA logic and do not require runtime calculation; the configuration command record area is used to cache all configuration commands and corresponding parameters received during offline, stored in chronological order.

[0011] As a preferred embodiment of the present invention, the parallel calculation of intermediate check values ​​for each segmented data block includes: dividing the data frame into continuous segmented data blocks of fixed byte length, each segmented data block having an actual byte length, and sending them in parallel to an independent cyclic redundancy check calculation channel; each channel using the same preset polynomial and the same initial value to independently calculate the intermediate check value for the corresponding segmented data block; merging the intermediate check values ​​according to the original segment order: for the first segment, using the intermediate check value as the current merged value; for the i-th segment, obtaining the shift factor value pre-stored based on the cumulative byte length of the segmented data block, performing polynomial multiplication of the intermediate check value of the i-th segment and the shift factor value over a finite field to obtain the product value, then performing an XOR operation between the current merged value and the product value, and using the result as the new current merged value; merging all segments sequentially to obtain a global check value; and performing an XOR operation between the global check value and a preset XOR value to obtain the final frame check sequence field.

[0012] As a preferred embodiment of the present invention, the comparison with the pre-stored WKC incremental expected value includes: performing the comparison only in normal online mode, and skipping the WKC incremental comparison when the port is in a virtual slave active state; and performing the WKC incremental comparison only for sub-messages with unicast addressing mode, skipping the comparison for broadcast and multicast sub-messages and keeping the deviation count register unchanged; for the sub-messages corresponding to this port, and when the port is directly connected to a single physical slave in a point-to-point manner: first reading the first WKC value of the sub-message before it is sent to the physical slave through the port, and defining the first WKC value as the value within the sub-message. The working counter field is the value before it is processed by the physical slave station; the sub-message is sent to the directly connected physical slave station through the port; after the same sub-message is processed by the physical slave station and returns through the same port, the second WKC value in the sub-message is read again as the processed value; the difference between the second WKC value and the first WKC value is calculated as the actual WKC increment, and the actual WKC increment is compared with the expected WKC increment value pre-stored in the shadow configuration register group: if they are not equal, the deviation count register of the corresponding slave station is incremented by one; if they are equal, the next sub-message is processed.

[0013] As a preferred embodiment of the present invention, the construction of the virtual loopback channel includes: a port state machine continuously monitoring the link signal loss flag of each port; when the link signal loss flag changes from invalid to valid, the data transmission and reception path of the port is switched to the internal virtual loopback channel and the physical transceiver is shielded; the virtual slave engine is activated, and the engine generates an alternative response data frame to reply to the master station based on the PDO mapping template and the alternative response data template in the shadow configuration register group; the distributed clock timestamp at the start of offline is recorded and stored in the distributed clock timestamp field before offline in the shadow configuration register group.

[0014] In a preferred embodiment of the present invention, the virtual slave engine generates alternative response data frames according to the following rules: For read operation sub-messages, the corresponding data in the alternative response data template is returned, and the working counter field in the sub-message is incremented by one; for write operation sub-messages, a write success status is returned, the working counter field in the sub-message is incremented by one, and a complete copy of the write operation sub-message is stored in the deep cache queue in the shadow configuration register group; for read-write operation sub-messages, the behavior of both read and write operations is performed simultaneously: read data is returned, the working counter field in the sub-message is incremented by two, and a copy of the write operation portion of the sub-message is pushed into the deep cache queue; for configuration commands, a command acceptance status is returned, and the type, address, data content, and length of the configuration command are stored in the configuration command record area in the shadow configuration register group.

[0015] As a preferred embodiment of the present invention, the direct recovery of the slave station's data exchange based on the PDO mapping template in the shadow configuration register group includes: when the link signal loss flag is restored to invalid, reading the PDO mapping template in the shadow configuration register group, writing the PDO mapping template into the corresponding synchronization manager and fieldbus memory management unit registers of the slave station through configuration commands, and simultaneously notifying the master station software to update the local shadow table through an interrupt request; reading the current global distributed clock reference time maintained internally by the FPGA; calculating the difference with the distributed clock timestamp before offline stored in the shadow configuration register group; if the difference is less than a first threshold, compensating the difference with a single command; if the difference is greater than or equal to the first threshold and less than or equal to a second threshold, generating multiple clock adjustment commands to gradually compensate; if the difference is greater than the second threshold, triggering an interrupt and maintaining the virtual slave station mode, waiting for master station intervention.

[0016] In a preferred embodiment of the present invention: after clock compensation is completed, if there are cached configuration commands in the configuration command record area, the configuration commands are reissued to the actual slave station in the order of recording and the record area of ​​the configuration commands is cleared; if there are valid write operation sub-message copies in the deep cache queue, the write operation sub-message copies are resent to the actual slave station in the first-in-first-out order and the deep cache queue is cleared; exit the virtual slave station mode and loopback mode, reconnect the port to the data frame forwarding path, and clear the virtual slave station activation flag.

[0017] In a preferred embodiment of the present invention, if a verification failure occurs during the data frame verification process, the data frame is discarded and a link alarm is triggered, and no retransmission request is sent to the peer device; at the same time, for data frames that fail verification, no subsequent WKC incremental comparison and virtual loopback processing are performed.

[0018] On the other hand, the present invention also provides the following technical solution: a virtual slave and incremental monitoring system based on the EtherCAT bus protocol of FPGA, further comprising: a shadow configurator module, which independently pre-stores the shadow configuration register group corresponding to each slave for each EtherCAT port of the FPGA, wherein the register group records at least the PDO mapping template and WKC incremental expected value of the slave; a frame checker module, the input end of which is connected to the receiving data path of the FPGA, configured to divide the received data frame into multiple segmented data blocks, calculate the intermediate check value of each segmented data block in parallel, and merge them in the segmented order to obtain a global check value, compare the global check value with the frame check sequence at the end of the frame, and output a check pass signal or a check failure signal; and an offline switcher module, including a port state machine, the input end of which is connected to the physical layer link signal loss flag, and the output end of which is connected to the transmit / receive path. The system includes: a path switch; a port state machine continuously monitors the link signal loss flag of each port; when the corresponding slave station is detected to be offline, it controls the path switch to switch to the internal virtual loopback channel and activates the virtual slave station engine; an incremental monitor module, whose input is connected to the verification pass signal of the frame checker module and the online status signal of the offline switcher module, configured to extract the actual WKC increment in the sub-packet when the slave station is online and the virtual slave station is not activated, compare it with the expected WKC increment value provided by the shadow configurator module, and record and store the number of deviations; and an online recovery module, whose input is connected to the link recovery signal of the offline switcher module, and connected to the shadow configurator module, the virtual slave station engine, and the physical slave station interface, configured to directly restore the data exchange of the slave station according to the PDO mapping template in the shadow configuration register group after the slave station is re-online.

[0019] The beneficial effects of this invention are as follows: By utilizing FPGA hardware-level parallel processing and the pre-store mechanism of the shadow configuration register group, this invention significantly improves the communication continuity and system robustness of the EtherCAT bus in scenarios where slave stations are abnormally offline. It can compress the latency of offline detection and virtual replacement response to the microsecond level, completely avoiding the accumulation of WKC deviation and master station alarm shutdown caused by link interruption in traditional solutions. At the same time, based on the real-time comparison of WKC incremental expected value and the statistics of deviation counts, it can accurately locate communication abnormal nodes and realize fault early warning, greatly reducing the cost of manual diagnosis and maintenance. In addition, by utilizing the deep cache queue and clock deviation compensation of the PDO mapping template, the data exchange recovery time after the slave station comes back online is shortened to within a single communication cycle, without the need to re-execute the complete protocol initialization process, thereby ensuring seamless continuous operation of high real-time applications such as motion control. Attached Figure Description

[0020] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. Wherein: Figure 1 This is a flowchart illustrating a virtual slave station and incremental monitoring method based on the EtherCAT bus protocol using FPGA, as shown in this invention.

[0021] Figure 2 This is a schematic diagram of the port state machine operation as shown in the present invention.

[0022] Figure 3 This is a schematic flowchart of CRC verification as shown in this invention. Detailed Implementation

[0023] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments.

[0024] Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without inventive effort should fall within the scope of protection of this invention.

[0025] Many specific details are set forth in the following description in order to provide a full understanding of the invention. However, the invention may also be practiced in other ways different from those described herein, and those skilled in the art can make similar extensions without departing from the spirit of the invention. Therefore, the invention is not limited to the specific embodiments disclosed below.

[0026] According to an embodiment of the present invention, in combination Figures 1-3 The flowchart shown illustrates a virtual slave and incremental monitoring method based on the EtherCAT bus protocol using FPGA, comprising: S1: Pre-store the shadow configuration register group of the corresponding slave for each port, and record the slave's PDO mapping template and WKC incremental expected value.

[0027] The configuration process includes: during the FPGA power-on initialization phase or after the master station completes the identification of the EtherCAT bus topology, the master station writes initial parameters to the shadow configuration register group, which is independently configured for each physical port inside the FPGA, through the ESC (EtherCAT slave controller) interface. The shadow configuration register group is implemented using the FPGA's internal block random access memory or distributed RAM. Each port corresponds to an independent set of register address spaces, and the groups are isolated from each other, supporting parallel read and write operations.

[0028] Before normal communication begins, the master station obtains the PDO mapping information and the expected increment value of the working counter WKC for each slave station through explicit configuration frames, such as the SDO configuration in the CoE or FoE. This information is then written into the corresponding shadow configuration register group within the FPGA according to the port number. Once written, the contents of this register group remain unchanged even if a slave station subsequently goes offline, until the master station actively updates it or the system is reset.

[0029] Furthermore, each port's shadow configuration register group contains at least a PDO mapping template storage area and a WKC incremental expectation value register; the PDO mapping template storage area records the mapping relationships of process data objects currently used by the slave in the form of an entry table. Each entry includes: a direction flag indicating whether the PDO is an input (slave → master) or an output (master → slave); an index and sub-index, which are PDO indices and sub-indices conforming to the CANopen specification; a length field, which is the data length in bytes; and a start address field.

[0030] The size of the PDO mapping template storage area is determined by the maximum number of PDO entries preset inside the FPGA, such as 32 entries. If the limit is exceeded, an alarm is triggered through the error flag register.

[0031] The WKC incremental expectation register stores an unsigned integer value, representing the number of times the WorkingCounter (WKC) field in the sub-message should be incremented after the physical slave station corresponding to this port correctly processes a sub-message that conforms to the PDO mapping template.

[0032] Preferably, determining the expected WKC increment includes: the master station pre-calculating the expected WKC increment based on the sub-message type defined in the EtherCAT standard (IEC 61158) and the role of the slave station in logical or physical addressing. If the sub-message is a read operation (RD) and the slave successfully returns data, the WKC increment should be 1; if the sub-message is a write operation (WR) and the slave successfully writes data, the WKC increment should be 1; if the sub-message is a read / write operation (LRW) and the slave completes both read and write operations simultaneously, the WKC increment should be 2, corresponding to successful read and successful write respectively; if the sub-message is a broadcast / multicast operation involving the slave, the WKC increment is also related to the slave's position in the sub-message addressing list, for example, by specifying the slave's contribution of 1 or 2 through the configuration register bitmask.

[0033] After calculating the expected value according to the above rules, the master station writes it to this register via a configuration frame, and also writes an enable bit to inform the FPGA to enable the WKC incremental monitoring function. If the enable bit is 0, for example, if the slave station does not support WKC monitoring, the subsequent comparison steps are bypassed by hardware.

[0034] To facilitate subsequent virtual slave and recovery operations, the shadow configuration register group may further include a shadow switch flag, indicating whether the shadow configuration of the port is valid and the configuration version number, which is used by the master station to detect whether the configuration has been updated.

[0035] In some embodiments, the step of pre-storing the shadow configuration register group of the corresponding slave station for each port further includes the following steps: Step S1.1: The port configuration controller inside the FPGA receives the configuration data frame from the master station.

[0036] The configuration data frame is accessed using EtherCAT's custom commands or through an extended ESC register, such as by allocating a dedicated register region for shadow configuration within the ESC implemented on the FPGA, with an address range of 0x0F00 to 0x0FFF.

[0037] The configuration frame contains: target port number, PDO mapping template data block, and WKC incremental expected value.

[0038] Sub-step S1.2: The port configuration controller selects the corresponding block RAM write enable signal according to the target port number, writes the PDO mapping template item by item into the PDO template storage area of ​​the port, and writes the WKC incremental expected value into the corresponding 16-bit register.

[0039] Sub-step S1.3: After the write operation is completed, the port configuration controller sets the shadow configuration valid flag of the corresponding port.

[0040] If the FPGA detects that a subsequent data frame has passed through this port and requires WKC comparison, it checks the flag; if invalid, it skips the comparison step and generates a warning interrupt to report to the master station.

[0041] Sub-step S1.4: The FPGA reads back the end checksum in the register group and compares it with the locally recalculated checksum. If they do not match, the valid flag is kept at 0 and a configuration error interrupt is triggered. The end checksum is included when written by the master station.

[0042] As can be seen, by pre-storing PDO mapping templates and WKC incremental expected values ​​independently for each port, this invention can quickly switch to virtual slave mode without renegotiation of configuration after the slave goes offline. At the same time, it provides an accurate WKC incremental comparison benchmark and supports simultaneous configuration of multiple ports using the FPGA parallel block RAM structure without increasing the forwarding latency of data frames.

[0043] S2: The port state machine continuously monitors the link signal loss flag for each port.

[0044] Each physical port is equipped with an independent port state machine, running at the FPGA system clock, such as 125 MHz. The state machine continuously monitors for link signal loss flags from the physical layer transceiver PHY. .when =0 indicates that the link is normal, when =1 indicates that the link is lost.

[0045] The detection of this flag provides the basis for subsequent online / offline branching.

[0046] S3: When the flag indicates that the corresponding slave station is online normally: receive the data frame, divide the data frame into multiple segmented data blocks for parallel verification, and simultaneously buffer the data frame; if the verification passes, extract the actual WKC increment from the sub-message of each slave station from the buffer, compare it with the pre-stored expected value of WKC increment and record the number of deviations; if the verification fails, discard the data frame and do not perform WKC comparison.

[0047] S3.1: In this embodiment of the invention, during EtherCAT communication, the FPGA receives Ethernet frames from the physical layer, including the EtherCAT frame header, sub-message sequence, and frame check sequence (FCS).

[0048] To improve throughput and reduce latency, this embodiment employs a segmented parallel CRC calculation and polynomial field merging method instead of the traditional serial byte-by-byte CRC calculation. Specifically: S3.1.1: After detecting the Start-of-Frame (SFD) delimiter, the FPGA's internal receive pipeline begins continuously receiving data bytes. Simultaneously, a segmentation controller divides the complete data frame into multiple consecutive data segments based on a preset segment length threshold. This preset segment length threshold, such as 64 bytes, 128 bytes, or 256 bytes, can be dynamically configured by the master station.

[0049] Specifically, data frames with a length less than the single segment threshold are considered as one segment; data frames with a length greater than the segment length threshold are divided into segments of a fixed byte length (e.g., 128 bytes). The actual byte length of the last segment can be less than the fixed byte length, and this actual length is recorded along with the segmented data blocks.

[0050] The splitting point is based solely on byte boundaries, without parsing the internal structure of the EtherCAT protocol, in order to ensure universality and high-speed processing.

[0051] Each segmented data block is accompanied by the following metadata: segment number; data start pointer, pointing to the position in the FPGA's internal receive FIFO; actual byte length.

[0052] S3.1.2: The FPGA allocates an independent CRC calculation channel for each segmented data block, and each channel starts up and runs in parallel at the same time.

[0053] The number of channels is equal to the maximum number of segments that can be processed simultaneously. For example, if it is designed to have 8 channels, when the number of data frame segments exceeds the number of channels, pipelined batch processing is adopted, that is, the next batch is started immediately after the first 8 segments are calculated.

[0054] Each CRC calculation channel includes the following hardware resources: a 32-bit CRC shift register; a combinational logic XOR tree to implement polynomial division; and a byte length counter to record the number of bytes processed.

[0055] For example, the standard Ethernet CRC-32 polynomial is used. The corresponding hexadecimal representation is 0x04C11DB7. The initial value of the shift register for each channel is fixed at 0xFFFFFFFF. Each byte is inverted bit by bit before input, conforming to the Ethernet standard. The final result is inverted bit by bit and then XORed with 0xFFFFFFFF.

[0056] During the calculation process, each channel independently performs standard CRC-32 calculation on its corresponding segmented data block to obtain an intermediate check value, which is a 32-bit unsigned integer.

[0057] It should be noted that this intermediate check value is not XORed with the final value (i.e., it is not XORed with 0xFFFFFFFF), but is retained as the remainder of the original polynomial for subsequent merging.

[0058] S3.1.3: The calculation of the global CRC check value is essentially the concatenation of the CRC results of each segmented data block in the polynomial field.

[0059] For example, let the complete data frame be ,in For the first There are segments, each with a length of [number]. byte, This represents the total number of segments after the complete data frame has been divided. (Given) For segmentation The intermediate value, with an initial value of 0xFFFFFFFF, is then used to merge the values.

[0060] in, This indicates the XOR operation of the polynomial coefficients (i.e., bitwise XOR). This means dividing by the generator polynomial. The remainder after; This indicates that the second segment will be... The CRC result is shifted left over the polynomial field. Each bit, to be aligned and Positional relationship within the original data frame; Extended to multiple segments: ; For i=2 to n,

[0061] The final global checksum value is temp.

[0062] Furthermore, a merging engine within the FPGA processes the segments sequentially according to their original order: because It may frequently take a fixed value, such as 128 bytes, which can be pre-calculated. value The result is stored in a lookup table inside the FPGA. For non-fixed lengths, it can be calculated in real time using combinational logic or a small-scale multiplier.

[0063] For the first segment (i=0): the intermediate value of the global cyclic redundancy check obtained after merging. = That is, the intermediate check value of the first segment.

[0064] For subsequent segments (i≥1): first read the values ​​from the lookup table. Then calculate the polynomial multiplication:

[0065] This multiplication can be implemented using a 32-bit polynomial multiplier, outputting a 64-bit intermediate result, followed by taking the remainder using a polynomial division module. Alternatively, it can be implemented using combinational logic.

[0066] The polynomial multiplier uses combinational logic to implement 32-bit polynomial multiplication on GF(2), with a modulo polynomial of 0x04C11DB7.

[0067] Calculate Then, for the temporary accumulator Perform XOR processing:

[0068] After the merge is complete, the global checksum is obtained. (Final XOR not performed).

[0069] Furthermore, FPGAs, upon obtaining Then: First, reverse the bits, then XOR with the preset value 0xFFFFFFFF to obtain the final 32-bit FCS field, which is directly compared with the FCS carried at the end of the data frame.

[0070] It should be noted that by using the polynomial field merging algorithm, the correct reconstruction of the segmented parallel CRC results is achieved, so that the overall verification delay only includes the calculation time of the slowest channel and a small number of clock cycles of segment merging (usually about the number of merges × a few clock cycles), which is much less than the time for serial processing of long frames.

[0071] S3.1.4: When the data frame ends, i.e., when the end-of-frame delimiter (EFD) is detected, the receive pipeline extracts the last 4 bytes of the frame tail as the received FCS. Simultaneously, the merging engine has just completed... The transformation to the final FCS.

[0072] The comparator performs a bit-by-bit equality check: if they are completely identical, it outputs a pass signal and the control logic passes the data frame to the next step; if they are different, it outputs a fail signal and triggers the discard and alarm process.

[0073] It is important to note that the comparison process is completed within one clock cycle, without introducing any additional delay.

[0074] S3.1.5: When the output verification fails, the FPGA performs the following operations: The entire current data frame in the receive FIFO is marked as invalid, the write pointer is rolled back to the beginning of the frame, and the memory space occupied by that frame is overwritten. At the same time, the receive controller's state machine returns to the state of waiting for the start of the next frame, and no data is sent to the EtherCAT processing pipeline.

[0075] The CRC error count field in the FPGA's internal status / error register group is incremented by 1. If this count reaches the master station's preset threshold, such as 10 times / second, a link alarm interrupt is triggered, and the master station is notified via the ESC interrupt status register. Simultaneously, the FPGA sets a link alarm flag, which can be read by the master station via the ESC register. The alarm information includes: the error port number, frame length, and timestamp (distributed clock time).

[0076] Following the IEC 61158 standard, EtherCAT does not employ a retransmission mechanism at the link layer, but instead relies on upper-layer protocols, such as CANopen application layer timeouts and retries.

[0077] Therefore, the above operation only discards erroneous frames, does not send any retransmission requests to the peer device, and does not suspend the bus.

[0078] It should be noted that the operation of this invention reduces the CRC check latency of long frames to 1 / N (N is the number of channels) of the original serial method through segmented parallel computing and rapid merging of polynomial fields, while maintaining full compatibility with standard Ethernet CRC-32. Furthermore, the pre-stored coefficient table in the merging algorithm avoids real-time polynomial division, saving FPGA logic resources.

[0079] Furthermore, the prerequisites for execution are that the link signal loss flag of the physical port corresponding to the sub-message is invalid, i.e., the slave is online; the virtual slave activation flag of the port is invalid, i.e., it is not in virtual loopback mode. If the virtual slave is active, this step is skipped directly, and WKC monitoring is not performed; the shadow configuration valid flag of the port is valid, and the enable bit of the WKC incremental expectation value register is 1; otherwise, the comparison is skipped.

[0080] In normal online mode, a WKC monitoring unit is inserted on the transmit / receive path of each port. This unit contains: two registers: In this embodiment of the invention, the field is 32 bits, while the actual EtherCAT WKC field is 16 bits. However, using 32 bits facilitates alignment and... A temporary sub-message buffer with a depth equal to the maximum length of one sub-message, for example, 256 bytes; a finite state machine (FSM) controls the timing of read-send-readback.

[0081] S3.2: When the sub-message arrives at the port input side, before it is sent to the physical slave station, the WKC monitoring unit parses the sub-message header offset, specifically bytes 12-13 of the EtherCAT sub-message header, relative to the start of the sub-message. The EtherCAT sub-message structure is as follows: bytes 0-1: command; bytes 2-3: index; bytes 4-7: address area; bytes 8-9: length (bits 3-14); the actual WKC field is located in bytes 10-11 (16 bits) of the sub-message.

[0082] The monitoring unit reads the 16-bit value, extends it to 32 bits, and then stores it. The register is used; simultaneously, a complete copy of the sub-message is stored in a temporary buffer. It's important to note that this is not a deep copy, but rather a pointer reference plus a length record; the actual data is retained in the receive FIFO to avoid memory copy overhead.

[0083] The first WKC value is the WKC field value of the sub-message before it enters the port and is processed by any physical slave station.

[0084] S3.3: The control logic passes the sub-message from the temporary buffer or directly through to the physical layer transceiver (PHY) and waits for the slave station to process it.

[0085] For slave stations supporting EtherCAT pass-through forwarding, the processing time is extremely short, such as a few bit intervals. The FPGA internally maintains a timeout counter, for example, 512 bit clock cycles. If no return sub-message is received within the timeout period, the slave station is considered faulty and an alarm is triggered. This counter value can be configured by the master station.

[0086] S3.4: When a sub-message returns from the physical slave station to the receiving path of the re-entry port, the monitoring unit locates the WKC field within the same sub-message again, reads the value, and stores it. register.

[0087] The second WKC value is the WKC field value returned by the same sub-message from the physical slave station.

[0088] S3.5: Actual WKC increment is: The subtraction is performed using unsigned 16-bit operations, ignoring overflow. WKC is a modulo-65536 counter, and the increment is obtained by taking the modulo of the difference. Since the slave station usually increments by 1 or 2 when it responds correctly, it will not cross the modulo value, so the subtraction can be performed directly.

[0089] It should be noted that if the sub-message is broadcast and multiple slave stations simultaneously increase WKC, the difference is the sum of the contributions from multiple slave stations. This embodiment only concerns the contribution of the physical slave station corresponding to this port to the sub-message; however, the individual increment of this slave station cannot be directly separated from the difference. To solve this problem, this embodiment uses exclusive addressing or a method of joint derivation through command type and shadow configuration, rather than simply relying on the global difference.

[0090] Furthermore, after completing the calculation of the actual WKC increment, the comparator performs the following: if the two are not equal, the FPGA increments the deviation count register corresponding to that port by one; if the two are equal, the deviation count register remains unchanged.

[0091] The deviation count register is a 32-bit register maintained independently by the FPGA for each port. It is used to accumulate and record the number of WKC increment mismatches that occur at that port. The master station can read the value of this register through the ESC register interface and can choose to clear it after reading.

[0092] It is important to note that if the sub-message type is LRW and the WKC increment upon success in the EtherCAT standard should be 2, then the expected value should be preset to 2. If the slave station only succeeds partially, for example, a successful read but a failed write, the actual increment may be 1, in which case a deviation record will be triggered.

[0093] Furthermore, when the sub-message is broadcast or multicast, the WKC increment is contributed by multiple slave stations, making it impractical to directly extract the contribution of the local port from the difference. This embodiment employs one of the following three strategies: Strategy A: The master station is required to configure the monitoring sub-messages for each port to only address the physical slave station corresponding to that port, such as using a dedicated segment with physical or logical addressing. In this case, the actual WKC increment is equal to the contribution of that slave station, which is quite effective. This is the default recommended mode.

[0094] Strategy B: Add a WKC contribution mask to the shadow configuration register group, indicating how much increment (0, 1, or 2) the slave should contribute to this sub-message type. During comparison, it is considered correct only if the lower bits of the actual increment match the mask. Specifically: if mask = 1, the least significant bit of the actual increment is expected to be 1; if mask = 2, bit 2 is expected to be 1, and so on. This method allows sharing sub-messages but with different slaves contributing different bits.

[0095] Strategy C: The FPGA hardware automatically filters out non-multicast / broadcast sub-messages for WKC monitoring, and skips the comparison for multicast messages and freezes the deviation counter.

[0096] This embodiment uses strategy A by default because it is simple and suitable for most industrial application scenarios, in which the master station can control the sub-message addressing mode.

[0097] In this embodiment, to prevent multiple slave stations from sharing sub-messages and causing WKC increments to fail to be stripped, the FPGA hardware automatically filters the addressing type flag in the sub-message header. For broadcast or multicast commands, the WKC monitoring unit does not perform calculations, and the deviation counter remains unchanged. The system selects whether to allow partial mask comparison of multicast messages through configuration register 0x0F10; the default value of 0 indicates that only unicast is monitored.

[0098] S4: When the flag indicates that the corresponding slave station is offline: immediately switch to the shadow configuration register group of the port to build a virtual loopback channel, and the virtual slave engine generates a response data frame to reply to the master station.

[0099] In this embodiment of the invention, step S4 is triggered immediately after the port state machine detects the loss of the link signal, and is independent of the data frame receiving pipeline. It is used to maintain virtual EtherCAT communication between the master station and the offline slave station.

[0100] S4.1: Each physical port is equipped with an independent Port FSM, running on the FPGA system clock (e.g., 125 MHz). The state machine continuously monitors the following signals: Link signal loss flag : SGMII / MII interface status from the physical layer transceiver (PHY). When the PHY detects no valid carrier, no synchronization clock, or a received signal amplitude below 50mV, =1; otherwise =0.

[0101] Optional, watchdog timeout flag: If no valid data frame is received for this port for M consecutive EtherCAT frame cycles, even if... A value of 0 is also considered a communication anomaly. This embodiment defaults to using physical layer signals as the primary signal. M is configurable, with a default value of 5 and a cycle time of 1ms.

[0102] Furthermore, the normal online state, i.e. =0 and the virtual slave activation flag is 0; offline detection status, i.e. When the state machine changes from 0 to 1, it immediately enters the offline activation process and jumps to S4.2.

[0103] S4.2: The data path of each port inside the FPGA includes a transmit path switch and a receive path switch; the transmit path switch selects whether the data frame is sent to the physical PHY or the internal virtual loopback queue; the receive path switch selects whether the data frame originates from the physical PHY or the internal virtual loopback queue.

[0104] Furthermore, when triggered offline, the transmit path switch switches from the PHY to the virtual loopback, and the receive path switch also switches to the virtual loopback. By writing to register 0x0010 via the MDIO interface, a low-power command is sent to the PHY to reduce power consumption and avoid electrical conflicts.

[0105] Path switching is completed within 3 system clock cycles. The system clock frequency is typically 125 MHz, with one clock cycle being 8 nanoseconds. During switching, any pending data frames stored in the port FIFO are cleared (by resetting the write pointer) to prevent interference from old data. It should be noted that if a frame is being received during switching, the system waits for the current frame to end or is forcibly truncated and an error flag is set.

[0106] S4.3: After the path switch is completed, the port state machine sets the virtual slave activation flag to 1 and starts the virtual slave engine. The VSSE reads the following pre-stored information from the port's shadow configuration register group: PDO mapping template, alternative response data template, and pre-offline distributed clock timestamp.

[0107] VSSE enters running state and begins processing all EtherCAT sub-packets sent to this port, no longer forwarding them to the physical PHY.

[0108] S4.4: The FPGA internally maintains a globally distributed clock reference time. This clock reference time is 64-bit, measured in nanoseconds, and is periodically calibrated by the master station via a DC synchronization mechanism. When the port state machine enters offline mode, it immediately reads this global DC reference time and stores it in the shadow configuration register set.

[0109] S4.5: VSSE generates alternative responses according to the following standardized rules: (1) Read operation sub-message: Based on the input data entries defined in the PDO mapping template, each entry returns a byte of all zeros. For example, if the template indicates that the slave should provide 8 bytes of input data, then VSSE generates 8 0x00s; for the status bit fields: the slave online status bit (bit0) is set to 0, while the slave offline warning flag bit (bit1) is set to 1; the remaining reserved bits remain 0.

[0110] According to the EtherCAT standard, a successful read operation response from a single slave should increment the WKC by 1. VSSE increments the WKC field in the sub-message header by 1.

[0111] The modified sub-message is immediately returned to the main station via the loopback channel.

[0112] (2) Write operation sub-message: Instead of performing an actual write operation, the system directly returns a write success status. In this case, the WKC field in the sub-message is incremented by 1 according to the standard, and the error code register is set to 0.

[0113] WKC increases by 1 when a single slave write is successful.

[0114] Complete copies of write operation sub-messages are pushed into the depth buffer queue in the shadow configuration register group in a first-in-first-out (FIFO) order. The depth buffer queue is a circular FIFO with a default depth of 16. If the number of write operation sub-messages exceeds the queue depth during offline operation, new messages are discarded and the overflow flag is set. During recovery, only messages already in the queue are replayed.

[0115] Send the modified response sub-message.

[0116] (3) Read / write operation sub-messages: Returns all zeros, with the length specified by the sub-message length field.

[0117] Write data copies are pushed into the deep cache queue through write operations.

[0118] According to the EtherCAT standard, WKC should be incremented by 2 upon successful LRW command, with 1 contributing to reads and 1 to writes. VSSE increments WKC by 2 (modulo 65536).

[0119] The read data area is filled with all zeros, WKC is incremented by 2 and then returned.

[0120] (4) Configuration command sub-message: VSSE does not actually perform the configuration, but returns a command acceptance status, where WKC is incremented by 1, indicating success. Simultaneously, it stores the type, address, data content, and length of the configuration command in chronological order into the configuration command record area of ​​the shadow configuration register group. This configuration command record area uses a circular queue with a default depth of 8 commands.

[0121] Once the slave server comes back online, these cached commands will be reissued to the real slave server.

[0122] As can be seen, the classification response mechanism is fully compatible with the EtherCAT protocol stack. The master station will not report errors or time out during offline periods, and the deep cache queue and configuration command record ensure that all write operations and configurations are not lost during offline periods, providing a data foundation for transparent recovery.

[0123] S4.6: Sending direction, i.e., master station → virtual slave station: The data frames sent by the master station arrive at the port input FIFO.

[0124] Because the transmit path switch has been switched to loopback, data frames are not sent to the PHY, but are instead sent to the VSSE input buffer.

[0125] VSSE generates responses according to S4.5 rules.

[0126] Receiving direction, i.e., virtual slave station → master station: The response sub-message generated by VSSE is placed into the port output FIFO.

[0127] The receive path switch reads the response from the loopback queue and sends it back to the master station as slave return data.

[0128] It should be noted that the master station cannot detect when the slave station is offline because each sub-message receives a timely and protocol-compliant response. The only difference is that the online status bit in the slave station's status word is cleared and the offline warning flag is set, allowing the master station to determine the offline event.

[0129] S5: After the slave station comes back online, the data exchange of the slave station is directly restored according to the PDO mapping template in the shadow configuration register group.

[0130] When the port state machine detects a link signal loss, the flag is reset to invalid. After the jump from 1 to 0 and the link stabilizes, execute the following recovery procedure. During recovery, the virtual slave engine continues to run until all sub-steps are successfully completed.

[0131] S5.1: Port State Machine Monitoring After the falling edge, the link stabilization timer is started. During the timer period, if... If the value remains 0 and there is no jitter, indicating that PHY auto-negotiation is complete and the clock is locked, then the slave station has been physically reconnected. If the timer expires before... If the value jumps back to 1, then abandon the current recovery and return to S4.1.

[0132] The duration of the link stabilization timer is configurable, with a default value of 10ms.

[0133] S5.2: The recovery controller first reads the PDO mapping template storage area in the port shadow configuration register group, and then rewrites it to the physical slave through a privileged path, such as a separate configuration state machine + ESC register direct write channel.

[0134] The recovery controller is an independent state machine within the FPGA.

[0135] S5.2.1: For each output PDO (master → slave), construct an EtherCAT configuration frame and write the start address, length, control word, and other registers of the corresponding synchronization manager SM2 of the slave in sequence.

[0136] S5.2.2: For each input PDO (slave → master), configure the SM3 and FMMU registers to map the process data to the ESC internal RAM.

[0137] S5.2.3: After writing to each register, immediately perform a readback check. If the readback value matches the written value, continue; if they do not match, retry a maximum of 3 times. If a retry fails, trigger a PDO configuration failure critical interrupt, maintain virtual slave mode, and report to the master station.

[0138] S5.2.4: At the same time, the recovery controller sends an interrupt request to the upper-level master station to notify the master station software to update the local shadow table, so that the master station software does not need to renegotiate.

[0139] S5.3: During slave station offline periods, its local clock stops counting or drifts, while the master station's DC reference clock continues to run, resulting in a clock difference ΔT. The recovery controller performs the following compensation: S5.3.1: Read the current global DC reference time, retrieve the previous timestamp from the shadow configuration register group, and calculate the difference between the two as ΔT.

[0140] S5.3.2: If ΔT < 1ms, the DC correction unit inside the FPGA sets the slave system time offset register to ΔT through a one-time ARMW command to achieve time jump.

[0141] S5.3.3: If ΔT ≥ 1ms, the FPGA first checks the pre-configured maximum automatic compensation threshold register, for example, the default value is 10ms. If ΔT ≤ the maximum automatic compensation threshold, a step-by-step compensation strategy is adopted: adjust ±100ns per DC cycle until the cumulative compensation reaches ΔT. This process takes ΔT / 100ns × 1ms, which is approximately 100 seconds when ΔT = 10ms, within an acceptable range.

[0142] If ΔT > the maximum automatic compensation threshold, automatic compensation is abandoned, and a clock deviation too large interrupt is directly reported to the master station. The system continues in virtual slave mode, waiting for the master station to perform a one-time calibration or a complete reconfiguration via an explicit DC resynchronization command. The first threshold defaults to 1ms, and the second threshold defaults to 10ms, both configurable via registers.

[0143] This mechanism avoids unreasonable long-term compensation under extreme biases.

[0144] S5.4: After clock alignment is complete or in parallel with it, but to ensure that the slave can accept commands, it is recommended to execute after alignment, and restore the controller to check the configuration command record area in the shadow configuration register group.

[0145] S5.4.1: Read each cached command sequentially from the head of the queue, including its type, address, data content, and length.

[0146] S5.4.2: Construct the corresponding EtherCAT configuration frame through CoE or FoE, send it to the actual slave station through the physical path, and wait for a response.

[0147] If the WKC increment in the response matches expectations (usually 1), proceed to the next instruction; if the response fails, i.e., a timeout or WKC remains unchanged, record the error in the status register, but continue processing the remaining commands.

[0148] S5.4.3: After all commands have been processed, clear the configuration command record area, i.e., reset the write pointer and set the queue empty flag to 1.

[0149] It should be noted that configuration command replay must be performed before write operation replay, because subsequent write operations depend on these configurations.

[0150] S5.5: Restore the controller's processing of the deep cache queue. The deep cache queue is a FIFO structure, replacing the original deep cache queue.

[0151] S5.5.1: Each entry in the queue contains: sub-message type, complete sub-message copy, and timestamp. The default queue depth is 16; when the queue depth is exceeded, the oldest entry is discarded and the overflow flag is set to 1.

[0152] A complete sub-message copy includes the header, data, and original WKC.

[0153] S5.5.2: Starting from the head of the queue, retrieve a copy of each write operation sub-message in sequence and send it to the actual slave station via the physical path.

[0154] S5.5.3: After sending, wait for the return of the sub-message and check whether the WKC increment meets the expectation, that is, the expected increment of the write operation is 1, and the expected increment of the write part in LRW is 1.

[0155] If successful, proceed to the next entry; if it fails, record the error and continue processing the remaining entries. Specifically, if the timeout for waiting for the returned sub-message is the same as in S3.3, a timeout or WKC increment not meeting expectations is considered a failure.

[0156] S5.5.4: After all write operations are replayed, clear the deep cache queue, including resetting the write pointer and setting the queue empty flag to 1.

[0157] It should be noted that the deep queue ensures that all write operations are not lost and remain in the same order during offline periods, solving the data overwrite problem of the deep cache queue. Furthermore, it does not block the entire recovery process when replay fails, and the master station can decide to perform a full synchronization based on the error flag.

[0158] S5.6: After completing all the above recovery steps or encountering an unrecoverable error but still needing to attempt a switchover, the recovery controller performs an exit operation, including the following sub-steps: S5.6.1: Set the flag in the port state machine to 0.

[0159] S5.6.2: Switch the transmit path switch back from the virtual loopback to the physical PHY, and the receive path switch also switches back to the physical PHY. Simultaneously, cancel the PHY's squelch / power-down state via MDIO. For example, the power-down potential can be cleared by writing to register 0x0010.

[0160] S5.6.3: Optionally, clear temporary states such as offline timestamps and deviation counters.

[0161] S5.6.4: Report the recovery completion event to the master station via the ESC interrupt status register and clear the flag.

[0162] After this, subsequent data frames will be processed directly by the physical slave station, and the virtual slave station engine will stop completely.

[0163] Furthermore, embodiments of the present invention also provide exception handling strategies, such as: if reconfiguring the PDO mapping template fails and retries fail after 3 attempts, then keep flag 1, trigger a critical error interrupt, and wait for the master station to intervene; if the clock compensation command has no response, then skip the compensation, record the warning, and continue with subsequent steps; if write operation replay fails, for example, if a write operation WKC is incorrect, then record it and continue processing subsequent write operations, and finally report the lost write operation count; if the depth queue overflows, that is, the write operations exceed the queue depth during offline, then only the operations in the queue are replayed during recovery, and the master station is reported to need full synchronization, etc.

[0164] It should be noted that the fault-tolerant design ensures that the recovery process will not be completely blocked due to individual failures. The master station can decide whether to perform a more thorough reset or a full initialization based on the priority of the error flags.

[0165] This invention also includes a virtual slave and incremental monitoring system based on the EtherCAT bus protocol of FPGA, comprising: a shadow configurator module, which independently pre-stores a shadow configuration register group for each EtherCAT port of the FPGA corresponding to the slave, wherein the register group records at least the PDO mapping template and WKC incremental expected value of the slave; a frame checker module, whose input is connected to the receiving data path of the FPGA, configured to divide the received data frame into multiple segmented data blocks, calculate the intermediate check value of each segmented data block in parallel, and merge them in segment order to obtain a global check value, compare the global check value with the frame check sequence at the end of the frame, and output a check pass signal or a check failure signal; and an offline switcher module, including a port state machine, whose input is connected to a physical layer link signal loss flag, and whose output is connected to a transmit / receive path switch; The port state machine continuously monitors the link signal loss flag of each port. When the corresponding slave station is detected to be offline, it controls the path switch to switch to the internal virtual loopback channel and activates the virtual slave station engine. The incremental monitor module is connected to the verification pass signal of the frame checker module and the online status signal of the offline switcher module. It is configured to extract the actual WKC increment in the sub-packet when the slave station is online and the virtual slave station is not activated, and compare it with the expected WKC increment value provided by the shadow configurator module, record and store the number of deviations. The online recovery module is connected to the link recovery signal of the offline switcher module and is connected to the shadow configurator module, the virtual slave station engine and the physical slave station interface respectively. It is configured to directly restore the data exchange of the slave station according to the PDO mapping template in the shadow configuration register group after the slave station is brought back online.

[0166] The frame checker module and the offline switcher module work in parallel and independently: the offline switcher switches the data path in real time according to the link signal loss flag, while the frame checker performs parallel checks on the received data frames; only in offline mode, if the check fails and the frame has entered the virtual engine buffer, it is discarded; when an offline switch occurs, the frames being checked or cached will be cleared to ensure state consistency.

[0167] The system also includes one or more processors and memory.

[0168] The memory is used to store operable instructions that, when executed by the one or more processors, cause the one or more processors to perform operations, including the flow of a virtual slave and incremental monitoring method based on the EtherCAT bus protocol of an FPGA as described in the foregoing embodiments, particularly... Figure 1 The flowchart of the method is shown.

[0169] Other aspects disclosed in the embodiments of the present invention also propose a computer-readable medium for storing software including instructions executable by one or more computers, which, upon execution, cause the one or more computers to perform operations including the flow of a virtual slave and incremental monitoring method based on the FPGA EtherCAT bus protocol of the foregoing embodiments, particularly... Figure 1 The flowchart of the method is shown.

[0170] It should be recognized that embodiments of the present invention may be implemented or carried out by computer hardware, a combination of hardware and software, or by computer instructions stored in a non-transitory computer-readable storage medium.

[0171] The method can be implemented using standard programming techniques, including a non-transitory computer-readable storage medium configured with a computer program in the computer program, wherein the storage medium is configured such that the computer operates in a specific and predefined manner.

[0172] Each program can be implemented in a high-level procedural or object-oriented programming language to communicate with the computer system; however, if required, the program can be implemented in assembly or machine language.

[0173] In any case, the language can be either compiled or interpreted.

[0174] Furthermore, for this purpose, the program can run on programmed application-specific integrated circuits.

[0175] The processes described herein (or variations and / or combinations thereof) can be executed under the control of one or more computer systems configured with executable instructions, and can be implemented by hardware or a combination thereof as code (e.g., executable instructions, one or more computer programs, or one or more applications) that commonly executes on one or more processors. The computer program includes a plurality of instructions executable by one or more processors.

[0176] Furthermore, the method can be implemented in any suitable computing platform, including but not limited to personal computers, minicomputers, mainframes, workstations, networked or distributed computing environments, standalone or integrated computer platforms, or in communication with charged particle tools or other imaging devices.

[0177] Various aspects of the present invention can be implemented in machine-readable code stored on a non-transitory storage medium or device, whether portable or integrated into a computing platform, such as a hard disk, optical read and / or write storage medium, RAM, ROM, etc., such that it can be read by a programmable computer, and when the storage medium or device is read by the computer, it can be used to configure and operate the computer to perform the processes described herein.

[0178] Furthermore, machine-readable code, or parts thereof, can be transmitted via wired or wireless networks.

[0179] When such media includes instructions or programs that combine with a microprocessor or other data processor to implement the steps described above, the invention described herein includes these and other different types of non-transitory computer-readable storage media.

[0180] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A virtual slave station and incremental monitoring method based on FPGA and EtherCAT bus protocol, characterized in that: include: Pre-store the corresponding slave station's shadow configuration register group for each port, and record the slave station's PDO mapping template and WKC incremental expected value; The port state machine continuously monitors the link signal loss flag for each port; When the flag indicates that the corresponding slave station is online normally: receive the data frame, divide the data frame into multiple segmented data blocks for parallel verification, and simultaneously buffer the data frame; If the verification passes, the actual WKC increment in the sub-message is extracted from the cache station by station, compared with the pre-stored expected WKC increment, and the number of deviations is recorded. If the verification fails, the data frame is discarded and no WKC comparison is performed; When the flag indicates that the corresponding slave station is offline: immediately switch to the shadow configuration register group of the port to build a virtual loopback channel, and the virtual slave station engine generates a response data frame to reply to the master station; Once the slave station comes back online, the data exchange of the slave station is directly restored according to the PDO mapping template in the shadow configuration register group.

2. The virtual slave station and incremental monitoring method based on FPGA and EtherCAT bus protocol as described in claim 1, characterized in that: The shadow configuration register group also stores: a distributed clock timestamp before offline, a deep cache queue, alternative response data templates required by the virtual slave engine, and a configuration command record area; wherein: The deep cache queue is used to store all process data write operation sub-messages sent by the master station to the corresponding port during offline periods, and is stored in first-in-first-out order. The alternative response data template is derived from the PDO mapping template: for each input data entry in the PDO mapping template, the default response is all zeros; for the status bit field, the online status of the controlled slave is set to zero and the slave offline warning flag is set at the same time; the derivation rules are fixed in the FPGA logic and do not require runtime calculation. The configuration command record area is used to cache all configuration commands and corresponding parameters received during offline periods, and stores them in chronological order.

3. The virtual slave and incremental monitoring method based on FPGA and EtherCAT bus protocol as described in claim 1, characterized in that: The data frame is divided into continuous segmented data blocks with a fixed byte length. Each segmented data block is accompanied by its actual byte length and is sent in parallel to an independent cyclic redundancy check calculation channel. Each channel uses the same preset polynomial and the same initial value to independently calculate the intermediate check value of the corresponding segmented data block; The intermediate check values ​​are merged according to the original segment order: for the first segment, the intermediate check value is used as the current merged value; For the i-th segment, obtain the shift factor value pre-stored based on the cumulative byte length of the segment data block, perform polynomial multiplication on the intermediate check value of the i-th segment and the shift factor value in a finite field to obtain the product value, and then perform an XOR operation on the current merged value and the product value, and use the result as the new current merged value. All segments are merged sequentially to obtain the global checksum; The final frame verification sequence field is obtained by performing an XOR operation between the global verification value and the preset XOR value.

4. The virtual slave and incremental monitoring method based on FPGA and EtherCAT bus protocol as described in claim 1, characterized in that: The comparison with the pre-stored expected value of WKC increments includes: It only executes in normal online mode, and skips WKC incremental comparison when the port is in virtual slave active state; and only performs WKC incremental comparison on sub-packets with unicast addressing mode. For broadcast and multicast sub-packets, it skips the comparison and keeps the offset count register unchanged. For the sub-message corresponding to this port, and when the port is directly connected to a single physical slave in a point-to-point manner: first read the first WKC value of the sub-message before it is sent to the physical slave through the port, and define the first WKC value as the value of the working counter field in the sub-message before it has been processed by the physical slave. The sub-message is sent through the port to the physical slave station directly connected to it; When the same sub-message is processed by the physical slave station and returns through the same port, the second WKC value in the sub-message is read again as the processed value. The difference between the second WKC value and the first WKC value is calculated as the actual WKC increment, and the actual WKC increment is compared with the expected WKC increment value pre-stored in the shadow configuration register group: If they are not equal, increment the offset count register of the corresponding slave station by one; if they are equal, continue processing the next sub-message.

5. The virtual slave and incremental monitoring method based on FPGA and EtherCAT bus protocol as described in claim 1, characterized in that: Constructing a virtual loopback channel includes: The port state machine continuously monitors the link signal loss flag of each port. When the link signal loss flag changes from invalid to valid, the data transmission and reception path of the port is switched to the internal virtual loopback channel and the physical transceiver is shielded. The virtual slave engine is activated, and the engine generates an alternative response data frame to reply to the master station based on the PDO mapping template and the alternative response data template in the shadow configuration register group. Record the distributed clock timestamp of the offline start time and store it in the distributed clock timestamp field before offline in the shadow configuration register group.

6. The virtual slave and incremental monitoring method based on FPGA and EtherCAT bus protocol as described in claim 2, characterized in that: The virtual slave engine generates alternative response data frames according to the following rules: For read operation sub-messages, return the corresponding data in the alternative response data template, and increment the work counter field in the sub-message by one; For a write operation sub-message, return a write success status, increment the work counter field in the sub-message by one, and store a complete copy of the write operation sub-message into the deep cache queue in the shadow configuration register group; For read and write operation sub-messages, the behavior of performing read and write operations simultaneously is as follows: return read data, increment the work counter field in the sub-message by two, and push the copy of the sub-message of the write operation part into the deep cache queue; For configuration commands, the command acceptance status is returned, and the type, address, data content, and length of the configuration command are stored in the configuration command record area of ​​the shadow configuration register group.

7. The virtual slave and incremental monitoring method based on FPGA and EtherCAT bus protocol as described in claim 2, characterized in that: Directly restoring the slave's data exchange based on the PDO mapping template in the shadow configuration register group includes: When the link signal loss flag is restored to invalid, the PDO mapping template in the shadow configuration register group is read, and the PDO mapping template is written into the corresponding synchronization manager and fieldbus memory management unit register of the slave station through the configuration command. At the same time, the master station software is notified to update the local shadow table through the interrupt request. Read the current global distributed clock reference time maintained internally by the FPGA; The difference is calculated between the distributed clock timestamp before offline stored in the shadow configuration register group; if the difference is less than a first threshold, the difference is compensated by a single command; if the difference is greater than or equal to the first threshold and less than or equal to a second threshold, multiple clock adjustment commands are generated to compensate step by step; if the difference is greater than the second threshold, an interrupt is triggered and the virtual slave mode is maintained, waiting for master station intervention.

8. The virtual slave and incremental monitoring method based on FPGA and EtherCAT bus protocol as described in claim 7, characterized in that: After clock compensation is completed, if there are cached configuration commands in the configuration command record area, the configuration commands are resent to the actual slave station in the order of recording and the record area of ​​the configuration commands is cleared; if there are valid write operation sub-message copies in the deep cache queue, the write operation sub-message copies are resent to the actual slave station in the first-in-first-out order and the deep cache queue is cleared. Exit virtual slave mode and loopback mode, reconnect the port to the data frame forwarding path, and clear the virtual slave activation flag.

9. The virtual slave and incremental monitoring method based on FPGA and EtherCAT bus protocol as described in claim 1, characterized in that: If a verification failure occurs during the data frame verification process, the data frame is discarded and a link alarm is triggered, and no retransmission request is sent to the peer device; at the same time, for data frames that fail verification, no subsequent WKC incremental comparison and virtual loopback processing are performed.

10. A virtual slave and incremental monitoring system based on FPGA and EtherCAT bus protocol, used to implement the virtual slave and incremental monitoring method based on FPGA and EtherCAT bus protocol as described in any one of claims 1 to 9, characterized in that: include: The shadow configurator module independently pre-stores the corresponding shadow configuration register group for each EtherCAT port of the FPGA. The register group records at least the PDO mapping template and WKC incremental expected value of the slave station. The frame checker module is connected to the receiving data path of the FPGA at its input end. It is configured to divide the received data frame into multiple segmented data blocks, calculate the intermediate check value of each segmented data block in parallel, and merge them in the order of segmentation to obtain the global check value. The global check value is compared with the frame check sequence at the end of the frame, and the check pass signal or check failure signal is output. The offline switcher module includes a port state machine, with an input end connected to a physical layer link signal loss flag and an output end connected to a transmit / receive path switch. The port state machine continuously monitors the link signal loss flag of each port. When it detects that the corresponding slave station is offline, it controls the path switch to switch to the internal virtual loopback channel and activates the virtual slave engine. The incremental monitor module is connected to the verification pass signal of the frame checker module and the online status signal of the offline switcher module at its input end. It is configured to extract the actual WKC increment in the sub-message when the slave station is online and the virtual slave station is not activated, and compare it with the expected WKC increment provided by the shadow configurator module, and record and store the number of deviations. The online recovery module is connected to the link recovery signal of the offline switcher module at its input end. It is also connected to the shadow configurator module, the virtual slave engine, and the physical slave interface, respectively. It is configured to directly restore the data exchange of the slave based on the PDO mapping template in the shadow configuration register group after the slave comes back online.

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