Array substrate and display device

Abstract

The present disclosure provides an array substrate and a display device. The array substrate comprises a plurality of pixel driving circuits; each of the plurality of pixel driving circuits comprises a driving transistor, a first light-emitting control transistor and a third reset transistor; the active layers of the driving transistor, the first light-emitting control transistor and the third reset transistor are located in a first semiconductor material layer; the first electrode of the driving transistor, the second electrode of the first light-emitting control transistor and the second electrode of the third reset transistor are located in the first semiconductor material layer; the first electrode of the driving transistor, the second electrode of the first light-emitting control transistor and the second electrode of the third reset transistor are part of an integral structure; and the first electrode of the driving transistor, the second electrode of the first light-emitting control transistor and the second electrode of the third reset transistor are connected to each other through one or more parts of the first semiconductor material layer.

Description

Technical Field

[0001] This invention relates to display technology, and more particularly to an array substrate and a display device. Background Technology

[0002] Organic light-emitting diode (OLED) displays are currently one of the hottest research areas in flat panel displays. OLEDs are driven by a driving current that needs to be kept constant to control brightness. An OLED display panel includes multiple pixel units, which are configured with pixel driving circuits arranged in multiple rows and columns. Summary of the Invention

[0003] In a first aspect, this disclosure provides an array substrate including a plurality of pixel driving circuits; wherein each pixel driving circuit includes a driving transistor, a first light-emitting control transistor, and a third reset transistor; the active layers of the driving transistor, the first light-emitting control transistor, and the third reset transistor are located on a first semiconductor material layer; a first electrode of the driving transistor, a second electrode of the first light-emitting control transistor, and a second electrode of the third reset transistor are located on the first semiconductor material layer; the first electrode of the driving transistor, the second electrode of the first light-emitting control transistor, and the second electrode of the third reset transistor are part of an integral structure; and the first electrode of the driving transistor, the second electrode of the first light-emitting control transistor, and the second electrode of the third reset transistor are connected to each other through one or more portions of the first semiconductor material layer.

[0004] In some embodiments of this disclosure, the array substrate further includes: a first light-emitting control electrode pad located on the first semiconductor material layer; and a plurality of light-emitting control signal lines located on the side of the first light-emitting control electrode pad away from the first semiconductor material layer; wherein the first light-emitting control electrode pad includes the gate of the first light-emitting control transistor; and each of the plurality of light-emitting control signal lines is connected to the first light-emitting control electrode pad through a via.

[0005] In some embodiments of this disclosure, the array substrate further includes: a second light-emitting control electrode pad located on the first semiconductor material layer; and a plurality of light-emitting control signal lines located on the side of the second light-emitting control electrode pad away from the first semiconductor material layer; wherein each pixel driving circuit further includes a second light-emitting control transistor; the second light-emitting control electrode pad includes the gate of the second light-emitting control transistor; and each of the plurality of light-emitting control signal lines is connected to the second light-emitting control electrode pad through a via.

[0006] In some embodiments of this disclosure, each pixel driving circuit further includes a storage capacitor, the storage capacitor including a first capacitor electrode and a second capacitor electrode; the first light-emitting control electrode pad and the first capacitor electrode are located in a first gate metal layer; the second capacitor electrode is located in a second gate metal layer, the second gate metal layer being located on the side of the first gate metal layer away from the first semiconductor material layer; the plurality of light-emitting control signal lines are located in a first signal line layer, the first signal line layer being located on the side of the second gate metal layer away from the first gate metal layer.

[0007] In some embodiments of this disclosure, each pixel driving circuit further includes a compensation transistor; the active layer of the compensation transistor is located on a second semiconductor material layer, the second semiconductor material layer being located on the side of the second gate metal layer away from the first gate metal layer; at least a portion of the gate of the compensation transistor is located on a third gate metal layer, the third gate metal layer being located on the side of the second semiconductor material layer away from the second gate metal layer; and the plurality of light emission control signal lines are located on a first signal line layer, the first signal line layer being located on the side of the third gate metal layer away from the second semiconductor material layer.

[0008] In some embodiments of this disclosure, the array substrate further includes: a first voltage connection pad and a plurality of first voltage supply lines; wherein the active layer of the first light-emitting control transistor, the first voltage connection pad, and the plurality of first voltage supply lines are located on three different layers; and a corresponding first voltage supply line among the plurality of first voltage supply lines is connected to the first voltage connection pad, and the first voltage connection pad is connected to the first electrode of the first light-emitting control transistor.

[0009] In some embodiments of this disclosure, the orthographic projection of the second electrode of the third reset transistor onto the substrate at least partially overlaps with the orthographic projection of the first voltage connection pad onto the substrate.

[0010] In some embodiments of this disclosure, the array substrate further includes: a plurality of light-emitting control signal lines; wherein each of the plurality of light-emitting control signal lines is configured to provide a light-emitting control signal to the gate of the first light-emitting control transistor; and the first voltage connection pad is located on the same layer as the plurality of light-emitting control signal lines.

[0011] In some embodiments of this disclosure, the first voltage connection pad is connected to the first electrode of a first light-emitting control transistor in two adjacent pixel driving circuits located in the same row.

[0012] In some embodiments of this disclosure, each of the first voltage supply lines includes a body and a plurality of extensions extending in a direction away from the body; each of the plurality of extensions is connected to the first voltage connection pad; and the first voltage connection pad is connected to the first electrode of the first light-emitting control transistor.

[0013] In some embodiments of this disclosure, each pixel driving circuit further includes a compensation transistor; the active layer of the compensation transistor is located on a second semiconductor material layer, the second semiconductor material layer being located on the side of the first semiconductor material layer away from the substrate; the orthographic projection of the body on the substrate substantially covers the orthographic projection of the active layer of the compensation transistor on the substrate.

[0014] In some embodiments of this disclosure, the orthographic projection of the body on the substrate substantially covers the orthographic projections of the first electrode of the compensation transistor, the active layer, and the second electrode on the substrate.

[0015] In some embodiments of this disclosure, each pixel driving circuit further includes a first reset transistor and a second reset transistor; wherein the array substrate further includes: a plurality of third reset signal lines configured to provide a third reset signal to a first electrode of the third reset transistor in the plurality of pixel driving circuits; a plurality of first reset signal lines configured to provide a first reset signal to a first electrode of the first reset transistor in the plurality of pixel driving circuits; and / or a plurality of second reset signal lines configured to provide a second reset signal to a first electrode of the second reset transistor in the plurality of pixel driving circuits; wherein the plurality of first reset signal lines, the plurality of second reset signal lines, and the plurality of third reset signal lines extend along a direction substantially parallel to a first direction.

[0016] In some embodiments of this disclosure, the array substrate further includes: a plurality of third reset signal lines configured to provide a third reset signal to a first electrode of a third reset transistor in the plurality of pixel driving circuits; a plurality of first low-voltage supply lines; a plurality of fourth reset signal lines; a plurality of fifth reset signal lines; a plurality of sixth reset signal lines; and a plurality of second low-voltage supply lines; wherein the plurality of third reset signal lines and the plurality of first low-voltage signal lines extend along a direction substantially parallel to a first direction; the plurality of fourth reset signal lines, the plurality of fifth reset signal lines, the plurality of sixth reset signal lines, and the plurality of second low-voltage supply lines extend along a direction substantially parallel to a second direction; the second direction is different from the first direction; and the plurality of fourth reset signal lines, the plurality of fifth reset signal lines, the plurality of sixth reset signal lines, and the plurality of second low-voltage supply lines are located in the same layer and on the side of the plurality of third reset signal lines and the plurality of first low-voltage signal lines away from the first semiconductor material layer.

[0017] In some embodiments of this disclosure, the plurality of fourth reset signal lines, the plurality of fifth reset signal lines, the plurality of sixth reset signal lines, and the plurality of second low-voltage supply lines are arranged alternately.

[0018] In some embodiments of this disclosure, the plurality of pixel driving circuits are arranged in J columns, where J is a positive integer; the J columns include the (8j-7)th column, the (8j-6)th column, the (8j-5)th column, the (8j-4)th column, the (8j-3)th column, the (8j-2)th column, the (8j-1)th column, and the (8j)th column, where j is a positive integer, 1 ≤ j ≤ (J / 8); one of the corresponding fourth reset signal line of the plurality of fourth reset signal lines, the corresponding fifth reset signal line of the plurality of fifth reset signal lines, the corresponding sixth reset signal line of the plurality of sixth reset signal lines, and the corresponding second low-voltage supply line of the plurality of second low-voltage supply lines, is located between the (8j-7) column and the (8j-6) column; another of the corresponding fourth reset signal line, the corresponding fifth reset signal line, the corresponding sixth reset signal line, and the corresponding second low-voltage supply line is located between the (8j-5) column and the (8j-4) column; yet another of the corresponding fourth reset signal line, the corresponding fifth reset signal line, the corresponding sixth reset signal line, and the corresponding second low-voltage supply line is located between the (8j-3) column and the (8j-2) column; and yet another of the corresponding fourth reset signal line, the corresponding fifth reset signal line, the corresponding sixth reset signal line, and the corresponding second low-voltage supply line is located between the (8j-1) column and the (8j) column.

[0019] In some embodiments of this disclosure, the array substrate further includes: a first corresponding anode, a second corresponding anode, a third corresponding anode, and a fourth corresponding anode; wherein the first corresponding anode is the anode of a sub-pixel of a first color, the second corresponding anode is the anode of a sub-pixel of a second color, and the third and fourth corresponding anodes are the anodes of two sub-pixels of a third color; the orthographic projection of the third corresponding anode on the substrate at least partially overlaps with the orthographic projections of two adjacent second voltage supply lines among the plurality of second voltage supply lines on the substrate, and at least partially overlaps with the orthographic projection of one of the corresponding fourth reset signal line, the corresponding fifth reset signal line, the corresponding sixth reset signal line, and the corresponding second low-voltage supply line on the substrate; and the orthographic projection of the fourth corresponding anode on the substrate at least partially overlaps with the orthographic projections of two adjacent second voltage supply lines among the plurality of second voltage supply lines on the substrate, and at least partially overlaps with the orthographic projection of one of the corresponding fourth reset signal line, the corresponding fifth reset signal line, the corresponding sixth reset signal line, and the corresponding second low-voltage supply line on the substrate.

[0020] In some embodiments of this disclosure, at least one of the first corresponding anode, the second corresponding anode, the third corresponding anode, or the fourth corresponding anode has its orthogonal projection on the substrate at least partially overlaps with the orthogonal projection of the second electrode of the third reset transistor on the substrate.

[0021] In a second aspect, this disclosure provides an array substrate including a plurality of pixel driving circuits: wherein each pixel driving circuit includes a second node connection line, a first light-emitting control transistor, a third reset transistor, and a second node connection line; the second node connection line is connected to the second electrode of the first light-emitting control transistor and to the second electrode of the third reset transistor; and the second node connection line is located on the same layer as the active layer of the first light-emitting control transistor and the third reset transistor.

[0022] In some embodiments of this disclosure, the array substrate further includes a plurality of light-emitting control signal lines; wherein each of the plurality of light-emitting control signal lines is configured to provide a control signal to the gate of the first light-emitting control transistor; and the plurality of light-emitting control signal lines are spaced apart from the second node connection line by at least three insulating layers.

[0023] In some embodiments of this disclosure, each pixel driving circuit further includes a first node connection line, a storage capacitor, and a compensation transistor; the first node connection line is connected to a first capacitor electrode of the storage capacitor and to a first electrode of the compensation transistor; and the plurality of light emission control signal lines and the first node connection line are located on the same layer.

[0024] In a third aspect, this disclosure provides a display device including the array substrate and one or more integrated circuits connected to the array substrate. Attached Figure Description

[0025] The following figures are merely illustrative examples based on various disclosed embodiments and are not intended to limit the scope of the invention.

[0026] Figure 1 This is a plan view of an array substrate according to some embodiments of the present disclosure.

[0027] Figure 2A This is a circuit diagram illustrating the structure of a pixel driving circuit according to some embodiments of the present disclosure.

[0028] Figure 2B This is a timing diagram illustrating the operation of a pixel driving circuit according to some embodiments of the present disclosure.

[0029] Figure 3AThis is a schematic diagram illustrating the structure of a pixel driving circuit in an array substrate according to some embodiments of the present disclosure.

[0030] Figure 3B It is shown Figure 3A The diagram shows a schematic representation of the structure of the first semiconductor material layer, the first gate metal layer, the second gate metal layer, the second semiconductor material layer, the third gate metal layer, and the first signal line layer in the array substrate.

[0031] Figure 3C It is shown Figure 3A The diagram shows a schematic of the arrangement of pixel driving circuits on the array substrate.

[0032] Figure 3D It is shown Figure 3A A schematic diagram of the structure of the first semiconductor material layer in the array substrate shown.

[0033] Figure 3E It is shown Figure 3A The diagram shows a schematic of the structure of the first gate metal layer in the array substrate.

[0034] Figure 3F It is shown Figure 3A A schematic diagram of the structure of the second gate metal layer in the array substrate shown.

[0035] Figure 3G It is shown Figure 3A A schematic diagram of the structure of the second semiconductor material layer in the array substrate shown.

[0036] Figure 3H It is shown Figure 3A The diagram shows a schematic of the structure of the third gate metal layer in the array substrate.

[0037] Figure 3I It is shown Figure 3A A schematic diagram of the passivation layer structure of the array substrate shown.

[0038] Figure 3J It is shown Figure 3A The diagram shows a schematic of the structure of the first signal line layer in the array substrate.

[0039] Figure 3K It is shown Figure 3A A schematic diagram of the structure of the first planarization layer in the array substrate shown.

[0040] Figure 3L It is shown Figure 3A A schematic diagram of the structure of the second signal line layer in the array substrate shown.

[0041] Figure 3M It is shown Figure 3A A schematic diagram of the structure of the second planarization layer in the array substrate shown.

[0042] Figure 3N It is shown Figure 3A The diagram shows a schematic of the structure of the third signal line layer in the array substrate.

[0043] Figure 3O It is shown Figure 3A A schematic diagram of the structure of the anode layer in the array substrate shown.

[0044] Figure 4A It is along Figure 3A A cross-sectional view of line A-A' in the diagram.

[0045] Figure 4B It is along Figure 3A A cross-sectional view of line B-B' in the diagram.

[0046] Figure 5 The voltage supply path in an array substrate according to some embodiments of the present disclosure is shown.

[0047] Figure 6 This is a schematic diagram illustrating the structure of a corresponding first voltage supply line in an array substrate according to some embodiments of the present disclosure.

[0048] Figure 7 It is shown Figure 3A A schematic diagram of the structure of the second semiconductor material layer and the corresponding first voltage supply line in the array substrate shown.

[0049] Figure 8A This is a schematic diagram illustrating the structure of a pixel driving circuit in an array substrate according to some embodiments of the present disclosure.

[0050] Figure 8B This is a schematic diagram showing the arrangement of pixel driving circuits in the array substrate shown in Figure 8A.

[0051] Figure 8C It is shown Figure 8A A schematic diagram of the structure of the first semiconductor material layer in the array substrate shown.

[0052] Figure 8D It is shown Figure 8A The diagram shows a schematic of the structure of the first gate metal layer in the array substrate.

[0053] Figure 8E It is shown Figure 8A A schematic diagram of the structure of the second gate metal layer in the array substrate shown.

[0054] Figure 8F It is shown Figure 8AA schematic diagram of the structure of the second semiconductor material layer in the array substrate shown.

[0055] Figure 8G It is shown Figure 8A The diagram shows a schematic of the structure of the third gate metal layer in the array substrate.

[0056] Figure 8H It is shown Figure 8A A schematic diagram of the structure of the passivation layer in the array substrate shown.

[0057] Figure 8I It is shown Figure 8A The diagram shows a schematic of the structure of the first signal line layer in the array substrate.

[0058] Figure 8J It is shown Figure 8A A schematic diagram of the structure of the first planarization layer in the array substrate shown.

[0059] Figure 8K It is shown Figure 8A A schematic diagram of the structure of the second signal line layer in the array substrate shown.

[0060] Figure 8L It is shown Figure 8A A schematic diagram of the structure of the second planarization layer in the array substrate shown.

[0061] Figure 8M It is shown Figure 8A The diagram shows a schematic of the structure of the third signal line layer in the array substrate.

[0062] Figure 8N It is shown Figure 8A A schematic diagram of the structure of the anode layer in the array substrate shown.

[0063] Figure 8O It is shown Figure 8A The diagram shows the structure of the third signal line layer and the anode layer in the array substrate.

[0064] Figure 8P It is shown Figure 8A The diagram shows the structure of the first semiconductor material layer and the anode layer in the array substrate.

[0065] Figure 9A A first interconnect reset signal network is shown in some embodiments according to this disclosure.

[0066] Figure 9B A first interconnect reset signal network is shown in some embodiments according to this disclosure.

[0067] Figure 10AA second interconnect reset signal network is shown according to some embodiments of the present disclosure.

[0068] Figure 10B A second interconnect reset signal network is shown according to some embodiments of the present disclosure.

[0069] Figure 11 A third interconnect reset signal network is shown in some embodiments according to this disclosure.

[0070] Figure 12 An interconnected low-voltage supply network is shown in some embodiments according to this disclosure.

[0071] Figure 13 It is shown Figure 3A A schematic diagram of the structure of the first semiconductor material layer in the array substrate shown. Detailed Implementation

[0072] This disclosure will now be described in more detail with reference to the following embodiments. It should be noted that the following description of some embodiments presented herein is for illustrative and descriptive purposes only. It is not exhaustive or limited to the precise forms disclosed.

[0073] This disclosure particularly provides an array substrate and a display device that substantially overcomes one or more problems caused by the limitations and disadvantages of the prior art. In one aspect, this disclosure provides an array substrate. In some embodiments, the array substrate includes a plurality of pixel driving circuits. Optionally, each pixel driving circuit in the plurality of pixel driving circuits includes a driving transistor, a data writing transistor, a first light-emitting control transistor, and a third reset transistor. Optionally, the active layers of the driving transistor, the data writing transistor, the first light-emitting control transistor, and the third reset transistor are located on a first semiconductor material layer. Optionally, the second electrode of the data writing transistor, the first electrode of the driving transistor, the second electrode of the first light-emitting control transistor, and the second electrode of the third reset transistor are located on the first semiconductor material layer. Optionally, the second electrode of the data writing transistor, the first electrode of the driving transistor, the second electrode of the first light-emitting control transistor, and the second electrode of the third reset transistor are part of an integral structure. Optionally, the second electrode of the data writing transistor, the first electrode of the driving transistor, the second electrode of the first light-emitting control transistor, and the second electrode of the third reset transistor are connected to each other through one or more portions of the first semiconductor material layer.

[0074] Various suitable pixel driving circuits can be used in the array substrate described in this disclosure. Examples of suitable driving circuits include 3T1C, 2T1C, 4T1C, 4T2C, 5T2C, 6T1C, 7T1C, 7T2C, 8T1C, and 8T2C. In some embodiments, each pixel driving circuit in a plurality of pixel driving circuits is an 8T1C driving circuit. Various suitable light-emitting elements can be used in the array substrate described in this disclosure. Examples of suitable light-emitting elements include organic light-emitting diodes (OLEDs), quantum dot OLEDs, and micro-LEDs. Optionally, the light-emitting element is a micro-LED. Optionally, the light-emitting element is an organic light-emitting diode including an organic light-emitting layer.

[0075] Figure 1 This is a plan view of an array substrate according to some embodiments of the present disclosure. (Refer to...) Figure 1 The array substrate comprises an array of subpixels Sp. Each subpixel includes electronic components, such as a light-emitting element. In one example, the light-emitting element is driven by a corresponding pixel driving circuit PDC. The array substrate includes multiple first gate lines (e.g., corresponding first gate line GL1), multiple second gate lines (e.g., corresponding second gate line GL2), multiple data lines (e.g., corresponding data line DL), multiple high-voltage supply lines (e.g., corresponding high-voltage supply line Vdd), and multiple low-voltage supply lines (e.g., corresponding low-voltage supply line Vss). Each subpixel Sp emits light driven by its corresponding pixel driving circuit PDC. In one example, a high-voltage signal (e.g., a VDD signal) is input to the corresponding pixel driving circuit PDC connected to the anode of the light-emitting element via the corresponding high-voltage supply line Vdd among the multiple high-voltage supply lines; a low-voltage signal (e.g., a VSS signal) is input to the cathode of the light-emitting element via the low-voltage supply line. The voltage difference between the high-voltage signal (e.g., the VDD signal) and the low-voltage signal (e.g., the VSS signal) is the driving voltage ΔV, which drives the light-emitting element to emit light.

[0076] Figure 2A This is a circuit diagram illustrating the structure of a pixel driving circuit according to some embodiments of the present disclosure. (Refer to...) Figure 2AIn some embodiments, the pixel driving circuit includes a driving transistor Td; a storage capacitor Cst having a first capacitor electrode Ce1 and a second capacitor electrode Ce2; a second reset transistor Tr2 having a gate connected to a corresponding second reset control signal line rst2 among a plurality of second reset control signal lines, a first electrode connected to a corresponding second reset signal line Vint2 among a plurality of second reset signal lines, and a second electrode connected to a second electrode of the driving transistor Td; a first transistor T1 having a gate connected to a corresponding first gate line GL1 among a plurality of first gate lines, a first electrode connected to a corresponding data line DL among a plurality of data lines, and a second electrode connected to a first electrode of the driving transistor Td; a third reset transistor Tr3 having a gate connected to a corresponding first reset control signal line rst1 among a plurality of first reset control signal lines, a first electrode connected to a corresponding third reset signal line Vint3 among a plurality of third reset signal lines, and a second electrode connected to a first electrode of the driving transistor Td; and a second transistor T2 having a corresponding second gate line among a plurality of second gate lines. The transistor GL2 has a gate, a first electrode connected to the storage capacitor Cst's first capacitor electrode Ce1 and the gate of the driving transistor Td, and a second electrode connected to the second electrode of the driving transistor Td; a third transistor T3 has a gate connected to a corresponding light-emitting control signal line em among a plurality of light-emitting control signal lines, a first electrode connected to a corresponding voltage supply line Vdd among a plurality of voltage supply lines, and a second electrode connected to the first electrode of the driving transistor Td and the second electrode of the first transistor T1; a fourth transistor T4 has a gate connected to a corresponding light-emitting control signal line em among a plurality of light-emitting control signal lines, a first electrode connected to the second electrode of the driving transistor Td and the second transistor T2, and a second electrode connected to the anode of the light-emitting element LE; and a first reset transistor Tr1 has a gate connected to a corresponding first reset control signal line rst1 among a plurality of first reset control signal lines, a first electrode connected to a corresponding first reset signal line Vint1 among a plurality of first reset signal lines, and a second electrode connected to the second electrode of the fourth transistor T4 and the anode of the light-emitting element LE. A second capacitor electrode Ce2 is connected to the corresponding voltage supply line and the first electrode of the third transistor T3.

[0077] In some embodiments, the pixel driving circuit includes a driving transistor Td, a data writing transistor (e.g., a first transistor T1), a compensation transistor (e.g., a second transistor T2), two light-emitting control transistors (e.g., a third transistor T3 and a fourth transistor T4), and three reset transistors (e.g., a first reset transistor Tr1, a second reset transistor Tr2, and a third reset transistor Tr3).

[0078] As used herein, a first electrode or a second electrode refers to one of a first terminal and a second terminal of a transistor, both of which are connected to the active layer of the transistor. The direction of current flowing through the transistor can be configured to be from the first electrode to the second electrode, or from the second electrode to the first electrode. Thus, depending on the direction of current flowing through the transistor, in one example, the first electrode is configured to receive an input signal and the second electrode is configured to output an output signal; in another example, the second electrode is configured to receive an input signal and the first electrode is configured to output an output signal.

[0079] The pixel driving circuit also includes a first node N1, a second node N2, a third node N3, and a fourth node N4. The first node N1 is connected to the gate of the driving transistor Td, the first capacitor electrode Ce1, and the first electrode of the second transistor T2. The second node N2 is connected to the second electrode of the third transistor T3, the second electrode of the first transistor T1, the second electrode of the third reset transistor Tr3, and the first electrode of the driving transistor Td. The third node N3 is connected to the second electrode of the driving transistor Td, the second electrode of the second transistor T2, the first electrode of the fourth transistor T4, and the second electrode of the second reset transistor Tr2. The fourth node N4 is connected to the second electrode of the fourth transistor T4, the second electrode of the first reset transistor Tr1, and the anode of the light-emitting element LE.

[0080] In some embodiments, the array substrate includes a plurality of sub-pixels. In some embodiments, the plurality of sub-pixels includes a corresponding first sub-pixel, a corresponding second sub-pixel, and a corresponding third sub-pixel. Optionally, a corresponding pixel of the array substrate includes a corresponding first sub-pixel, a corresponding second sub-pixel, and a corresponding third sub-pixel. The plurality of sub-pixels in the array substrate are arranged in an array. In one example, the array of the plurality of sub-pixels includes a repeating array in the format S1-S2-S3, wherein S1 represents a corresponding first sub-pixel, S2 represents a corresponding second sub-pixel, and S3 represents a corresponding third sub-pixel. In another example, the S1-S2-S3 format is a C1-C2-C3 format, wherein C1 represents a corresponding first sub-pixel of a first color, C2 represents a corresponding second sub-pixel of a second color, and C3 represents a corresponding third sub-pixel of a third color. In another example, the C1-C2-C3 format is an RGB format, wherein the corresponding first sub-pixel is a red sub-pixel, the corresponding second sub-pixel is a green sub-pixel, and the corresponding third sub-pixel is a blue sub-pixel.

[0081] In another example, the array of multiple subpixels includes a repeating array in the format S1-S2-S3-S4, where S1 represents the corresponding first subpixel, S2 represents the corresponding second subpixel, S3 represents the corresponding third subpixel, and S4 represents the corresponding fourth subpixel. In another example, the S1-S2-S3-S4 format is a C1-C2-C3-C4 format, where C1 represents the corresponding first subpixel of the first color, C2 represents the corresponding second subpixel of the second color, C3 represents the corresponding third subpixel of the third color, and C4 represents the corresponding fourth subpixel of the fourth color. In yet another example, the S1-S2-S3-S4 format is a C1-C2-C3-C2' format, where C1 represents the corresponding first subpixel of the first color, C2 represents the corresponding second subpixel of the second color, C3 represents the corresponding third subpixel of the third color, and C2' represents the corresponding fourth subpixel of the second color. In another example, the C1-C2-C3-C2' format is RGBG format, where the corresponding first subpixel is a red subpixel, the corresponding second subpixel is a green subpixel, the corresponding third subpixel is a blue subpixel, and the corresponding fourth subpixel is a green subpixel.

[0082] In some embodiments, the smallest repeating unit of the plurality of sub-pixels of the array substrate includes a corresponding first sub-pixel, a corresponding second sub-pixel, and a corresponding third sub-pixel. Optionally, each of the first sub-pixel, the second sub-pixel, and the third sub-pixel includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a first reset transistor Tr1, a second reset transistor Tr2, a third reset transistor Tr3, a driving transistor Td, and a storage capacitor Cst.

[0083] In an alternative embodiment, the smallest repeating unit of the plurality of sub-pixels of the array substrate includes a corresponding first sub-pixel, a corresponding second sub-pixel, a corresponding third sub-pixel, and a corresponding fourth sub-pixel. Optionally, each of the first sub-pixel, the second sub-pixel, the third sub-pixel, and the fourth sub-pixel includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a first reset transistor Tr1, a second reset transistor Tr2, a third reset transistor Tr3, a driving transistor Td, and a storage capacitor Cst.

[0084] This disclosure can be implemented in pixel driving circuits having various types of transistors, including pixel driving circuits having p-type transistors, pixel driving circuits having n-type transistors, and pixel driving circuits having one or more p-type transistors and one or more n-type transistors. (See also...) Figure 2AThe second transistor T2 is an n-type transistor, such as a metal-oxide-semiconductor (MOS) transistor, while the other transistors are p-type transistors, such as polysilicon transistors. For p-type transistors, the active control signal (e.g., the turn-on control signal) is a low-voltage signal, while the inactive control signal (e.g., the cut-off control signal) is a high-voltage signal. For n-type transistors, the active control signal (e.g., the turn-on control signal) is a high-voltage signal, while the inactive control signal (e.g., the cut-off control signal) is a low-voltage signal.

[0085] Figure 2B This is a timing diagram illustrating the operation of a pixel driving circuit according to some embodiments of the present disclosure. (Refer to...) Figure 2A and Figure 2B During one frame of an image, the operation of the pixel driving circuit includes a reset sub-stage t1, a data writing sub-stage t2, and a light emission sub-stage t3. In the initial sub-stage t0, a cutoff reset control signal is provided to the gate of the second reset transistor Tr2 via the corresponding second reset control signal line rst2 to turn off the second reset transistor Tr2. Cutoff reset control signals are provided to the gates of the first reset transistor Tr1 and the third reset transistor Tr3 via the corresponding first reset control signal line rst1 to turn off the first reset transistor Tr1 and the third reset transistor Tr3. In the initial sub-stage t0, a cutoff signal is provided to the corresponding first gate line GL1, therefore the first transistor T1 is turned off.

[0086] In reset phase t1, a turn-on reset control signal is provided to the gate of the first reset transistor Tr1 via the corresponding first reset control signal line rst1 to turn on the first reset transistor Tr1; allowing the initialization voltage signal from the corresponding first reset signal line Vint1 to pass from the first electrode of the first reset transistor Tr1 to the second electrode of the first reset transistor Tr1; and sequentially to node N4. The anode of the light-emitting element LE is initialized. A turn-on reset control signal is provided to the gate of the third reset transistor Tr3 via the corresponding first reset control signal line rst1 to turn on the third reset transistor Tr3; allowing the initialization voltage signal from the corresponding third reset signal line Vint3 to pass from the first electrode of the third reset transistor Tr3 to the second electrode of the third reset transistor Tr3; and sequentially to node N2. Node N2 is initialized. The second capacitor electrode Ce2 receives a high-voltage signal from the corresponding voltage supply line Vdd. Due to the increased voltage difference between the first capacitor electrode Ce1 and the second capacitor electrode Ce2, the first capacitor electrode Ce1 is charged in reset phase t1. In reset phase t1, a cutoff signal is provided to the corresponding first gate line GL1, therefore the first transistor T1 is turned off. The corresponding light-emitting control signal line em is provided with a high-voltage signal to cut off the third transistor T3 and the fourth transistor T4.

[0087] During the data writing sub-stage t2, a turn-on reset control signal is provided to the gate of the second reset transistor Tr2 via the second reset control signal line rst2 to turn on the second reset transistor Tr2; this allows the initialization voltage signal from the corresponding second reset signal line Vint2 to be transmitted from the first electrode of the second reset transistor Tr2 to the second electrode of the second reset transistor Tr2, and then to the second electrode of the driving transistor Td. The second electrode of the driving transistor Td is then initialized.

[0088] During the data writing sub-stage t2, a cutoff reset control signal is again provided to the gates of the first reset transistor Tr1 and the third reset transistor Tr3 via the corresponding first reset control signal line rst1, thus cutting off the first reset transistor Tr1 and the third reset transistor Tr3. The corresponding first gate line GL1 and the corresponding second gate line GL2 are respectively provided with conduction signals, therefore the first transistor T1 and the second transistor T2 are turned on. The first electrode of the driving transistor Td is connected to the second electrode of the second transistor T2. The gate of the driving transistor Td is electrically connected to the first electrode of the second transistor T2. Since the second transistor T2 is turned on during the data writing sub-stage t2, the gate and second electrode of the driving transistor Td are connected and short-circuited, so only the PN junction between the gate and the first electrode of the driving transistor Td is effective, thus making the driving transistor Td a diode connection mode. The first transistor T1 is turned on during the data writing sub-stage t2. The data voltage signal transmitted via the corresponding data line DL is received by the first electrode of the first transistor T1 and sequentially transmitted to the first electrode of the driving transistor Td, which is connected to the second electrode of the first transistor T1. Node N2, connected to the first electrode of the driving transistor Td, has a data voltage signal level. Since only the PN junction between the gate of the driving transistor Td and the first electrode is active, during the data write sub-stage t2, the voltage level of node N1 gradually rises to (Vdata + Vth), where Vdata is the data voltage signal level and Vth is the threshold voltage Th of the PN junction. Because the voltage difference between the first capacitor electrode Ce1 and the second capacitor electrode Ce2 decreases to a relatively small value, the storage capacitor Cst discharges. The corresponding light-emitting control signal line em provides a high-voltage signal to cut off the third transistor T3 and the fourth transistor T4.

[0089] In the light-emitting stage t3, a cutoff reset control signal is provided to the gate of the second reset transistor Tr2 via the corresponding second reset control signal line rst2 to turn off the second reset transistor Tr2. A cutoff reset control signal is provided to the gates of the first reset transistor Tr1 and the third reset transistor Tr3 via the corresponding first reset control signal line rst1 to turn off the first reset transistor Tr1 and the third reset transistor Tr3. The corresponding first gate line GL1 and the corresponding second gate line GL2 are respectively provided with cutoff signals, and the first transistor T1 and the second transistor T2 are turned off. The corresponding light-emitting control signal line em provides a low-voltage signal to turn on the third transistor T3 and the fourth transistor T4. In the light-emitting stage t3, the voltage level of node N1 is maintained at (Vdata + Vth), and the driving transistor Td is turned on by this voltage level, operating in the saturation region. A path is formed through the third transistor T3, the driving transistor Td, and the fourth transistor T4 to the light-emitting element LE. The driving transistor Td generates a driving current to drive the light-emitting element LE to emit light. The voltage level at node N3, which is connected to the second electrode of the driving transistor Td, is equal to the emission voltage of the light-emitting element LE.

[0090] Figure 3A This is a schematic diagram illustrating the structure of a pixel driving circuit in an array substrate according to some embodiments of the present disclosure. Figure 3B It is shown Figure 3A The diagram shows a schematic representation of the structure of the first semiconductor material layer, the first gate metal layer, the second gate metal layer, the second semiconductor material layer, the third gate metal layer, and the first signal line layer in the array substrate. Figure 3C It is shown Figure 3A The diagram shows a schematic of the arrangement of pixel driving circuits on the array substrate. Figures 3A to 3C A portion of an array substrate with two adjacent pixel driving circuits (including PDC1 and PDC2) is shown.

[0091] Figure 3D It is shown Figure 3A A schematic diagram of the structure of the first semiconductor material layer in the array substrate shown. Figure 3E It is shown Figure 3A The diagram shows a schematic of the structure of the first gate metal layer in the array substrate. Figure 3F It is shown Figure 3A A schematic diagram of the structure of the second gate metal layer in the array substrate shown. Figure 3G It is shown Figure 3A A schematic diagram of the structure of the second semiconductor material layer in the array substrate shown. Figure 3H It is shown Figure 3A The diagram shows a schematic of the structure of the third gate metal layer in the array substrate. Figure 3I It is shown Figure 3AA schematic diagram of the passivation layer structure of the array substrate shown. Figure 3J It is shown Figure 3A The diagram shows a schematic of the structure of the first signal line layer in the array substrate. Figure 3K It is shown Figure 3A A schematic diagram of the structure of the first planarization layer in the array substrate shown. Figure 3L It is shown Figure 3A A schematic diagram of the structure of the second signal line layer in the array substrate shown. Figure 3M It is shown Figure 3A A schematic diagram of the structure of the second planarization layer in the array substrate shown. Figure 3N It is shown Figure 3A The diagram shows a schematic of the structure of the third signal line layer in the array substrate. Figure 3O It is shown Figure 3A A schematic diagram of the structure of the anode layer in the array substrate shown. Figure 4A It is along Figure 3A A cross-sectional view of line A-A' in the diagram. Figure 4B It is along Figure 3A A cross-sectional view of line B-B' in the diagram.

[0092] refer to Figures 3A to 3N , Figure 4A and Figure 4BIn some embodiments, the array substrate includes a substrate BS; a buffer layer BUF located on the substrate BS; a first semiconductor material layer SML1 located on the side of the buffer layer BUF away from the substrate BS; a gate insulating layer GI located on the side of the first semiconductor material layer SML1 away from the substrate BS; a first gate metal layer Gate1 located on the side of the gate insulating layer GI away from the first semiconductor material layer SML1; an insulating layer IN located on the side of the first gate metal layer Gate1 away from the gate insulating layer GI; a second gate metal layer Gate2 located on the side of the insulating layer IN away from the first gate metal layer Gate1; a first interlayer dielectric layer ILD1 located on the side of the second gate metal layer Gate2 away from the insulating layer IN; a second semiconductor material layer SML2 located on the side of the first interlayer dielectric layer ILD1 away from the second gate metal layer SML2; and a second interlayer dielectric layer ILD2 located on the side of the second semiconductor material layer SML2 away from the first interlayer dielectric layer ILD1. The system comprises: a third gate metal layer (Gate3) located on the side of the second interlayer dielectric layer (ILD2) away from the second semiconductor material layer (SML2); a passivation layer (PVX) located on the side of the third gate metal layer (Gate3) away from the second interlayer dielectric layer (ILD2); a first signal line layer (SD1) located on the side of the passivation layer (PVX) away from the third gate metal layer (Gate3); a first planarization layer (PLN1) located on the side of the first signal line layer (SD1) away from the passivation layer (PVX); a second signal line layer (SD2) located on the side of the first planarization layer (PLN1) away from the first signal line layer (SD1); a second planarization layer (PLN2) located on the side of the second signal line layer (SD2) away from the first planarization layer (PLN1); a third signal line layer (SD3) located on the side of the second planarization layer (PLN2) away from the second signal line layer (SD2); a third planarization layer (PLN3) located on the side of the third signal line layer (SD3) away from the second planarization layer (PLN2); and an anode layer (ADL) located on the side of the third planarization layer (PLN3) away from the third signal line layer (SD3).

[0093] Reference Figure 2A , Figure 3A , Figure 3D , Figure 4A and Figure 4BIn some embodiments, the first semiconductor material layer SML1 includes at least an active layer of the plurality of transistors (including first transistor T1, third transistor T3, fourth transistor T4, first reset transistor Tr1, second reset transistor Tr2, third reset transistor Tr3, and driving transistor Td) of the pixel driving circuit. Optionally, the first semiconductor material layer SML1 also includes at least corresponding portions of the first electrodes of the plurality of transistors (including first transistor T1, third transistor T3, fourth transistor T4, first reset transistor Tr1, second reset transistor Tr2, third reset transistor Tr3, and driving transistor Td) of the pixel driving circuit. Optionally, the first semiconductor material layer SML1 also includes at least corresponding portions of the second electrodes of the plurality of transistors (including first transistor T1, third transistor T3, fourth transistor T4, first reset transistor Tr1, second reset transistor Tr2, third reset transistor Tr3, and driving transistor Td) of the pixel driving circuit. Optionally, the first semiconductor material layer SML1 includes an active layer, a first electrode, and a second electrode for a plurality of transistors (including a first transistor T1, a third transistor T3, a fourth transistor T4, a first reset transistor Tr1, a second reset transistor Tr2, a third reset transistor Tr3, and a driving transistor Td) of the pixel driving circuit. Various suitable semiconductor materials can be used to fabricate the first semiconductor material layer SML1. Examples of semiconductor materials used to fabricate the first semiconductor material layer SML1 include silicon-based semiconductor materials, such as polycrystalline silicon, monocrystalline silicon, and amorphous silicon.

[0094] exist Figure 3D In, corresponding to Figure 3C The pixel driving circuit of PDC2 is labeled with markings indicating components of each of the multiple transistors (T1, T3, T4, Tr1, Tr2, Tr3, and Td) in the pixel driving circuit. For example, the first transistor T1 includes an active layer ACT1, a first electrode S1, and a second electrode D1. The third transistor T3 includes an active layer ACT3, a first electrode S3, and a second electrode D3. The fourth transistor T4 includes an active layer ACT4, a first electrode S4, and a second electrode D4. The first reset transistor Tr1 includes an active layer ACTr1, a first electrode Sr1, and a second electrode Dr1. The second reset transistor Tr2 includes an active layer ACTr2, a first electrode Sr2, and a second electrode Dr2. The third reset transistor Tr3 includes an active layer ACTr3, a first electrode Sr3, and a second electrode Dr3. The driving transistor Td includes an active layer ACTd, a first electrode Sd, and a second electrode Dd.

[0095] Optionally, the active layers (ACT1, ACT3, ACT4, ACTr1, ACTr2, ACT3, and ACTd), the first electrodes (S1, S3, S4, Sr1, Sr2, Sr3, and Sd), and the second electrodes (D1, D3, D4, Dr1, Dr2, Dr3, and Dd) of each transistor (T1, T3, T4, Tr1, Tr2, Tr3, and Td) are located on the same layer.

[0096] In some embodiments, at least a portion of the active layers (ACT1, ACT3, ACT4, ACTr1, ACTr3, and ACTd) of the plurality of transistors (T1, T3, T4, Tr1, Tr3, and Td) in the pixel driving circuit, at least a portion of the first electrode (S1, S3, S4, Sr1, Sr3, and Sd), and at least a portion of the second electrode (D1, D3, D4, Dr1, Dr3, and Dd) are part of the overall structure. Optionally, in the same pixel driving circuit, a portion (ACTr2, Sr2, Dr2) of the second reset transistor Tr2 located on the first semiconductor material layer is spaced apart from the overall structure (T1, T3, T4, Tr1, and Td). Figure 3D As shown, in some embodiments, at least a portion of the active layers (ACT1, ACT3, ACT4, ACT1, ACT3, and ACTd) of a plurality of transistors (T1, T3, T4, Tr1, Tr3, and Td) in two adjacent pixel driving circuits, at least a portion of the first electrode (S1, S3, S4, Sr1, Sr3, and Sd), and at least a portion of the second electrode (D1, D3, D4, Dr1, Dr3, and Dd) are part of the overall structure.

[0097] Reference Figure 2A , Figure 3A , Figure 3E , Figure 4A as well as Figure 4B In some embodiments, the first gate metal layer Gate1 includes a plurality of first gate lines (e.g., corresponding first gate line GL1), a plurality of first reset control signal lines (e.g., corresponding first reset control signal line rst1), a plurality of second reset control signal lines (e.g., corresponding second reset control signal line rst2), a first light emission control electrode pad emP1, a second light emission control electrode pad emP2, and a first capacitor electrode Ce1 of the storage capacitor Cst in the pixel driving circuit.

[0098] In some embodiments, the first light-emitting control electrode pad emP1 includes the gate G3 of the third transistor T3. Optionally, the first light-emitting control electrode pad emP1 includes the gate of the third transistor of the first adjacent pixel driving circuit and the second adjacent pixel driving circuit located in the same row. In some embodiments, the second light-emitting control electrode pad emP2 includes the gate G4 of the fourth transistor T4. Optionally, the second light-emitting control electrode pad emP2 includes the gate of the fourth transistor of the first adjacent pixel driving circuit and the third adjacent pixel driving circuit located in the same row. The third adjacent pixel driving circuit, the first adjacent pixel driving circuit, and the second adjacent pixel driving circuit are arranged sequentially in the same row.

[0099] Various suitable electrode materials and various suitable manufacturing methods can be used to fabricate the first gate metal layer Gate1. For example, conductive materials can be deposited on a substrate and patterned using a plasma-enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for fabricating the first gate metal layer Gate1 include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloys, copper-molybdenum alloys, molybdenum-aluminum alloys, aluminum-chromium alloys, copper-chromium alloys, molybdenum-chromium alloys, copper-molybdenum-aluminum alloys, etc. Optionally, a plurality of first gate lines (e.g., corresponding first gate line GL1), a plurality of first reset control signal lines (e.g., corresponding first reset control signal line rst1), a plurality of second reset control signal lines (e.g., corresponding second reset control signal line rst2), a first light-emitting control electrode pad emP1, a second light-emitting control electrode pad emP2, and the first capacitor electrode Ce1 of the storage capacitor Cst are located on the same layer.

[0100] As used herein, the term "same layer" refers to a relationship between layers formed simultaneously in the same step. In one example, multiple first gate lines and first capacitor electrodes Ce1 are located in the same layer when they are formed due to one or more steps of the same patterning process performed in the same material layer. In another example, multiple first gate lines and first capacitor electrodes Ce1 can be formed in the same layer by simultaneously performing the steps of forming multiple first gate lines and the step of forming first capacitor electrodes Ce1. The term "same layer" does not always mean that the layer thickness or layer height is the same in a cross-sectional view.

[0101] In some embodiments, refer to Figure 3A , Figure 3B , Figure 3E , Figure 3J and Figure 4AThe first light-emitting control electrode pad emP1 and the second light-emitting control electrode pad emP2 are connected to corresponding light-emitting control signal lines em among a plurality of light-emitting control signal lines. Optionally, the first light-emitting control electrode pad emP1 and the second light-emitting control electrode pad emP2 are located in the first gate metal layer Gate1. Optionally, each light-emitting control signal line em is located in the first signal line layer SD1. In one example, the corresponding light-emitting control signal line em is connected to the first light-emitting control electrode pad emP1 through a via extending through the passivation layer PVX, the second interlayer dielectric layer ILD2, the first interlayer dielectric layer ILD1, and the insulating layer IN. In another example, the corresponding light-emitting control signal line em is connected to the second light-emitting control electrode pad emP2 through a via extending through the passivation layer PVX, the second interlayer dielectric layer ILD2, the first interlayer dielectric layer ILD1, and the insulating layer IN.

[0102] Reference Figure 2A , Figure 3A , Figure 3F , Figure 4A as well as Figure 4B In some embodiments, the second gate metal layer Gate2 includes at least portions of a plurality of second gate lines in the pixel driving circuit (e.g., corresponding first branches of the second gate lines GL2-1), a plurality of second reset signal lines (e.g., corresponding second reset signal line Vint2), and a second capacitor electrode Ce2 of the storage capacitor Cst. Various suitable electrode materials and various suitable manufacturing methods can be used to fabricate the second gate metal layer Gate2. For example, conductive materials can be deposited on a substrate and patterned using a plasma-enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for fabricating the second gate metal layer Gate2 include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloys, copper-molybdenum alloys, molybdenum-aluminum alloys, aluminum-chromium alloys, copper-chromium alloys, molybdenum-chromium alloys, copper-molybdenum-aluminum alloys, etc. Optionally, at least portions of the plurality of second gate lines in the pixel driving circuit (e.g., corresponding first branches of the second gate lines GL2-1), the plurality of second reset signal lines (e.g., corresponding second reset signal line Vint2), and the second capacitor electrode Ce2 of the storage capacitor Cst are located in the same layer.

[0103] Reference Figure 2A , Figure 3A , Figure 3G , Figure 4A and Figure 4BIn some embodiments, the second semiconductor material layer SML2 includes at least the active layer ACT2 of the second transistor T2 in the pixel driving circuit. Optionally, the second semiconductor material layer SML2 also includes at least a portion of the first electrode S2 of the second transistor T2 in the pixel driving circuit. Optionally, the second semiconductor material layer SML2 also includes at least a portion of the second electrode D2 of the second transistor T2 in the pixel driving circuit. Optionally, the second semiconductor material layer SML2 includes the active layer ACT2 of the second transistor T2, the first electrode S2, and the second electrode D2. In this array substrate, at least the active layer ACT2 of the second transistor T2 is located in a layer different from at least the active layers of other transistors in the pixel driving circuit. Various suitable semiconductor materials can be used to fabricate the second semiconductor material layer SML2. Examples of semiconductor materials used to fabricate the second semiconductor material layer SML2 include metal oxide-based semiconductor materials (e.g., indium gallium zinc oxide) and metal oxynitride-based semiconductor materials (e.g., zinc oxynitride).

[0104] exist Figure 3G In, corresponding to Figure 3B The pixel driving circuit of PDC1 is labeled with a marker indicating the components of the second transistor in the pixel driving circuit. For example, the second transistor T2 includes an active layer ACT2, a first electrode S2, and a second electrode D2. Optionally, the active layer ACT2, the first electrode S2, and the second electrode D2 of the second transistor T2 are located on the same layer.

[0105] refer to Figure 2A , Figure 3A , Figure 3H , Figure 4A and Figure 4B In some embodiments, the third gate metal layer Gate3 includes at least portions of a plurality of second gate lines (e.g., corresponding second branches of the second gate lines GL2-2), a plurality of first reset signal lines (e.g., corresponding first reset signal line Vint1), and a plurality of third reset signal lines (e.g., corresponding third reset signal line Vint3). Various suitable electrode materials and various suitable manufacturing methods can be used to fabricate the third gate metal layer Gate3. For example, conductive materials can be deposited on a substrate and patterned using a plasma-enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for fabricating the third gate metal layer Gate3 include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloys, copper-molybdenum alloys, molybdenum-aluminum alloys, aluminum-chromium alloys, copper-chromium alloys, molybdenum-chromium alloys, copper-molybdenum-aluminum alloys, etc.

[0106] Figure 3I Show Figure 3A The array substrate shown has vias extending through the passivation layer.

[0107] refer to Figure 2A , Figure 3A , Figure 3J , Figure 4A and Figure 4B In some embodiments, the first signal line layer SD1 includes a plurality of light emission control signal lines (e.g., corresponding light emission control signal lines em); a first voltage connection pad VCP1; a second voltage connection pad VCP2; a first data connection pad DCP1; a first node connection line Cln1; a third node connection line Cln3; a first relay electrode RE1; a first reset signal connection line Cli1; a second reset signal connection line Cli2; and a third reset signal connection line Cli3.

[0108] Various suitable conductive materials and various suitable manufacturing methods can be used to fabricate the first signal line layer SD1. For example, the conductive material can be deposited on a substrate and patterned by a plasma-enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for fabricating the first signal line layer include, but are not limited to, titanium, aluminum, copper, molybdenum, chromium, aluminum-copper alloys, copper-molybdenum alloys, molybdenum-aluminum alloys, aluminum-chromium alloys, copper-chromium alloys, molybdenum-chromium alloys, copper-molybdenum-aluminum alloys, etc. In some embodiments, the first signal line layer comprises multiple sublayers stacked together. In one example, the first signal line layer comprises a stacked titanium / aluminum / titanium multilayer structure. In another example, the first signal line layer comprises a stacked molybdenum / aluminum / molybdenum multilayer structure. Optionally, multiple light-emitting control signal lines (e.g., corresponding light-emitting control signal lines em); a first voltage connection pad VCP1; a second voltage connection pad VCP2; a first data connection pad DCP1; a first node connection line Cln1; a third node connection line Cln3; a first relay electrode RE1; a first reset signal connection line Cli1; a second reset signal connection line Cli2; and a third reset signal connection line Cli3 are located in the same layer.

[0109] In some embodiments, the first node connection line Cln1 connects multiple components of the pixel driving circuit to node N1. (See reference...) Figure 4A The first node connection line Cln1 is connected to the first capacitor electrode Ce1 through the first via v1, and to the second transistor T2 (e.g., connected to the first electrode S2 of the second transistor T2) through the second via v2. Optionally, the first node connection line Cln1 corresponds to Figure 2A The node N1 described in the text.

[0110] In some embodiments, the orthographic projection of the second electrode Dr3 of the third reset transistor Tr3 onto the substrate BS at least partially overlaps with the orthographic projection of the first voltage connection pad VCP1 onto the substrate BS. The inventors of this disclosure have found that this structure helps stabilize the voltage level at node N2 by keeping the voltage at the first voltage connection pad VCP1 constant.

[0111] refer to Figure 2A , Figure 3A , Figure 3E , Figure 3F , Figure 4A and Figure 4B In some embodiments, a portion of the second capacitor electrode Ce2 is absent from the via region H. Optionally, except for the portion of the via region H where the second capacitor electrode Ce2 is absent, the orthographic projection of the second capacitor electrode Ce2 onto the substrate BS substantially (e.g., at least 80%, at least 85%, at least 90%, at least 95%, at least 98%, at least 99%, or 100%) covers and is greater than the orthographic projection of the first capacitor electrode Ce1 onto the substrate BS. Optionally, the first via v1 extends through the passivation layer PVX, the second interlayer dielectric layer ILD2, the first interlayer dielectric layer ILD1, the via region H, and the insulating layer IN.

[0112] In some embodiments, the first node connection line Cln1 intersects with a corresponding second gate line among a plurality of second gate lines. For example... Figure 3A , Figure 3B and Figure 4A As shown, the first node connection line Cln1 intersects with the first branch GL2-1 of the corresponding second gate line in the second gate metal layer Gate2 and the second branch GL2-2 of the corresponding second gate line in the third gate metal layer Gate3.

[0113] In some embodiments, reference Figure 4B The third node connection line Cln3 is connected to the second electrode Dr2 of the second reset transistor Tr2 through the third via v3, to the second electrode D2 of the second transistor T2 through the fourth via v4, and to the second electrode Dd of the driving transistor Td and the first electrode S4 of the fourth transistor T4 through the fifth via v5. Optionally, the third node connection line Cln3 corresponds to Figure 2A Node N3 as described in [the document]. Optionally, the third node connection line Cln3 intersects with a corresponding second gate line among the plurality of second gate lines. [Example...] Figure 3A , Figure 3B and Figure 4B As shown, the third node connection line Cln3 intersects with the first branch GL2-1 of the corresponding second gate line in the second gate metal layer Gate2 and the second branch GL2-2 of the corresponding second gate line in the third gate metal layer Gate3.

[0114] In some embodiments, the orthographic projection of the third node connection line Cln3 on the substrate BS at least partially overlaps with the orthographic projection of the active layer ACT2 of the second transistor T2 on the substrate (e.g., at least 50%, at least 55%, at least 60%, at least 65%, at least 70%, at least 75%, at least 80%, at least 85%, at least 90%, at least 95%, at least 98%, or at least 99%). Optionally, the third node connection line Cln3 extends in a direction substantially parallel to the direction in which the active layer ACT2 of the second transistor T2 extends. Optionally, the orthographic projection of the third node connection line Cln3 on the substrate BS at least partially overlaps with the orthographic projection of the first electrode S2 of the second transistor T2 on the substrate. Optionally, the orthographic projection of the third node connection line Cln3 on the substrate BS at least partially overlaps with the orthographic projection of the second electrode D2 of the second transistor T2 on the substrate. As used herein, the term “substantially parallel” means an angle in the range of 0 to 45 degrees, such as 0 to 5 degrees, 0 to 10 degrees, 0 to 15 degrees, 0 to 20 degrees, 0 to 25 degrees, and 0 to 30 degrees.

[0115] In this array substrate, the second electrode D1 of the first transistor T1, the first electrode Sd of the driving transistor Td, the second electrode D3 of the third transistor T3, and the second electrode Dr3 of the third reset transistor Tr3 are located in the same layer, for example, in the first semiconductor material layer SML1. In some embodiments, the second electrode D1 of the first transistor T1, the first electrode Sd of the driving transistor Td, the second electrode D3 of the third transistor T3, and the second electrode Dr3 of the third reset transistor Tr3 are part of an integral structure. In some embodiments, the second electrode D1 of the first transistor T1, the first electrode Sd of the driving transistor Td, the second electrode D3 of the third transistor T3, and the second electrode Dr3 of the third reset transistor Tr3 are connected to each other in the first semiconductor material layer SML1. The second electrode D1 of the first transistor T1, the first electrode Sd of the driving transistor Td, the second electrode D3 of the third transistor T3, and the second electrode Dr3 of the third reset transistor Tr3 are connected to each other through one or more portions of the first semiconductor material layer SML1, for example, there are no connecting lines in layers other than the first semiconductor material layer SML1.

[0116] In some embodiments, a corresponding light emission control signal line em among a plurality of light emission control signal lines is connected to a first light emission control electrode pad emP1 and a second light emission control electrode pad emP2 in the first gate metal layer Gate1.

[0117] Figure 3K Show Figure 3A The vias extending through the first planarization layer in the array substrate shown.

[0118] refer to Figure 2A , Figure 3A , Figure 3B , Figure 3L , Figure 4A and Figure 4B In some embodiments, the second signal line layer SD2 includes a plurality of first voltage supply lines (e.g., corresponding first voltage supply lines Vddh), a plurality of first low voltage supply lines (e.g., corresponding first low voltage supply lines Vss1), a second relay electrode RE2, and a second data connection pad DCP2. Various suitable conductive materials and various suitable fabrication methods can be used to fabricate the second signal line layer SD2. For example, the conductive material can be deposited on a substrate and patterned using a plasma-enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for fabricating the second signal line layer SD2 include, but are not limited to, titanium, aluminum, copper, molybdenum, chromium, aluminum-copper alloys, copper-molybdenum alloys, molybdenum-aluminum alloys, aluminum-chromium alloys, copper-chromium alloys, molybdenum-chromium alloys, copper-molybdenum-aluminum alloys, etc. In one example, the second signal line layer includes a stacked titanium / aluminum / titanium multilayer structure. In another example, the second signal line layer includes a stacked molybdenum / aluminum / molybdenum multilayer structure. Optionally, the plurality of first voltage supply lines (e.g., corresponding first voltage supply lines Vddh), the second relay electrode RE2, and the second data connection pad DCP2 are located in the same layer.

[0119] Figure 3M Show Figure 3A The vias extending through the second planarization layer in the array substrate shown.

[0120] refer to Figure 2A , Figure 3A , Figure 3N , Figure 4A and Figure 4B In some embodiments, the third signal line layer SD3 includes a plurality of second voltage supply lines (e.g., corresponding second voltage supply lines Vddv), an anode contact pad ACP, a plurality of data lines (e.g., corresponding data lines DL), a plurality of fourth reset signal lines (e.g., corresponding fourth reset signal line Vint4), a plurality of fifth reset signal lines (e.g., corresponding fifth reset signal line Vint5), a plurality of sixth reset signal lines (e.g., corresponding sixth reset signal line Vint6), and a plurality of second low-voltage supply lines (e.g., corresponding second low-voltage supply line Vss2). In some embodiments, the corresponding first voltage supply line Vddh and the corresponding second voltage supply line Vddv are configured to provide a first reference voltage signal (e.g., a high reference voltage signal). Optionally, the corresponding low-voltage supply line VSS is configured to provide a second reference voltage signal (e.g., a low reference voltage signal). Optionally, the first reference voltage signal is a constant voltage signal, the second reference voltage signal is a constant voltage signal, and the voltage level of the first reference voltage signal is higher than the voltage level of the second reference voltage signal.

[0121] Various suitable conductive materials and various suitable fabrication methods can be used to fabricate the third signal line layer SD3. For example, the conductive material can be deposited on a substrate and patterned using a plasma-enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for fabricating the third signal line layer SD3 include, but are not limited to, titanium, aluminum, copper, molybdenum, chromium, aluminum-copper alloys, copper-molybdenum alloys, molybdenum-aluminum alloys, aluminum-chromium alloys, copper-chromium alloys, molybdenum-chromium alloys, copper-molybdenum-aluminum alloys, etc. In one example, the second signal line layer comprises a stacked titanium / aluminum / titanium multilayer structure. In another example, the second signal line layer comprises a stacked molybdenum / aluminum / molybdenum multilayer structure. Optionally, multiple second voltage supply lines (e.g., corresponding second voltage supply line Vddv), anode contact pad ACP, multiple data lines (e.g., corresponding data line DL), multiple fourth reset signal lines (e.g., corresponding fourth reset signal line Vint4), multiple fifth reset signal lines (e.g., corresponding fifth reset signal line Vint5), multiple sixth reset signal lines (e.g., corresponding sixth reset signal line Vint6), and multiple low-voltage supply lines (e.g., corresponding low-voltage supply line Vss) are located on the same layer.

[0122] Reference Figure 2A , Figure 3A , Figure 3O , Figure 4A and Figure 4B In some embodiments, the anode layer ADL includes multiple anodes AD.

[0123] refer to Figure 2A , Figure 3A , Figure 3B , Figure 3J , Figure 3L , Figure 3N , Figure 4A and Figure 4B In some embodiments, a plurality of first voltage supply lines and a plurality of second voltage supply lines are interconnected to form a voltage supply network. A corresponding first voltage supply line Vddh of the plurality of first voltage supply lines is connected to a first voltage connection pad VCP1, which is connected to a first electrode of a third transistor T3, thereby providing a voltage supply signal to the first electrode of the third transistor T3. Each first voltage supply line Vddh of the plurality of first voltage supply lines is connected to a second voltage connection pad VCP2, which is connected to a second capacitor electrode Ce2 of a storage capacitor Cst, thereby providing a voltage supply signal to the second capacitor electrode Ce2 of the storage capacitor Cst.

[0124] In some embodiments, a first reset signal connection line Cli1 connects a corresponding first reset signal line Vint1 among a plurality of first reset signal lines to a first electrode Sr1 of a first reset transistor Tr1. The first reset signal connection line Cli1 is configured to transmit a reset signal from the corresponding first reset signal line Vint1 to the first electrode Sr1 of the first reset transistor Tr1.

[0125] In some embodiments, the second reset signal connection line Cli2 connects a corresponding second reset signal line Vint2 among a plurality of second reset signal lines to the first electrode Sr2 of the second reset transistor Tr2. The second reset signal connection line Cli2 is configured to transmit a reset signal from the corresponding second reset signal line Vint2 to the first electrode Sr1 of the second reset transistor Tr2.

[0126] In some embodiments, the third reset signal connection line Cli3 connects a corresponding third reset signal line Vint3 among a plurality of third reset signal lines to the first electrode Sr3 of the third reset transistor Tr3. The third reset signal connection line Cli3 is configured to transmit a reset signal from the corresponding third reset signal line Vint3 to the first electrode Sr3 of the third reset transistor Tr3. In one example, the third reset signal connection line Cli3 is connected to the first electrode of the third reset transistor in two adjacent pixel driving circuits located in the same row, and is configured to transmit a reset signal from the corresponding third reset signal line Vint3 to the first electrode of the third reset transistor in two adjacent pixel driving circuits located in the same row.

[0127] In some embodiments, the first relay electrode RE1 is connected to the second electrode D4 of the fourth transistor T4 (and / or the second electrode Dr1 of the first reset transistor Tr1) and to the second relay electrode RE2. The second relay electrode is connected to the first relay electrode RE1 and to the anode contact pad ACP. In one example, the anode contact pad ACP is located on the third signal line layer SD3, the second relay electrode RE2 is located on the second signal line layer SD2, and the first relay electrode RE1 is located on the first signal line layer SD1. In another example, the anode contact pad ACP is connected to the second relay electrode RE2 through a via extending through the second planarization layer PLN2, the second relay electrode RE2 is connected to the first relay electrode RE1 through a via extending through the first planarization layer PLN1, and the first relay electrode RE1 is connected to the second electrode D4 of the fourth transistor T4 (and / or the second electrode Dr1 of the first reset transistor Tr1) through a via extending through the passivation layer PVX, the second interlayer dielectric layer ILD2, the first interlayer dielectric layer ILD1, the insulating layer IN, and the gate insulating layer GI.

[0128] In some embodiments, a first data connection pad DCP1 is connected to a first electrode S1 of a first transistor T1 and to a second data connection pad DCP2. The second data connection pad DCP2 is connected to the first data connection pad DCP1 and to a corresponding data line DL among a plurality of data lines. In one example, the first data connection pad DCP1 is located on a first signal line layer SD1, the second data connection pad DCP2 is located on a second signal line layer SD2, and the corresponding data line DL is located on a third signal line layer SD3. In another example, the corresponding data line DL is connected to the second data connection pad DCP2 via a via extending through a second planarization layer PLN2, the second data connection pad DCP2 is connected to the first data connection pad DCP1 via a via extending through a first planarization layer PLN1, and the first data connection pad DCP1 is connected to the first electrode S1 of the first transistor T1 via a via extending through a passivation layer PVX, a second interlayer dielectric layer ILD2, a first interlayer dielectric layer ILD1, an insulating layer IN, and a gate insulating layer GI.

[0129] In this array substrate, each light-emitting control signal line em is not located in the first gate metal layer, but in the first signal line layer. In this array substrate, refer to... Figure 3A , Figure 3B and Figure 3D The second electrode D1 of the first transistor T1, the first electrode Sd of the driving transistor Td, the second electrode D3 of the third transistor T3, and the second electrode Dr3 of the third reset transistor Tr3 are located in the same layer, for example, in the first semiconductor material layer SML1. In some embodiments, the second electrode D1 of the first transistor T1, the first electrode Sd of the driving transistor Td, the second electrode D3 of the third transistor T3, and the second electrode Dr3 of the third reset transistor Tr3 are part of an integral structure. In some embodiments, the second electrode D1 of the first transistor T1, the first electrode Sd of the driving transistor Td, the second electrode D3 of the third transistor T3, and the second electrode Dr3 of the third reset transistor Tr3 are connected to each other in the first semiconductor material layer SML1. The second electrode D1 of the first transistor T1, the first electrode Sd of the driving transistor Td, the second electrode D3 of the third transistor T3, and the second electrode Dr3 of the third reset transistor Tr3 are connected to each other through one or more portions of the first semiconductor material layer SML1, for example, there are no connecting lines in layers other than the first semiconductor material layer SML1.

[0130] The inventors of this disclosure have discovered that the unique and complex structure of this array substrate significantly reduces the parasitic capacitance between components, for example, located in the first signal line layer and components located in the first gate metal layer, thereby greatly improving the display quality.

[0131] In some embodiments, reference Figures 3A to 3NThe first pixel driving circuits that are directly adjacent to each other and in the current level (e.g., in the same row) Figure 3C The corresponding layer of PDC1 and the second pixel driving circuit (e.g., Figure 3C The corresponding layer of PDC2 in the array, for example, has a mirror symmetry with respect to each other with respect to a plane that is perpendicular to the main surface of the array substrate and substantially parallel to the multiple data lines (e.g., at least 80%, at least 85%, at least 90%, at least 95%, at least 98%, at least 99%, or completely symmetrical).

[0132] As used herein, the term "corresponding layer of the first pixel driving circuit and corresponding layer of the second pixel driving circuit" is not intended to include layers that are not part of the pixel driving circuit. For example, "corresponding layer of the first pixel driving circuit and corresponding layer of the second pixel driving circuit" does not include an anode layer or a pixel defining layer. In some embodiments, "corresponding layer of the first pixel driving circuit and corresponding layer of the second pixel driving circuit" does not include a third signal line layer. In some embodiments, "corresponding layer of the first pixel driving circuit and corresponding layer of the second pixel driving circuit" does not include a second signal line layer. In some embodiments, "corresponding layer of the first pixel driving circuit and corresponding layer of the second pixel driving circuit" does not include a first signal line layer. In some embodiments, "corresponding layer of the first pixel driving circuit and corresponding layer of the second pixel driving circuit" does not include a third gate metal layer. In some embodiments, "corresponding layer of the first pixel driving circuit and corresponding layer of the second pixel driving circuit" does not include a second gate metal layer.

[0133] In one example, "the corresponding layer of the first pixel driving circuit and the corresponding layer of the second pixel driving circuit" refers to at least one conductive layer of the first pixel driving circuit and at least one conductive layer of the second pixel driving circuit. In a specific example, "corresponding layer" includes at least one of a first semiconductor material layer, a first gate metal layer, a second gate metal layer, a second semiconductor material layer, a third gate metal layer, a first signal line layer, a second signal line layer, or a third signal line layer. In another specific example, "corresponding layer" further includes at least one of a gate insulating layer, an insulating layer, a first interlayer dielectric layer, a second interlayer dielectric layer, a passivation layer, a first planarization layer, or a second planarization layer. In another specific example, "the corresponding layer of the first pixel driving circuit and the corresponding layer of the second pixel driving circuit" includes a first semiconductor material layer. In another specific example, "the corresponding layer of the first pixel driving circuit and the corresponding layer of the second pixel driving circuit" includes a first gate metal layer. In another specific example, "the corresponding layer of the first pixel driving circuit and the corresponding layer of the second pixel driving circuit" includes a second semiconductor material layer.

[0134] In the relevant array substrate, multiple light-emitting control signal lines are typically located in a first gate metal layer, and each of the multiple light-emitting control signal lines typically includes the gates of a third transistor and a fourth transistor. The relevant array substrate typically includes voltage connection lines that intersect with the respective light-emitting control signal lines. The voltage connection lines are connected to one or more voltage supply lines and to the first electrode of the third transistor. The inventors of this disclosure have discovered that in the relevant array substrate, there is a relatively large parasitic capacitance between the voltage connection lines (e.g., located in the first signal line layer) and the respective light-emitting control signal lines located in the first gate metal layer, which adversely affects display quality.

[0135] In this array substrate, each light-emitting control signal line em is not located in the first gate metal layer, but in the first signal line layer. The first light-emitting control electrode pad emP1 and the second light-emitting control electrode pad emP2 are connected to the corresponding light-emitting control signal line em among the plurality of light-emitting control signal lines. Optionally, the first light-emitting control electrode pad emP1 and the second light-emitting control electrode pad emP2 are located in the first gate metal layer. Optionally, the corresponding light-emitting control signal line em is located in the first signal line layer. The inventors of this disclosure have discovered that this unique and complex structure significantly reduces the parasitic capacitance between the first gate metal layer and the first signal line layer, thereby significantly improving display quality.

[0136] Figure 5 A voltage supply path in an array substrate according to some embodiments of the present disclosure is shown. (Refer to...) Figure 5 , Figure 3D , Figure 3J and Figure 3L In some embodiments, the array substrate includes a third transistor configured to receive a voltage supply signal; a first voltage connection pad VCP1; and a corresponding first voltage supply line Vddh among a plurality of first voltage supply lines; wherein the active layer of the third transistor, the first voltage connection pad VCP1, and the corresponding first voltage supply line Vddh are located on three different layers. Optionally, the active layer of the third transistor is located on a first semiconductor material layer; the first voltage connection pad VCP1 is located on a first signal line layer, and the corresponding first voltage supply line Vddh is located on a second signal line layer. In some embodiments, the corresponding first voltage supply line Vddh is connected to the first voltage connection pad VCP1, and the first voltage connection pad VCP1 is connected to the first electrode S3 of the third transistor.

[0137] In some embodiments, refer to Figure 5 , Figure 3D , Figure 3J and Figure 3LThe array substrate also includes a corresponding light emission control signal line em configured to provide a light emission control signal to the gate of the third transistor. In some embodiments, the corresponding light emission control signal line em and the first voltage connection pad VCP1 are located on the same layer.

[0138] In some embodiments, the first voltage connection pad VCP1 is connected to the first electrode of the third transistor in two adjacent pixel driving circuits located in the same row. Figure 5 The Chinese characters are labeled as S3 and S3').

[0139] Figure 6 This is a schematic diagram illustrating the structure of a corresponding first voltage supply line in an array substrate according to some embodiments of the present disclosure. Reference Figure 6 In some embodiments, the corresponding first voltage supply line Vddh includes a body MB and a plurality of extensions ET extending in a direction away from the body MB. Optionally, the plurality of extensions ET extend in the same direction away from the body MB. In some embodiments, a corresponding extension ET of the plurality of extensions ET is connected to a first voltage connection pad VCP1, and the first voltage connection pad VCP1 is connected to the first electrode S3 of the third transistor. Optionally, two adjacent extensions ET of the plurality of extensions ET are connected to the first voltage connection pad VCP1, and the first voltage connection pad VCP1 is connected to the first electrode of the third transistor in two adjacent pixel driving circuits located in the same row. Figure 5 The Chinese inscription is indicated as S3 and S3'.

[0140] Figure 7 It is shown Figure 3A A schematic diagram of the structure of the second semiconductor material layer and the corresponding first voltage supply line in the array substrate shown. (Refer to...) Figure 7 In some embodiments, the orthographic projection of the body MB onto the substrate substantially covers (e.g., covers at least 80%, at least 85%, at least 90%, at least 95%, at least 99%, or completely covers) the orthographic projection of the active layer ACT2 of the second transistor T2 onto the substrate. Optionally, the orthographic projection of the body MB onto the substrate substantially covers (e.g., covers at least 80%, at least 85%, at least 90%, at least 95%, at least 99%, or completely covers) the orthographic projections of the first electrode S2, the active layer ACT2, and the second electrode D2 of the second transistor T2 onto the substrate. The inventors of this disclosure have found that the unique and complex structure of this array substrate contributes to enhanced stability of the second transistor T2.

[0141] Figure 8A This is a schematic diagram illustrating the structure of a pixel driving circuit in an array substrate according to some embodiments of the present disclosure. Figure 8BThis is a schematic diagram showing the arrangement of pixel driving circuits in the array substrate shown in Figure 8A. Figure 8C It is shown Figure 8A A schematic diagram of the structure of the first semiconductor material layer in the array substrate shown. Figure 8D It is shown Figure 8A The diagram shows a schematic of the structure of the first gate metal layer in the array substrate. Figure 8E It is shown Figure 8A A schematic diagram of the structure of the second gate metal layer in the array substrate shown. Figure 8F It is shown Figure 8A A schematic diagram of the structure of the second semiconductor material layer in the array substrate shown. Figure 8G It is shown Figure 8A The diagram shows a schematic of the structure of the third gate metal layer in the array substrate. Figure 8H It is shown Figure 8A A schematic diagram of the structure of the passivation layer in the array substrate shown. Figure 8I It is shown Figure 8A The diagram shows a schematic of the structure of the first signal line layer in the array substrate. Figure 8J It is shown Figure 8A A schematic diagram of the structure of the first planarization layer in the array substrate shown. Figure 8K It is shown Figure 8A A schematic diagram of the structure of the second signal line layer in the array substrate shown. Figure 8L It is shown Figure 8A A schematic diagram of the structure of the second planarization layer in the array substrate shown. Figure 8M It is shown Figure 8A The diagram shows a schematic of the structure of the third signal line layer in the array substrate. Figure 8N It is shown Figure 8A A schematic diagram of the structure of the anode layer in the array substrate shown. Figures 8A to 8N A portion of an array substrate is shown, comprising twelve adjacent pixel driving circuits (including PDC1, PDC2, PDC3, PDC4, PDC5, PDC6, PDC7, PDC8, PDC9, PDC10, PDC11, and PDC12). Figure 8B The PDC1 and PDC2 depicted in the text correspond to Figure 3C PDC1 and PDC2 are depicted in the text.

[0142] Reference Figures 8A to 8NIn some embodiments, the array substrate includes pixel driving circuits arranged in J columns, where J is a positive integer. The array substrate includes a plurality of fourth reset signal lines (e.g., a corresponding fourth reset signal line Vint4), a plurality of fifth reset signal lines (e.g., a corresponding fifth reset signal line Vint5), a plurality of sixth reset signal lines (e.g., a corresponding sixth reset signal line Vint6), and a plurality of second low-voltage supply lines (e.g., a corresponding second low-voltage supply line Vss2). In some embodiments, the J columns include the (8j-7)th column C(8j-7), the (8j-6)th column C(8j-6), the (8j-5)th column C(8j-5), the (8j-4)th column C(8j-4), the (8j-3)th column C(8j-3), the (8j-2)th column C(8j-2), the (8j-1)th column C(8j-1), and the (8j)th column C(8j) of the J columns, where J and j are positive integers, and 1≤j≤J / 8.

[0143] In some embodiments, one of the corresponding fourth reset signal line Vint4, the corresponding fifth reset signal line Vint5, the corresponding sixth reset signal line Vint6, and the corresponding second low-voltage supply line Vss2 is located between column (8j-7) C(8j-7) and column (8j-6) C(8j-6) in the J columns; the other of the corresponding fourth reset signal line Vint4, the corresponding fifth reset signal line Vint5, the corresponding sixth reset signal line Vint6, and the corresponding second low-voltage supply line Vss2 is located between column (8j-5) C(8j-5) and column (8j-4) C(8j-6) in the J columns. 4) Between; the other of the corresponding fourth reset signal line Vint4, the corresponding fifth reset signal line Vint5, the corresponding sixth reset signal line Vint6 and the corresponding second low voltage supply line Vss2 is located between column (8j-3) C(8j-3) and column (8j-2) C(8j-2) in the J columns; and the other of the corresponding fourth reset signal line Vint4, the corresponding fifth reset signal line Vint5, the corresponding sixth reset signal line Vint6 and the corresponding second low voltage supply line Vss2 is located between column (8j-1) C(8j-1) and column (8j) C(8j) in the J columns.

[0144] In such Figures 8A to 8NIn one example shown, the corresponding sixth reset signal line Vint6 is located between column (8j-7) C(8j-7) and column (8j-6) C(8j-6) in the J columns; the corresponding fourth reset signal line Vint4 is located between column (8j-5) C(8j-5) and column (8j-4) C(8j-4) in the J columns; the corresponding second low-voltage supply line Vss2 is located between column (8j-3) C(8j-3) and column (8j-2) C(8j-2) in the J columns; and the corresponding fifth reset signal line Vint5 is located between column (8j-1) C(8j-1) and column (8j) C(8j) in the J columns. The corresponding sixth reset signal line Vint6, the corresponding fourth reset signal line Vint4, the corresponding second low-voltage supply line Vss2, and the corresponding fifth reset signal line Vint5 are arranged sequentially.

[0145] As used herein, the terms "column (8j-7)," "column (8j-6)," "column (8j-5)," "column (8j-4)," "column (8j-3)," "column (8j-2)," "column (8j-1)," and "column (8j)" are used in the context of the J columns. The array substrate may or may not include additional columns preceding the first column of the J columns and / or additional columns following the last column of the J columns. In the context of the array substrate, the terms "column (8j-7)," "column (8j-5)," "column (8j-3)," and "column (8j-1)" do not necessarily represent odd-numbered columns, and the terms "column (8j-6)," "column (8j-4)," "column (8j-2)," and "column (8j)" do not necessarily represent even-numbered columns. In one example, column (8j-7) is an odd-numbered column in the context of the J columns, but may be an even-numbered column in the context of the array substrate. In another example, column (8j-7) is an odd-numbered column in the context of column J, and also an odd-numbered column in the context of the array substrate. In one example, column (8j-6) is an even-numbered column in the context of column J, but can be an odd-numbered column in the context of the array substrate. In another example, column (8j-6) is an even-numbered column in the context of column J, and also an even-numbered column in the context of the array substrate. In one example, column (8j-5) is an odd-numbered column in the context of column J, but can be an even-numbered column in the context of the array substrate. In another example, column (8j-5) is an odd-numbered column in the context of column J, and also an odd-numbered column in the context of the array substrate. In one example, column (8j-4) is an even-numbered column in the context of column J, but can be an odd-numbered column in the context of the array substrate. In another example, column (8j-4) is an even-numbered column in the context of column J, and also an even-numbered column in the context of the array substrate. In one example, column (8j-3) is an odd-numbered column in the context of column J, but can be an even-numbered column in the context of the array substrate. In another example, column (8j-3) is an odd-numbered column in the context of column J, and is also an odd-numbered column in the context of the array substrate. In one example, column (8j-2) is an even-numbered column in the context of column J, but can be an odd-numbered column in the context of the array substrate. In another example, column (8j-2) is an even-numbered column in the context of column J, and is also an even-numbered column in the context of the array substrate. In one example, column (8j-1) is an odd-numbered column in the context of column J, but can be an even-numbered column in the context of the array substrate. In another example, column (8j-1) is an odd-numbered column in the context of column J, and is also an odd-numbered column in the context of the array substrate. In one example, column (8j) is an even-numbered column in the context of column J, but can be an odd-numbered column in the context of the array substrate. In another example, column (8j) is an even column in the context of column J, and also an even column in the context of the array substrate.

[0146] See Figure 8N In some embodiments, the anode layer includes a first corresponding anode RAD1, a second corresponding anode RAD2, a third corresponding anode RAD3, and a fourth corresponding anode RAD4. In one example, the first corresponding anode RAD1 is the anode for a sub-pixel of a first color (e.g., a red sub-pixel), the second corresponding anode RAD2 is the anode for a sub-pixel of a second color (e.g., a blue sub-pixel), and the third corresponding anode RAD3 and the fourth corresponding anode RAD4 are the anodes for two sub-pixels of a third color (e.g., two green sub-pixels). In some embodiments, the array of multiple sub-pixels in the array substrate includes a repeating array in the form of RGBG, where R represents a red sub-pixel, B represents a blue sub-pixel, and G represents a green sub-pixel.

[0147] In some embodiments, the first corresponding anode RAD1 includes a first main anode portion MAP1 and a first extension E1 extending in a direction away from the first main anode portion MAP1. The first extension E1 connects the first main anode portion MAP1 to the first corresponding anode connecting pad. In some embodiments, the second corresponding anode RAD2 includes a second main anode portion MAP2 and a second extension E2 extending in a direction away from the second main anode portion MAP2. The second extension E2 connects the second main anode portion MAP2 to the second corresponding anode connecting pad. In some embodiments, the third corresponding anode RAD3 includes a third main anode portion MAP3 and a third extension E3 extending in a direction away from the third main anode portion MAP3. The third extension E3 connects the third main anode portion MAP3 to the third corresponding anode connecting pad. In some embodiments, the fourth corresponding anode RAD4 includes a fourth main anode portion MAP4 and a fourth extension E4 extending in a direction away from the fourth main anode portion MAP4. The fourth extension E4 connects the fourth main anode portion MAP4 to the fourth corresponding anode connecting pad. Optionally, the first extension E1 extends in a direction away from the first main anode portion MAP1 along a direction substantially parallel to the first direction DR1. Optionally, the second extension E2 extends in a direction substantially parallel to the first direction DR1, moving away from the second main anode portion MAP2. Optionally, the third extension E3 extends in a direction substantially parallel to the second direction DR2, moving away from the third main anode portion MAP3. Optionally, the fourth extension E4 extends in a direction substantially parallel to the second direction DR2, moving away from the fourth main anode portion MAP4.

[0148] Figure 8O It is shown Figure 8A A schematic diagram of the structure of the third signal line layer and the anode layer in the array substrate shown. In some embodiments, refer to... Figure 8M , Figure 8N and Figure 8O The orthographic projection of the first main anode portion MAP1 on the substrate at least partially overlaps with the orthographic projections of two adjacent data lines among the plurality of data lines on the substrate. Optionally, the orthographic projection of the first main anode portion MAP1 on the substrate at least partially overlaps with the orthographic projections of two adjacent second voltage supply lines among the plurality of second voltage supply lines on the substrate. In some embodiments, the orthographic projection of the second main anode portion MAP2 on the substrate at least partially overlaps with the orthographic projections of two adjacent data lines among the plurality of data lines on the substrate. Optionally, the orthographic projection of the second main anode portion MAP2 on the substrate at least partially overlaps with the orthographic projections of two adjacent second voltage supply lines among the plurality of second voltage supply lines on the substrate. Optionally, the two adjacent data lines are configured to provide data signals to the pixel driving circuits in the (8j-k1)th column and the (8j-(k1+1))th column, where J is a positive integer, 1 ≤ j ≤ (J / 8), and k1 is a positive integer and 1 ≤ k1 < j. Optionally, two adjacent second voltage supply lines are configured to provide voltage supply signals to the pixel driving circuits in columns (8j-k1) and (8j-(k1+1)), where J is a positive integer, 1 ≤ j ≤ (J / 8), and k1 is an odd positive integer, 1 ≤ k1 < j. Examples of columns (8j-k1) and (8j-(k1+1)) include columns (8j-1) C(8j-1) and (8j-2) C(8j-2), columns (8j-3) C(8j-3) and (8j-4) C(8j-4), columns (8j-5) C(8j-5) and (8j-6) C(8j-6).

[0149] In some embodiments, the orthographic projection of the first main anode portion MAP1 on the substrate does not overlap with the orthographic projections of the plurality of fourth reset signal lines, the plurality of fifth reset signal lines, the plurality of sixth reset signal lines, or the plurality of second low-voltage supply lines on the substrate. In some embodiments, the orthographic projection of the second main anode portion MAP2 on the substrate does not overlap with the orthographic projections of the plurality of fourth reset signal lines, the plurality of fifth reset signal lines, the plurality of sixth reset signal lines, or the plurality of second low-voltage supply lines on the substrate.

[0150] In some embodiments, the orthographic projection of the third main anode portion MAP3 on the substrate at least partially overlaps with the orthographic projections of two adjacent second voltage supply lines among the plurality of second voltage supply lines on the substrate, and at least partially overlaps with the orthographic projection of one of the corresponding fourth reset signal line Vint4, the corresponding fifth reset signal line Vint5, the corresponding sixth reset signal line Vint6, and the corresponding second low-voltage supply line Vss2 on the substrate. In some embodiments, the orthographic projection of the fourth main anode portion MAP4 on the substrate at least partially overlaps with the orthographic projections of two adjacent second voltage supply lines among the plurality of second voltage supply lines on the substrate, and at least partially overlaps with the orthographic projection of one of the corresponding fourth reset signal line Vint4, the corresponding fifth reset signal line Vint5, the corresponding sixth reset signal line Vint6, and the corresponding second low-voltage supply line Vss2 on the substrate. Optionally, two adjacent second voltage supply lines are configured to provide voltage supply signals to the pixel driving circuits in columns (8j-k2) and (8j-(k2+1)), where J is a positive integer, 1≤j≤(J / 8), k2 is zero or an even positive integer, and 0≤k2<j. Examples of columns (8j-k2) and (8j-(k2+1)) include columns (8j) C(8j) and (8j-1) C(8j-1), columns (8j-2) C(8j-2) and (8j-3) C(8j-3), columns (8j-4) C(8j-4) and (8j-5) C(8j-5), columns (8j-6) C(8j-6) and (8j-7) C(8j-7).

[0151] Figure 8P It is shown Figure 8A A schematic diagram of the structure of the first semiconductor material layer and the anode layer in the array substrate shown. (Refer to...) Figure 8C , Figure 8N , Figure 8P , Figure 3D and Figure 3O The orthographic projection of the first main anode portion MAP1 on the substrate at least partially overlaps with the orthographic projection of the active layer of the third reset transistor in the two adjacent pixel driving circuits. Optionally, the two adjacent pixel driving circuits include columns (8j-k1) and (8j-(k1+1)), where J is a positive integer, 1≤j≤(J / 8), and k1 is a positive integer, 1≤k1<j. Examples of columns (8j-k1) and (8j-(k1+1)) include columns (8j-1) C(8j-1) and (8j-2) C(8j-2), columns (8j-3) C(8j-3) and (8j-4) C(8j-4), columns (8j-5) C(8j-5) and (8j-6) C(8j-6).

[0152] In some embodiments, the orthographic projection of at least one of the first corresponding anode RAD1, the second corresponding anode RAD2, the third corresponding anode RAD3, or the fourth corresponding anode RAD4 onto the substrate at least partially overlaps with the orthographic projection of the second electrode Dr3 of the third reset transistor Tr3 onto the substrate.

[0153] Figure 9A A first interconnect reset signal network is shown according to some embodiments of the present disclosure. Reference Figure 9A In some embodiments, the array substrate includes a first interconnect reset signal network configured to provide a first reset signal to a plurality of pixel driving circuits. For example, the first interconnect reset signal network is configured to provide a first reset signal to a first electrode of a first reset transistor in a plurality of pixel driving circuits. In some embodiments, the first interconnect reset signal network includes a plurality of first reset signal lines extending substantially parallel to a first direction DR1; and a plurality of fourth reset signal lines extending substantially parallel to a second direction DR2; wherein the plurality of first reset signal lines intersect the plurality of fourth reset signal lines. As used herein, the term “substantially parallel” means an angle in the range of 0 degrees to 45 degrees, for example, 0 degrees to 5 degrees, 0 degrees to 10 degrees, 0 degrees to 15 degrees, 0 degrees to 20 degrees, 0 degrees to 25 degrees, and 0 degrees to 30 degrees.

[0154] Optionally, each of the plurality of first reset signal lines Vint1 is connected to at least one of the plurality of fourth reset signal lines; and each of the plurality of fourth reset signal lines Vint4 is connected to at least one of the plurality of first reset signal lines.

[0155] In some embodiments, each first reset signal line Vint1 includes a plurality of alternating first portions P1 and a plurality of second portions P2. Two adjacent second portions of the plurality of second portions P2 are connected via first portions of the plurality of first portions P1. Two adjacent first portions of the plurality of first portions P1 are connected via second portions of the plurality of second portions P2. A corresponding second portion of the plurality of second portions P2 is connected to a corresponding fourth reset signal line Vint4.

[0156] In some embodiments, the plurality of first portions P1, the plurality of second portions P2, and each fourth reset signal line Vint4 are located on three different layers. In a particular example, the plurality of first portions P1 are located on a third gate metal layer, the plurality of second portions P2 are located on a first signal line layer, and each fourth reset signal line Vint4 is located on a third signal line layer. The inventors of this disclosure have discovered that the unique and complex structure of the first interconnect reset signal network optimizes the layout of signal lines in the array substrate.

[0157] Figure 9B A first interconnect reset signal network is shown according to some embodiments of the present disclosure. See also Figure 9B The corresponding first reset signal line Vint1 includes a first main line portion MLP1 and multiple second portions P2. The first main line portion MLP1 is a continuous line portion connected to the multiple second portions P2. The corresponding second portion of the multiple second portions P2 is connected to the corresponding fourth reset signal line Vint4.

[0158] Figure 10A A second interconnect reset signal network is shown according to some embodiments of the present disclosure. Reference Figure 10A In some embodiments, the array substrate includes a second interconnect reset signal network configured to provide a second reset signal to a plurality of pixel driving circuits. For example, the second interconnect reset signal network is configured to provide a second reset signal to a first electrode of a second reset transistor in a plurality of pixel driving circuits. In some embodiments, the second interconnect reset signal network includes a plurality of second reset signal lines extending substantially parallel to a first direction DR1; and a plurality of fifth reset signal lines extending substantially parallel to a second direction DR2; wherein the plurality of second reset signal lines intersect the plurality of fifth reset signal lines.

[0159] Optionally, each of the plurality of second reset signal lines Vint2 is connected to at least one of the plurality of fifth reset signal lines; and each of the plurality of fifth reset signal lines Vint5 is connected to at least one of the plurality of second reset signal lines.

[0160] In some embodiments, each second reset signal line Vint2 includes a plurality of alternately arranged third portions P3 and a plurality of fourth portions P4. Two adjacent fourth portions of the plurality of fourth portions P4 are connected by third portions of the plurality of third portions P3. Two adjacent third portions of the plurality of third portions P3 are connected by fourth portions of the plurality of fourth portions P4. A corresponding fourth portion of the plurality of fourth portions P4 is connected to a corresponding fifth reset signal line Vint5.

[0161] In some embodiments, the plurality of third portions P3, the plurality of fourth portions P4, and each fifth reset signal line Vint5 are located on three different layers. In a particular example, the plurality of third portions P3 are located on a second gate metal layer, the plurality of fourth portions P4 are located on a first signal line layer, and each fifth reset signal line Vint5 is located on a third signal line layer. The inventors of this disclosure have discovered that the unique and complex structure of the second interconnect reset signal network optimizes the layout of signal lines in the array substrate.

[0162] Figure 10BA second interconnect reset signal network is shown according to some embodiments of this disclosure. See also Figure 10B The corresponding second reset signal line Vint2 includes a second main line portion MLP2 and multiple fourth portions P4. The second main line portion MLP2 is a continuous line portion connected to the multiple fourth portions P4. The corresponding fourth portion of the multiple fourth portions P4 is connected to the corresponding fifth reset signal line Vint5.

[0163] Figure 11 A third interconnect reset signal network according to some embodiments of the present disclosure is shown. (Refer to...) Figure 11 In some embodiments, the array substrate includes a third interconnect reset signal network configured to provide a third reset signal to a plurality of pixel driving circuits. For example, the third interconnect reset signal network is configured to provide a third reset signal to a first electrode of a third reset transistor in a plurality of pixel driving circuits. In some embodiments, the third interconnect reset signal network includes a plurality of third reset signal lines extending substantially parallel to a first direction DR1; and a plurality of sixth reset signal lines extending substantially parallel to a second direction DR2; wherein the plurality of third reset signal lines intersect the plurality of sixth reset signal lines.

[0164] Optionally, each of the plurality of third reset signal lines Vint3 is connected to at least one of the plurality of sixth reset signal lines; and each of the plurality of sixth reset signal lines Vint6 is connected to at least one of the plurality of third reset signal lines.

[0165] In some embodiments, the array substrate further includes a plurality of reset connection pads (RCPs). Each reset connection pad (RCP) is connected to a separate third reset signal line among a plurality of third reset signal lines, and to a separate sixth reset signal line among a plurality of sixth reset signal lines.

[0166] In some embodiments, the third reset signal lines Vint3, the sixth reset signal lines Vint6, and the reset pads RCP are located on three different layers. In a particular example, the third reset signal lines Vint3 are located on the third gate metal layer, the reset pads RCP are located on the first signal line layer, and the sixth reset signal lines Vint6 are located on the third signal line layer.

[0167] Figure 12 An interconnected low-voltage supply network according to some embodiments of the present disclosure is shown. (Refer to...) Figure 12In some embodiments, the array substrate includes an interconnect low-voltage supply network configured to provide low-voltage supply signals to a plurality of pixel driving circuits. For example, the interconnect low-voltage supply network is configured to provide low-voltage supply signals to the cathodes of the plurality of pixel driving circuits. In some embodiments, the interconnect low-voltage supply network includes a plurality of first low-voltage supply lines extending substantially parallel to a first direction DR1; and a plurality of second low-voltage supply lines extending substantially parallel to a second direction DR2; wherein the plurality of first low-voltage supply lines intersect the plurality of second low-voltage supply lines.

[0168] Optionally, each of the plurality of first low-voltage supply lines Vss1 is connected to at least one of the plurality of second low-voltage supply lines; and each of the plurality of second low-voltage supply lines Vss2 is connected to at least one of the plurality of first low-voltage supply lines.

[0169] In some embodiments, each of the first low-voltage supply lines Vss1 and each of the second low-voltage supply lines Vss2 are located on two different layers. In a particular example, each of the first low-voltage supply lines Vss1 is located on a second signal line layer, and each of the second low-voltage supply lines Vss2 is located on a third signal line layer.

[0170] In the relevant array substrate, the reset signal line along the second direction is typically located in the first signal line layer, close to the first gate metal layer. The proximity of the reset signal line along the second direction to the gate line located in the first gate metal layer results in relatively large parasitic capacitance, which in turn increases the load in the gate line. This increased load in the gate line requires an increased drive load on the gate scan circuitry (e.g., gate-on-array circuitry). The inventors of this disclosure have discovered that by providing the reset signal line along the second direction in a third signal line layer spaced several layers apart from the first gate metal layer, the drive load requirement on the gate scan circuitry can be reduced.

[0171] In some embodiments, the array substrate includes a plurality of first gate lines configured to provide gate scan signals to the gates of first transistors in a plurality of pixel driving circuits; a plurality of first voltage supply lines located on the side of the plurality of first gate lines away from the substrate, the plurality of first voltage supply lines being configured to provide voltage supply signals to the first electrodes of third and fourth transistors in the plurality of pixel driving circuits; and a plurality of fourth reset signal lines, a plurality of fifth reset signal lines, or a plurality of sixth reset signal lines located on the side of the plurality of first voltage supply lines away from the plurality of first gate lines. The plurality of fourth reset signal lines, the plurality of fifth reset signal lines, or the plurality of sixth reset signal lines extend along a second direction.

[0172] In the relevant array substrate, reset signal lines (e.g., multiple fourth reset signal lines, multiple fifth reset signal lines, or multiple sixth reset signal lines) are arranged alternately along a second direction, and the reset signal lines along the second direction are typically located on the side of the multiple first voltage supply lines close to the multiple first gate lines, for example, typically located in the first signal line layer. The arrangement of the reset signal lines along the second direction in the relevant array substrate results in different capacitances of nodes (e.g., node N1, node N2, or node N3) in pixel driving circuits of different columns, leading to display non-uniformity in the array substrate. The inventors of this disclosure have discovered that by spacing the multiple first voltage supply lines along the second direction from the multiple first gate lines, the multiple first voltage supply lines shield the nodes and reset signal lines along the second direction, thereby significantly improving display uniformity.

[0173] In the relevant array substrate, multiple light-emitting control signal lines are typically located in the first gate metal layer, and each of the multiple light-emitting control signal lines typically includes the gates of a third transistor and a fourth transistor. The relevant array substrate typically includes second node interconnects (e.g., located in the first signal line layer) that connect the second electrode D3 of the third transistor T3 to the second electrode Dr3 of the third reset transistor Tr3. The inventors of this disclosure have found that the presence of the second node interconnects in the relevant array substrate results in a relatively large parasitic capacitance between the second node interconnects located in the first signal line layer and the respective light-emitting control signal lines located in the first gate metal layer, thereby adversely affecting display quality. Furthermore, the relevant array substrate requires a relatively large number of vias to connect the second node interconnects located in the first signal line layer and the components located in the first semiconductor material layer, affecting the layout of the signal lines in the relevant array substrate.

[0174] Figure 13 It is shown Figure 3A A schematic diagram of the structure of the first semiconductor material layer in the array substrate shown. (Reference) Figure 13 In some embodiments, each pixel driving circuit in the plurality of pixel driving circuits includes a second node connection line Cln2, which is connected to the second electrode D3 of the first light-emitting control transistor T3 and to the second electrode Dr3 of the third reset transistor Tr3. In this array substrate, the second node connection line Cln2 is located on the same layer as the active layer of the first light-emitting control transistor T3 and the third reset transistor Tr3.

[0175] In some embodiments, reference Figure 4A and Figure 13The plurality of light-emitting control signal lines em are spaced apart from the second node connection line Cln2 by at least three insulating layers, such as three, four, or five insulating layers. In some embodiments, the plurality of light-emitting control signal lines em are spaced apart from the second node connection line Cln2 by at least three of the following: gate insulating layer GI, insulating layer IN, first interlayer dielectric layer ILD1, second interlayer dielectric layer ILD2, or passivation layer PVX. In one example, the plurality of light-emitting control signal lines em are spaced apart from the second node connection line Cln2 by gate insulating layer GI, insulating layer IN, first interlayer dielectric layer ILD1, second interlayer dielectric layer ILD2, and passivation layer PVX.

[0176] The inventors of this disclosure have discovered that by spacing the plurality of light-emitting control signal lines em and the second node connection line Cln2 apart by at least three insulating layers, the parasitic capacitance between the second node connection line Cln2 and the plurality of light-emitting control signal lines em can be significantly reduced, thereby achieving improved display quality.

[0177] In some embodiments, reference Figure 4A Multiple light-emitting control signal lines em and the first node connection line Cln1 are located on the same layer. See also the following in some embodiments: Figure 4A and Figure 13 The first node connection line Cln1 and the second node connection line Cln2 are spaced apart by at least three insulating layers, such as three, four, or five insulating layers. In some embodiments, the first node connection line Cln1 and the second node connection line Cln2 are spaced apart by at least three of the following: gate insulating layer GI, insulating layer IN, first interlayer dielectric layer ILD1, second interlayer dielectric layer ILD2, or passivation layer PVX. In one example, the first node connection line Cln1 and the second node connection line Cln2 are spaced apart by the following: gate insulating layer GI, insulating layer IN, first interlayer dielectric layer ILD1, second interlayer dielectric layer ILD2, and passivation layer PVX.

[0178] In another aspect, the present invention provides a display device comprising an array substrate manufactured as described herein or by means of the methods described herein, and one or more integrated circuits connected to the array substrate. Examples of suitable display devices include, but are not limited to, electronic paper, mobile phones, tablet computers, televisions, monitors, laptop computers, digital photo albums, GPS, etc. Optionally, the display device is an organic light-emitting diode (OLED) display device. Optionally, the display device is a miniature OLED display device. Optionally, the display device is a miniature OLED display device.

[0179] In another aspect, this disclosure provides a method for manufacturing an array substrate. In some embodiments, the method includes forming a plurality of pixel driving circuits. Optionally, forming each pixel driving circuit in the plurality of pixel driving circuits includes forming a driving transistor, forming a data writing transistor, forming a first light-emitting control transistor, and forming a third reset transistor. Optionally, the active layers of the driving transistor, data writing transistor, first light-emitting control transistor, and third reset transistor are formed in a first semiconductor material layer. Optionally, the second electrode of the data writing transistor, the first electrode of the driving transistor, the second electrode of the first light-emitting control transistor, and the second electrode of the third reset transistor are formed in the first semiconductor material layer. Optionally, the second electrode of the data writing transistor, the first electrode of the driving transistor, the second electrode of the first light-emitting control transistor, and the second electrode of the third reset transistor are formed as part of an integral structure. Optionally, the second electrode of the data writing transistor, the first electrode of the driving transistor, the second electrode of the first light-emitting control transistor, and the second electrode of the third reset transistor are connected to each other through one or more portions of the first semiconductor material layer.

[0180] For illustrative and descriptive purposes, the foregoing description of embodiments of the invention has been provided. It is not exhaustive, nor is it intended to limit the invention to the precise forms or exemplary embodiments disclosed. Therefore, the foregoing description should be considered illustrative rather than restrictive. Clearly, many modifications and variations will be apparent to those skilled in the art. The embodiments were chosen and described to explain the principles of the invention and its best mode of practical application, thereby enabling those skilled in the art to understand the various embodiments of the invention and the various modifications suitable for the particular use or implementation contemplated. The scope of the invention is intended to be defined by the appended claims and their equivalents, wherein, unless otherwise stated, all terms are to be interpreted in their broadest reasonable sense. Therefore, the terms “the invention,” “the present invention,” etc., do not necessarily limit the scope of the claims to the specific embodiments, and references to exemplary embodiments of the invention do not imply limitation of the invention, nor should such limitation be inferred. The invention is defined only by the spirit and scope of the appended claims. Furthermore, these claims may involve the use of “first,” “second,” etc., followed by nouns or elements. These terms should be understood as nomenclature and should not be construed as limiting the number of elements modified by these nomenclatures unless a specific number has been given. Any advantages and benefits described may not apply to all embodiments of the invention. It should be understood that changes to the described embodiments can be made by those skilled in the art without departing from the scope of the invention as defined by the appended claims. Furthermore, the elements and components in this disclosure are not intended for public distribution, whether or not they are expressly recited in the appended claims.

Claims

1. An array substrate comprising multiple pixel driving circuits; in, Each pixel driving circuit in the plurality of pixel driving circuits includes a driving transistor, a first light-emitting control transistor, and a third reset transistor; the active layers of the driving transistor, the first light-emitting control transistor, and the third reset transistor are located in the first semiconductor material layer; The first electrode of the driving transistor, the second electrode of the first light-emitting control transistor, and the second electrode of the third reset transistor are located in the first semiconductor material layer; the first electrode of the driving transistor, the second electrode of the first light-emitting control transistor, and the second electrode of the third reset transistor are part of the overall structure; The first electrode of the driving transistor, the second electrode of the first light-emitting control transistor, and the second electrode of the third reset transistor are connected to each other through one or more portions of the first semiconductor material layer. It also includes a plurality of third reset signal lines configured to provide a third reset signal to the first electrode of the third reset transistor in the plurality of pixel driving circuits; And a plurality of first reset control signal lines, which are at least configured to provide a cutoff reset control signal and a turn-on reset control signal to the gate of a third reset transistor in the plurality of pixel driving circuits; The third reset signal line and the first reset control signal line, corresponding to the same pixel driving circuit, have at least partial overlap in their orthogonal projections onto the substrate of the array substrate.

2. The array substrate according to claim 1, wherein, Also includes: The first light-emitting control electrode pad is located on the first semiconductor material layer; as well as A plurality of light-emitting control signal lines are located on the side of the first light-emitting control electrode pad away from the first semiconductor material layer; wherein the first light-emitting control electrode pad includes the gate of the first light-emitting control transistor; and each of the plurality of light-emitting control signal lines is connected to the first light-emitting control electrode pad through a via.

3. The array substrate according to claim 1, further comprising: The second light-emitting control electrode pad is located on the first semiconductor material layer; as well as Multiple light-emitting control signal lines are located on the side of the second light-emitting control electrode pad away from the first semiconductor material layer; Each pixel driving circuit further includes a second light-emitting control transistor; The second light-emitting control electrode pad includes the gate of the second light-emitting control transistor; and Each of the plurality of light-emitting control signal lines is connected to the second light-emitting control electrode pad via a via.

4. The array substrate according to claim 2 or 3, wherein, Each pixel driving circuit also includes a storage capacitor, which includes a first capacitor electrode and a second capacitor electrode. The first light-emitting control electrode pad and the first capacitor electrode are located in the first gate metal layer; The second capacitor electrode is located on the second gate metal layer, which is located on the side of the first gate metal layer away from the first semiconductor material layer; the plurality of light emission control signal lines are located on the first signal line layer, which is located on the side of the second gate metal layer away from the first gate metal layer.

5. The array substrate according to claim 4, wherein, Each pixel driving circuit also includes a compensation transistor; The active layer of the compensation transistor is located on the second semiconductor material layer, and the second semiconductor material layer is located on the side of the second gate metal layer away from the first gate metal layer. At least a portion of the gate of the compensation transistor is located in a third gate metal layer, which is located on the side of the second semiconductor material layer away from the second gate metal layer. as well as The plurality of light-emitting control signal lines are located in the first signal line layer, which is located on the side of the third gate metal layer away from the second semiconductor material layer.

6. The array substrate according to claim 1, further comprising a first voltage connection pad and a plurality of first voltage supply lines; in, The active layer of the first light-emitting control transistor, the first voltage connection pad, and the plurality of first voltage supply lines are located on three different layers; as well as A corresponding first voltage supply line of the plurality of first voltage supply lines is connected to the first voltage connection pad, and the first voltage connection pad is connected to the first electrode of the first light-emitting control transistor.

7. The array substrate according to claim 6, wherein, It also includes a plurality of second voltage supply lines, wherein the plurality of first voltage supply lines and the plurality of second voltage supply lines are interconnected with each other; Each of the first voltage supply lines extends along a first direction and is located on the side of the first voltage connection pad away from the substrate. Each of the second voltage supply lines extends along the second direction and is located on the side of the layer where the first voltage supply line is located away from the substrate. The first direction and the second direction intersect.

8. The array substrate according to claim 6, wherein, The orthographic projection of the second electrode of the third reset transistor on the substrate of the array substrate at least partially overlaps with the orthographic projection of the first voltage connection pad on the substrate.

9. The array substrate according to claim 6 further includes a plurality of light-emitting control signal lines, wherein, Each of the plurality of light-emitting control signal lines is configured to provide a light-emitting control signal to the gate of the first light-emitting control transistor; as well as The first voltage connection pad is located on the same layer as the plurality of light-emitting control signal lines.

10. The array substrate according to claim 6, wherein, The first voltage connection pad is connected to the first electrode of the first light-emitting control transistor in two adjacent pixel driving circuits located in the same row.

11. The array substrate according to claim 6, wherein, Each of the first voltage supply lines includes a main body and a plurality of extensions extending in a direction away from the main body; Each of the plurality of extensions is connected to the first voltage connection pad; and The first voltage connection pad is connected to the first electrode of the first light-emitting control transistor.

12. The array substrate according to claim 11, wherein, Each pixel driving circuit also includes a compensation transistor; The active layer of the compensation transistor is located on the second semiconductor material layer, which is located on the side of the first semiconductor material layer away from the substrate. The orthographic projection of the main body onto the substrate substantially overlaps the orthographic projection of the active layer of the compensation transistor onto the substrate.

13. The array substrate according to claim 12, wherein, The orthographic projection of the main body on the substrate substantially covers the orthographic projections of the first electrode of the compensation transistor, the active layer, and the second electrode on the substrate.

14. The array substrate according to claim 1, wherein, Each pixel driving circuit also includes a first reset transistor and a second reset transistor. The array substrate further includes: A plurality of first reset signal lines configured to provide a first reset signal to a first electrode of a first reset transistor in the plurality of pixel driving circuits, and / or a plurality of second reset signal lines configured to provide a second reset signal to a first electrode of a second reset transistor in the plurality of pixel driving circuits; The plurality of first reset signal lines, the plurality of second reset signal lines, and the plurality of third reset signal lines extend along a direction substantially parallel to the first direction.

15. The array substrate according to claim 1, further comprising a first corresponding anode, a second corresponding anode, and a third corresponding anode; wherein the first corresponding anode is the anode of a sub-pixel of a first color, the second corresponding anode is the anode of a sub-pixel of a second color, and the third corresponding anode is the anode of a sub-pixel of a third color; The orthogonal projection of at least one of the first corresponding anode, the second corresponding anode, or the third corresponding anode on the substrate at least partially overlaps with the orthogonal projection of the second electrode of the third reset transistor on the substrate; The orthogonal projection of the first corresponding anode and / or the second corresponding anode on the substrate completely covers the orthogonal projection of the second electrode of the third reset transistor on the substrate.

16. An array substrate comprising multiple pixel driving circuits: in, Each pixel driving circuit in the plurality of pixel driving circuits includes a second node connection line, a first light-emitting control transistor, and a third reset transistor. The second node connection line is connected to the second electrode of the first light-emitting control transistor and to the second electrode of the third reset transistor; as well as The second node connection line is located on the same layer as the active layer of the first light-emitting control transistor and the third reset transistor; It also includes a plurality of third reset signal lines configured to provide a third reset signal to the first electrode of the third reset transistor in the plurality of pixel driving circuits; And a plurality of first reset control signal lines, which are at least configured to provide a cutoff reset control signal and a turn-on reset control signal to the gate of a third reset transistor in the plurality of pixel driving circuits; The third reset signal line and the first reset control signal line, corresponding to the same pixel driving circuit, have at least partial overlap in their orthogonal projections onto the substrate of the array substrate.

17. The array substrate according to claim 15, wherein, Also includes: Multiple light emission control signal lines; Each of the plurality of light-emitting control signal lines is configured to provide a control signal to the gate of the first light-emitting control transistor. The plurality of light-emitting control signal lines are spaced apart from the second node connection lines by at least three insulating layers.

18. The array substrate according to claim 17, wherein, Each pixel driving circuit also includes a first node connection line, a storage capacitor, and a compensation transistor; The first node connection line is connected to the first capacitor electrode of the storage capacitor and to the first electrode of the compensation transistor; as well as The plurality of light-emitting control signal lines and the first node connection line are located on the same layer.

19. The array substrate according to claim 16, wherein, It also includes a first corresponding anode, a second corresponding anode, and a third corresponding anode; wherein the first corresponding anode is the anode of a sub-pixel of a first color, the second corresponding anode is the anode of a sub-pixel of a second color, and the third corresponding anode is the anode of a sub-pixel of a third color; The orthogonal projection of at least one of the first corresponding anode, the second corresponding anode, or the third corresponding anode on the substrate at least partially overlaps with the orthogonal projection of the second electrode of the third reset transistor on the substrate; The orthogonal projection of the first corresponding anode and / or the second corresponding anode on the substrate completely covers the orthogonal projection of the second electrode of the third reset transistor on the substrate.

20. A display device comprising an array substrate according to any one of claims 1 to 15 and one or more integrated circuits connected to the array substrate.

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