Anti-latch-up integrated circuit structure

Abstract

This invention provides a latch-up resistant integrated circuit structure, including a semiconductor substrate, a first N-type well forming an N-type isolation ring, and a first heavily doped N-type region and a first heavily doped P-type region disposed within the first N-type well and spaced apart from each other. The first heavily doped P-type region, the first N-type well, and the P-type region surrounding the first N-type well together constitute a parasitic bipolar junction transistor (BJT) structure for rapid latch-up current discharge. The P-type region surrounding the first N-type well includes the substrate, the isolation P-well, and the P-well within the adjacent core / IO circuitry. This application utilizes the BJT structure to significantly reduce the turn-on voltage to discharge current at a faster rate, while maintaining a voltage higher than the IO operating voltage. It exhibits excellent tolerance in both sinking and pumping current modes, significantly improving chip reliability.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to an anti-latch-up integrated circuit structure. Background Technology

[0002] In modern integrated circuit (IC) design, with the continuous increase in chip integration density and the decrease in operating voltage, device size continues to shrink, resulting in increasingly closer spacing between devices. This high-density layout makes the formation of parasitic bipolar transistors unavoidable. Parasitic NPN transistors and parasitic PNP transistors in the substrate may couple to each other, forming a parasitic structure similar to a silicon controlled rectifier (SCR). Under specific triggering conditions, such as the influence of transient signals like voltage overshoot, current injection, or electromagnetic interference, this parasitic SCR structure may be accidentally turned on, forming a low-impedance path between power supply (VDD) and ground (VSS). Once turned on, this low-impedance path persists even after the trigger signal disappears, causing a large current to flow through the chip; this phenomenon is known as latch-up.

[0003] Latch-up is a serious problem affecting chip reliability. In mild cases, it can cause chip malfunctions, and in severe cases, it can cause the chip to burn out permanently due to excessive heat generated by excessive current.

[0004] This problem is particularly acute in System-on-Chip (SoC) circuits that integrate circuitry across different voltage domains. To balance performance and power consumption, these chips typically include input / output (I / O) circuitry that uses higher voltages (e.g., 5V) and core logic circuitry that uses lower voltages (e.g., 1.5V). See also... Figure 1 The figure illustrates two typical cross-voltage domain layouts of isolation ring structures commonly used in the prior art and the latch-up risks they face.

[0005] Figure 1 The left side (A. 5V IO PMOS and internal 1.5V NMOS) shows a configuration where a high-voltage IO PMOS device is adjacent to a low-voltage internal core NMOS device. In this structure, the high-voltage IO PMOS is located in the N-well on the right side of the left diagram, and the low-voltage internal NMOS is located in the P-well on the left side. A conventional isolation structure is provided between them, typically including an N-type active region connected to the IO power supply (VDD IO) and a P-type active region connected to ground (VSS). However, the parasitic SCR path indicated by the arrows in the diagram (flowing from the source / body region of the IO PMOS through the substrate to the source of the internal NMOS) shows that, due to the high potential difference between VDD IO and VSS, a large current could still penetrate the isolation region and cause latch-up upon triggering.

[0006] Figure 1The right side (A.5V IO NMOS and internal 1.5V PMOS) shows the adjacent high-voltage IO NMOS device and the low-voltage internal core PMOS device. In this structure, the high-voltage IO NMOS is located in the P-well on the left side of the right diagram, and the low-voltage internal PMOS is located in the N-well on the right side of the right diagram. An isolation ring connecting VDD IO and VSS is also provided between them. The arrows in the diagram indicate the parasitic path from the core power supply (VDD internal) through the N-well and P-substrate to VSS. In this hybrid voltage design, the voltage and structural configuration between the IO power supply (VDD IO) and the internal core circuit power supply (VDD internal), as well as between them and ground, makes it easier to trigger parasitic SCR structures across voltage domains.

[0007] Existing isolation ring technologies aim to collect minority carriers injected into the substrate, thereby blocking or weakening the feedback loop of parasitic SCRs. However, with the continuous evolution of process nodes, the traditional simple isolation ring structure (i.e., connecting power or ground only through doped regions) is gradually reaching its limit in suppressing strong latch-up paths between high-voltage and low-voltage domains. Especially... Figure 1 With the compact layout shown, relying solely on traditional diode-type leakage mechanisms is often insufficient to provide adequate protection, and the risk of latch-up remains high.

[0008] Therefore, the industry urgently needs a new type of isolation structure that can further improve latch-up resistance without significantly increasing chip area. Summary of the Invention

[0009] The purpose of this invention is to solve the technical problem that the isolation ring structure in the prior art has limited ability to suppress latch-up effect and is difficult to meet the reliability requirements of highly integrated chips, thereby providing an integrated circuit structure that can significantly improve latch-up resistance.

[0010] To achieve the above and other related objectives, the present invention provides a latch-up resistant integrated circuit structure, comprising:

[0011] Semiconductor substrate;

[0012] A first N-type well is disposed in the semiconductor substrate and forms an N-type isolation ring for isolating the input / output (IO) circuit region and the core logic circuit region;

[0013] The first heavily doped N-type region and the first heavily doped P-type region are both disposed within the first N-type well and are spaced apart from each other in the horizontal direction.

[0014] The first heavily doped P-type region, the first N-type well, and the P-type region surrounding the first N-type well together constitute a parasitic bipolar junction transistor (BJT) structure for fast dissipation of latch-up current.

[0015] The P-type region surrounding the first N-type well includes the semiconductor substrate, the first P-type well disposed outside the first N-type well for isolation, and the P-type well adjacent to the core logic circuit region and / or IO circuit region of the first N-type well.

[0016] Preferably, the first heavily doped N-type region is electrically connected to the IO power supply potential; the first heavily doped P-type region is in a floating state.

[0017] Preferably, an isolation layer is provided on the surface of the first heavily doped P-type region to prevent the first heavily doped P-type region from forming an electrical connection and short-circuiting with the first heavily doped N-type region.

[0018] Preferably, the isolation layer is a silicide barrier layer or a polycrystalline silicon layer.

[0019] Preferably, the integrated circuit structure further includes a first P-type well, which is disposed in the semiconductor substrate and adjacent to the first N-type well; a second heavily doped P-type region is disposed in the first P-type well, and the second heavily doped P-type region is electrically connected to ground potential; the first P-type well participates in current discharge as part of the collector region of the bipolar junction transistor structure.

[0020] Preferably, when the integrated circuit structure is configured to consist of a core NMOS transistor and an IO PMOS transistor: the core logic circuit region includes a second P-type well located at the edge, a gate structure is disposed within the second P-type well, and a second heavily doped N-type region and a third heavily doped N-type region are respectively disposed on both sides of the gate structure, the second heavily doped N-type region and the third heavily doped N-type region are respectively electrically connected to ground potential and internal input / output terminal; a fifth heavily doped P-type region is also disposed within the second P-type well as a lead-out region and is electrically connected to ground potential; the second P-type well participates in current discharge as part of the collector region of the bipolar junction transistor structure; the IO circuit region includes a second N-type well located at the edge, a gate structure is disposed within the second N-type well, and a third heavily doped P-type region and a fourth heavily doped P-type region are respectively disposed on both sides of the gate structure, the third heavily doped P-type region and the fourth heavily doped P-type region are respectively electrically connected to input / output terminal and IO power supply potential; a fourth heavily doped N-type region is also disposed within the second N-type well as a lead-out region and is electrically connected to IO power supply potential.

[0021] Preferably, when the integrated circuit structure is configured to consist of an IO NMOS transistor and a core PMOS transistor: the IO circuit region includes a second P-type well located at the edge, a gate structure is disposed within the second P-type well, and a second heavily doped N-type region and a third heavily doped N-type region are respectively disposed on both sides of the gate structure, the second heavily doped N-type region and the third heavily doped N-type region are respectively electrically connected to the input / output terminal and ground potential; a fifth heavily doped P-type region is also disposed within the second P-type well as a lead-out region and is electrically connected to ground potential; the second P-type well participates in current discharge as part of the collector region of the bipolar junction transistor structure; the core logic circuit region includes a second N-type well located at the edge, a gate structure is disposed within the second N-type well, and a third heavily doped P-type region and a fourth heavily doped P-type region are respectively disposed on both sides of the gate structure, the third heavily doped P-type region and the fourth heavily doped P-type region are respectively electrically connected to the core circuit power supply potential and the internal input / output terminal; a fourth heavily doped N-type region is also disposed within the second N-type well as a lead-out region and is electrically connected to the core circuit power supply potential.

[0022] Preferably, the voltage value of the power supply potential of the core circuit is lower than the voltage value of the power supply potential of the IO circuit.

[0023] Preferably, the semiconductor substrate may also optionally include an N-type buried layer and / or a deep N-type well disposed below the first N-type well and the core logic circuit region.

[0024] Preferably, the integrated circuit structure and the bipolar junction transistor structure thereof exhibit hysteresis characteristics under transmission line pulse (TLP) testing on the path from the IO power supply potential (VDD_IO) to the ground potential (VSS), wherein the turn-on voltage (Vt1) is reduced to discharge current with faster conduction speed, and the sustaining voltage (Vh) meets the operating voltage requirements of the IO power supply potential.

[0025] As described above, the latch-up resistant integrated circuit structure of the present invention has the following beneficial effects:

[0026] This application constructs a parasitic bipolar junction transistor (BJT) structure by setting a heavily doped P-type region within the N-type well that forms an N-type isolation ring, and combining it with the N-type well and the surrounding P-type region (including the substrate, adjacent P-type wells, and the P-type wells of the core / IO region). This structure utilizes the current amplification characteristics of the BJT to significantly reduce the latch-up voltage to achieve rapid current discharge, while maintaining a sustaining voltage higher than the IO operating voltage to prevent false triggering. Furthermore, this structure effectively improves the latch-up trigger threshold in both sinking and pumping modes, fundamentally enhancing the latch-up robustness of multi-voltage domain hybrid integrated circuits. Attached Figure Description

[0027] Figure 1 The diagram shown is a cross-sectional schematic of a latching isolation ring structure in the prior art.

[0028] Figure 2 The diagram shown is a schematic diagram of an anti-latch-up integrated circuit structure using a silicide barrier layer in an embodiment of the present invention;

[0029] Figure 3 This is a schematic diagram of an anti-latch-up integrated circuit structure using a silicide barrier layer in another configuration according to an embodiment of the present invention;

[0030] Figure 4 The diagram shown is a schematic diagram of an anti-latch-up integrated circuit structure using a polysilicon layer in an embodiment of the present invention;

[0031] Figure 5 This is a schematic diagram of an anti-latch-up integrated circuit structure using a polysilicon layer in another configuration according to an embodiment of the present invention;

[0032] Figure 6 The diagram shown is a schematic representation of an anti-latch-up integrated circuit structure including an N-type buried layer in an embodiment of the present invention.

[0033] Figure 7 This is a schematic diagram of an anti-latch-up integrated circuit structure including an N-type buried layer in another configuration according to an embodiment of the present invention;

[0034] Figure 8 The diagram shows a comparison of transmission line pulse test results between the structure of this invention and the existing technology structure. Detailed Implementation

[0035] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0036] A latch-up resistant integrated circuit structure includes a semiconductor substrate 101.

[0037] The semiconductor substrate 101 can be a bulk semiconductor substrate, such as a bulk silicon substrate, or a semiconductor-on-insulator (SOI) substrate. The material of the semiconductor substrate 101 can include, but is not limited to: elemental semiconductors, such as silicon (Si), germanium (Ge), and diamond; compound semiconductors, such as silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), or indium antimonide (InSb); and alloy semiconductors, such as silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), or gallium arsenide phosphide indium (GaInAsP). Furthermore, the substrate can also include an epitaxial layer, such as a silicon germanium layer epitaxially grown on bulk silicon, or it can be a strained substrate to enhance performance. The SOI substrate can include a buried oxide layer (BOX) and a semiconductor layer located above the BOX layer, which can also be any of the semiconductor materials listed above.

[0038] Various doped regions, such as P-type wells or N-type wells, can also be formed in the substrate 101 according to design requirements. A first N-type well (intermediate NW) 102 is disposed in the semiconductor substrate 101 and forms an N-type isolation ring for isolating the input / output (IO) circuit region and the core logic circuit region. The first N-type well 102 can be formed by implanting N-type dopants containing phosphorus or arsenic. Compared to using only a simple guard ring, utilizing a specific well region structure as an isolation ring can more effectively collect charge carriers. A first heavily doped N-type region 105 and a first heavily doped P-type region 106 are both disposed within the first N-type well 102 and are horizontally spaced apart from each other. The first heavily doped P-type region 106, the first N-type well 102, and the P-type regions surrounding the first N-type well 102 (including the semiconductor substrate 101, adjacent first P-type wells 114, and P-type wells within the core / IO circuit region) together constitute a bipolar junction transistor (BJT) structure for assisting in the discharge of latch-up current. This embodiment constructs the BJT structure within an N-type isolation ring, utilizing the high current gain characteristic of the BJT during conduction to assist in discharging latch-up current. Compared to the traditional simple diode-based current discharging method, this BJT structure exhibits a higher amplification factor and faster current discharging response, thereby significantly enhancing the structure's ability to suppress latch-up effects, particularly in highly integrated chip designs with multiple voltage domains coexisting.

[0039] In some embodiments, the first heavily doped N-type region 105 is electrically connected to the IO power supply potential (VDD_IO); the first heavily doped P-type region 106 is in a floating state. By connecting the first heavily doped N-type region 105 to a high potential, the isolation ring is ensured to be correctly biased, while the first heavily doped P-type region 106, as a floating base region or other auxiliary structure, is not directly connected to a fixed potential. This helps to adjust the local electric field distribution and form the desired parasitic BJT characteristics. For a better understanding of this structure, please refer to... Figure 2 as well as Figure 2 The scene shown. Figure 2 This diagram illustrates a typical embodiment where the IO circuit region has a 5V IO PMOS transistor (corresponding to the right-hand structure), while the core logic circuit region has a 1.5V core NMOS transistor (corresponding to the left-hand structure). In this configuration, the intermediate N-type isolation ring (first N-type well 102) is located between the two well regions of different voltage domains, playing a crucial role in isolation. The diagram clearly shows that the first heavily doped N-type region 105 (N+) is connected to VDD IO, while the intermediate first heavily doped P-type region 106 (P+) is not led out and is in a floating state.

[0040] In some embodiments, an isolation layer 107 is provided on the surface of the first heavily doped P-type region 106 to prevent the formation of electrical connections between the first heavily doped P-type region 106 and the first heavily doped N-type region 105. The isolation layer 107 can physically block the formation of contact holes or the growth of silicides during the metallization process, thereby ensuring that the region remains electrically floating.

[0041] In some embodiments, the isolation layer 107 is a silicide barrier layer (SAB) or a polysilicon layer. If a silicide barrier layer is used, its material may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, or combinations thereof, formed by processes such as chemical vapor deposition (CVD) or atomic layer deposition (ALD), and retained in a specific area after photolithography and etching processes to prevent the formation of a conductive silicide layer on the surface of the first heavily doped P-type region 106 by subsequent self-aligned metal silicide processes. If a polysilicon layer is used, it can be deposited and patterned using polysilicon materials compatible with gate fabrication processes, acting as a physical barrier layer. Figures 2 to 5 As shown, the isolation layer 107 covers the first heavily doped p-type region 106. Wherein, Figure 2 and Figure 3 The example demonstrates the use of a silicide barrier layer (SAB) as the isolation layer 107. This SAB layer covers the P+ region, preventing the formation of silicide on it and thus preventing short circuits or being led out by the P+ regions (105) on either side. Figure 4 and Figure 5Another embodiment is shown, in which the isolation layer 107 is composed of a polysilicon layer, which is also located above the P+ region and serves a similar isolation and blocking function.

[0042] In some embodiments, the integrated circuit structure further includes a first P-type well (intermediate PW) 114, which is disposed in the semiconductor substrate 101 and adjacent to the first N-type well 102; a second heavily doped P-type region 115 is disposed within the first P-type well 114, and the second heavily doped P-type region 115 is electrically connected to ground potential (VSS). The first P-type well 114 can be formed by implanting a P-type dopant containing boron or boron difluoride. As part of the collector region of the intermediate P-type protection structure and the bipolar junction transistor structure, it is disposed adjacent to the N-type isolation ring and grounded, which can further absorb holes implanted into the substrate, and together with the N-type isolation ring, form a complete latch-up protection barrier. The first P-type well (intermediate PW) 114 is located between the intermediate first N-type well 102 and the IO circuit region (second N-type well 104) on the right, and its internal P+ region (115) is grounded, effectively further isolating the high voltage noise of the IO region from the core region.

[0043] In some embodiments, when the integrated circuit structure is configured to consist of a core NMOS transistor and an IO PMOS transistor: the core logic circuit region includes a second P-type well 103 located at the edge, a gate structure is disposed in the second P-type well 103, and a second heavily doped N-type region 108 and a third heavily doped N-type region 109 are respectively disposed on both sides of the gate structure, the second heavily doped N-type region 108 and the third heavily doped N-type region 109 are respectively electrically connected to ground potential (VSS) and internal input / output terminal (internalIO); a fifth heavily doped P-type region 110 is also disposed in the second P-type well 103 as a lead-out region and is electrically connected to ground potential (VSS). The I / O circuit region includes a second N-type well 104 located at the edge. A gate structure is disposed within the second N-type well 104. A third heavily doped P-type region 112 and a fourth heavily doped P-type region 111 are respectively disposed on both sides of this gate structure. The third heavily doped P-type region 112 and the fourth heavily doped P-type region 111 are electrically connected to the I / O power supply potential (VDD_IO) and the input / output terminal (IO), respectively. A fourth heavily doped N-type region 113 is also disposed within the second N-type well 104 as a lead-out region and is electrically connected to the I / O power supply potential (VDD_IO). This configuration corresponds to a scenario where a high-voltage I / O PMOS device is adjacent to a low-voltage core NMOS device. The gate structure typically includes a gate dielectric layer (such as silicon dioxide or a high-k dielectric) and a gate electrode (such as polysilicon or a metal gate) used to control the transistor channel. This specific connection configuration is shown in detail in... Figure 2 and Figure 4 middle. Figure 2The left side is the core logic circuit area, which clearly shows the NMOS device connection in the 1.5V PW (second P-type well 103): the source N+ (108) and body contact P+ (110) are connected to VSS, and the drain N+ (109) is connected to internalIO. Figure 2 The right side shows the IO circuit area, illustrating the PMOS device connections within the NW (second N-type well 104): the source P+ (112) and body contact N+ (113) are connected to VDD IO, and the drain P+ (111) is connected to the IO port. This layout separates the high-voltage IO area from the low-voltage core area through the intermediate isolation rings (102 and 114) to prevent latch-up triggering. Figure 4 Structure and Figure 2 Similar, the difference lies in Figure 4 The middle isolation layer 107 is made of polycrystalline silicon.

[0044] In some embodiments, when the integrated circuit structure is configured to consist of an IO NMOS transistor and a core PMOS transistor: the IO circuit region includes a second P-type well 103 located at the edge, a gate structure is disposed in the second P-type well 103, and a second heavily doped N-type region 108 and a third heavily doped N-type region 109 are respectively disposed on both sides of the gate structure, the second heavily doped N-type region 108 and the third heavily doped N-type region 109 are electrically connected to the input / output terminal (IO) and ground potential (VSS) respectively; a fifth heavily doped P-type region 110 is also disposed in the second P-type well 103 as a lead-out region and is electrically connected to ground potential (VSS). The core logic circuit region includes a second N-type well 104 located at the edge. A gate structure is disposed within the second N-type well 104, and a third heavily doped P-type region 111 and a fourth heavily doped P-type region 112 are respectively disposed on both sides of the gate structure. The third heavily doped P-type region 111 and the fourth heavily doped P-type region 112 are electrically connected to the core circuit power supply potential (VDD_internal) and the internal input / output terminal (internal IO), respectively. A fourth heavily doped N-type region 113 is also disposed within the second N-type well 104 as a lead-out region and is electrically connected to the core circuit power supply potential (VDD_internal). This configuration corresponds to another common scenario where a high-voltage IO NMOS device is adjacent to a low-voltage core PMOS device. In this type of cross-voltage domain layout, the latch-up risk is particularly prominent. For details of the specific structure of this embodiment, please refer to [link to specific details]. Figure 3 and Figure 5 . Figure 3 The left side shows the IO circuit area, in which PW (second P-type well 103) serves as the body region of the IO NMOS. Its source N+ (108) is connected to IO, and its drain N+ (109) and body contact P+ (110) are connected to VSS. Figure 3The right side shows the core logic circuit area, in which the 1.5VNW (second N-type well 104) serves as the body region of the Core PMOS. Its body contact N+ (113) is connected to VDD_internal, and the source / drain P+ is connected to VDD_internal and internal IO respectively. Figure 5 The same circuit configuration using polysilicon as the isolation layer 107 is shown. These illustrations clearly show how the modified isolation ring structure in the middle is embedded between these two typical devices.

[0045] In some embodiments, the voltage value of the core circuit power supply potential (VDD_internal) is lower than the voltage value of the I / O power supply potential (VDD_IO). For example, the core circuit power supply potential can be 1.5V, 1.2V, 0.9V, or other low-voltage logic levels, while the I / O power supply potential can be 3.3V, 5V, or other high-voltage interface levels. The existence of this voltage difference makes the triggering of the parasitic PNPN structure more sensitive, therefore this structure has important protective significance against such potential latch-up paths driven by voltage differences.

[0046] In some embodiments, the semiconductor substrate further includes an N-type buried layer (NBL) and / or a deep N-type well (DNW) 117, which is disposed below the first N-type well 102 and the core logic circuit region. The deep N-type well or N-type buried layer can be formed by implanting N-type impurities such as phosphorus deep into the substrate using a high-energy ion implantation process. They provide an additional isolation barrier in the vertical direction, effectively blocking noise currents or parasitic turn-on paths flowing through the deep substrate, preventing latch-up caused by the diffusion of deep carriers, and further improving the overall structure's noise immunity and latch-up robustness. Figure 6 and Figure 7 An embodiment incorporating an N-type buried layer (NBL) 117 is specifically shown. Figure 6 As can be seen, the NBL 117 is located below the entire active region, including the 1.5V PW 103 on the left, the isolation ring region (102 / 114) in the middle, and the IO NW 104 on the right. As a deep N-type confinement layer, the NBL effectively cuts off the parasitic path in the vertical direction. Figure 7 The application of NBL 117 was also demonstrated, but it was for a configuration where the IO NMOS and Core PMOS were adjacent.

[0047] The integrated circuit structure proposed in this invention significantly improves latch-up resistance through the above-mentioned innovative design.

[0048] In some embodiments, this integrated circuit structure exhibits excellent reliability in latch-up current injection tests. The structure of this application is compared with conventional structures in terms of latch-up resistance. In the sink current test mode, the pass current of the conventional structure is 225 mA, while the pass current of the structure of this application is significantly increased to 500 mA, more than doubling. In the pump current test mode, the pass current of the conventional structure is 125 mA, while the structure of this application increases to 200 mA. This indicates that the structure can withstand stronger current disturbances without latch-up failure.

[0049] Furthermore, this integrated circuit structure exhibits hysteresis characteristics under transmission line pulse (TLP) testing on the path from the IO power supply potential (VDD_IO) to the ground potential (VSS). The turn-on voltage (Vt1) is reduced to approximately 11V to discharge current with a faster conduction speed, while the sustaining voltage (Vh) is greater than 6V to meet the operating voltage requirements of the IO power supply potential. Compared to traditional isolation ring structures (with a turn-on voltage of approximately 14.5V to 15V), the structure of this invention significantly reduces the turn-on threshold, meaning it can respond and discharge current more quickly in the early stages of electrostatic discharge or latch-up events across power domains.

[0050] To more intuitively demonstrate the beneficial effects of the structure of this invention, please refer to the appendix. Figure 8 The diagram illustrates a comparison of transmission line pulse (TLP) test results between an integrated circuit structure according to an embodiment of the present invention and a conventional isolation ring structure. The test is performed on the path from the IO power supply potential (VDD_IO) to the ground potential (VSS) port, with the horizontal axis representing voltage (V) and the vertical axis representing current (A).

[0051] like Figure 8 As shown, the red curve represents the "prior technology," which has a higher turn-on voltage, starting conduction between approximately 14.5V and 15V, and the curve is relatively steep, showing no obvious low-impedance hysteresis characteristics and a relatively delayed response. In contrast, the green curve represents the "embodiment of this application," exhibiting significantly superior performance: its trigger latch-up voltage (Vt1) is significantly reduced to approximately 11V, and after triggering, it exhibits obvious hysteresis characteristics, with the voltage rapidly dropping, but its sustaining voltage (Vh) remains stable at around 6.5V. This comparison demonstrates that the present invention, by integrating a BJT structure in an N-type isolation ring, effectively lowers the turn-on threshold of parasitic paths across power domains, utilizes rapid conduction capability to discharge potentially dangerous currents, and simultaneously ensures that the hysteresis-induced sustaining voltage (approximately 6.5V) remains higher than the normal operating voltage of the high-voltage I / O (typically 5V), thereby avoiding false triggering during normal system power-on / off or operation and greatly enhancing the latch-up immunity of the integrated circuit.

[0052] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0053] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A latch-up resistant integrated circuit structure, characterized in that, include: Semiconductor substrate; A first N-type well is disposed in the semiconductor substrate and forms an N-type isolation ring for isolating the input / output (IO) circuit region and the core logic circuit region; The first heavily doped N-type region and the first heavily doped P-type region are both disposed within the first N-type well and are spaced apart from each other in the horizontal direction. The first heavily doped P-type region, the first N-type well, and the P-type region surrounding the first N-type well together constitute a parasitic bipolar junction transistor (BJT) structure for fast dissipation of latch-up current. The P-type region surrounding the first N-type well includes the semiconductor substrate, the first P-type well disposed outside the first N-type well for isolation, and the P-type well adjacent to the core logic circuit region and / or IO circuit region of the first N-type well.

2. The latch-up resistant integrated circuit structure according to claim 1, characterized in that: The first heavily doped N-type region is electrically connected to the IO power supply potential (VDD_IO); the first heavily doped P-type region is in a floating state.

3. The latch-up resistant integrated circuit structure according to claim 2, characterized in that: An isolation layer is provided on the surface of the first heavily doped P-type region to prevent the formation of electrical connections between the first heavily doped P-type region and the first heavily doped N-type region.

4. The latch-up resistant integrated circuit structure according to claim 3, characterized in that: The isolation layer is a silicide barrier layer or a polycrystalline silicon layer.

5. The latch-up resistant integrated circuit structure according to claim 2, characterized in that: The integrated circuit structure further includes a first P-type well, which is disposed in the semiconductor substrate and adjacent to the first N-type well; a second heavily doped P-type region is disposed in the first P-type well, which is electrically connected to ground potential (VSS); the first P-type well participates in current discharge as part of the collector region of the bipolar junction transistor structure.

6. The latch-up resistant integrated circuit structure according to claim 5, characterized in that: When the integrated circuit structure is configured to consist of a core NMOS transistor and an IO PMOS transistor: the core logic circuit region includes a second P-type well located at the edge, a gate structure is disposed within the second P-type well, and a second heavily doped N-type region and a third heavily doped N-type region are respectively disposed on both sides of the gate structure. The second heavily doped N-type region and the third heavily doped N-type region are electrically connected to ground potential (VSS) and internal input / output terminals, respectively. The second P-type well also has a fifth doped P-type region as a lead-out region, which is electrically connected to ground potential (VSS). The second P-type well participates in current discharge as part of the collector region of the bipolar junction transistor structure. The IO circuit region includes a second N-type well located at the edge. The second N-type well has a gate structure, and a third doped P-type region and a fourth doped P-type region are respectively provided on both sides of the gate structure. The third doped P-type region and the fourth doped P-type region are electrically connected to the input / output terminal (IO) and the IO power supply potential (VDD_IO), respectively. The second N-type well also has a fourth doped N-type region as a lead-out region, which is electrically connected to the IO power supply potential (VDD_IO).

7. The latch-up resistant integrated circuit structure according to claim 5, characterized in that: When the integrated circuit structure is configured to consist of IO NMOS transistors and core PMOS transistors: the IO circuit region includes a second P-type well located at the edge, within which a gate structure is disposed. A second heavily doped N-type region and a third heavily doped N-type region are respectively disposed on both sides of the gate structure. The second heavily doped N-type region and the third heavily doped N-type region are electrically connected to the input / output terminal (IO) and ground potential (VSS), respectively. A fifth heavily doped P-type region is also disposed within the second P-type well as a lead-out region and is electrically connected to ground potential (VSS). The second P-type well participates in current discharge as part of the collector region of the bipolar junction transistor structure. The core logic circuit region includes a second N-type well located at the edge, within which a gate structure is disposed. A third heavily doped P-type region and a fourth heavily doped P-type region are respectively disposed on both sides of the gate structure. The third heavily doped P-type region and the fourth heavily doped P-type region are electrically connected to the core circuit power supply potential (VDD_internal) and the internal input / output terminal (internal), respectively. IO); The second N-type well is further provided with a fourth doped N-type region as an extraction region, which is electrically connected to the core circuit power supply potential (VDD_internal).

8. The latch-up resistant integrated circuit structure according to claim 6 or 7, characterized in that: The voltage value of the core circuit power supply potential (VDD_internal) is lower than the voltage value of the IO power supply potential (VDD_IO).

9. The latch-up resistant integrated circuit structure according to claim 1, characterized in that: The semiconductor substrate further includes an N-type buried layer (NBL) and / or a deep N-type well (DNW), wherein the N-type buried layer or deep N-type well is disposed below the first N-type well and the core logic circuit region.

10. The latch-up resistant integrated circuit structure according to claim 1, characterized in that: The integrated circuit structure and the bipolar junction transistor structure it constitutes exhibit hysteresis characteristics under transmission line pulse (TLP) testing on the path from the IO power supply potential (VDD_IO) to the ground potential (VSS), wherein the turn-on voltage (Vt1) is reduced to discharge current with faster conduction speed, and the sustaining voltage (Vh) meets the operating voltage requirements of the IO power supply potential.

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