A display panel and display device

Abstract

This application discloses a display panel and a display device, relating to the field of display technology. The display panel includes a substrate and a circuit functional layer located on one side of the substrate; the circuit functional layer includes a plurality of pixel circuits located in the display area; at least a portion of the pixel circuits includes a first transistor and a light-emitting element; the first transistor includes a first active structure, a first gate, and a second gate, the first gate being located on the side of the first active structure closer to the substrate, and the second gate being located on the side of the first active structure farther from the substrate; the circuit functional layer further includes a first conductive structure located on the side of the second gate farther from the substrate; wherein, the first conductive structure includes a first overlapping portion; along a direction perpendicular to the plane of the substrate, the first overlapping portion overlaps with the overlapping area of ​​the first gate and the second gate of the same first transistor, and the first overlapping portion overlaps with the first gate and the second gate of the same first transistor. Using the above technical solution can improve performance.

Description

Technical Field

[0001] This application relates to the field of display technology, and more particularly to a display panel and a display device. Background Technology

[0002] With the development of multimedia technology, the importance of display products has steadily increased, but the performance of display products still needs to be improved. Summary of the Invention

[0003] This application provides a display panel and a display device to improve the performance of display products.

[0004] According to one aspect of this application, a display panel is provided, comprising: a substrate and a circuit functional layer located on one side of the substrate; The circuit functional layer includes multiple pixel circuits located in the display area; At least part of the pixel circuitry includes a first transistor and a light-emitting element; The first transistor includes a first active structure, a first gate, and a second gate. The first gate is located on the side of the first active structure closer to the substrate, and the second gate is located on the side of the first active structure farther from the substrate. The circuit functional layer also includes a first conductive structure located on the side of the second gate away from the substrate; The first conductive structure includes a first overlapping portion; along a direction perpendicular to the plane of the substrate, the first overlapping portion overlaps with the overlapping area of ​​the first gate and the second gate of the same first transistor, and the first overlapping portion overlaps with the first gate and the second gate of the same first transistor.

[0005] According to another aspect of this application, a display panel is provided, comprising: a substrate and a circuit functional layer located on one side of the substrate; The circuit functional layer includes multiple pixel circuits located in the display area; At least part of the pixel circuitry includes a second transistor and a light-emitting element; The second transistor includes a second active structure, a third gate, and a fourth gate. The third gate is located on the side of the second active structure closer to the substrate, and the fourth gate is located on the side of the second active structure farther from the substrate. The circuit functional layer also includes a second conductive structure located on the side of the fourth gate away from the substrate; The second conductive structure includes a second overlapping portion; along a direction perpendicular to the plane of the substrate, the second overlapping portion overlaps with the overlapping region of the third gate and the second active structure of the same second transistor, and the second overlapping portion overlaps with the third gate and the second active structure of the same second transistor.

[0006] According to another aspect of this application, a display device is provided, including any of the above-described display panels.

[0007] The technical solution of this application, by setting a first transistor with a dual-gate structure in the pixel circuit, and having the first overlapping portion of the first conductive structure overlap with the first gate and the second gate of the same first transistor, allows the first gate and the second gate of the first transistor to be electrically connected, which is beneficial to increasing the on-state current of the first transistor, improving the switching speed of the first transistor, and realizing high-frequency refresh. At the same time, along the direction perpendicular to the plane of the substrate, the first overlapping portion of the first conductive structure overlaps with the overlapping area of ​​the first gate and the second gate of the same first transistor, which allows the first extension area of ​​the first gate and the second extension area of ​​the second gate to overlap along the direction perpendicular to the plane of the substrate. This can improve the performance of the first transistor while reducing the extension area space occupied by the first transistor in the direction perpendicular to the plane of the substrate, thereby reducing the space occupied by the pixel circuit, which is beneficial to improving the resolution and thinning of the display panel.

[0008] By setting a second transistor with a dual-gate structure in the pixel circuit, and having the second overlapping portion of the second conductive structure overlap with the third gate and the second active structure of the same second transistor, the third gate of the second transistor and the source or drain region of the second active structure can be electrically connected. This helps to suppress the threshold voltage drift of the second transistor, improve its working stability, and extend its service life, thereby improving the display effect and reliability of the display panel 010. At the same time, along the direction perpendicular to the plane of the substrate, the second overlapping portion of the second conductive structure overlaps with the overlapping area of ​​the third gate and the second active structure of the same second transistor. This allows the first extension area of ​​the third gate and the third extension area of ​​the second active structure to overlap along the direction perpendicular to the plane of the substrate. This can improve the performance of the second transistor while reducing the space occupied by the extension area of ​​the second transistor in the direction perpendicular to the plane of the substrate, thereby reducing the space occupied by the pixel circuit and improving the resolution and thinness of the display panel.

[0009] In addition, when the display panel is a transparent display panel or a partially transparent display panel, it is also beneficial to improve the light transmittance of the display panel.

[0010] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this application, nor is it intended to limit the scope of this application. Other features of this application will become readily apparent from the following description. Attached Figure Description

[0011] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0012] Figure 1 This is a top view schematic diagram of a display panel provided in an embodiment of this application. Figure 1 ; Figure 2 This is a schematic diagram of the film layer structure of a display panel provided in an embodiment of this application. Figure 1 ; Figure 3 This is a top view of a first transistor provided in an embodiment of this application. Figure 1 ; Figure 4 This is a top view schematic diagram of a display panel provided in an embodiment of this application. Figure 2 ; Figure 5 This is a schematic diagram of the film layer structure of a display panel provided in an embodiment of this application. Figure 2 ; Figure 6 This is a schematic diagram of the circuit structure of a pixel circuit provided in an embodiment of this application. Figure 1 ; Figure 7 This is a schematic diagram of the film layer structure of a display panel provided in an embodiment of this application. Figure 3 ; Figure 8 This is a schematic diagram of the film layer structure of a display panel provided in an embodiment of this application. Figure 4 ; Figure 9 This is a top view of a first transistor provided in an embodiment of this application. Figure 2 ; Figure 10 This is a schematic diagram of the film structure of a first transistor provided in an embodiment of this application; Figure 11 This is a schematic diagram of the film layer structure of a display panel provided in an embodiment of this application. Figure 5 ; Figure 12 This is a top view of a first transistor provided in an embodiment of this application. Figure 3 ; Figure 13 This is a flowchart of a method for manufacturing a display panel provided in an embodiment of this application. Figure 1 ; Figure 14 This is a schematic diagram of the film layer structure of a display panel provided in an embodiment of this application. Figure 6 ; Figure 15 This is a top view of a second transistor provided in an embodiment of this application. Figure 1 ; Figure 16 This is a schematic diagram of the film layer structure of a display panel provided in an embodiment of this application. Figure 7 ; Figure 17 This is a schematic diagram of the circuit structure of a pixel circuit provided in an embodiment of this application. Figure 2 ; Figure 18 This is a schematic diagram of the film layer structure of a display panel provided in an embodiment of this application. Figure 8 ; Figure 19 This is a top view of a second transistor provided in an embodiment of this application. Figure 2 ; Figure 20 This is a schematic diagram of the film layer structure of a display panel provided in an embodiment of this application. Figure 9 ; Figure 21 This is a top view of a second transistor provided in an embodiment of this application. Figure 3 ; Figure 22 This is a flowchart of a method for manufacturing a display panel provided in an embodiment of this application. Figure 2 ; Figure 23 This is a schematic diagram of the film layer structure of a display panel provided in an embodiment of this application. Figure 10 ; Figure 24 This is a schematic diagram of the film layer structure of a display panel provided in an embodiment of this application. Figure 10 one; Figure 25 This is a schematic diagram of the structure of a display device provided in an embodiment of this application. Detailed Implementation

[0013] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of protection of the present application.

[0014] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0015] This application provides a display panel, including: a substrate and a circuit functional layer located on one side of the substrate; the circuit functional layer includes a plurality of pixel circuits located in the display area. At least a portion of the pixel circuit includes a first transistor and a light-emitting element; the first transistor includes a first active structure, a first gate, and a second gate, the first gate being located on the side of the first active structure closer to the substrate, and the second gate being located on the side of the first active structure farther from the substrate; the circuit functional layer further includes a first conductive structure located on the side of the second gate farther from the substrate; wherein, the first conductive structure includes a first overlapping portion; along a direction perpendicular to the plane of the substrate, the first overlapping portion overlaps with the overlapping area of ​​the first gate and the second gate of the same first transistor, and the first overlapping portion overlaps with the first gate and the second gate of the same first transistor; and / or, at least a portion of the pixel circuit includes a second transistor and a light-emitting element; the second transistor includes a second active structure, a third gate, and a fourth gate, the third gate being located on the side of the second active structure closer to the substrate, and the fourth gate being located on the side of the second active structure farther from the substrate; the circuit functional layer further includes a second conductive structure located on the side of the fourth gate farther from the substrate; wherein, the second conductive structure includes a second overlapping portion; along a direction perpendicular to the plane of the substrate, the second overlapping portion overlaps with the overlapping area of ​​the third gate and the second active structure of the same second transistor, and the second overlapping portion overlaps with the third gate and the second active structure of the same second transistor.

[0016] By employing the above technical solution, a transistor with a dual-gate structure is set in the pixel circuit, and the first overlapping portion of the first conductive structure overlaps with the first gate and the second gate of the same first transistor, so that the first gate and the second gate of the first transistor are electrically connected. This is beneficial to increase the on-state current of the first transistor, improve the switching speed of the first transistor, and realize high-frequency refresh. At the same time, along the direction perpendicular to the plane of the substrate, the overlapping area of ​​the first overlapping portion of the first conductive structure with the overlapping area of ​​the first gate and the second gate of the same first transistor can make the first extension area of ​​the first gate and the second extension area of ​​the second gate overlap along the direction perpendicular to the plane of the substrate. This can improve the performance of the first transistor while reducing the extension area space occupied by the first transistor in the direction perpendicular to the plane of the substrate, thereby reducing the space occupied by the pixel circuit, which is beneficial to improving the resolution and thinness of the display panel.

[0017] By setting a second transistor with a dual-gate structure in the pixel circuit, and having the second overlapping portion of the second conductive structure overlap with the third gate and the second active structure of the same second transistor, the third gate of the second transistor and the source or drain region of the second active structure can be electrically connected. This helps to suppress the threshold voltage drift of the second transistor, improve its working stability, and extend its service life, thereby improving the display effect and reliability of the display panel 010. At the same time, along the direction perpendicular to the plane of the substrate, the second overlapping portion of the second conductive structure overlaps with the overlapping area of ​​the third gate and the second active structure of the same second transistor. This allows the first extension area of ​​the third gate and the third extension area of ​​the second active structure to overlap along the direction perpendicular to the plane of the substrate. This can improve the performance of the second transistor while reducing the space occupied by the extension area of ​​the second transistor in the direction perpendicular to the plane of the substrate, thereby reducing the space occupied by the pixel circuit and improving the resolution and thinness of the display panel.

[0018] In addition, when the display panel is a transparent display panel or a partially transparent display panel, it is also beneficial to improve the light transmittance of the display panel.

[0019] The above is the core idea of ​​this application. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application. The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings.

[0020] It should be noted that the implementation methods provided in this application can be combined with each other without contradiction.

[0021] Figure 1 This is a top view schematic diagram of a display panel provided in an embodiment of this application. Figure 1 , Figure 2 This is a schematic diagram of the film layer structure of a display panel provided in an embodiment of this application. Figure 1 , Figure 2 It can be Figure 1 A cross-sectional view of the central display panel 010 along the dotted line A-A'. (Reference) Figure 1 and Figure 2 The display panel 010 includes a substrate 100 and a circuit functional layer 200 located on one side of the substrate 100. The circuit functional layer 200 includes a plurality of pixel circuits 201 located in the display area AA. At least some of the pixel circuits 201 include a first transistor M01 and a light-emitting element D1. The first transistor M01 includes a first gate 001, a second gate 002, and a first active structure 003. The first gate 001 is located on the side of the first active structure 003 closer to the substrate 100, and the second gate 002 is located on the side of the first active structure 003 away from the substrate 100.

[0022] Figure 3 This is a top view of a first transistor provided in an embodiment of this application. Figure 1 , Figure 3 The cross-sectional structure of the first transistor M01 along the dashed line B-B' is as follows Figure 2 As shown. Reference Figure 2 and Figure 3 The circuit functional layer 200 also includes a first conductive structure 202 located on the side of the second gate 002 away from the substrate 100, wherein the first conductive structure 202 includes a first overlapping portion J1; along the direction perpendicular to the plane where the substrate 100 is located, the first overlapping portion J1 overlaps with the overlapping area of ​​the first gate 001 and the second gate 002 of the same first transistor M01, and the first overlapping portion J1 overlaps with the first gate 001 and the second gate 002 of the same first transistor M01.

[0023] The substrate 100 includes a rigid substrate or a flexible substrate. The rigid substrate is made of materials including, but not limited to, glass and silicon. The flexible substrate is made of materials including, but not limited to, polyimide (PI), polyethylene terephthalate (PET), and polymethyl methacrylate (PMMA). The pixel circuit 201 located in the display area AA includes, but is not limited to, pixel circuits such as 2T1C, 6T2C, 7T1C, and 8T1C. The first transistor M01 can be any transistor in the pixel circuit 201; the first transistor M01 can be an LTPS-TFT or an IGZO-TFT; the first transistor M01 can be a P-type transistor or an N-type transistor. This application embodiment does not limit the location of the first transistor M01 in the pixel circuit 201, the material of the active structure, or the channel type. The light-emitting element D1 includes, but is not limited to, OLED and LED light-emitting structures.

[0024] Specifically, the first transistor M01 is a dual-gate transistor, and the first gate 001 is an additional gate of the first transistor M01. By setting the first gate 001, the first transistor M01 can have better channel charge control capability. The second gate 002 is the driving gate of the first transistor M01, and the potential of the second gate 002 can control the on and off states of the first transistor M01. The first conductive structure 202 can be used to transmit the gate driving signal and provide the gate driving signal to the second gate 002 to control the potential of the second gate 002. The first overlapping portion J1 of the first conductive structure 202 can overlap with the second extension region EZ2 of the second gate 002 to achieve a reliable electrical connection between the first conductive structure 202 and the second gate 002.

[0025] In particular, along the direction perpendicular to the plane where the substrate 100 is located, the first overlapping portion J1 of the first conductive structure 202 also overlaps with the first extension region EZ1 of the first gate 001, so that the first conductive structure 202 can also provide a gate drive signal to the first gate 001 to control the potential of the first gate 001; at the same time, the first gate 001 and the second gate 002 can be electrically connected through the first overlapping portion J1, so that the potentials of the first gate 001 and the second gate 002 are the same, which is beneficial to increase the on-state current of the first transistor M01 and improve the switching speed. Furthermore, along the direction perpendicular to the plane of the substrate 100, the first overlapping portion J1 overlaps with the overlapping area of ​​the first gate 001 and the second gate 002 of the same first transistor M01. That is, the first overlapping portion J1 overlaps simultaneously with the first extension area EZ1 of the first gate 001 and the second extension area EZ2 of the second gate 002. The newly added extension area (first extension area EZ1) overlaps with the original extension area (second extension area EZ2), eliminating the need for additional space for overlapping the newly added gate (first gate 001). This is beneficial for improving the performance of the first transistor M01 while reducing the impact on the arrangement of the pixel circuit 201 in the display panel 010, thereby improving resolution and thinning. It avoids increasing the extension area space occupied by the first transistor M01 in the direction perpendicular to the plane of the substrate 100, which would affect the arrangement of the pixel circuit 201 in the display panel 010 and be detrimental to improving the performance of the display panel.

[0026] Continue to refer to Figure 2 and Figure 3 The first active structure 003 includes a third extension region EZ3 and a fourth extension region EZ4. The first transistor M01 includes four extension regions (first extension region EZ1, second extension region EZ2, third extension region EZ3 and fourth extension region EZ4). However, the vertical projections of the first extension region EZ1 and the second extension region EZ2 onto the plane of the substrate 100 overlap, so that the vertical projection of the first transistor M01 onto the plane of the substrate 100 occupies only three extension region spaces. While improving the performance of the first transistor M01, it can also effectively reduce the space occupied, thereby improving the performance of the display panel 010.

[0027] For example, the display panel 010 also includes a protective layer 012 disposed between the substrate 100 and the circuit functional layer 200 and adjacent to the substrate 100. The protective layer 012 includes, but is not limited to, film structures such as a barrier layer, a transition layer, and a buffer layer, which can reduce or prevent foreign matter, moisture, or external air from penetrating from the side of the substrate 100 away from the circuit functional layer 200 and provide a flat surface to the circuit functional layer 200.

[0028] When fabricating the first transistor M01 in the circuit functional layer 200, the first gate 001 can be formed first, then the first active structure 003 can be formed, and finally the second gate 002 can be formed. In the direction perpendicular to the plane where the substrate 100 is located, a part of the overlapping area of ​​the second gate 002 and the first gate 001 does not overlap with the first active structure 003 (the second extension area EZ2 and the first extension area EZ1 overlap, but neither of them overlaps with the first active structure 003). This part of the area can overlap with the first overlapping portion J1 of the first conductive structure 202 (both the second extension area EZ2 and the first extension area EZ1 overlap with the first overlapping portion J1).

[0029] After the first transistor M01 is fabricated (i.e., after the second gate 002 is formed), a first dielectric layer 210 can be formed on the side of the second gate 002 away from the substrate 100. Then, a first conductive structure 202 is formed on the side of the first dielectric layer 210 away from the substrate 100. The first overlapping portion J1 of the first conductive structure 202 can simultaneously overlap the second extension region EZ2 of the second gate 002 and the first extension region EZ1 of the first gate 001.

[0030] After forming the first conductive structure 202, a light-emitting element D1 can be fabricated on the side of the first conductive structure 202 away from the substrate 100. The light-emitting element D1 includes a first electrode LE1, a second electrode LE2, and a light-emitting layer LE3 located between the first electrode LE1 and the second electrode LE2. It is understood that the display panel 010 may also include structures such as an encapsulation layer 023, a touch function layer 300, an optical function layer 400, and a cover plate 500 located on the side of the light-emitting element D1 away from the substrate 100. These will not be described in detail in the embodiments of this application.

[0031] It is also understood that the pixel circuits 201 located in the display area AA in the circuit functional layer 200 may all include the first transistor M01, or only some of the pixel circuits 201 may include the first transistor M01. That is, the pixel circuits 201 located in a portion of the display area AA in the circuit functional layer 200 may not include the first transistor M01, while the pixel circuits 201 located in a portion of the display area AA in the circuit functional layer 200 may include the first transistor M01. In optional embodiments, all transistors in the pixel circuits 201 in the circuit functional layer 200 that have the first transistor M01 may be the first transistor M01. In other optional embodiments, the transistors in the pixel circuits 201 in the circuit functional layer 200 that have the first transistor M01 may also be partially the first transistor M01. That is, the pixel circuits 201 in the circuit functional layer 200 that have the first transistor M01 may also include other transistors that differ from one or more of the first transistor M01 in terms of film layer location, structure, material, and connection method, such as the second transistor M02 provided later.

[0032] In this configuration, along a direction perpendicular to the plane of the substrate 100, the first extension region EZ1 of the first gate 001 of the first transistor M01 and the second extension region EZ2 of the second gate 002 overlap, and both the first extension region EZ1 and the second extension region EZ2 simultaneously overlap with the first contact portion J1 of the first conductive structure 202. Regardless of which transistors in the display panel 010 are the first transistor M01, a first conductive structure 202 is provided directly above the side away from the substrate 100 (i.e., the overlapping area along the direction perpendicular to the plane of the substrate 100). Along a direction perpendicular to the plane of the substrate 100, the first contact portion J1 of the first conductive structure 202 simultaneously overlaps with the first extension region EZ1 of the first gate 001 and the second extension region EZ2 of the second gate 002 of the same first transistor M01. This improves transistor performance and effectively reduces space occupation, thus enhancing the performance of the display panel.

[0033] In this embodiment, by setting a first transistor with a dual-gate structure in the pixel circuit, and having the first overlapping portion of the first conductive structure overlap with the first gate and the second gate of the same first transistor, the first gate and the second gate of the first transistor can be electrically connected. This is beneficial for increasing the on-state current of the first transistor, improving the switching speed of the first transistor, and achieving high-frequency refresh. At the same time, along the direction perpendicular to the plane of the substrate, the first overlapping portion of the first conductive structure overlaps with the overlapping area of ​​the first gate and the second gate of the same first transistor. This allows the first extension area of ​​the first gate and the second extension area of ​​the second gate to overlap along the direction perpendicular to the plane of the substrate. This can improve the performance of the first transistor while reducing the space occupied by the extension area of ​​the first transistor in the direction perpendicular to the plane of the substrate, thereby reducing the space occupied by the pixel circuit and improving the resolution and thinness of the display panel. In addition, when the display panel is a transparent display panel or a partially transparent display panel, it is also beneficial for improving the light transmittance of the display panel.

[0034] In an optional embodiment, Figure 4 This is a top view schematic diagram of a display panel provided in an embodiment of this application. Figure 2 , Figure 5 This is a schematic diagram of the film layer structure of a display panel provided in an embodiment of this application. Figure 2 ,refer to Figure 4 and Figure 5The display area AA includes a functional device setting area FA and a main display area MA that at least partially surrounds the functional device setting area FA. The functional device setting area FA includes a pixel circuit 201 and functional devices 261 located on the side of the pixel circuit 201 near the substrate 100. The circuit functional layer 200 located in the functional device setting area FA includes a first transistor M01 and a first conductive structure 202 that overlaps with a first gate 001 and a second gate 002 of the same first transistor M01.

[0035] The functional device setting area FA includes, but is not limited to, the under-display camera area CUP and the fingerprint recognition area FR. When the functional device setting area FA is the under-display camera area CUP, the functional device 261 can be an image sensor to perform functions such as image capture, video recording, and facial recognition. When the functional device setting area FA is the fingerprint recognition area FR, the functional device 261 can be an optical sensor to perform fingerprint recognition. In one embodiment, along the direction perpendicular to the plane of the substrate 100, the functional device 261 does not overlap with the pixel circuit 201.

[0036] For example, taking the functional device setting area FA as the fingerprint recognition area FR, refer to... Figure 5 The circuit functional layer 200 of the display panel 010 also includes a photosensitive layer 260 located between the pixel circuit 201 and the substrate 100. The photosensitive layer 260 includes a functional device 261 (optical sensor) and a light guiding layer 262 located on the side of the functional device 261 away from the substrate 100. The light guiding layer 262 includes a light guiding opening 263. The functional device 261 (optical sensor) can perform fingerprint recognition by transmitting light through the light guiding opening 263. By setting a first transistor M01 and a first conductive structure 202 that overlaps with the first gate 001 and the second gate 002 of the same first transistor M01 in the circuit functional layer 200 of the functional device setting area FA, the space occupied by the pixel circuit 201 in the functional device setting area FA can be reduced, and the light transmittance of the photosensitive layer 260 in the functional device setting area FA away from the substrate can be increased, which is beneficial to improving the sensitivity and accuracy of fingerprint recognition.

[0037] In other alternative embodiments, the circuit functional layer located in the main display area may also be provided with a first transistor and a first conductive structure connected to the first gate and second gate of the same first transistor. Figure 5 (Not shown).

[0038] In another alternative embodiment, the first transistor M01 includes a driving transistor M3 and / or a switching transistor STFT; the driving transistor M3 is used to selectively provide a driving signal to the light-emitting element D1; the switching transistor STFT is used to selectively provide an electrical signal to the driving transistor M3 and / or the light-emitting element D1.

[0039] For example, Figure 6 This is a schematic diagram of the circuit structure of a pixel circuit provided in an embodiment of this application. Figure 1 ,refer to Figure 6 The pixel circuit 201 is a 7T1C pixel circuit. The pixel circuit 201 includes a first light-emitting control transistor M1, a write transistor M2, a drive transistor M3, a compensation transistor M4, an initialization transistor M5, a second light-emitting control transistor M6, a reset transistor M7, and a storage capacitor Cst. The switching transistor STFT includes the first light-emitting control transistor M1, the write transistor M2, the compensation transistor M4, the initialization transistor M5, the second light-emitting control transistor M6, and the reset transistor M7. The drive transistor M3 and / or the switching transistor STFT in the pixel circuit 201 can be configured as the first transistor M01, making this part of the transistor a dual-gate transistor. Along a direction perpendicular to the substrate 100, the first extension region EZ1 of the first gate 001 and the second extension region EZ2 of the second gate 002 overlap, both overlapping with the first overlapping portion J1 of the first conductive structure 202. In one embodiment, at least a portion of the driving transistor M3, compensation transistor M4, and initialization transistor M5 in the pixel circuit 201 are first transistors M01; in another embodiment, at least a portion of the transistors in the pixel circuit 201 are all configured as first transistors M01; in yet another embodiment, at least a portion of the driving transistor M3 in the pixel circuit 201 is configured as first transistor M01.

[0040] It should be noted that, Figure 6 The diagram only shows one example of the circuit structure of the pixel circuit 201, but it is not limited to this. At least one of the driving transistor M3 and the switching transistor STFT in the pixel circuit 201 can be a first transistor M01, and its first gate 001 and second gate 002 can both be connected to the first overlapping portion J1 of the first conductive structure 202.

[0041] In yet another alternative embodiment, the first active structure 003 of the first transistor M01 comprises a metal oxide material.

[0042] Among them, the metal oxide materials include, but are not limited to, IGZO, such as one or more oxide materials selected from indium (In), gallium (Ga), tin (Sn), zirconium (Zr), hafnium (Hf), titanium (Ti) and zinc (Zn).

[0043] For example, metal oxide materials can be prepared using physical vapor deposition (PVD) techniques, such as magnetron sputtering, without the need for crystallization to form a crystal structure. This results in better uniformity of the metal oxide materials, which is beneficial for increasing the consistency of the performance of each pixel circuit 201. In addition, the preparation difficulty and cost of metal oxide materials are relatively low. Moreover, using metal oxide materials as active structures can reduce leakage current through their wide bandgap and interface state density.

[0044] Based on the above embodiments, the first active structure 003 of the first transistor M01 is a linear design. This helps to reduce the channel width-to-length ratio, further reducing the space occupied by the first transistor M01; and when the first active structure 003 includes a metal oxide material, the uniformity of the first active structure 003 is better, enabling the first transistor M01 to have higher mobility and lower leakage current, meeting usage requirements without the need for a long channel width-to-length ratio.

[0045] Optional, Figure 7 This is a schematic diagram of the film layer structure of a display panel provided in an embodiment of this application. Figure 3 ,refer to Figure 7 The circuit functional layer 200 further includes a first dielectric layer 210 located between the second gate 002 and the first conductive structure 202, and a second dielectric layer 220 located between the first gate 001 and the second gate 002. The first dielectric layer 210 includes a first etched hole H01, the second dielectric layer 220 includes a second etched hole H02, and the second gate 002 includes a third etched hole H03; wherein, along a direction perpendicular to the plane of the substrate 100, the first etched hole H01, the second etched hole H02, and the third etched hole H03 overlap simultaneously; a first overlapping portion J1 is provided in each of the first etched hole H01, the second etched hole H02, and the third etched hole H03.

[0046] Specifically, the first overlapping portion J1 can overlap with the second gate 002 through the first etched hole H01. The first overlapping portion J1 can also overlap with the first gate 001 through the first etched hole H01, the second etched hole H02, and the third etched hole H03. Along the direction perpendicular to the plane of the substrate 100, the first etched hole H01, the second etched hole H02, and the third etched hole H03 overlap simultaneously. The first etched hole H01, the second etched hole H02, and the third etched hole H03 can form a composite via penetrating the first dielectric layer 210, the second gate 002, and the second dielectric layer 220. This helps to reduce the number of vias in the first dielectric layer 210, eliminating the need to additionally provide vias for overlapping the first gate 001 in the first dielectric layer 210. This helps to reduce the space occupied by the pixel circuit 201, thereby improving the performance of the display panel 010.

[0047] For example, when forming the second gate 002, the third etch hole H03 can be formed in the same process; when exposing and developing the surface of the first dielectric layer 210 and etching the first dielectric layer 210 to form the first etch hole H01, the second dielectric layer 220 located between the second gate 002 and the first gate 001 can also be etched through the third etch hole H03 of the second gate 002 in the same process to form the second etch hole H02. The first etched hole H01 of the first dielectric layer 210 and the second etched hole H02 of the second dielectric layer 220 can be formed in the same process. On the one hand, this helps to reduce the number of processes, eliminating the need to form the first etched hole H01 and the second etched hole H02 in two separate processes, which helps to improve the fabrication efficiency and reduce the fabrication cost. On the other hand, using the second gate 002 as a mask to form the second etched hole H02 can reduce the precision requirements in the fabrication process, eliminating the need to consider the alignment problem between the third etched hole H03 and the second etched hole H02 of the second dielectric layer 220 (if the first etched hole H01 and the second etched hole H02 are formed in two separate processes, the precision requirements in the fabrication process need to be increased to ensure that the third etched hole H03 is aligned with the second etched hole H02), which helps to reduce the fabrication difficulty and production cost.

[0048] In an alternative embodiment, reference continues. Figure 7 The diameter of the first etched hole H01 on the side closer to the substrate 100 is less than or equal to the diameter of the first etched hole H01 on the side farther from the substrate 100.

[0049] For example, along the direction perpendicular to the plane of the substrate 100, the diameter of the first etched hole H01 is smaller the closer it is to the substrate 100. In this way, when the first overlapping portion J1 is formed, the first overlapping portion J1 can be effectively attached to the sidewall of the first etched hole H01, thereby improving the reliability of the first overlapping portion J1 overlapping with the first gate 001 and the second gate 002.

[0050] Based on the above embodiments, continue to refer to Figure 7 The angle α between the sidewall of the first etched hole H01 and the plane of the substrate 100 facing the first dielectric layer 210 is less than or equal to 90°, which can ensure that the first overlapping part J1 will not break when it is on the sidewall of the first etched hole H01, thus preventing an open circuit.

[0051] In another alternative embodiment, reference continues... Figure 7 The diameter of the second etched hole H02 on the side closer to the substrate 100 is less than or equal to the diameter of the second etched hole H02 on the side farther from the substrate 100.

[0052] For example, along the direction perpendicular to the plane of the substrate 100, the diameter of the second etched hole H02 is smaller the closer it is to the substrate 100. In this way, when the first overlapping portion J1 is formed, the first overlapping portion J1 can be effectively attached to the sidewall of the second etched hole H02, thereby improving the reliability of the first overlapping portion J1 and the first gate 001 overlapping.

[0053] Based on the above embodiments, continue to refer to Figure 7 The angle β between the sidewall of the second etched hole H02 and the plane of the substrate 100 facing the second dielectric layer 220 is less than or equal to 90°, which can ensure that the first overlapping part J1 will not break when it is on the sidewall of the second etched hole H02, thus preventing an open circuit.

[0054] In another alternative embodiment, the minimum diameter of the third etched hole H03 is greater than or equal to 1.5 μm.

[0055] For example, along the direction perpendicular to the plane of the substrate 100, the closer to the substrate 100, the smaller the diameter of the third etched hole H03. The minimum diameter of the third etched hole H03 is the diameter of the side of the third etched hole H03 closest to the substrate 100. The second gate 002 can serve as a mask layer or protective layer for forming the lower second etched hole H02. By limiting the minimum diameter of the third etched hole H03 to be greater than or equal to 1.5 μm, the maximum diameter of the lower third etched hole H03 can be limited. When the process of forming the second etched hole H02 is determined, the sidewall slope of the second etched hole H02 and the thickness of the second dielectric layer 220 can be determined. By limiting the minimum diameter of the third etched hole H03 (i.e., the maximum diameter of the second etched hole H02) to be greater than or equal to 1.5 μm, the minimum diameter of the second etched hole H02 can be determined, avoiding the second etched hole H02 from having too small a minimum diameter or not exposing the lower first gate 001, which would affect the reliability of the contact connection between the first overlapping portion J1 and the first gate 001.

[0056] In another alternative embodiment, the diameter of the first etched hole H01 closest to the substrate 100 is greater than the diameter of the third etched hole H03 furthest from the substrate 100.

[0057] Specifically, the minimum aperture of the first etched hole H01 is larger than the maximum aperture of the third etched hole H03, so that the first etched hole H01 can completely cover the third etched hole H03 and expose part of the second gate 002. Thus, when the first etched hole H01, the third etched hole H03, and the second etched hole H02 form the first overlapping portion J1, the first overlapping portion J1 can be formed on the surface of the second gate 002 away from the substrate 100. This allows the first overlapping portion J1 to not only contact and connect with the sidewall of the second gate 002 (i.e., the sidewall of the third etched hole H03), but also to contact and connect with the surface of the second gate 002 away from the substrate 100. This helps to increase the contact area between the first overlapping portion J1 and the second gate 002, reduce the contact resistance, and increase the overlapping reliability between the first overlapping portion J1 and the second gate 002.

[0058] Based on the above embodiments, continue to refer to Figure 7 The distance between the edge of the first etch hole H01 closest to the substrate 100 and the edge of the third etch hole H03 furthest from the substrate 100 is ΔDT1, wherein ΔDT1 is greater than or equal to the thickness of the second gate 002 and less than or equal to 0.5μm.

[0059] For example, the thickness of the second gate 002 is typically 0.3 μm. By setting ΔDT1 to be greater than or equal to the thickness of the second gate 002, the contact area between the first overlapping portion J1 and the surface of the second gate 002 away from the substrate 100 can be effectively increased, reducing the contact resistance. At the same time, ΔDT1 ≤ 0.5 μm is beneficial to reducing the area of ​​the extension region of the second gate 002 and the aperture size of the first etched hole H01, thereby reducing the space occupied by the first transistor M01.

[0060] Optional, Figure 8 This is a schematic diagram of the film layer structure of a display panel provided in an embodiment of this application. Figure 4 , Figure 9 This is a top view of a first transistor provided in an embodiment of this application. Figure 2 , Figure 9 The cross-sectional structure of the first transistor M01 along the dashed line C-C' is as follows Figure 8 As shown. Reference Figure 8 and Figure 9 Along a direction perpendicular to the plane of substrate 100, the first gate 001 and the second gate 002 overlap. The dimensions of the first gate 001 and the second gate 002 in the first direction DR1 are different; the first direction DR1 is parallel to the plane of substrate 100.

[0061] The first direction DR1 may intersect or be parallel to the direction of the channel length of the first active structure 003. In this embodiment, the direction of the first direction DR1 is not specifically limited. In one embodiment, the first direction DR1 may be the column direction (second direction X) of the display panel 010; in another embodiment, the first direction DR1 may be the row direction (third direction Y) of the display panel 010; in yet another embodiment, the first direction DR1 may also be a direction that intersects both the column direction (second direction X) and the row direction (third direction Y).

[0062] Specifically, both the first gate 001 and the second gate 002 are made of metallic materials. Due to factors such as geometric stress concentration and mismatch in mechanical properties between materials, the inorganic dielectric layer at the step edges of the first gate 001 and the second gate 002 is prone to cracking. This is especially true when the display panel 010 is bumped or impacted, as cracks in the inorganic dielectric layer can affect the electrical connection stability of conductive structures in other film layers, increase connection impedance, and cause reliability issues. This problem is particularly prominent in dual-gate structures. Typically, the two gates in a dual-gate structure are designed with the same size, or even fabricated using the same mask. When the size and placement of the two gates are exactly the same, the cracking effect of the inorganic dielectric layer at the step slope of the two gates will be superimposed in the vertical space, exacerbating the unreliability caused by the cracks. This application embodiment improves the unreliability caused by the crack effect at the step slope edge of the first gate 001 and the second gate 002 of the first transistor M01 by setting the dimensions of the first gate 001 and the second gate 002 to be different in the first direction DR1. It avoids the crack effect at the step slope edge of the first gate 001 and the second gate 002 from superimposing in the longitudinal space, causing serious consequences and affecting the performance of the display panel 010.

[0063] For example, the orthographic projection of the first gate 001 onto the plane of the substrate 100 is the first projection, and the orthographic projection of the second gate 002 onto the plane of the substrate 100 is the second projection. The minimum distance MD between the edge of the first projection and the edge of the second projection of the same first transistor M01 is greater than or equal to 0.5 μm. By limiting the minimum distance MD between the edge of the first projection and the edge of the second projection to be greater than or equal to 0.5 μm, the stepped slope edges of the first gate 001 and the second gate 002 can be staggered in the vertical space. This effectively improves the unreliability caused by cracks at the stepped slope edges of the first gate 001 and the second gate 002, and avoids the edges of the stepped slopes of the first gate 001 and the second gate 002 being too close in the vertical space, which would cause the crack effects of the first gate 001 and the second gate 002 to superimpose in the vertical space and increase unreliability.

[0064] In an alternative embodiment, reference continues. Figure 8 and Figure 9 The size of the second gate 002 in the first direction DR1 is larger than the size of the first gate 001 in the first direction DR1.

[0065] For example, the vertical projection of the second gate 002 onto the plane of the substrate 100 can cover the vertical projection of the first gate 001 onto the plane of the substrate 100, and the vertical projection of the second extension region EZ2 onto the plane of the substrate 100 can also cover the vertical projection of the first extension region EZ1 onto the plane of the substrate 100. By increasing the size of the upper second gate 002, it is beneficial to reduce the number of metal step slopes directly exposed on the side of the light-emitting layer, encapsulation layer, and touch layer, thereby reducing the impact of inorganic dielectric layer cracking effect on the electrode layer, light-emitting layer, encapsulation layer, touch layer, and other film layers.

[0066] The crack effect of the inorganic dielectric layer at the step slope edge of the lower first gate 001 may affect the upper second gate 002, but the impact is small. On the one hand, the step slope edge of the lower first gate 001 is usually located near the edge of the second gate 002 in the vertical space. Even if the crack effect of the inorganic dielectric layer at the step slope edge of the first gate 001 affects the electrical connection of the second gate 002, it only affects the structural integrity near the edge of the second gate 002 and does not affect the core (functional, actually used for electrical connection) area of ​​the second gate 002. Therefore, it will not affect the performance of the first transistor M01. On the other hand, the first gate 001 and the second gate 002, which overlap in the direction perpendicular to the plane of the substrate 100, are usually close in the vertical space. Even if there is a crack in the inorganic dielectric layer between them, the crack is usually not too large, and the adverse effect is far less than the impact on the electrode layer, light-emitting layer, encapsulation layer, touch layer and other film layers. Therefore, by setting the size of the second gate 002 in the first direction DR1 to be larger than the size of the first gate 001 in the first direction DR1, the problem of poor reliability caused by the crack effect of the first gate 001 and the second gate 002 of the first transistor M01 can be effectively improved.

[0067] In another alternative embodiment, Figure 10 This is a schematic diagram of the film structure of a first transistor provided in an embodiment of this application, with reference to... Figure 10 The second gate 002 includes a first deposition layer DL1 and a second deposition layer DL2; wherein the first deposition layer DL1 is located on the side of the second deposition layer DL2 close to the substrate 100, and the Young's modulus of the first deposition layer DL1 is smaller than the Young's modulus of the second deposition layer DL2.

[0068] Young's modulus is a physical quantity that measures a material's ability to resist tensile or compressive deformation within its elastic range, and its unit is Pascal (Pa), megapascal (MPa), or gigapascal (GPa). Materials with a low Young's modulus generally have better plasticity, are easier to stretch, and are less prone to fracture. By setting a first deposition layer DL1 with a low Young's modulus on the side of the second gate 002 closest to the substrate 100, it is beneficial to reduce the impact of crack effects at the step slope edge of the lower first gate 001 on the upper second gate 002. Moreover, setting the first deposition layer DL1 only in the upper second gate 002 helps to reduce fabrication steps and lower fabrication costs.

[0069] For example, the first gate 001 and the second deposition layer DL2 may include molybdenum (Mo) metal, and the first deposition layer DL1 may include titanium (Ti) material.

[0070] Optional, Figure 11 This is a schematic diagram of the film layer structure of a display panel provided in an embodiment of this application. Figure 5 , Figure 12 This is a top view of a first transistor provided in an embodiment of this application. Figure 3 ,refer to Figure 11 and Figure 12 The circuit functional layer 200 also includes a first signal trace SL1 located on the side of the first transistor M01 near the substrate 100, and the first signal trace SL1 is electrically connected to multiple pixel circuits 201. Figure 11 and Figure 12 (not shown in the image); along a direction perpendicular to the plane of substrate 100, the first signal trace SL1 overlaps simultaneously with the first gate 001 and the second gate 002 of multiple first transistors M01.

[0071] The first signal trace SL1 is used to transmit electrical signals and provide electrical signals to the pixel circuit 201. In one embodiment, the first signal trace SL1 extends along the row direction (third direction Y) and can be electrically connected to multiple pixel circuits 201 located in the same row. For example, the first signal trace SL1 is a scan trace used to transmit signals such as write control signal S2P, compensation control signal S2N, initialization control signal S1N, and reset control signal S1P. In another embodiment, the first signal trace SL1 extends along the column direction (second direction X) and can be electrically connected to multiple pixel circuits 201 located in the same column. For example, the first signal trace SL1 is used to transmit signals such as write data signal Data, initialization signal VREF1, and reset signal VREF2.

[0072] For example, taking the first signal line SL1 as an example, which is electrically connected to the gates of the other transistors in the pixel circuit 201 except for the first transistor M01, and the first signal line SL1 can provide gate drive signals to the gates of the other transistors, refer to... Figure 11 In the pixel circuit 201, at least a portion of the switching transistors STFTs are not configured as the first transistor M01. These STFTs include a switching gate 004 and a switching active structure 005, wherein both the switching gate 004 and the switching active structure 005 may be located on the side of the first transistor M01 closest to the substrate 100. In one embodiment, the first signal trace SL1 may be disposed on the same layer as the switching gate 004. Furthermore, the switching gate 004 may also reuse the first signal trace SL1. Figure 11 (Not shown in the image).

[0073] Continue to refer to Figure 11 and Figure 12 The first signal trace SL1 is located on the side of the first transistor M01 closest to the substrate 100. This reduces the impact of crack effects on the first gate 001 and the second gate 002 of the first transistor M01, preventing the first signal trace SL1 from breaking due to crack effects on the first gate 001 and / or the second gate 002, thus affecting the electrical connection of the first signal trace SL1. Furthermore, along a direction perpendicular to the plane of the substrate 100, the first signal trace SL1 overlaps simultaneously with the first gate 001 and the second gate 002 of multiple first transistors M01, saving space in the circuit functional layer 200, increasing light transmittance, and also contributing to the high resolution and thinness of the display panel 010. In one embodiment, the size of the first signal trace SL1 in the first direction DR1 is different from the size of the second gate 002 in the first direction DR1, and / or the size of the first signal trace SL1 in the first direction DR1 is different from the size of the first gate 001 in the first direction DR1, to avoid the superposition of crack effects at the stepped slope edge of the first signal trace SL1 in the longitudinal space, which could cause serious consequences and affect the performance of the display panel 010.

[0074] In an alternative embodiment, reference continues. Figure 12 The size of the first signal trace SL1 in the second direction X is smaller than the size of the second gate 002 in the second direction X; the second direction X is parallel to the plane where the substrate 100 is located and intersects with the extension direction of the first signal trace SL1.

[0075] For example, the first signal trace SL1 extends along the row direction, and the second direction X can be the column direction. The first signal trace SL1 can be electrically connected to multiple pixel circuits 201 located in the same row. Along the extension direction of the first signal trace SL1, the size of the first signal trace SL1 is usually larger than the size of the second gate 002. By setting the size of the first signal trace SL1 to be smaller than the size of the second gate 002 along the second direction X, it is beneficial to reduce the number of metal step slopes directly exposed on the side of the light-emitting layer, encapsulation layer, and touch layer, thereby reducing the impact of inorganic dielectric layer crack effect on the electrode layer, light-emitting layer, encapsulation layer, touch layer, and other film layers.

[0076] It is understood that in other alternative implementations, the first signal trace may also extend along the column direction, and the second direction may be the row direction.

[0077] In another alternative embodiment, reference continues... Figure 12 The size of the first signal trace SL1 in the second direction X is smaller than the size of the first gate 001 in the second direction X. The second direction X is parallel to the plane where the substrate 100 is located and intersects with the extension direction of the first signal trace SL1. This also helps to reduce the number of metal step slopes directly exposed on the side of the light-emitting layer, the encapsulation layer, and the touch layer, thereby reducing the impact of inorganic dielectric layer cracking effect on the electrode layer, the light-emitting layer, the encapsulation layer, the touch layer, and other film layers.

[0078] For example, along the second direction X, the size of the first signal trace SL1 is smaller than the size of the first gate 001, and the size of the first gate 001 is smaller than the size of the second gate 002. This helps to reduce the number of metal step ramps directly exposed to the second gate 002 and improve the reliability of the second gate 002.

[0079] In another optional embodiment, the first signal trace SL1 includes a first edge LS1 and a second edge LS2 disposed opposite each other along a third direction Y, the third direction Y being parallel to the extension direction of the first signal trace SL1. The orthographic projection of the first gate 001 onto the plane of the substrate 100 is the first projection, and the orthographic projection of the second gate 002 onto the plane of the substrate 100 is the second projection. The orthographic projections of the first edge LS1 and the second edge LS2 onto the plane of the substrate 100 are covered by the first projection, and the minimum distance between the first edge LS1 and the edge of the first projection and the minimum distance between the second edge LS2 and the edge of the first projection are both greater than zero; and / or, the orthographic projections of the first edge LS1 and the second edge LS2 onto the plane of the substrate 100 are covered by the second projection, and the minimum distance between the first edge LS1 and the edge of the second projection and the minimum distance between the second edge LS2 and the edge of the second projection are both greater than zero.

[0080] Specifically, along the direction perpendicular to the plane of substrate 100, both the first edge LS1 and the second edge LS2 overlap with the first gate 001, and the distance between the first edge LS1 and the second edge LS2 and the edge of the first gate 001 along the direction perpendicular to the plane of substrate 100 is greater than zero; and / or, along the direction perpendicular to the plane of substrate 100, both the first edge LS1 and the second edge LS2 overlap with the second gate 002, and the distance between the first edge LS1 and the second edge LS2 and the edge of the second gate 002 along the direction perpendicular to the plane of substrate 100 is greater than zero. In the longitudinal space (the direction perpendicular to the plane of substrate 100), the first edge LS1 and the second edge LS2 are recessed relative to the edge of the first gate 001 toward the first signal trace SL1 and / or the central region of the first gate 001; and / or, in the longitudinal space (the direction perpendicular to the plane of substrate 100), the first edge LS1 and the second edge LS2 are recessed relative to the edge of the second gate 002 toward the central region of the first signal trace SL1 and / or the second gate 002. This helps to reduce the number of metal steps and slopes directly exposed on the side away from the substrate 100, reduce the impact of inorganic dielectric layer cracking effect, and improve the reliability of display panel 010.

[0081] For example, the first signal trace SL1 can run through the display area AA in the third direction Y (row direction) and connect all pixel circuits 201 in the same row. Although the size of the first signal trace SL1 is larger than the size of the first gate 001 in the third direction Y (row direction), the first edge LS1 and the second edge LS2 of the first signal trace SL1 are recessed relative to the first gate 001 of the first transistor M01 located at the outermost side of all pixel circuits 201 in the same row; and / or, the first edge LS1 and the second edge LS2 of the first signal trace SL1 are recessed relative to the second gate 002 of the first transistor M01 located at the outermost side of all pixel circuits 201 in the same row. This can prevent the crack effect of the first edge LS1 and / or the second edge LS2 from affecting the film structure of the first transistor M01 on the side away from the substrate 100 (the crack effect of the first edge LS1 and the second edge LS2 has a small impact on the first gate 001 and the second gate 002 of the first transistor M01. Even if it does have an impact, it only affects the structural integrity near the edges of the first gate 001 and the second gate 002 and does not affect the core area of ​​the first gate 001 and the second gate 002).

[0082] It is understood that, in other alternative implementations, the second signal trace may run through the display area AA in the sixth direction (column direction) and connect all pixel circuits 201 in the same column.

[0083] Based on the same inventive concept, this application also proposes a method for preparing a display panel. Figure 2 , Figure 5 , Figure 7 , Figure 8 , Figure 11 The display panel shown. Figure 13 This is a flowchart of a method for manufacturing a display panel provided in an embodiment of this application. Figure 1 ,refer to Figure 13 The preparation methods include: S110. Provide a substrate, and sequentially fabricate a first gate, a first active structure, and a second gate on one side of the substrate; wherein the second gate includes a third etched hole.

[0084] For example, refer to Figure 2 , Figure 5 , Figure 7 , Figure 8 and Figure 11 Before fabricating the first gate 001, the first active structure 003, and the second gate 002 on one side of the substrate 100, structures such as a protective layer 012, a photosensitive layer 260, a switching active structure 005, a switching gate 004, a first signal trace SL1, and a dielectric layer disposed adjacent to these structures may be selectively formed. Then, the first gate 001 is formed first, followed by the first active structure 003, and finally the second gate 002. In one embodiment, a third etched hole H03 may be formed in the same process when forming the second gate 002.

[0085] S120, a first dielectric layer is formed on the surface of the second gate on the side away from the substrate.

[0086] For example, after the second gate 002 is formed, a first dielectric layer 210 can be formed on the side surface of the second gate 002 away from the substrate 100. The first dielectric layer 210 can fill and cover the third etched hole H03.

[0087] S130. A first photoresist layer is formed on the surface of the first dielectric layer away from the substrate, and the first photoresist layer is patterned; wherein, the first photoresist layer includes a first mask hole, and in a direction perpendicular to the plane of the substrate, the first mask hole overlaps with a third etching hole.

[0088] Specifically, a photolithography process can be used to pattern the entire first dielectric layer 210. In an optional embodiment, the minimum diameter of the first mask aperture is greater than the maximum diameter of the third etched aperture H03.

[0089] S140. Using the first photoresist as a mask, the first dielectric layer is etched through the first mask hole to form a first etching hole that exposes the third etching hole. Then, using the second gate as a mask, the second dielectric layer located between the first gate and the second gate is etched through the third etching hole to form a second etching hole that exposes the first gate.

[0090] For example, an etching process is used to form a first etch hole H01 located in the first dielectric layer 210. After the first etch hole H01 is formed, etching can continue. Using the second gate 002 as a mask, the second dielectric layer 220 located between the first gate 001 and the second gate 002 is etched to form a second etch hole H02 that exposes the first gate 001. In this way, the first etch hole H01 and the second etch hole H02 can be formed in one etching process.

[0091] S150, A first conductive structure is formed on the side of the first dielectric layer away from the substrate; the first conductive structure includes a first overlap portion, which overlaps with the first gate and the second gate of the same first transistor through a first etch hole, a third etch hole and a second etch hole.

[0092] For example, after forming the first etched hole H01 and the second etched hole H02, a full-layer conductive layer can be formed on the surface of the first dielectric layer 210 away from the substrate 100. The conductive layer can be formed on the surface of the first dielectric layer 210 away from the substrate 100, and the conductive layer can also be formed on the sidewalls of the first etched hole H01, the third etched hole H03, the second etched hole H02, and the exposed surface of the first gate 001 away from the substrate 100. Then, the conductive layer is patterned to obtain a first conductive structure 202 that overlaps with the first gate 001 and the second gate 002.

[0093] In this embodiment, the first etched hole in the first dielectric layer and the second etched hole in the second dielectric layer can be formed in the same process, which helps to reduce the number of processes. It eliminates the need to form the first etched hole and the second etched hole in two separate processes, thereby improving the fabrication efficiency and reducing the fabrication cost. At the same time, using the second gate as a mask to form the second etched hole can reduce the precision requirements in the fabrication process. It eliminates the need to consider the alignment problem between the third etched hole and the second etched hole in the second dielectric layer, which helps to reduce the fabrication difficulty and production cost.

[0094] The display panel manufacturing method provided in this application embodiment is used to manufacture the display panel provided in the above-mentioned embodiment of this application. It has the corresponding technical features and beneficial effects of the display panel. For the contents not described in detail in the embodiments of the display panel manufacturing method, please refer to the description of the display panel above, and they will not be repeated here. Similarly, the display panel of this application embodiment also has the functional modules and beneficial effects of executing the display panel manufacturing method provided in the embodiments of this application. For the contents not described in detail in the embodiments of the display panel, please refer to the description of the display panel manufacturing method above, and they will not be repeated here.

[0095] Based on the same inventive concept, embodiments of this application also provide another display panel. Figure 14This is a schematic diagram of the film layer structure of a display panel provided in an embodiment of this application. Figure 6 , Figure 14 It can be Figure 1 A cross-sectional view of the central display panel 010 along the dotted line A-A'. (Reference) Figure 1 and Figure 14 The display panel 010 includes a substrate 100 and a circuit functional layer 200 located on one side of the substrate 100; the circuit functional layer 200 includes a plurality of pixel circuits 201 located in the display area AA, at least some of the pixel circuits 201 include a second transistor M02 and a light-emitting element D1; the second transistor M02 includes a third gate 006, a fourth gate 007 and a second active structure 008, the third gate 006 is located on the side of the second active structure 008 close to the substrate 100, and the fourth gate 007 is located on the side of the second active structure 008 away from the substrate 100.

[0096] Figure 15 This is a top view of a second transistor provided in an embodiment of this application. Figure 1 , Figure 15 The cross-sectional structure of the second transistor M02 along the dashed line D-D' is as follows Figure 14 As shown. Reference Figure 14 and Figure 15 The circuit functional layer 200 also includes a second conductive structure 203 located on the side of the fourth gate 007 away from the substrate 100; wherein, the second conductive structure 203 includes a second overlapping portion J2; along the direction perpendicular to the plane where the substrate 100 is located, the second overlapping portion J2 overlaps with the overlapping area of ​​the third gate 006 and the second active structure 008 of the same second transistor M02, and the second overlapping portion J2 overlaps with the third gate 006 and the second active structure 008 of the same second transistor M02.

[0097] The pixel circuit 201 located in the display area AA includes, but is not limited to, pixel circuits such as 2T1C, 6T2C, 7T1C, and 8T1C. The second transistor M02 can be any transistor in the pixel circuit 201. The second transistor M02 can be an LTPS-TFT or an IGZO-TFT. The second transistor M02 can be a P-type transistor or an N-type transistor. In this embodiment, the placement of the second transistor M02 in the pixel circuit 201, the material of the active structure, and the channel type are not limited.

[0098] Specifically, the second transistor M02 is a dual-gate transistor, and the third gate 006 is an additional gate for the second transistor M02. By setting the third gate 006, the second transistor M02 can have better channel charge control capability. The fourth gate 007 is the driving gate of the second transistor M02, and the potential of the fourth gate 007 can control the on / off state of the second transistor M02. The second conductive structure 203 can be used to transmit source or drain signals and provide signals to the source or drain region of the second active structure 008. The second overlapping portion J2 of the second conductive structure 203 can overlap with the third extension region EZ3' of the second active structure 008 to achieve a reliable electrical connection between the second conductive structure 203 and the source or drain region of the second active structure 008.

[0099] In particular, along the direction perpendicular to the plane of the substrate 100, the second overlapping portion J2 of the second conductive structure 203 also overlaps with the first extension region EZ1' of the third gate 006, so that the second conductive structure 203 can also provide a signal to the third gate 006 to control the potential of the third gate 006; at the same time, the source region or drain region of the third gate 006 and the second active structure 008 can be electrically connected through the second overlapping portion J2, so that the potential of the third gate 006 and the source region or drain region of the second active structure 008 are the same, which helps to suppress the threshold voltage drift of the second transistor M02, improve its working stability, extend its service life, and thus improve the display effect and reliability of the display panel 010. Furthermore, along the direction perpendicular to the plane of the substrate 100, the second overlapping portion J2 overlaps with the overlapping area of ​​the second active structure 008 and the third gate 006 of the same second transistor M02. That is, the second overlapping portion J2 simultaneously overlaps with the third extension area EZ3' of the second active structure 008 and the first extension area EZ1' of the third gate 006. The newly added extension area (first extension area EZ1') overlaps with the original extension area (third extension area EZ3'), eliminating the need for additional space for overlapping the newly added gate (third gate 006). This is beneficial for improving the performance of the second transistor M02 while reducing the impact on the arrangement of the pixel circuit 201 in the display panel 010, thereby improving resolution and thinning. It avoids increasing the extension area space occupied by the second transistor M02 in the direction perpendicular to the plane of the substrate 100, which would affect the arrangement of the pixel circuit 201 in the display panel 010 and be detrimental to improving the performance of the display panel.

[0100] The fourth gate 007 includes a second extension region ( Figure 14 and Figure 15(Not shown) The second transistor M02 also includes four extension regions (first extension region EZ1', second extension region, third extension region EZ3' and fourth extension region EZ4'), but the vertical projections of the first extension region EZ1' and the third extension region EZ3' onto the plane of the substrate 100 overlap, so that the vertical projection of the second transistor M02 onto the plane of the substrate 100 only occupies the space of three extension regions. This can effectively reduce the space occupied while improving the performance of the second transistor M02, thereby improving the performance of the display panel 010.

[0101] For example, when fabricating the second transistor M02 in the circuit functional layer 200, a third gate 006 can be formed first, then a second active structure 008 can be formed, and finally a fourth gate 007 can be formed. In this case, along the direction perpendicular to the plane of the substrate 100, a portion of the overlapping area of ​​the second active structure 008 and the third gate 006 does not overlap with the fourth gate 007 (the third extension region EZ3' and the first extension region EZ1' overlap, but neither overlaps with the fourth gate 007). This portion of the area can overlap with the second overlap portion J2 of the second conductive structure 203 (both the third extension region EZ3' and the first extension region EZ1' overlap with the first overlap portion J1).

[0102] After the second transistor M02 is fabricated (i.e. after the fourth gate 007 is formed), the second conductive structure 203 is formed. The second overlapping portion J2 of the second conductive structure 203 can simultaneously overlap the third extension region EZ3' of the second active structure 008 and the first extension region EZ1' of the third gate 006.

[0103] After the second conductive structure 203 is formed, structures such as the light-emitting element D1, the encapsulation layer 023, the touch function layer 300, the optical function layer 400, and the cover plate 500 can be fabricated on the side of the second conductive structure 203 away from the substrate 100. These will not be described one by one in the embodiments of this application.

[0104] It is understood that the pixel circuits 201 located in the display area AA in the circuit functional layer 200 may all include the second transistor M02, or only some of the pixel circuits 201 may include the second transistor M02. That is, the pixel circuits 201 located in a portion of the display area AA in the circuit functional layer 200 may not include the second transistor M02, while the pixel circuits 201 located in a portion of the display area AA in the circuit functional layer 200 may include the second transistor M02. In optional embodiments, all transistors in the pixel circuits 201 in the circuit functional layer 200 that have the second transistor M02 may be the second transistor M02. In other optional embodiments, the transistors in the pixel circuits 201 in the circuit functional layer 200 that have the second transistor M02 may also be partially the second transistor M02. That is, the pixel circuits 201 in the circuit functional layer 200 that have the second transistor M02 may also include other transistors that differ from one or more of the second transistor M02 in terms of film layer location, structure, material, and connection method, such as the first transistor M01 provided above.

[0105] In this configuration, along a direction perpendicular to the plane of the substrate 100, the first extension region EZ1' of the third gate 006 of the second transistor M02 and the third extension region EZ3' of the second active structure 008 overlap, and both the first extension region EZ1' and the third extension region EZ3' simultaneously overlap with the second overlap portion J2 of the second conductive structure 203. Regardless of which transistors in the display panel 010 are the second transistor M02, a second conductive structure 203 is provided directly above the side away from the substrate 100 (i.e., the overlapping area along the direction perpendicular to the plane of the substrate 100). Along a direction perpendicular to the plane of the substrate 100, the second overlap portion J2 of the second conductive structure 203 simultaneously overlaps with the first extension region EZ1' of the third gate 006 of the same second transistor M02 and the third extension region EZ3' of the second active structure 008. This can improve transistor performance and effectively reduce space occupation, thereby improving the performance of the display panel.

[0106] In this embodiment, by setting a second transistor with a dual-gate structure in the pixel circuit, and having the second overlapping portion of the second conductive structure overlap with the third gate and the second active structure of the same second transistor, the third gate of the second transistor and the source or drain region of the second active structure can be electrically connected. This helps to suppress the threshold voltage drift of the second transistor, improve its working stability, and extend its service life, thereby improving the display effect and reliability of the display panel 010. At the same time, along the direction perpendicular to the plane of the substrate, the second overlapping portion of the second conductive structure overlaps with the overlapping area of ​​the third gate and the second active structure of the same second transistor. This allows the first extension area of ​​the third gate and the third extension area of ​​the second active structure to overlap along the direction perpendicular to the plane of the substrate. This can improve the performance of the second transistor while reducing the space occupied by the extension area of ​​the second transistor in the direction perpendicular to the plane of the substrate, thereby reducing the space occupied by the pixel circuit and improving the resolution and thinness of the display panel. In addition, when the display panel is a transparent display panel or a partially transparent display panel, it also helps to improve the light transmittance of the display panel.

[0107] In one optional embodiment, the display panel 010 may simultaneously have a first transistor M01 and a second transistor M02. Based on this, the same pixel circuit 201 may simultaneously have a first transistor M01 and a second transistor M02. In another optional embodiment, the display panel 010 may only have a second transistor M02. Based on this, the pixel circuit 201 may only have a second transistor M02. Similarly, the display panel 010 may also only have a first transistor M01. Based on this, the pixel circuit 201 may only have a first transistor M01.

[0108] It should be noted that the fill patterns and reference numerals in the figures can be used to distinguish different structures. Although Figure 14 The filling pattern of the third gate 006 and Figure 2 The first gate 001 has the same filling pattern, but the reference numerals are different, therefore, they can have different structures. Similarly, Figure 14 The fourth gate 007 and Figure 2 The second gate 002 can have different structures. Figure 14 The second active structure 008 and Figure 2 The first active structure 003 can be of different structures. Figure 14 The second conductive structure 203 and Figure 2 The first conductive structure 202 can be of different structures.

[0109] It should also be noted that the filling patterns in the figure are not used to distinguish film materials; that is, the same filling pattern can represent the same film material or different film materials. Although Figure 14The filling pattern of the third gate 006 and Figure 2 The filling pattern of the first gate 001 is the same, but the film materials of the two can be the same or different. This application embodiment... Figure 14 The third gate 006 and Figure 2 The relationship between the first gate 001 (e.g., film layer relationship, positional relationship, etc.) is not limited. In one embodiment, the third gate 006 and the first gate 001 can be made of the same film layer material. Based on this, the third gate 006 and the first gate 001 can be disposed in the same layer and formed in the same process. In another embodiment, the third gate 006 and the first gate 001 can also be made of different film layer materials. The third gate 006 and the first gate 001 can be disposed in different layers and formed in different processes.

[0110] Similarly, Figure 14 The fourth gate 007 and Figure 2 The film material of the second gate 002 can be the same or different. The embodiments of this application specify... Figure 14 The fourth gate 007 and Figure 2 The relationship between the second gate 002 (e.g., film layer relationship, positional relationship, etc.) is not limited; Figure 14 The second active structure 008 and Figure 2 The membrane material of the first active structure 003 can be the same or different, as described in the embodiments of this application. Figure 14 The second active structure 008 and Figure 2 The relationships between the first active structure 003 (e.g., film layer relationships, positional relationships, etc.) are not limited; Figure 14 The second conductive structure 203 and Figure 2 The film material of the first conductive structure 202 can be the same or different, as described in the embodiments of this application. Figure 14 The second conductive structure 203 and Figure 2 The relationships between the first conductive structures 202 (such as film layer relationships, positional relationships, etc.) are not limited.

[0111] In an optional embodiment, Figure 16 This is a schematic diagram of the film layer structure of a display panel provided in an embodiment of this application. Figure 7 ,refer to Figure 4 and Figure 16The display area AA includes a functional device setting area FA and a main display area MA that at least partially surrounds the functional device setting area FA. The functional device setting area FA includes a pixel circuit 201 and a functional device 261 located on the side of the pixel circuit 201 near the substrate 100. The circuit functional layer 200 located in the functional device setting area FA includes a second transistor M02 and a second conductive structure 203 that overlaps with the third gate 006 and the second active structure 008 of the same second transistor M02.

[0112] For example, taking the functional device setting area FA as the fingerprint recognition area FR, refer to... Figure 16 By setting a second transistor M02 and a second conductive structure 203 connected to the third gate 006 and the second active structure 008 of the same second transistor M02 in the circuit functional layer 200 of the functional device setting area FA, the space occupied by the pixel circuit 201 in the functional device setting area FA can be reduced, and the light transmittance of the photosensitive layer 260 in the functional device setting area FA away from the substrate can be increased, which is beneficial to improving the sensitivity and accuracy of fingerprint recognition.

[0113] In other alternative embodiments, the circuit functional layer located in the main display area may also be provided with a second transistor and a second conductive structure that overlaps with the third gate and the second active structure of the same second transistor. Figure 16 (Not shown).

[0114] In another optional embodiment, the second transistor M02 includes a driving transistor M3 and / or a switching transistor STFT; the driving transistor M3 is used to selectively provide a driving signal to the light-emitting element D1; the switching transistor STFT is used to selectively provide an electrical signal to the driving transistor M3 and / or the light-emitting element D1. Furthermore, if the pixel circuit 201 also includes a first transistor M01, the first transistor M01 may include any transistor other than the second transistor M02, that is, the first transistor M01 and the second transistor M02 do not share the same transistor.

[0115] For example, Figure 17 This is a schematic diagram of the circuit structure of a pixel circuit provided in an embodiment of this application. Figure 2 ,refer to Figure 17The pixel circuit 201 is a 7T1C pixel circuit. The pixel circuit 201 includes a first light-emitting control transistor M1, a write transistor M2, a drive transistor M3, a compensation transistor M4, an initialization transistor M5, a second light-emitting control transistor M6, a reset transistor M7, and a storage capacitor Cst. The switching transistor STFT includes the first light-emitting control transistor M1, the write transistor M2, the compensation transistor M4, the initialization transistor M5, the second light-emitting control transistor M6, and the reset transistor M7. The drive transistor M3 and / or the switching transistor STFT in the pixel circuit 201 can be configured as the second transistor M02, making this part of the transistor a dual-gate transistor. Along a direction perpendicular to the substrate 100, the first extension region EZ1' of the third gate 006 and the third extension region EZ3' of the second active structure 008 overlap, both overlapping with the second overlapping portion J2 of the second conductive structure 203. In one embodiment, at least some of the driving transistors M3, compensation transistors M4, and initialization transistors M5 in the pixel circuit 201 are second transistors M02; in another embodiment, all transistors in at least some of the pixel circuit 201 are configured as second transistors M02; in yet another embodiment, at least some of the driving transistors M3 in the pixel circuit 201 are configured as second transistors M02.

[0116] It should be noted that, Figure 17 The diagram only shows one example of the circuit structure of the pixel circuit 201, but it is not limited to this. At least one of the driving transistor M3 and the switching transistor STFT in the pixel circuit 201 can be the second transistor M02, and its third gate 006 and the second active structure 008 can both be connected to the second overlapping portion J2 of the second conductive structure 203.

[0117] In another optional embodiment, the second active structure 008 of the second transistor M02 includes a metal oxide material. Furthermore, if the pixel circuit 201 also includes a first transistor M01, and the first active structure 003 of the first transistor M01 also includes a metal oxide material, the second active structure 008 can be disposed on the same layer as the first active structure 003; furthermore, the third gate 006 can be disposed on the same layer as the first gate 001, and / or, the fourth gate 007 can be disposed on the same layer as the second gate 002.

[0118] Based on the above embodiments, the second active structure 008 of the second transistor M02 is a linear design. This helps to reduce the channel width-to-length ratio, further reducing the space occupied by the second transistor M02; and when the second active structure 008 includes a metal oxide material, it can achieve better uniformity, resulting in higher mobility and lower leakage current, thus meeting usage requirements without the need for a long channel width-to-length ratio.

[0119] Optional, Figure 18 This is a schematic diagram of the film layer structure of a display panel provided in an embodiment of this application. Figure 8 ,refer to Figure 18 The circuit functional layer 200 further includes a third dielectric layer 230 located between the second active structure 008 and the second conductive structure 203, and a fourth dielectric layer 240 located between the third gate 006 and the second active structure 008. The third dielectric layer 230 includes a fourth etched hole H04, the fourth dielectric layer 240 includes a fifth etched hole H05, and the second active structure 008 includes a sixth etched hole H06; wherein, along a direction perpendicular to the plane of the substrate 100, the fourth etched hole H04, the fifth etched hole H05, and the sixth etched hole H06 overlap simultaneously; a second overlapping portion J2 is provided in each of the fourth etched hole H04, the fifth etched hole H05, and the sixth etched hole H06.

[0120] Specifically, the second overlapping portion J2 can overlap with the second active structure 008 through the fourth etched hole H04, and the second overlapping portion J2 can also overlap with the third gate 006 through the fourth etched hole H04, the fifth etched hole H05, and the sixth etched hole H06. Along the direction perpendicular to the plane of the substrate 100, the fourth etched hole H04, the fifth etched hole H05, and the sixth etched hole H06 overlap simultaneously, and the fourth etched hole H04, the fifth etched hole H05, and the sixth etched hole H06 can form a composite via penetrating the third dielectric layer 230, the second active structure 008, and the third gate 006. In this way, it is beneficial to reduce the number of vias in the third dielectric layer 230, and there is no need to provide additional vias for overlapping the third gate 006 in the third dielectric layer 230. This is beneficial to reduce the space occupied by the pixel circuit 201, thereby improving the performance of the display panel 010.

[0121] For example, when forming the second active structure 008, the sixth etch hole H06 can be formed in the same process; when exposing and developing the surface of the third dielectric layer 230 and etching the third dielectric layer 230 to form the fourth etch hole H04, the fourth dielectric layer 240 located between the second active structure 008 and the third gate 006 can also be etched through the sixth etch hole H06 of the second active structure 008 in the same process to form the fifth etch hole H05. The fourth etched hole H04 of the third dielectric layer 230 and the fifth etched hole H05 of the fourth dielectric layer 240 can be formed in the same process. On the one hand, this helps to reduce the number of processes, eliminating the need to form the fourth etched hole H04 and the fifth etched hole H05 in two separate processes, which improves the fabrication efficiency and reduces the fabrication cost. On the other hand, using the second active structure 008 as a mask to form the fifth etched hole H05 can reduce the precision requirements in the fabrication process, eliminating the need to consider the alignment problem between the sixth etched hole H06 and the fifth etched hole H05 of the fourth dielectric layer 240 (if the fourth etched hole H04 and the fifth etched hole H05 are formed in two separate processes, the precision requirements in the fabrication process need to be increased to ensure that the sixth etched hole H06 and the fifth etched hole H05 are aligned), which helps to reduce the fabrication difficulty and production cost.

[0122] In an alternative embodiment, reference continues. Figure 18 The diameter of the fourth etch hole H04 on the side closer to the substrate 100 is less than or equal to the diameter of the fourth etch hole H04 on the side farther from the substrate 100.

[0123] For example, along the direction perpendicular to the plane of the substrate 100, the diameter of the fourth etched hole H04 is smaller the closer it is to the substrate 100. In this way, when the second overlapping portion J2 is formed, the second overlapping portion J2 can be effectively attached to the sidewall of the fourth etched hole H04, thereby improving the reliability of the second overlapping portion J2 overlapping with the third gate 006 and the second active structure 008.

[0124] Based on the above embodiments, continue to refer to Figure 18 The angle γ between the sidewall of the fourth etched hole H04 and the plane of the substrate 100 facing the third dielectric layer 230 is less than or equal to 90°, which can ensure that the second overlapping part J2 will not break when it is on the sidewall of the fourth etched hole H04, thus preventing an open circuit.

[0125] In another alternative embodiment, reference continues... Figure 18 The diameter of the fifth etched hole H05 on the side closer to the substrate 100 is less than or equal to the diameter of the fifth etched hole H05 on the side farther from the substrate 100.

[0126] For example, along the direction perpendicular to the plane of the substrate 100, the diameter of the fifth etched hole H05 is smaller the closer it is to the substrate 100. In this way, when the second overlapping portion J2 is formed, the second overlapping portion J2 can be effectively attached to the sidewall of the fifth etched hole H05, thereby improving the reliability of the second overlapping portion J2 and the third gate 006 overlapping.

[0127] Based on the above embodiments, continue to refer to Figure 18 The angle δ between the sidewall of the fifth etched hole H05 and the plane of the substrate 100 facing the fourth dielectric layer 240 is less than or equal to 90°, which ensures that the second overlap J2 will not break when it is on the sidewall of the fifth etched hole H05, thus preventing an open circuit.

[0128] In another alternative embodiment, the minimum diameter of the sixth etched hole H06 is greater than or equal to 1.5 μm.

[0129] For example, along the direction perpendicular to the plane where the substrate 100 is located, the closer to the substrate 100, the smaller the diameter of the sixth etch hole H06. The minimum diameter of the sixth etch hole H06 is the diameter of the side of the sixth etch hole H06 closest to the substrate 100. The second active structure 008 can serve as a mask or protective layer for forming the lower fifth etch hole H05. By limiting the minimum diameter of the sixth etch hole H06 to be greater than or equal to 1.5 μm, the maximum diameter of the lower fifth etch hole H05 can be limited. When the process of forming the fifth etch hole H05 is determined, the sidewall slope of the fifth etch hole H05 and the thickness of the fourth dielectric layer 240 can be determined. By limiting the minimum diameter of the sixth etch hole H06 (i.e. the maximum diameter of the fifth etch hole H05) to be greater than or equal to 1.5 μm, the minimum diameter of the fifth etch hole H05 can be determined, avoiding the fifth etch hole H05 from having too small a minimum diameter or not exposing the lower third gate 006, which would affect the reliability of the contact connection between the second overlapping part J2 and the third gate 006.

[0130] In another alternative embodiment, the diameter of the fourth etch hole H04 closest to the substrate 100 is greater than the diameter of the sixth etch hole H06 furthest from the substrate 100.

[0131] Specifically, the minimum aperture of the fourth etched hole H04 is greater than the maximum aperture of the sixth etched hole H06, so that the fourth etched hole H04 can completely cover the sixth etched hole H06 and expose part of the second active structure 03'. Thus, when the fourth etched hole H04, the fifth etched hole H05, and the sixth etched hole H06 form the second overlapping portion J2, the second overlapping portion J2 can be formed on the surface of the second active structure 03' away from the substrate 100. This allows the second overlapping portion J2 to contact and connect not only with the sidewall of the second active structure 03' (i.e., the sidewall of the sixth etched hole H06) but also with the surface of the second active structure 03' away from the substrate 100. This helps to increase the contact area between the second overlapping portion J2 and the second active structure 03', reduce the contact impedance, and increase the overlapping reliability between the second overlapping portion J2 and the second active structure 03'.

[0132] Based on the above embodiments, continue to refer to Figure 18 The distance between the edge of the fourth etched hole H04 closest to the substrate 100 and the edge of the sixth etched hole H06 furthest from the substrate 100 is ΔDT2. ΔDT2 is greater than or equal to the thickness of the second active structure 03' and less than or equal to 0.5 μm. By setting ΔDT2 to be greater than or equal to the thickness of the second active structure 03', the contact area between the second overlapping portion J2 and the surface of the second active structure 03' furthest from the substrate 100 can be effectively increased, reducing contact resistance. Simultaneously, ΔDT2 ≤ 0.5 μm helps to reduce the area of ​​the extension region of the second active structure 03' and the aperture size of the fourth etched hole H04, thereby reducing the space occupied by the second transistor M02.

[0133] Optional, Figure 19 This is a top view of a second transistor provided in an embodiment of this application. Figure 2 , Figure 19 The cross-sectional structure of the second transistor M02 along the dashed line E-E' is as follows Figure 21 As shown. Reference Figure 18 and Figure 19 Along a direction perpendicular to the plane of substrate 100, the third gate 006 and the fourth gate 007 overlap. The dimensions of the third gate 006 in the fourth direction DR1' are different from those of the fourth gate 007 in the fourth direction DR1'; the fourth direction DR1' is parallel to the plane of substrate 100.

[0134] The fourth direction DR1' may intersect or be parallel to the first direction DR1 described above. In this embodiment, the direction of the fourth direction DR1' is not specifically limited.

[0135] Specifically, both the third gate 006 and the fourth gate 007 are made of metallic materials. Due to factors such as geometric stress concentration and mismatch in mechanical properties between materials, cracks easily appear in the inorganic dielectric layer at the step edges of the third gate 006 and the fourth gate 007, leading to reliability issues. By setting the dimensions of the third gate 006 and the fourth gate 007 of the second transistor M02 to be different in the fourth direction DR1', the unreliability caused by the crack effect at the step slope edge of the third gate 006 and the fourth gate 007 can be improved. This avoids the crack effect at the step slope edge of the third gate 006 and the fourth gate 007 from superimposing in the vertical space, causing serious consequences and affecting the performance of the display panel 010.

[0136] For example, the orthographic projection of the third gate 006 onto the plane of the substrate 100 is the third projection, and the orthographic projection of the fourth gate 007 onto the plane of the substrate 100 is the fourth projection. The minimum distance MD' between the edge of the third projection and the edge of the fourth projection of the same second transistor M02 is greater than or equal to 0.5 μm. By limiting the minimum distance MD' between the edge of the third projection and the edge of the fourth projection to be greater than or equal to 0.5 μm, the stepped slope edges of the third gate 006 and the fourth gate 007 can be staggered in the vertical space. This effectively improves the unreliability caused by cracks at the stepped slope edges of the third gate 006 and the fourth gate 007, and avoids the edges of the stepped slopes of the third gate 006 and the fourth gate 007 being too close in the vertical space, which would cause the crack effects of the third gate 006 and the fourth gate 007 to be superimposed in the vertical space, increasing unreliability.

[0137] In an alternative embodiment, reference continues. Figure 18 and Figure 19 The dimension of the fourth gate 007 in the fourth direction DR1' is larger than that of the third gate 006 in the fourth direction DR1'. By increasing the dimension of the fourth gate 007 in the fourth direction DR1', it is beneficial to reduce the number of metal step ramps directly exposed to the light-emitting layer, encapsulation layer, and touch layer, thereby reducing the impact of inorganic dielectric layer cracking on the electrode layer, light-emitting layer, encapsulation layer, touch layer, and other film layers. At the same time, the edge of the step ramp of the lower third gate 006 is usually located near the edge of the fourth gate 007 in the vertical space, and the overlapping third gate 006 and fourth gate 007 in the direction perpendicular to the plane of the substrate 100 are usually close in the vertical space. Therefore, the cracking effect of the inorganic dielectric layer at the edge of the step ramp of the lower third gate 006 has a smaller impact on the upper fourth gate 007.

[0138] In another alternative embodiment, the fourth gate 007 includes a third deposited layer and a fourth deposited layer ( Figure 18 and Figure 19(not shown in the figure). The third deposition layer is located on the side of the fourth deposition layer near the substrate 100, and the Young's modulus of the third deposition layer is less than that of the fourth deposition layer.

[0139] Materials with low Young's modulus generally have better plasticity, are easier to stretch, and are less prone to fracture. By setting a third deposition layer with a low Young's modulus on the side of the fourth gate 007 near the substrate 100, it is beneficial to reduce the impact of crack effects at the step slope edge of the lower third gate 006 on the upper fourth gate 007. Moreover, setting the first deposition layer DL1 only in the upper fourth gate 007 helps to reduce fabrication steps and lower fabrication costs.

[0140] For example, the third gate 006 and the fourth deposition layer may include molybdenum (Mo) metal, and the third deposition layer may include titanium (Ti) material. If the pixel circuit 201 further includes a first transistor M01, and the second gate 002 of the first transistor M01 includes a first deposition layer DL1 and a second deposition layer DL2, in one embodiment, the third deposition layer of the fourth gate 007 may be formed in the same process as the first deposition layer DL1 of the second gate 002, and the fourth deposition layer of the fourth gate 007 may be formed in the same process as the second deposition layer DL2 of the second gate 002.

[0141] Optional, Figure 20 This is a schematic diagram of the film layer structure of a display panel provided in an embodiment of this application. Figure 9 , Figure 21 This is a top view of a second transistor provided in an embodiment of this application. Figure 3 ,refer to Figure 20 and Figure 21 The circuit functional layer 200 also includes a second signal trace SL2 located on the side of the second transistor M02 near the substrate 100, and the second signal trace SL2 is electrically connected to a plurality of pixel circuits 201 located in the same row. Figure 20 and Figure 21 (not shown in the image); along a direction perpendicular to the plane of substrate 100, the second signal trace SL2 simultaneously overlaps with the third gate 006 and the fourth gate 007 of multiple second transistors M02.

[0142] The second signal trace SL2 is used to transmit electrical signals and provide electrical signals to the pixel circuit 201. In one embodiment, the second signal trace SL2 extends along the row direction and is used to transmit signals such as write control signal S2P, compensation control signal S2N, initialization control signal S1N, and reset control signal S1P. In another embodiment, the second signal trace SL2 extends along the column direction and is used to transmit signals such as write data signal Data, initialization signal VREF1, and reset signal VREF2. If the circuit functional layer 200 also includes the first signal trace SL1 described above, the second signal trace SL2 and the first signal trace SL1 described above can be the same signal trace, or they can be different signal traces. This application embodiment does not limit this.

[0143] For example, taking the second signal trace SL2 as an example, which is electrically connected to the gates of the other transistors in the pixel circuit 201 besides the second transistor M02, and the second signal trace SL2 can provide gate drive signals to the gates of the other transistors, refer to... Figure 20 In the pixel circuit 201, at least a portion of the switching transistors STFTs are not configured as the second transistor M02. These STFTs include a switching gate 004 and a switching active structure 005, wherein both the switching gate 004 and the switching active structure 005 may be located on the side of the second transistor M02 closest to the substrate 100. In one embodiment, the second signal trace SL2 may be disposed on the same layer as the switching gate 004. Furthermore, the switching gate 004 may also reuse the second signal trace SL2. Figure 20 (Not shown in the image).

[0144] Continue to refer to Figure 20 and Figure 21The second signal trace SL2 is located on the side of the second transistor M02 closest to the substrate 100, which can reduce the impact of the crack effect of the third gate 006 and the fourth gate 007 of the second transistor M02, and avoid the crack effect of the third gate 006 and / or the fourth gate 007 causing the second signal trace SL2 to break, affecting the electrical connection of the second signal trace SL2. In addition, along the direction perpendicular to the plane where the substrate 100 is located, the second signal trace SL2 overlaps with the third gate 006 and the fourth gate 007 of multiple second transistors M02 at the same time, which can save space in the circuit functional layer 200, increase light transmittance, and also help to achieve high resolution and thinness of the display panel 010. In one embodiment, the size of the second signal trace SL2 in the fourth direction DR1' is different from the size of the fourth gate 007 in the fourth direction DR1', and / or the size of the second signal trace SL2 in the fourth direction DR1' is different from the size of the third gate 006 in the fourth direction DR1', so as to avoid the crack effect at the step slope edge of the second signal trace SL2 from being superimposed in the longitudinal space, causing serious consequences and affecting the performance of the display panel 010.

[0145] In an alternative embodiment, reference continues. Figure 21 The size of the second signal trace SL2 in the fifth direction X' is smaller than the size of the fourth gate 007 in the fifth direction X'; the fifth direction X' is parallel to the plane where the substrate 100 is located and intersects with the extension direction of the second signal trace SL2.

[0146] For example, the second signal trace SL2 extends along the row direction, and the fifth direction X' can be the column direction. The second signal trace SL2 can be electrically connected to multiple pixel circuits 201 located in the same row. Along the extension direction of the second signal trace SL2, the size of the second signal trace SL2 is usually larger than the size of the fourth gate 007. By setting the size of the second signal trace SL2 to be smaller than the size of the fourth gate 007 along the fifth direction X', it is beneficial to reduce the number of metal step slopes directly exposed on the side of the light-emitting layer, encapsulation layer, and touch layer, thereby reducing the impact of inorganic dielectric layer crack effect on the electrode layer, light-emitting layer, encapsulation layer, touch layer, and other film layers.

[0147] It is understood that in other alternative implementations, the second signal trace may also extend along the column direction, and the fifth direction may also be the row direction.

[0148] If the circuit functional layer 200 further includes the first signal trace SL1 described above, in one embodiment, the extension direction of the second signal trace SL2 is the same as the extension direction of the first signal trace SL1, and the fifth direction X' may be parallel to the second direction X; in another embodiment, the extension direction of the second signal trace SL2 intersects the extension direction of the first signal trace SL1, and the fifth direction X' may intersect the second direction X.

[0149] In another alternative embodiment, reference continues... Figure 21 The size of the second signal trace SL2 in the fifth direction X' is smaller than the size of the third gate 006 in the fifth direction X'. The fifth direction X' is parallel to the plane where the substrate 100 is located and intersects with the extension direction of the second signal trace SL2. This also helps to reduce the number of metal step slopes directly exposed on the side of the light-emitting layer, the encapsulation layer, and the touch layer, thereby reducing the impact of inorganic dielectric layer cracking effect on the electrode layer, the light-emitting layer, the encapsulation layer, the touch layer, and other film layers.

[0150] In another optional embodiment, the second signal trace SL2 includes a third edge LS3 and a fourth edge LS4 disposed opposite each other along a sixth direction Y', the sixth direction Y' being parallel to the extension direction of the second signal trace SL2. The orthographic projection of the third gate 006 onto the plane of the substrate 100 is the third projection, and the orthographic projection of the fourth gate 007 onto the plane of the substrate 100 is the fourth projection. The orthographic projections of the third edge LS3 and the fourth edge LS4 onto the plane of the substrate 100 are covered by a first projection, and the minimum distance between the third edge LS3 and the edge of the first projection and the minimum distance between the fourth edge LS4 and the edge of the first projection are both greater than zero; and / or, the orthographic projections of the third edge LS3 and the fourth edge LS4 onto the plane of the substrate 100 are covered by a second projection, and the minimum distance between the third edge LS3 and the edge of the second projection and the minimum distance between the fourth edge LS4 and the edge of the second projection are both greater than zero.

[0151] Specifically, along the direction perpendicular to the plane of substrate 100, both the third edge LS3 and the fourth edge LS4 overlap with the third gate 006, and the distance between the third edge LS3 and the fourth edge LS4 and the edge of the third gate 006 along the direction perpendicular to the plane of substrate 100 is greater than zero; and / or, along the direction perpendicular to the plane of substrate 100, both the third edge LS3 and the fourth edge LS4 overlap with the fourth gate 007, and the distance between the third edge LS3 and the fourth edge LS4 and the edge of the fourth gate 007 along the direction perpendicular to the plane of substrate 100 is greater than zero. In the vertical space (the direction perpendicular to the plane of substrate 100), the third edge LS3 and the fourth edge LS4 are recessed relative to the edge of the third gate 006 toward the central region of the second signal trace SL2 and / or the third gate 006; and / or, in the vertical space (the direction perpendicular to the plane of substrate 100), the third edge LS3 and the fourth edge LS4 are recessed relative to the edge of the fourth gate 007 toward the central region of the second signal trace SL2 and / or the fourth gate 007. This helps to reduce the number of metal steps and slopes directly exposed on the side away from the substrate 100, reduce the impact of inorganic dielectric layer cracking effect, and improve the reliability of display panel 010.

[0152] For example, the second signal trace SL2 can pass through the display area AA in the sixth direction Y' (row direction) and connect all pixel circuits 201 in the same row. Although the size of the second signal trace SL2 is larger than the size of the third gate 006 along the sixth direction Y' (row direction), the third edge LS3 and the fourth edge LS4 of the second signal trace SL2 are recessed relative to the third gate 006 of the second transistor M02 located at the outermost edges of all pixel circuits 201 in the same row; and / or, the fourth edge LS4 of the second signal trace SL2 is recessed relative to the third gate 006 of the second transistor M02 located at the outermost edges of all pixel circuits 201 in the same row. The third edge LS3 and the fourth edge LS4 of the gate 007 and the second signal trace SL2 are recessed to avoid the crack effect of the third edge LS3 and / or the fourth edge LS4 affecting the film structure of the second transistor M02 away from the substrate 100 (the crack effect of the third edge LS3 and the fourth edge LS4 has a small impact on the third gate 006 and the fourth gate 007 of the second transistor M02. Even if it does have an impact, it only affects the structural integrity near the edges of the third gate 006 and the fourth gate 007, and does not affect the core area of ​​the third gate 006 and the fourth gate 007).

[0153] It is understood that, in other alternative implementations, the second signal trace may run through the display area AA in the sixth direction (column direction) and connect all pixel circuits 201 in the same column.

[0154] If the circuit functional layer 200 further includes the first signal trace SL1 described above, in one embodiment, the extension direction of the second signal trace SL2 is the same as the extension direction of the first signal trace SL1, and the sixth direction Y' may be parallel to the third direction Y; in another embodiment, the extension direction of the second signal trace SL2 intersects the extension direction of the first signal trace SL1, and the sixth direction Y' may intersect with the third direction Y.

[0155] Based on the same inventive concept, this application also proposes a method for preparing a display panel. Figure 14 , Figure 16 , Figure 18 , Figure 20 The display panel shown. Figure 22 This is a flowchart of a method for manufacturing a display panel provided in an embodiment of this application. Figure 2 ,refer to Figure 22 The preparation methods include: S210. Provide a substrate and sequentially fabricate a third gate and a second active structure on one side of the substrate; wherein the second active structure includes a sixth etched hole.

[0156] For example, refer to Figure 14 , Figure 16 , Figure 18 and Figure 20 Before fabricating the third gate 006 and the second active structure 008 on one side of the substrate 100, structures such as a protective layer 012, a photosensitive layer 260, a switching active structure 005, a switching gate 004, a second signal trace SL2, and a dielectric layer disposed adjacent to these structures may be selectively formed. Then, the third gate 006 is formed first, followed by the second active structure 008. In one embodiment, the sixth etch hole H06 may be formed in the same process as the second active structure 008.

[0157] S220, a third dielectric layer is formed on the surface of the second active structure away from the substrate.

[0158] For example, after forming the second active structure 008, a third dielectric layer 230 may be formed on the surface of the second active structure 008 away from the substrate 100, and the third dielectric layer 230 may fill and cover the sixth etched hole H06.

[0159] S230. A second photoresist layer is formed on the surface of the third dielectric layer away from the substrate, and the second photoresist layer is patterned; wherein, the second photoresist layer includes a second mask hole, and in a direction perpendicular to the plane of the substrate, the second mask hole overlaps with the sixth etching hole.

[0160] Specifically, photolithography can be used to pattern the entire third dielectric layer 230. In an optional embodiment, the minimum diameter of the second mask aperture is greater than the maximum diameter of the sixth etched aperture H06.

[0161] S240. Using the second photoresist as a mask, the third dielectric layer is etched through the second mask hole to form a fourth etching hole that exposes the sixth etching hole. Then, using the second active structure as a mask, the fourth dielectric layer located between the third gate and the second active structure is etched through the sixth etching hole to form a fifth etching hole that exposes the third gate.

[0162] For example, an etching process is used to form a fourth etch hole H04 located in the third dielectric layer 230. After the fourth etch hole H04 is formed, etching can continue. Using the second active structure 008 as a mask, the fourth dielectric layer 240 located between the third gate 006 and the second active structure 008 is etched to form a fifth etch hole H05 that exposes the third gate 006. In this way, the fourth etch hole H04 and the fifth etch hole H05 can be formed in one etching process.

[0163] S250, A second conductive structure is formed on the side of the third dielectric layer away from the substrate; the second conductive structure includes a second overlap portion, which overlaps with the third gate and the second active structure of the same second transistor through a fourth etch hole, a sixth etch hole and a fifth etch hole.

[0164] For example, after forming the fourth etch hole H04 and the fifth etch hole H05, a full-layer conductive layer can be formed on the surface of the third dielectric layer 230 away from the substrate 100. The conductive layer can be formed on the surface of the third dielectric layer 230 away from the substrate 100, and the conductive layer can also be formed on the sidewalls of the fourth etch hole H04, the sixth etch hole H06, the fifth etch hole H05, and the exposed surface of the third gate 006 away from the substrate 100. Then, the conductive layer is patterned to obtain a second conductive structure 203 that simultaneously overlaps with the third gate 006 and the second active structure 008.

[0165] In this embodiment, the fourth etched hole in the third dielectric layer and the fifth etched hole in the fourth dielectric layer can be formed in the same process, which helps to reduce the number of processes. It eliminates the need to form the fourth and fifth etched holes in two separate processes, thereby improving the fabrication efficiency and reducing the fabrication cost. At the same time, using the second active material as a mask to form the fifth etched hole can reduce the precision requirements in the fabrication process. It eliminates the need to consider the alignment problem between the sixth etched hole and the fifth etched hole in the fourth dielectric layer, which helps to reduce the fabrication difficulty and production cost.

[0166] In an optional embodiment, the circuit functional layer 200 further includes a first conductive structure 202, and the first conductive structure 202 and the second conductive structure 203 can be disposed in the same layer and formed in the same process.

[0167] In another optional embodiment, the pixel circuit 201 further includes a first transistor M01, and the first active structure 003 of the first transistor M01 and the second active structure 008 of the second transistor M02 are made of the same material. The first active structure 003 and the second active structure 008 can be disposed in the same layer and formed in the same process. In one embodiment, the first gate 001 and the third gate 006 can be disposed in the same layer and formed in the same process; in another embodiment, the second gate 002 and the fourth gate 007 can be disposed in the same layer and formed in the same process.

[0168] The display panel manufacturing method provided in this application embodiment is used to manufacture the display panel provided in the above-mentioned embodiment of this application. It has the corresponding technical features and beneficial effects of the display panel. For the contents not described in detail in the embodiments of the display panel manufacturing method, please refer to the description of the display panel above, and they will not be repeated here. Similarly, the display panel of this application embodiment also has the functional modules and beneficial effects of executing the display panel manufacturing method provided in the embodiments of this application. For the contents not described in detail in the embodiments of the display panel, please refer to the description of the display panel manufacturing method above, and they will not be repeated here.

[0169] In addition to the display panel 010 shown above, the display panel 010 may also be implemented in other ways. Figure 23This is a schematic diagram of the film layer structure of a display panel provided in an embodiment of this application. Figure 10 ,refer to Figure 23 At least part of the pixel circuit 201 may simultaneously include a first transistor M01 and a second transistor M02. The first gate 001 and the second gate 002 of the first transistor M01 may be connected to the first overlap portion J1 of the first conductive structure 202. The third gate 006 and the second active structure 008 of the second alertness sensor M02 may be electrically connected to the second overlap portion J2 of the second conductive structure 203.

[0170] For example, at least some of the switching transistors in the pixel circuit 201 can be configured as a first transistor M01, such that the potentials of its first gate 001 and second gate 002 are the same. This is beneficial for increasing the on-state current of the switching transistor and improving the switching speed. The driving transistor in the pixel circuit 201 can be configured as a second transistor M02, such that the potentials of its third gate 006 and the source or drain region of the second active structure 008 are the same. This is beneficial for suppressing the threshold voltage drift of the driving transistor, improving its operational stability, extending its service life, and thus improving the display effect and reliability of the display panel 010.

[0171] In one implementation, continue to refer to Figure 23 A portion of the structure in the first transistor M01 can be disposed on the same layer as a portion of the structure in the second transistor M02, and formed in the same process. In another embodiment, Figure 24 This is a schematic diagram of the film layer structure of a display panel provided in an embodiment of this application. Figure 10 1. Reference Figure 24 The structure in the first transistor M01 can also be formed in different processes as all the structures in the second transistor M02.

[0172] It is understood that the above description only exemplifies some embodiments of the display panel, and the film layer structure of the display panel provided in this application is not limited to the above structure. Any transistor in the pixel circuit can be configured as a first transistor or a second transistor, and the first transistor and the second transistor can be located at the same or different film layer positions. In the absence of contradiction, different embodiments can be combined with each other.

[0173] Based on the same inventive concept, embodiments of this application also provide a display device. Figure 25 This is a schematic diagram of the structure of a display device provided in an embodiment of this application, such as... Figure 25 As shown, the display device 020 includes the display panel 010 provided in any embodiment of this application. The display device 020 provided in the embodiments of this application can be... Figure 25The mobile phone shown can also be any electronic product with display function, including but not limited to the following categories: television, laptop, desktop monitor, tablet, digital camera, smart bracelet, smart glasses, in-vehicle display, medical device, industrial control equipment, touch interactive terminal, etc. This application embodiment does not make any special limitation in this regard.

[0174] Note that the above are merely preferred embodiments and the technical principles employed in this application. Those skilled in the art will understand that this application is not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions can be made without departing from the scope of protection of this application. Therefore, although this application has been described in detail through the above embodiments, this application is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of this application, the scope of which is determined by the scope of the appended claims.

Claims

1. A display panel, characterized in that, include: A substrate and a circuit functional layer located on one side of the substrate; The circuit functional layer includes multiple pixel circuits located in the display area; At least a portion of the pixel circuitry includes a first transistor and a light-emitting element; The first transistor includes a first active structure, a first gate, and a second gate. The first gate is located on the side of the first active structure closer to the substrate, and the second gate is located on the side of the first active structure farther from the substrate. The circuit functional layer also includes a first conductive structure located on the side of the second gate away from the substrate; The first conductive structure includes a first overlapping portion; along a direction perpendicular to the plane of the substrate, the first overlapping portion overlaps with the overlapping area of ​​the first gate and the second gate of the same first transistor, and the first overlapping portion overlaps with the first gate and the second gate of the same first transistor.

2. The display panel according to claim 1, characterized in that, The first transistor includes a driving transistor and / or a switching transistor; The driving transistor is used to selectively provide driving signals to the light-emitting element; The switching transistor is used to selectively provide electrical signals to the driving transistor and / or the light-emitting element.

3. The display panel according to claim 1, characterized in that, The first active structure of the first transistor comprises a metal oxide material.

4. The display panel according to claim 3, characterized in that, The first active structure of the first transistor is a linear design.

5. The display panel according to claim 1, characterized in that, The circuit functional layer further includes a first dielectric layer located between the second gate and the first conductive structure, and a second dielectric layer located between the first gate and the second gate; The first dielectric layer includes a first etched hole; the second dielectric layer includes a second etched hole; the second gate includes a third etched hole; In this process, the first etched hole, the second etched hole, and the third etched hole overlap simultaneously along a direction perpendicular to the plane of the substrate; the first overlapping portion is provided in the first etched hole, the second etched hole, and the third etched hole.

6. The display panel according to claim 5, characterized in that, The diameter of the first etched hole on the side closer to the substrate is less than or equal to the diameter of the first etched hole on the side farther from the substrate.

7. The display panel according to claim 5, characterized in that, The angle between the sidewall of the first etched hole and the plane of the substrate facing the first dielectric layer is less than or equal to 90°.

8. The display panel according to claim 5, characterized in that, The diameter of the second etched hole on the side closer to the substrate is less than or equal to the diameter of the second etched hole on the side farther from the substrate.

9. The display panel according to claim 5, characterized in that, The angle between the sidewall of the second etched hole and the plane of the substrate facing the second dielectric layer is less than or equal to 90°.

10. The display panel according to claim 5, characterized in that, The minimum diameter of the third etched hole is greater than or equal to 1.5 μm.

11. The display panel according to claim 5, characterized in that, The diameter of the first etched hole closest to the substrate is greater than the diameter of the third etched hole furthest from the substrate.

12. The display panel according to claim 11, characterized in that, The distance between the edge of the first etched hole closest to the substrate and the edge of the third etched hole furthest from the substrate is ΔDT1, wherein ΔDT1 is greater than or equal to the thickness of the second gate and less than or equal to 0.5 μm.

13. The display panel according to claim 1, characterized in that, Along a direction perpendicular to the plane of the substrate, the first gate and the second gate overlap; The dimensions of the first gate and the second gate in the first direction are different; the first direction is parallel to the plane of the substrate.

14. The display panel according to claim 13, characterized in that, The dimension of the second gate in the first direction is greater than the dimension of the first gate in the first direction.

15. The display panel according to claim 13, characterized in that, The second gate includes a first deposited layer and a second deposited layer; wherein the first deposited layer is located on the side of the second deposited layer closer to the substrate, and the Young's modulus of the first deposited layer is less than that of the second deposited layer.

16. The display panel according to claim 13, characterized in that, The circuit functional layer further includes a first signal trace located on the side of the first transistor near the substrate; the first signal trace is electrically connected to the plurality of pixel circuits. Along a direction perpendicular to the plane of the substrate, the first signal trace simultaneously overlaps with the first gate and the second gate of a plurality of the first transistors.

17. The display panel according to claim 16, characterized in that, The dimension of the first signal trace in the second direction is smaller than the dimension of the second gate in the second direction; the second direction is parallel to the plane where the substrate is located and intersects with the extension direction of the first signal trace.

18. The display panel according to claim 16, characterized in that, The dimension of the first signal trace in the second direction is smaller than the dimension of the first gate in the second direction; the second direction is parallel to the plane where the substrate is located and intersects with the extension direction of the first signal trace.

19. The display panel according to claim 16, characterized in that, The first signal trace includes a first edge and a second edge disposed opposite to each other along a third direction; the third direction is parallel to the extension direction of the first signal trace; The orthographic projection of the first gate onto the plane where the substrate is located is the first projection, and the orthographic projection of the second gate onto the plane where the substrate is located is the second projection; The orthographic projections of the first edge and the second edge onto the plane where the substrate is located are covered by the first projection, and the minimum distance between the first edge and the edge of the first projection and the minimum distance between the second edge and the edge of the first projection are both greater than zero; and / or, the orthographic projections of the first edge and the second edge onto the plane where the substrate is located are covered by the second projection, and the minimum distance between the first edge and the edge of the second projection and the minimum distance between the second edge and the edge of the second projection are both greater than zero.

20. The display panel according to claim 1, characterized in that, The orthographic projection of the first gate onto the plane of the substrate is the first projection, and the orthographic projection of the second gate onto the plane of the substrate is the second projection. The minimum distance between the edge of the first projection and the edge of the second projection is greater than or equal to 0.5 μm.

21. The display panel according to claim 1, characterized in that, The display area includes a functional device setting area and a main display area that at least partially surrounds the functional device setting area; the functional device setting area includes the pixel circuit and functional devices located on the side of the pixel circuit closer to the substrate. The circuit functional layer located in the functional device setting area includes the first transistor and the first conductive structure that overlaps with the first gate and the second gate of the same first transistor.

22. A display panel, characterized in that, include: A substrate and a circuit functional layer located on one side of the substrate; The circuit functional layer includes multiple pixel circuits located in the display area; At least a portion of the pixel circuitry includes a second transistor and a light-emitting element; The second transistor includes a second active structure, a third gate, and a fourth gate, wherein the third gate is located on the side of the second active structure closer to the substrate, and the fourth gate is located on the side of the second active structure farther from the substrate. The circuit functional layer also includes a second conductive structure located on the side of the fourth gate away from the substrate; The second conductive structure includes a second overlapping portion; along a direction perpendicular to the plane of the substrate, the second overlapping portion overlaps with the overlapping region of the third gate and the second active structure of the same second transistor, and the second overlapping portion overlaps with the third gate and the second active structure of the same second transistor.

23. The display panel according to claim 22, characterized in that, The second transistor includes a driving transistor and / or a switching transistor; The driving transistor is used to selectively provide driving signals to the light-emitting element; The switching transistor is used to selectively provide electrical signals to the driving transistor and / or the light-emitting element.

24. The display panel according to claim 22, characterized in that, The second active structure of the second transistor comprises a metal oxide material.

25. The display panel according to claim 24, characterized in that, The second active structure of the second transistor is a linear design.

26. The display panel according to claim 22, characterized in that, The circuit functional layer further includes a third dielectric layer located between the second active structure and the second conductive structure, and a fourth dielectric layer located between the third gate and the second active structure; The third dielectric layer includes a fourth etched hole; the fourth dielectric layer includes a fifth etched hole; The second active structure includes a sixth etched hole; In this process, the fourth, fifth, and sixth etched holes overlap simultaneously along a direction perpendicular to the plane of the substrate; and the second overlapping portion is provided in each of the fourth, fifth, and sixth etched holes.

27. The display panel according to claim 26, characterized in that, The diameter of the fourth etched hole on the side closest to the substrate is less than or equal to the diameter of the fourth etched hole on the side furthest from the substrate.

28. The display panel according to claim 26, characterized in that, The angle between the sidewall of the fourth etched hole and the plane of the substrate facing the third dielectric layer is less than or equal to 90°.

29. The display panel according to claim 26, characterized in that, The diameter of the fifth etched hole on the side closest to the substrate is less than or equal to the diameter of the fifth etched hole on the side furthest from the substrate.

30. The display panel according to claim 26, characterized in that, The angle between the sidewall of the fifth etched hole and the plane of the substrate facing the fourth dielectric layer is less than or equal to 90°.

31. The display panel according to claim 26, characterized in that, The minimum diameter of the sixth etched hole is greater than or equal to 1.5 μm.

32. The display panel according to claim 26, characterized in that, The diameter of the fourth etched hole closest to the substrate is greater than the diameter of the sixth etched hole furthest from the substrate.

33. The display panel according to claim 32, characterized in that, The distance between the edge of the fourth etched hole closest to the substrate and the edge of the sixth etched hole furthest from the substrate is ΔDT2, wherein ΔDT2 is greater than or equal to the thickness of the second active structure and less than or equal to 0.5 μm.

34. The display panel according to claim 22, characterized in that, The third gate and the fourth gate overlap along a direction perpendicular to the plane of the substrate; The dimensions of the third gate in the fourth direction are different from those of the fourth gate in the fourth direction; the fourth direction is a direction parallel to the plane of the substrate.

35. The display panel according to claim 34, characterized in that, The dimension of the fourth gate in the fourth direction is larger than the dimension of the third gate in the fourth direction.

36. The display panel according to claim 34, characterized in that, The fourth gate includes a third deposition layer and a fourth deposition layer; wherein the third deposition layer is located on the side of the fourth deposition layer closer to the substrate, and the Young's modulus of the third deposition layer is less than that of the fourth deposition layer.

37. The display panel according to claim 34, characterized in that, The circuit functional layer further includes a second signal trace located on the side of the second transistor near the substrate; the second signal trace is electrically connected to the plurality of pixel circuits. Along a direction perpendicular to the plane of the substrate, the second signal trace simultaneously overlaps with the third gate and the fourth gate of a plurality of second transistors.

38. The display panel according to claim 37, characterized in that, The dimension of the second signal trace in the fifth direction is smaller than the dimension of the fourth gate in the fifth direction; the fifth direction is parallel to the plane of the substrate and intersects with the extension direction of the second signal trace.

39. The display panel according to claim 37, characterized in that, The dimension of the second signal trace in the fifth direction is smaller than the dimension of the third gate in the fifth direction; the fifth direction is parallel to the plane of the substrate and intersects with the extension direction of the second signal trace.

40. The display panel according to claim 37, characterized in that, The second signal trace includes a third edge and a fourth edge disposed opposite to each other along a sixth direction; the sixth direction is parallel to the extension direction of the second signal trace; The orthographic projection of the third gate onto the plane where the substrate is located is the third projection, and the orthographic projection of the fourth gate onto the plane where the substrate is located is the fourth projection. The orthographic projections of the third edge and the fourth edge onto the plane of the substrate are covered by the third projection, and the minimum distance between the third edge and the edge of the third projection and the minimum distance between the fourth edge and the edge of the third projection are both greater than zero; and / or, the orthographic projections of the third edge and the fourth edge onto the plane of the substrate are covered by the fourth projection, and the minimum distance between the third edge and the edge of the fourth projection and the minimum distance between the fourth edge and the edge of the fourth projection are both greater than zero.

41. The display panel according to claim 22, characterized in that, The orthographic projection of the third gate onto the plane of the substrate is the third projection, and the orthographic projection of the fourth gate onto the plane of the substrate is the fourth projection. The minimum distance between the edge of the third projection and the edge of the fourth projection is greater than or equal to 0.5 μm.

42. The display panel according to claim 22, characterized in that, The display area includes a functional device setting area and a main display area that at least partially surrounds the functional device setting area; the functional device setting area includes the pixel circuit and functional devices located on the side of the pixel circuit closer to the substrate. The circuit functional layer located in the functional device setting area includes the second transistor and the second conductive structure that overlaps with the third gate and the second active structure of the same second transistor.

43. A display device, characterized in that, include: The display panel according to any one of claims 1 to 42.

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