Display panel and display device
By setting a first buffer layer in the same layer as the light-shielding layer in the display panel, and raising the insulating layer to ensure that it is parallel to the substrate, the ESD defect problem of WOLED display devices is solved, and the production yield and reliability are improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- HEFEI XINSHENG OPTOELECTRONICS TECH CO LTD
- Filing Date
- 2026-03-17
- Publication Date
- 2026-06-09
AI Technical Summary
WOLED display devices are prone to electrostatic discharge (ESD) defects during the manufacturing process, which leads to a decrease in production yield.
A first buffer layer is set in the display panel, which is on the same layer as the light-shielding layer, and the insulating layer of the second electrode plate is raised to ensure that the insulating layer is parallel to the substrate surface and forms a film layer of uniform thickness, thereby improving the voltage withstand performance of the capacitor and reducing the risk of electrostatic breakdown.
It improved the production yield of display panels, reduced the incidence of ESD defects, and enhanced the reliability of display devices.
Smart Images
Figure CN122180268A_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of display technology, and more particularly to a display panel and display device. Background Technology
[0002] With the development of display technology, display devices (such as televisions and computers) are increasingly used in people's lives. Among them, white organic light-emitting diode (WOLED) display devices are a technology that uses white light-emitting diodes with a color filter layer to achieve color display. They have the advantages of high adaptability to large sizes and long lifespan, and are therefore widely used in high-end large-size display devices.
[0003] However, WOLED display devices are prone to electrostatic discharge (ESD) defects during the manufacturing process, which leads to a decrease in the production yield of the display devices. Summary of the Invention
[0004] The purpose of this disclosure is to provide a display panel and display device to improve the problem of ESD defects in the display panel.
[0005] To achieve the above objectives, the embodiments of this disclosure provide the following technical solutions: In a first aspect, a display panel is provided. The display panel includes a substrate, a light-shielding layer, an active layer, a first conductive layer, an insulating layer, and a first buffer layer. The light-shielding layer is disposed on one side of the substrate; the light-shielding layer includes a first electrode. The active layer is disposed on the side of the light-shielding layer away from the substrate, and the first conductive layer is disposed on the side of the active layer away from the substrate; the first conductive layer includes a second electrode, the second electrode at least partially opposite the first electrode to form a capacitor; and at least a portion of the edge of the second electrode extends beyond the first electrode. The insulating layer is disposed between the first conductive layer and the light-shielding layer, and is in contact with both the first conductive layer and the light-shielding layer. The first buffer layer is disposed in the same layer as the light-shielding layer; and the orthographic projection of the portion of the second electrode extending beyond the first electrode onto the substrate is within the range of the orthographic projection of the first buffer layer onto the substrate; within the range of the orthographic projection of the second electrode onto the insulating layer, the insulating layer is close to the surface of the substrate and parallel to the substrate.
[0006] In this configuration, by providing a first buffer layer, the portion of the insulating layer extending beyond the first electrode plate can be raised. This ensures that within the area of the second electrode plate's projection onto the insulating layer, the insulating layer is close to the surface of the substrate 10 and parallel to the substrate. Consequently, within the area of the second electrode plate's projection onto the insulating layer, the insulating layer is a film layer parallel to the substrate and of uniform thickness, thereby improving the problem of decreased capacitor withstand voltage and reducing the risk of electrostatic discharge (ESD) breakdown. Furthermore, this improves the ESD performance of the display panel and increases the production yield of the display panel.
[0007] In some embodiments, the surface of the first buffer layer away from the substrate is flush with the surface of the first electrode plate away from the substrate.
[0008] In some embodiments, the first buffer layer is located away from the surface of the substrate, extends beyond the surface of the first electrode plate away from the substrate, and covers the light-shielding layer; the first buffer layer is located away from the surface of the substrate and is parallel to the substrate.
[0009] In some embodiments, the display panel further includes a transistor, the transistor including a gate, an active portion, a source, and a drain. The display panel further includes a second conductive layer disposed between the active layer and the first conductive layer; the gate is located in the second conductive layer, the active portion is located in the active layer; the source and the drain are located in the first conductive layer, and are made of the same material as the second electrode and are fabricated in the same layer.
[0010] In some embodiments, the insulating layer includes an interlayer insulating layer and a second buffer layer, wherein the interlayer insulating layer is disposed between the first conductive layer and the second conductive layer, and the second buffer layer is disposed between the active layer and the light-shielding layer.
[0011] In some embodiments, the display panel further includes a transistor, the transistor including a gate, an active portion, a source, and a drain; the display panel further includes a second conductive layer disposed on the side of the first conductive layer away from the substrate; the source and the drain are located in the second conductive layer, the active portion is located in the active layer; the gate is located in the first conductive layer, and is made of the same material as the second electrode plate and is fabricated in the same layer.
[0012] In some embodiments, the insulating layer includes a second buffer layer disposed between the active layer and the light-shielding layer.
[0013] In some embodiments, the display panel includes a display area and a peripheral area located on at least one side of the display area; the display panel further includes a gate driving circuit disposed on one side of the substrate and located in the peripheral area; the gate driving circuit includes the transistor and the capacitor.
[0014] In some embodiments, when the surface of the first buffer layer away from the substrate is flush with the surface of the first electrode plate away from the substrate, the first buffer layer and the light-shielding layer cover the peripheral area, and the first buffer layer does not cover the display area. Alternatively, when the surface of the first buffer layer away from the substrate extends beyond the surface of the first electrode plate away from the substrate and covers the light-shielding layer, and the surface of the first buffer layer away from the substrate is parallel to the substrate, the first buffer layer covers the peripheral area but does not cover the display area.
[0015] Secondly, a display device is provided. The display device includes a display panel as described in the above embodiments.
[0016] The above-described display device has the same structure and beneficial technical effects as the display panel provided in some of the above embodiments, and will not be described again here. Attached Figure Description
[0017] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.
[0018] Figure 1 This is a structural diagram of a display device according to some embodiments; Figure 2 for Figure 1 A cross-sectional view along section line AA; Figure 3 This is a structural diagram of a display panel according to some embodiments; Figure 4 for Figure 3 A cross-sectional view along section line BB; Figure 5 for Figure 3 A cross-sectional view along the central section line CC; Figure 6 for Figure 3 A cross-sectional view along the central section line DD; Figure 7for Figure 3 Another cross-sectional view along section line CC; Figure 8 for Figure 3 Another cross-sectional view along section line DD; Figure 9 for Figure 3 Another cross-sectional view along the section line CC. Detailed Implementation
[0019] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.
[0020] Unless the context otherwise requires, throughout the specification and claims, the term "comprise" and its other forms, such as the third-person singular "comprises" and the present participle "comprising," are interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiments," "example," "specific example," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.
[0021] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.
[0022] In describing some embodiments, the term "connection" and its derivative expressions may be used. The term "connection" should be interpreted broadly; for example, "connection" can be a mechanical connection or an electrical connection; it can be a fixed connection or a detachable connection, or an integral connection; it can be a direct connection or an indirect connection through an intermediate medium; it can be a connection within two components. Those skilled in the art will understand the specific meaning of the above terms herein based on the specific circumstances.
[0023] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.
[0024] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.
[0025] As used herein, “about,” “approximately,” or “approximately” includes the stated value and the average value within an acceptable range of deviation from the given value, wherein the acceptable range of deviation is determined by a person skilled in the art taking into account the measurement under discussion and the error associated with the measurement of the given quantity (i.e., the limitations of the measurement system).
[0026] As used herein, “parallel,” “perpendicular,” and “equal” include the described situation and situations that are similar to the described situation, within an acceptable deviation range, which is determined by those skilled in the art taking into account the measurement under discussion and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, “parallel” includes absolute parallelism and approximate parallelism, where an acceptable deviation range for approximate parallelism may be, for example, within 5°; “perpendicular” includes absolute perpendicularity and approximate perpendicularity, where an acceptable deviation range for approximate perpendicularity may also be, for example, within 5°; “equal” includes absolute equality and approximate equality, where an acceptable deviation range for approximate equality may be, for example, a difference between the two equals being less than or equal to 5% of either one.
[0027] In this disclosure, terms such as “down,” “below,” “above,” and “up” are used to explain the relationships between components shown in the accompanying drawings. The terms may be relative concepts and described based on the directions shown in the drawings, or based on the sequence of process steps, but are not limited thereto.
[0028] It should be understood that when a layer or element is referred to as being on another layer or substrate, it can mean that the layer or element is directly on the other layer or substrate, or that there is an intermediate layer between the layer or element and the other layer or substrate.
[0029] The term "relative" means that the first element can be directly or indirectly relative to the second element. In the case where the third element is between the first and second elements, although they are still relative to each other, the first and second elements can be understood as being indirectly relative to each other.
[0030] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and the area of regions are enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as being limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched areas shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the areas of the device, nor are they intended to limit the scope of the exemplary embodiments.
[0031] See Figure 1 The present disclosure provides a display device 1000, which is a product with image display functionality. Exemplarily, the display device 1000 can be any device that displays either moving (e.g., video) or fixed (e.g., still image) content, and whether it is text or an image.
[0032] For example, such as Figure 1 As shown, the display device 1000 can be any product or component with display function, such as a television, laptop computer, tablet computer, mobile phone, personal digital assistant (PDA), navigator, wearable device, augmented reality (AR) device, virtual reality (VR) device, or car center console screen.
[0033] In some examples, such as Figure 1 As shown, the display device 1000 can be a large-size display device. For example, such as Figure 1 As shown, display device 1000 is a television.
[0034] It should be noted that the shape of the display surface of the display device 1000 is not unique depending on the application scenario. The shape of the display surface of the display device 1000 can be any of the following: circular, elliptical, or polygonal. This embodiment of the present disclosure does not impose any specific limitation.
[0035] In some embodiments, such as Figure 2As shown, the display device 1000 includes a display panel 100, a housing 200, a circuit board 300, and a cover plate 400.
[0036] In some examples, such as Figure 2 As shown, the housing 200 can be a box-shaped structure with an opening. The display panel 100 and circuit board 300 can be disposed inside the housing 200. The cover plate 400 is disposed on the display side 100A of the display panel 100 and is located at the opening of the housing 200. It should be noted that the display panel 100 has a display side 100A and a non-display side 100B disposed opposite to each other. The display side 100A refers to the side of the display panel 100 that displays the image (…). Figure 2 The upper side of the display panel 100), the non-display side 100B refers to the side opposite to the display side 100A ( Figure 2 (Lower side of the central display panel 100).
[0037] In addition, the circuit board 300 can be bound to the end of the display panel 100 and bent to the non-display side 100B of the display panel 100 to reduce the outer bezel of the display panel 100 and increase the screen ratio.
[0038] In some embodiments, such as Figure 3 As shown, the display panel 100 has a display area AA and a peripheral area BB disposed on at least one side of the display area AA. Figure 3 Taking the peripheral area BB surrounding the display area AA as an example, the display area AA is used to display images, and the peripheral area BB is used to house the display driving circuit, thereby controlling the display area AA to display the target image.
[0039] For example, such as Figure 3 As shown, the display panel 100 includes a substrate 10 and a plurality of sub-pixels P disposed on the substrate 10, wherein the sub-pixels P are located in the display area AA.
[0040] The substrate 10 described above can be a flexible substrate 10 or a rigid substrate 10. The material of the flexible substrate 10 may include polyimide (PI), and the material of the rigid substrate 10 may include glass. For example, the substrate 10 may be rigid, and the material of the substrate 10 may include glass.
[0041] In some examples, such as Figure 3 As shown, multiple sub-pixels P are arranged along rows and columns. Each row includes at least one sub-pixel P arranged along a first direction X, and each column includes at least one sub-pixel P arranged along a second direction Y. The first direction X intersects the second direction Y. For example, the first direction X is perpendicular to the second direction Y.
[0042] For example, such as Figure 3 and Figure 4As shown, each sub-pixel P includes a pixel circuit and a light-emitting device, which are connected to drive the light-emitting device to emit light.
[0043] In some embodiments, such as Figure 4 As shown, the display panel 100 further includes a pixel circuit layer 110 and a light-emitting device layer 120 sequentially disposed on the substrate 10. The pixel circuit layer 110 is used to house the pixel circuits, and the light-emitting device layer 120 is used to house the light-emitting devices.
[0044] Please continue reading. Figure 4 The display panel 100 also includes a light-shielding layer 20, which is disposed on the side of the pixel circuit layer 110 close to the substrate 10, so as to shield the devices (such as transistors) in the pixel circuit layer 110, thereby preventing light from affecting the lifespan of the devices.
[0045] Please continue reading. Figure 4 The display panel 100 also includes an encapsulation layer 130 and a color filter layer 140. The encapsulation layer 130 is disposed on the side of the light-emitting device layer 120 away from the substrate 10 to protect the display panel 100 and improve its lifespan. The color filter layer 140 is disposed on the side of the encapsulation layer 130 away from the substrate 10. The color filter layer 140 includes a black matrix 141 and multiple light-filtering sections 142. The black matrix 141 has multiple openings, and the light-filtering sections 142 are located within the openings or may overlap with the openings 511; no specific limitation is made here.
[0046] For example, the plurality of filter portions 142 may include filter portions of different colors, such as red filter portions, green filter portions, and blue filter portions. The red filter portions, green filter portions, and blue filter portions are respectively configured to transmit red light, green light, and blue light.
[0047] In some embodiments, the plurality of sub-pixels P include three primary color sub-pixels, such as red sub-pixels, green sub-pixels and blue sub-pixels, thereby enabling the display panel 100 to display a color image.
[0048] In some examples, the light-emitting layer in the light-emitting device of sub-pixel P is made of a material that can excite light of the target color. For example, the light-emitting device of the green sub-pixel is made of a light-emitting layer material that can excite green light, the light-emitting device of the blue sub-pixel is made of a light-emitting layer material that can excite blue light, and the light-emitting device of the red sub-pixel is made of a light-emitting layer material that can excite red light.
[0049] In other examples, the light-emitting devices of multiple sub-pixels P all emit light of a single color, and the single-color light is converted into the target color by a filter section 142 located above the light-emitting device. For example, the light-emitting devices of multiple sub-pixels P all emit white light or blue light, and the white light or blue light is then converted into the target color light by the corresponding filter section 142.
[0050] The following description uses WOLED as an example to illustrate the embodiments of this disclosure, but the embodiments of this disclosure are not limited thereto.
[0051] In some embodiments, such as Figure 3 As shown, the display panel 100 also includes a gate driver on array (GOA) 210, a source driver IC 220, multiple scan signal lines GL, and multiple data lines DL. The gate driver on array 210, the source driver IC 220, the multiple scan signal lines GL, and the multiple data lines DL are disposed on the substrate 10. The gate driver on array 210 and the source driver IC 220 are located in the peripheral region BB. The gate driver on array 210 is connected to the pixel circuit of a row of sub-pixels P via the scan signal lines GL, and the source driver IC 220 is connected to the pixel circuit of a column of sub-pixels P via the data signal lines DL, and transmits data signals to the pixel circuit of the column of sub-pixels P.
[0052] For example, such as Figure 5 As shown, the gate driving circuit 210 includes a transistor TFT and a capacitor C. The transistor TFT includes an active portion ACT, a gate G, a source S, and a drain D. The capacitor C includes a first plate C1 and a second plate C2. For example, the source S of the transistor TFT is connected to the first plate C1 of the capacitor C. Figure 5 (The example shown is that the source S of the transistor TFT is connected to the first plate C1 of the capacitor C. Alternatively, the gate G of the transistor TFT is connected to the first plate C1 of the capacitor C. This embodiment does not specifically limit the specific connection.)
[0053] It is understood that the aforementioned transistor TFT can be a low-temperature polycrystalline silicon (LTPS) thin-film transistor, or an oxide thin-film transistor, or a combination of both. Specifically, the active portion of the LTPS thin-film transistor is made of low-temperature polycrystalline silicon (LTPS). Low-Temperature Polycrystalline Oxide (LTPO) thin-film transistors (LTPS) utilize oxide semiconductors in their active components. Given the advantages of LTPS, such as high mobility and fast charging, and the advantages of oxide thin-film transistors, such as low leakage current, LTPS and oxide thin-film transistors are integrated onto a single display panel 100 to form a LTPO display panel. This leverages the advantages of both, reducing the power consumption of the display panel 100 and improving image display quality.
[0054] The following illustrative description of embodiments of this disclosure takes the gate drive circuit 210 using LTPO or Oxide as an example, but this disclosure is not limited thereto.
[0055] In some examples, such as Figure 6 As shown, the display panel 100 includes a first conductive layer 40 and an insulating layer 50. The first conductive layer is disposed on the side of the light-shielding layer 20 away from the substrate 10, and the insulating layer 50 is disposed between the first conductive layer 40 and the light-shielding layer 20, and is in contact with both the first conductive layer 40 and the light-shielding layer 20. The light-shielding layer 20 includes a first electrode C1, and the first conductive layer 40 includes a second electrode C2. The second electrode C2 is at least partially opposite to the first electrode C1, forming a capacitor C. Furthermore, at least a portion of the edge of the second electrode C2 extends beyond the first electrode C1.
[0056] In related technologies, the fabrication of the gate driving circuit involves operations such as cleaning and etching of the film layer on the substrate, which involve friction. Since the gate driving circuit is located at the edge of the display panel, static electricity accumulates in the area where the gate driving circuit is located. Because at least a portion of the edge of the first electrode plate lies within the range of the second electrode plate, the insulating layer exhibits a stepped structure in the area projected from the second electrode plate onto the insulating layer. That is, a portion of the insulating layer is located on the side of the first electrode plate away from the substrate, a portion extends along the sidewall of the first electrode plate, and another portion is located in the same layer as the first electrode plate. In this case, because the sidewall of the first electrode plate has a sloping structure, the thickness of the portion of the insulating layer extending along the sidewall of the first electrode plate is reduced compared to the other two portions, resulting in a decrease in the capacitor's withstand voltage performance and an increased risk of electrostatic discharge (ESD) breakdown. Furthermore, this leads to ESD defects in the display panel and a decrease in the production yield of the display panel.
[0057] Based on this, such as Figures 5-8As shown, an embodiment of this disclosure provides a display panel 100 that further includes a first buffer layer 60, which is disposed in the same layer as the light-shielding layer 20. Furthermore, the portion of the second electrode C2 extending beyond the first electrode C1, projected onto the substrate 10, falls within the range of the projected projection of the first buffer layer 60 onto the substrate 10. Within the range of the projected projection of the second electrode C2 onto the insulating layer 50, the insulating layer 50 is close to the surface of the substrate 10 and parallel to the substrate 10.
[0058] In this configuration, by providing a first buffer layer 60, the insulating layer 50 located on the portion of the second electrode C2 extending beyond the first electrode C1 can be raised. This ensures that within the area of the orthogonal projection of the second electrode C2 onto the insulating layer 50, the insulating layer 50 is close to the surface of the substrate 10 and parallel to the substrate 10. Consequently, within the area of the orthogonal projection of the second electrode C2 onto the insulating layer 50, the insulating layer 50 is a film layer parallel to the substrate 10 and of uniform thickness. This improves the problem of decreased voltage withstand performance of the capacitor C and reduces the risk of electrostatic discharge (ESD) breakdown of the capacitor C. Furthermore, it improves the ESD defects in the display panel 100 and increases the production yield of the display panel 100.
[0059] It should be noted that the first buffer layer 60 and the light-shielding layer 20 are disposed in the same layer, meaning that the first buffer layer 60 is close to the surface of the substrate 10 and the light-shielding layer 20 is located on the same plane as the surface of the substrate 10.
[0060] For example, the material of the insulating layer 50 may include inorganic materials. For instance, the material of the insulating layer 50 may include at least one of silicon nitride and silicon oxide. In this way, the insulating layer 50 can serve as the insulating medium between the two plates of the capacitor C.
[0061] In some embodiments, such as Figure 5 and Figure 6 As shown, the first buffer layer 60 is flush with the surface of the first electrode C1, which is away from the substrate 10. In other words, the thickness of the first buffer layer 60 is the same as the thickness of the first electrode C1 along the direction perpendicular to the substrate 10. This allows the insulating layer 50 above the first buffer layer 60 and the first electrode C1 to be a film layer parallel to the substrate 10 and of uniform thickness, thereby improving the problem of decreased voltage withstand performance of the capacitor C and reducing the risk of electrostatic discharge (ESD) damage to the capacitor C. Furthermore, this improves the ESD defects in the display panel 100 and increases the production yield of the display panel 100.
[0062] For example, the material of the first buffer layer 60 includes an inorganic material. For instance, the material of the first buffer layer 60 includes at least one of silicon nitride and silicon oxide.
[0063] In some examples, such as Figure 3 and Figure 5As shown, the first buffer layer 60 and the light-shielding layer 20 cover the peripheral area BB, but the first buffer layer 60 does not cover the display area AA. In other words, the first buffer layer 60 is only located in the peripheral area BB, and together with the light-shielding layer 20, they cover the peripheral area BB.
[0064] It is understood that when fabricating the first buffer layer 60 and the first electrode C1, the first buffer layer 60 can be fabricated first in the peripheral region BB, and then the light-shielding layer 20 can be fabricated. Specifically, a film layer for forming the first buffer layer 60 is deposited on the substrate 10, and then the film layer is patterned and etched; the etched area is used to form the first electrode C1. Alternatively, the first electrode C1 can be fabricated first, and then the first electrode C1 can be fabricated; this embodiment does not specifically limit the specific method used.
[0065] In other embodiments, such as Figure 7 and Figure 8 As shown, the first buffer layer 60 extends away from the surface of the substrate 10, beyond the surface of the first electrode C1 away from the substrate 10, and covers the light-shielding layer 20. The first buffer layer 60 is parallel to the substrate 10. In other words, along a direction perpendicular to the substrate 10, at least a portion of the thickness of the first buffer layer 60 is greater than the thickness of the first electrode C1, so that the first buffer layer 60 covers the surface of the first electrode C1 away from the substrate 10. That is, the first buffer layer 60 planarizes the light-shielding layer 20. In this way, the insulating layer 50 located above the first buffer layer 60 and the first electrode C1 can also be a film layer with uniform thickness parallel to the substrate 10, thereby improving the problem of decreased voltage withstand performance of the capacitor C and reducing the risk of electrostatic discharge breakdown of the capacitor C. Furthermore, it improves the problem of ESD defects in the display panel 100 and improves the production yield of the display panel 100.
[0066] For example, the material of the first buffer layer 60 includes an organic material to achieve planarization of the light-shielding layer 20. For instance, the material of the first buffer layer 60 includes at least one of polymethyl methacrylate (PMMA) and polyacrylate.
[0067] In some examples, such as Figure 3 and Figure 7 As shown, the first buffer layer 60 covers the surrounding area BB but does not cover the display area AA.
[0068] It is understandable that, when preparing the first buffer layer 60 and the first electrode C1, the light-shielding layer 20 can be prepared first, followed by the preparation of the first buffer layer 60. The light-shielding layer 20 is at least partially located in the peripheral region BB, and then the light-shielding layer 20 is planarized to form the first buffer layer 60.
[0069] In some embodiments, such as Figure 5 and Figure 6 As shown, the display panel 100 also includes an active layer 30 and a second conductive layer 70. The active layer 30 is disposed between the light-shielding layer 20 and the first conductive layer 40, and the second conductive layer 70 is disposed between the active layer 30 and the first conductive layer 40. The gate electrode G is located in the second conductive layer 70, the active portion ACT is located in the active layer 30, and the source electrode S and drain electrode D are located in the first conductive layer 40, and are made of the same material as the second electrode C2 and fabricated in the same layer. In this way, the source electrode S and drain electrode D of the transistor TFT can be formed with the second electrode C2 of the capacitor C in a single patterning process, simplifying the process flow, thereby saving production costs and improving production efficiency.
[0070] For example, the source electrode S, drain electrode D, and second electrode C2 are all made of the same material, and all are metallic materials. For instance, the source electrode S, drain electrode D, and second electrode C2 are all made of at least one of Ti, Al, and Au.
[0071] In some examples, such as Figure 5 and Figure 6 As shown, the insulating layer 50 includes an interlayer insulating layer 51 and a second buffer layer 52. The interlayer insulating layer 51 is disposed between the first conductive layer 40 and the second conductive layer 70, and the second buffer layer 52 is disposed between the active layer 30 and the light-shielding layer 20. In this case, the interlayer insulating layer 51 can be used to isolate the first conductive layer 40 and the second conductive layer 70, preventing a short circuit between the source (S) and drain (D) of the transistor TFT and the gate (G). The second buffer layer 52 can be used to isolate the active layer 30 and the light-shielding layer 20.
[0072] In other embodiments, such as Figure 9 As shown, the second conductive layer 70 is disposed on the side of the first conductive layer 40 away from the substrate 10. The source S and drain D are located in the second conductive layer 70, the active portion ACT is located in the active layer 30, and the gate G is located in the first conductive layer 40, and is made of the same material as the second electrode C2 and fabricated in the same layer. In this way, the gate G of the transistor TFT can be formed with the second electrode C2 of the capacitor C in a single patterning process, simplifying the process flow, thereby saving production costs and improving production efficiency.
[0073] For example, the gate G and the second electrode C2 are made of the same material, and both are metallic materials. For instance, the gate G and the second electrode C2 are both made of at least one of Ti, Al, and Au.
[0074] In some examples, such as Figure 9 As shown, the insulating layer 50 includes a second buffer layer 52, which is disposed between the active layer 30 and the light-shielding layer 20. In this case, the second buffer layer 52 can be used to isolate the active layer 30 and the light-shielding layer 20.
[0075] Please continue reading. Figure 5 , Figure 7and Figure 9 The display panel 100 may further include a gate insulating layer 80, which is located between the gate G and the active layer 30. The portion of the active layer 30 opposite to the gate G forms a channel, and the gate insulating layer 80 is used to isolate the gate G and the channel to prevent short circuits.
[0076] The above are merely specific embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.
Claims
1. A display panel, characterized in that, include: Substrate; A light-shielding layer is disposed on one side of the substrate; the light-shielding layer includes a first electrode plate; An active layer is disposed on the side of the light-shielding layer away from the substrate; A first conductive layer is disposed on the side of the active layer away from the substrate; the first conductive layer includes a second electrode plate, which is at least partially opposite to the first electrode plate to form a capacitor; Furthermore, at least a portion of the edge of the second electrode plate extends beyond the first electrode plate; An insulating layer is disposed between the first conductive layer and the light-shielding layer, and is in contact with the first conductive layer and the light-shielding layer; The first buffer layer is disposed in the same layer as the light-shielding layer; Furthermore, the orthographic projection of the portion of the second electrode plate extending beyond the first electrode plate onto the substrate is within the range of the orthographic projection of the first buffer layer onto the substrate; Within the range of the orthogonal projection of the second electrode plate onto the insulating layer, the insulating layer is close to the surface of the substrate and parallel to the substrate.
2. The display panel according to claim 1, characterized in that, The surface of the first buffer layer away from the substrate is flush with the surface of the first electrode plate away from the substrate.
3. The display panel according to claim 1, characterized in that, The first buffer layer is located away from the surface of the substrate, extends beyond the surface of the first electrode plate away from the substrate, and covers the light-shielding layer; the first buffer layer is located away from the surface of the substrate and is parallel to the substrate.
4. The display panel according to claim 1, characterized in that, It also includes transistors, each transistor comprising a gate, an active portion, a source, and a drain; the display panel further includes: A second conductive layer is disposed between the active layer and the first conductive layer; the gate is located in the second conductive layer, and the active portion is located in the active layer; the source and the drain are located in the first conductive layer, and are made of the same material as the second electrode plate and are fabricated in the same layer.
5. The display panel according to claim 4, characterized in that, The insulating layer includes an interlayer insulating layer and a second buffer layer. The interlayer insulating layer is disposed between the first conductive layer and the second conductive layer, and the second buffer layer is disposed between the active layer and the light-shielding layer.
6. The display panel according to claim 1, characterized in that, It also includes transistors, each transistor comprising a gate, an active portion, a source, and a drain; the display panel further includes: The second conductive layer is disposed on the side of the first conductive layer away from the substrate; the source and the drain are located in the second conductive layer, and the active portion is located in the active layer; the gate is located in the first conductive layer and is made of the same material as the second electrode plate and is fabricated in the same layer.
7. The display panel according to claim 6, characterized in that, The insulating layer includes a second buffer layer, which is disposed between the active layer and the light-shielding layer.
8. The display panel according to claim 4 or 6, characterized in that, The display panel includes a display area and a peripheral area located on at least one side of the display area; the display panel further includes: A gate driving circuit is disposed on one side of the substrate and located in the peripheral region; the gate driving circuit includes the transistor and the capacitor.
9. The display panel according to claim 8, characterized in that, When the surface of the first buffer layer away from the substrate is flush with the surface of the first electrode plate away from the substrate, the first buffer layer and the light-shielding layer cover the peripheral area, but the first buffer layer does not cover the display area; or... When the first buffer layer extends beyond the surface of the first electrode plate away from the substrate and covers the light-shielding layer, and when the first buffer layer is parallel to the substrate and away from the substrate, the first buffer layer covers the peripheral area but does not cover the display area.
10. A display device, characterized in that, The display panel includes any one of claims 1 to 9.