Multi-channel fiber grating demodulation control system and method

Abstract

The application discloses a kind of multi-channel fiber grating demodulation control systems and methods, belong to fiber grating demodulation technical field, system includes external sensing module, external signal processing module, STM32 auxiliary control unit and FPGA main control unit;External sensing module provides light source, switching detection channel and acquires reflected spectrum signal;External signal processing module is connected with external sensing module optical path, carries out filtering and analog-digital conversion to reflected spectrum signal, and outputs digital spectrum signal;STM32 auxiliary control unit is electrically connected with external sensing module, controls detection channel switching;FPGA main control unit is electrically connected with external signal processing module and STM32 auxiliary control unit, executes system timing synchronous control, issues detection channel switching control instruction to STM32 auxiliary control unit, and carries out real-time peak searching to digital spectrum signal and obtains demodulation result.The application adopts FPGA and STM32 collaborative architecture, can realize multi-channel high-precision real-time spectrum demodulation, adapts multi-channel high-speed sensing detection scene.

Description

Technical Field

[0001] This invention relates to the field of fiber Bragg grating demodulation technology, specifically to a multi-channel fiber Bragg grating demodulation control system and method. Background Technology

[0002] With the continuous advancement of infrastructure construction and large-scale industrial production activities in my country, engineering environments are placing higher demands on the accuracy, real-time performance, and reliability of multi-physical parameter monitoring. Fiber optic sensing technology, with its unique advantages, is gradually replacing traditional electronic sensors as the mainstream monitoring solution. Among them, fiber Bragg grating (FBG) sensors are widely used in various sensing scenarios due to their passive nature, intrinsic safety, resistance to electromagnetic interference, and ease of achieving distributed and networked monitoring. FBG sensors sense changes in external physical parameters such as temperature, stress, pressure, and displacement by detecting the center wavelength drift of reflected light. Therefore, high-precision demodulation of minute wavelength drifts is the core key to promoting the practical application and engineering of FBG sensing technology.

[0003] Currently, fiber Bragg grating demodulation technology has developed into several mature solutions. Microcontroller or DSP-controlled solutions are widely used in low-speed, single-channel, and low-real-time scenarios due to their simple design, low cost, and low power consumption. Traditional offline peak-finding algorithms are highly stable and can meet the requirements for conventional precision spectral peak identification. Basic modulation and demodulation technologies are reliable in small to medium data volumes and low-frequency transmissions. However, when facing the demands of modern sensing applications requiring multi-channel, high-speed, and high-precision processing, existing technologies have significant limitations: the processing speed and I / O port switching rate of microcontrollers and DSPs are difficult to match the requirements of high-speed switching and real-time data processing across multiple channels; traditional offline peak-finding requires storing the complete spectrum before calculation, consuming significant storage resources and resulting in low demodulation efficiency in scenarios with multiple peak values ​​and large data volumes; and when high-speed data transmission and multi-module collaborative operation increase the requirements for cross-clock domain signal connection and channel switching synchronization, making it difficult for existing timing control schemes to guarantee stable data transmission.

[0004] Existing demodulation technologies have insufficient real-time processing capabilities and low resource utilization efficiency, making them unsuitable for multi-channel, high-speed, and high-precision demodulation requirements. Summary of the Invention

[0005] In view of this, it is necessary to provide a multi-channel fiber Bragg grating demodulation control system and method to solve the technical problems of insufficient real-time processing capability, low resource utilization efficiency, and inability to adapt to the needs of multi-channel high-speed and high-precision demodulation in the existing technology.

[0006] To address the aforementioned technical problems, in a first aspect, the present invention provides a multi-channel fiber Bragg grating demodulation control system, comprising: External sensing module, external signal processing module, STM32 auxiliary control unit and FPGA main control unit; The external sensing module is used to provide a light source, switch the sensing channel to be detected, and acquire reflectance spectrum signals. The external signal processing module is optically connected to the external sensing module and is used to filter and convert the acquired reflectance spectral signal into an analog-to-digital signal, and output a digital spectral signal. The STM32 auxiliary control unit is electrically connected to the external sensing module and is used to control the switching of the sensing channel to be detected. The FPGA main control unit is electrically connected to the external signal processing module and the STM32 auxiliary control unit, and is used to perform system timing synchronization control, issue switching control commands for the sensor channels to be detected to the STM32 auxiliary control unit, and perform real-time peak finding processing on the digital spectral signal to obtain demodulation results. In one possible implementation, the external sensing module includes an ASE light source, a circulator, an optical switch, and a multi-channel FBG sensor; The light-emitting end of the ASE light source is connected to the incident end of the circulator to output broadband continuous light and provide a stable reference light source for the sensing optical path. The circulator's output end is connected to an optical switch to unidirectionally guide the light source's optical path into the optical switch; the circulator's reflective end is connected to the optical path of an external signal processing module to unidirectionally send the light signal reflected by the FBG sensor into the external signal processing module for spectral signal processing, while suppressing optical path back-transmission interference. The input end of the optical switch is connected to the output end of the circulator, and the output end is connected to the multi-channel FBG sensor for switching multiple optical paths; each channel of the multi-channel FBG sensor corresponds to a detection point. The multi-channel FBG sensor is used to sense the physical quantity to be detected and generate a reflectance spectrum signal.

[0007] In one possible implementation, the external signal processing module includes a CCD demodulation module, a signal operational amplifier, an ADC converter, and a temperature compensation circuit. The CCD demodulation module is optically connected to the external sensing module and is used to receive the reflection spectrum signal output by the external sensing module and output the original analog spectrum signal. The signal operational amplifier is electrically connected to the CCD demodulation module and is used to filter and reduce noise and amplify the amplitude of the original analog spectral signal, and output the conditioned analog spectral signal. The ADC converter is electrically connected to the signal operational amplifier and is used to convert the conditioned analog spectral signal into a digital spectral signal. The temperature compensation circuit is electrically connected to the CCD demodulation module and is used to acquire the real-time operating temperature of the CCD demodulation module and the real-time operating temperature of the system, and output an analog temperature signal.

[0008] In one possible implementation, the STM32 auxiliary control unit is also connected to the external signal processing module for configuring the operating parameters of the ADC converter; the STM32 auxiliary control unit includes an STM32 controller and an STM32 built-in ADC conversion chip. The STM32's built-in ADC conversion chip is used to convert the analog temperature signal into a digital temperature signal. The STM32 controller is connected to the STM32 built-in ADC conversion chip and is used to control the STM32 built-in ADC conversion chip to perform analog-to-digital conversion and send the digital temperature signal to the FPGA main control unit.

[0009] In one possible implementation, the FPGA main control unit includes internal FPGA functional timing logic circuits, system hardware circuits, and external signal receiving ports; The external signal receiving port is used to receive the digital spectral signal output by the external signal processing module and the digital temperature signal output by the STM32 auxiliary control unit. The internal functional timing logic circuit of the FPGA is electrically connected to the external signal receiving port to generate the system working timing and to perform real-time peak finding and demodulation of the spectral signal based on the digital spectral signal. The system hardware circuit is electrically connected to the internal functional timing logic circuit of the FPGA, and is used to provide stable power supply and program configuration and operation support for the FPGA main control unit.

[0010] In one possible implementation, the FPGA internal functional sequential logic circuit includes a top-level module, an AD acquisition and CCD control module, an optical switch driving module, an internal clock frequency divider module, an FBG peak finding module, a filtering module, a peak calculation module, a floating-point conversion IP core, and a division operation IP core. The top-level module is used to coordinate the collaborative work of various sub-modules under the internal functional timing logic circuit of the FPGA, and to schedule timing and data flow. The AD acquisition and CCD control module is connected to the external signal processing module and the top-level module, and is used to control AD ​​conversion and CCD demodulation and acquire digital spectral signals. The optical switch driver module is connected to the STM32 auxiliary control unit and the top-level module, and is used to drive the optical switch to complete multi-channel switching. The internal clock divider module is connected to the top-level module and is used to provide timing synchronization signals for the system. The FBG peak finding module is connected to the top-level module and is used for peak finding processing of digital spectral signals; The filtering module is connected to the FBG peak finding module and is used to perform filtering and noise reduction processing on the digital spectral signal received by the peak finding module. The peak calculation module is connected to the filtering module and is used to calculate the center wavelength corresponding to the peak value of the filtered and denoised digital spectral signal. The floating-point conversion IP core is connected to the peak calculation module and is used to convert the digital spectral signal in the peak region and its product with the corresponding center wavelength into floating-point format respectively. The division operation IP core is connected to the peak calculation module and the floating-point conversion IP core, and is used to perform a division operation on the sum of the products in floating-point format and the sum of the spectral signals, and feed the operation result back to the peak calculation module.

[0011] In one possible implementation, the internal functional timing logic circuit of the FPGA further includes a 422 data cache module, a USB data cache module, a USB control module, and a 422 control module; The USB data cache module and the 422 data cache module are both connected to the top-level module and are used to temporarily store demodulated data. The USB control module is connected to the top-level module and the USB data cache module, and is used to control the USB interface communication timing to realize data interaction with external devices. The 422 control module is connected to the top-level module and the 422 data cache module, and is used to control the communication timing of the 422 interface to realize data interaction with external devices.

[0012] In one possible implementation, the system hardware circuit includes a system power supply circuit, a reset circuit, an external clock circuit, and a debugging and configuration circuit. The reset circuit is used to provide power-on reset and manual reset signals to the FPGA main control unit to complete the system power-on initialization. The system power supply circuit is used to output multiple stable voltages to provide stable power supply for the FPGA main control unit; The debugging and configuration circuit is used to support online FPGA program download, firmware configuration, and online system debugging. The external clock circuit is used to output an external reference clock signal, providing the original clock source for each logic module inside the FPGA.

[0013] In one possible implementation, the system further includes a host computer and a data communication interface module; The data communication interface module is electrically connected to the FPGA main control unit and is used to forward the demodulation control commands from the host computer and the demodulation results output by the FPGA main control unit; the data communication interface module includes a USB 2.0 high-speed communication module and a 422 serial port communication module; The host computer is electrically connected to the data communication interface module and is used to send demodulation control commands to the FPGA main control unit, receive the demodulation results output by the FPGA main control unit, and perform temperature compensation on the demodulation results based on the digital temperature signal to obtain the temperature-compensated demodulation results.

[0014] Secondly, the present invention also provides a multi-channel fiber Bragg grating demodulation control method, based on the multi-channel fiber Bragg grating demodulation control system described in any of the above implementations, comprising: The external sensing module provides a light source, switches the sensing channel to be detected, and collects the reflectance spectrum signal. The external signal processing module filters and performs analog-to-digital conversion on the acquired reflectance spectrum signal to output a digital spectrum signal. The switching of the sensor channel to be detected is controlled by the STM32 auxiliary control unit. The FPGA main control unit executes system timing synchronization control, sends the control command for switching the sensor channel to be detected to the STM32 auxiliary control unit, and performs real-time peak finding processing on the digital spectral signal to obtain the demodulation result.

[0015] The beneficial effects of this invention are as follows: The multi-channel fiber optic grating demodulation control system provided by this invention, firstly, can stably supply light source through an external sensing module, flexibly realize multi-channel sensing channel switching, and accurately acquire reflectance spectral signals, possessing good multi-channel adaptability and providing a continuous and reliable raw optical signal input foundation for demodulation operations; secondly, through the optical path connection between the external signal processing module and the external sensing module, it can perform regularization filtering and analog-to-digital conversion processing on the acquired reflectance spectral signals, and output pure and stable digital spectral signals, improving the accuracy and adaptability of subsequent signal processing; furthermore, through the STM32 auxiliary... The auxiliary control unit is electrically connected to the external sensing module, which can reliably control the switching of the sensing channels under test, ensuring stable and orderly channel switching and sharing the task of underlying logic control. Finally, through the FPGA main control unit, it is electrically connected to the external signal processing module and the STM32 auxiliary control unit, which can uniformly execute the system timing synchronization control, orderly send down the control commands for switching of the sensing channels under test, and perform real-time peak finding processing on the digital spectral signal to quickly obtain the demodulation result. Overall, it has high real-time performance, high resource utilization efficiency and high-precision demodulation performance, and can well adapt to the needs of multi-channel, high-speed and high-precision sensing applications. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 A schematic diagram of an embodiment of the multi-channel fiber optic grating demodulation control system provided by the present invention; Figure 2 A schematic diagram of an embodiment of the FPGA internal functional sequential logic circuit provided by the present invention; Figure 3 A schematic diagram of an embodiment of the FPGA top-level module provided by the present invention; Figure 4 A schematic flowchart of an embodiment of the multi-channel fiber Bragg grating demodulation control method provided by the present invention; Figure 5 This is a schematic flowchart of another embodiment of the multi-channel fiber Bragg grating demodulation control method provided by the present invention; Figure 6 A schematic flowchart of an embodiment of the SG filtering provided by the present invention; Figure 7 This is a schematic flowchart of an embodiment of the working process of the FBG peak finding module provided by the present invention; Figure 1 In the middle section: 1: Host computer, 2: External sensing module, 2-1: ASE light source, 2-2: Circulator, 2-3: Optical switch, 2-4: Multi-channel FBG sensor, 3: FPGA main control unit, 3-1: FPGA internal functional timing logic circuit, 3-2: System hardware circuit, 3-21: Reset circuit, 3-22: System power supply circuit, 3-23: Debugging and configuration circuit, 3-24: External clock circuit, 3-3: External signal receiving port, 4: STM32 auxiliary control unit, 4-1: STM32 controller, 4-2: STM32 built-in ADC conversion chip, 5: External signal processing module, 5-1: CCD demodulation module, 5-2: Signal operational amplifier, 5-3: ADC converter, 5-4: Temperature compensation circuit, 6: Data communication interface module, 6-1: USB 2.0 high-speed communication module, 6-2: 422 serial communication module; Figure 3In the middle: 3-11: Top-level module, 3-12: AD acquisition and CCD control module, 3-13: Optical switch driver module, 3-14: Internal clock divider module, 3-15: FBG peak finding module, 3-16: Peak value calculation module, 3-17: Floating-point conversion IP core, 3-18: Division operation IP core, 3-19: 422 data buffer module, 3-20: Filtering module, 3-110: USB data buffer module, 3-111: USB control module, 3-112: 422 control module. Detailed Implementation

[0018] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0019] In the description of the embodiments of the present invention, unless otherwise stated, "multiple" means two or more. "And / or" describes the relationship between related objects, indicating that there can be three relationships. For example, A and / or B can represent three situations: A exists alone, A and B exist simultaneously, and B exists alone.

[0020] The terms "first," "second," etc., used in the embodiments of this invention are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a technical feature defined with "first" or "second" may explicitly or implicitly include at least one of that feature.

[0021] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of the invention. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0022] Before demonstrating the embodiments, the following terms will be explained.

[0023] Fiber Bragg grating: A passive optical device with a periodic refractive index modulation structure etched in the core region of an optical fiber, which can reflect specific wavelength optical signals in response to changes in external physical quantities, and is the basic element of the fiber optic sensing of this invention. ASE light source: Amplified spontaneous emission light source with wide spectrum and low coherence emission characteristics, providing stable and continuous incident reference light for the sensing optical path of this invention; FIFO buffer: First-in-first-out data storage unit, used for data buffering across clock domains in digital systems to match the data transmission rates of different modules; Timing synchronization: Enables all hardware modules of the system to work together according to a unified clock cycle, ensuring the timing matching of signal acquisition, processing, and transmission; System reset: The operation that forces the internal registers and working state machine of a digital device to return to their initial idle state. It is used for device power-on initialization and abnormal reset.

[0024] This invention provides a multi-channel fiber Bragg grating demodulation control system and method, which will be described below.

[0025] Figure 1 This is a schematic diagram of an embodiment of the multi-channel fiber optic grating demodulation control system provided by the present invention, as shown below. Figure 1 As shown, the multi-channel fiber Bragg grating demodulation control system includes: External sensing module 2, external signal processing module 5, STM32 auxiliary control unit 4, and FPGA main control unit 3; External sensing module 2 is used to provide a light source, switch the sensing channel to be detected, and acquire reflectance spectrum signals; The external signal processing module 5 is optically connected to the external sensing module 2 and is used to filter and convert the acquired reflectance spectrum signal into digital spectrum signal. The STM32 auxiliary control unit 4 is electrically connected to the external sensing module 2 and is used to control the switching of the sensing channel to be detected. The FPGA main control unit 3 is electrically connected to the external signal processing module 5 and the STM32 auxiliary control unit 4. It is used to perform system timing synchronization control, send the switching control command of the sensor channel to be detected to the STM32 auxiliary control unit 4, and perform real-time peak finding processing on the digital spectral signal to obtain the demodulation result.

[0026] In some embodiments of the present invention, the FPGA main control unit 3 is an FPGA chip, specifically the EP4CE10E22C8.

[0027] In summary, the multi-channel fiber Bragg grating demodulation control system provided in this embodiment of the invention firstly, through an external sensing module, can stably supply a light source, flexibly switch between multiple sensing channels, and accurately acquire reflectance spectral signals, possessing excellent multi-channel adaptability and providing a continuous and reliable raw optical signal input foundation for demodulation operations; secondly, through an external signal processing module connected to the external sensing module's optical path, it can perform regularization filtering and analog-to-digital conversion processing on the acquired reflectance spectral signals, outputting pure and stable digital spectral signals, improving the accuracy and adaptability of subsequent signal processing; and thirdly, through STM32 assistance... The control unit is electrically connected to the external sensing module, which can reliably control the switching of the sensing channels under test, ensuring stable and orderly channel switching and sharing the task of underlying logic control. Finally, through the FPGA main control unit, it is electrically connected to the external signal processing module and the STM32 auxiliary control unit, which can uniformly execute the system timing synchronization control, orderly send down the control commands for switching of the sensing channels under test, and perform real-time peak finding processing on the digital spectral signal to quickly obtain the demodulation result. Overall, it has high real-time performance, high resource utilization efficiency and high-precision demodulation performance, and can well adapt to the needs of multi-channel, high-speed and high-precision sensing applications.

[0028] In some embodiments of the present invention, such as Figure 1 As shown, the external sensing module 2 includes an ASE light source 2-1, a circulator 2-2, an optical switch 2-3, and a multi-channel FBG sensor 2-4; The light-emitting end of the ASE light source 2-1 is connected to the incident end of the circulator 2-2 to output broadband continuous light and provide a stable reference light source for the sensing optical path. The output end of the circulator 2-2 is connected to the optical switch 2-3 to guide the light source light path unidirectionally into the optical switch; the reflection end of the circulator 2-2 is connected to the optical path of the external signal processing module 5 to send the light signal reflected by the FBG sensor 2-4 unidirectionally into the external signal processing module 5 for spectral signal processing, while suppressing optical path back-transmission interference. The input end of the optical switch 2-3 is connected to the output end of the circulator 2-2, and the output end is connected to the multi-channel FBG sensor 2-4 for switching multiple optical paths; each channel of the multi-channel FBG sensor 2-4 corresponds to a detection point. Multi-channel FBG sensors 2-4 are used to sense the physical quantity to be detected and generate a reflectance spectrum signal.

[0029] In this embodiment, the structure of the external sensing module 2 can output a stable broadband reference light source, realize unidirectional optical path transmission and multi-channel optical path switching, effectively suppress optical path back-transmission interference, accurately sense the physical quantities at each detection point and generate reflection spectrum signals, providing a reliable optical path and original optical signal basis for subsequent demodulation.

[0030] In some embodiments of the present invention, such as Figure 1 As shown, the external signal processing module 5 includes a CCD demodulation module 5-1, a signal operational amplifier 5-2, an ADC converter 5-3, and a temperature compensation circuit 5-4. The CCD demodulation module 5-1 is optically connected to the external sensing module 2 and is used to receive the reflection spectrum signal output by the external sensing module 2 and output the original analog spectrum signal. The signal operational amplifier 5-2 is electrically connected to the CCD demodulation module 5-1, and is used to filter and reduce noise and amplify the amplitude of the original analog spectral signal, and output the conditioned analog spectral signal. The ADC converter 5-3 is electrically connected to the signal operational amplifier 5-2 and is used to convert the conditioned analog spectral signal into a digital spectral signal. The temperature compensation circuit 5-4 is electrically connected to the CCD demodulation module 5-1 and is used to acquire the real-time operating temperature of the CCD demodulation module 5-1 and the real-time operating temperature of the system, and output an analog temperature signal.

[0031] In some embodiments of the present invention, the real-time operating temperature of the CCD demodulation module 5-1 and the real-time operating temperature of the system are collected to correct the spectral drift of the CCD demodulation device and the entire system caused by temperature changes. In this embodiment, each module in the external signal processing module 5 can complete the photoelectric conversion of spectral signals, hardware filtering and amplification, and analog-to-digital conversion. At the same time, it can collect the device operating temperature in real time and compensate and correct spectral drift, effectively improving signal purity and digital signal adaptability, and ensuring the overall accuracy of spectral demodulation.

[0032] In some embodiments of the present invention, such as Figure 1 As shown, the STM32 auxiliary control unit 4 is also connected to the external signal processing module 5 for configuring the operating parameters of the ADC converter 5-3; the STM32 auxiliary control unit 4 includes an STM32 controller 4-1 and an STM32 built-in ADC conversion chip 4-2. The STM32 has a built-in ADC converter chip 4-2 used to convert analog temperature signals into digital temperature signals. The STM32 controller 4-1 is connected to the STM32 built-in ADC conversion chip 4-2 and is used to control the STM32 built-in ADC conversion chip 4-2 to perform analog-to-digital conversion and send the digital temperature signal to the FPGA main control unit 3.

[0033] In some embodiments of the present invention, the signal operational amplifier 5-2 performs hardware filtering and amplification of the analog spectral signal output by the CCD demodulation module 5-1 through an ADA4807 operational amplifier combined with an RC low-pass filter network, suppressing high-frequency noise introduced during photoelectric conversion and transmission. The ADC converter 5-3 converts the analog signal into a digital signal through the single-channel SHA mode of the AD9826 chip. The optical switch driver module 3-13 receives the control signal from the STM32 auxiliary control unit 4 and drives the optical switch 2-3 to complete multi-channel optical path switching. The temperature compensation circuit 5-4 collects the temperature signal and sends it to the STM32 auxiliary control unit 4. After analog-to-digital conversion is completed by the STM32 built-in ADC conversion chip 4-2, the obtained temperature value is fed back to the FPGA main control unit 3. The STM32 controller 4-1 communicates with the FPGA main control unit 3 via the UART asynchronous serial port protocol, receives the channel switching command from the FPGA main control unit 3, drives the optical switch 2-3 to complete the optical path switching, and simultaneously collects the temperature data of the temperature compensation circuit 5-4 and feeds it back to the FPGA main control unit 3 to realize wavelength temperature compensation. When the optical switch 2-3 switches, the STM32 auxiliary control unit 4 sets a delay of 0.8ms to ensure that the switching is stable before feeding back the status, which adapts to the timing requirements of multi-channel cyclic demodulation.

[0034] This embodiment employs a dedicated chip architecture combined with UART communication and timing delay design, which can accurately complete the analog-to-digital conversion of temperature signals, channel command interaction and stable control of optical path switching, achieve wavelength temperature compensation, and adapt to the timing requirements of multi-channel cyclic demodulation.

[0035] In some embodiments of the present invention, such as Figure 1 As shown, the FPGA main control unit 3 includes an internal FPGA functional timing logic circuit 3-1, a system hardware circuit 3-2, and an external signal receiving port 3-3. External signal receiving port 3-3 is used to receive the digital spectral signal output by external signal processing module 5 and the digital temperature signal output by STM32 auxiliary control unit 4; The internal functional timing logic circuit 3-1 of the FPGA is electrically connected to the external signal receiving port 3-3 to generate the system working timing and to complete real-time peak finding and demodulation of the spectral signal based on the digital spectral signal. The system hardware circuit 3-2 is electrically connected to the FPGA internal functional timing logic circuit 3-1, which is used to provide stable power supply and program configuration and operation support for the FPGA main control unit 3.

[0036] This embodiment, by dividing functional logic, hardware circuits, and signal receiving ports, can stably receive multiple external spectral and temperature signals, autonomously generate system operating timing, and complete real-time peak finding and demodulation. The hardware power supply and program configuration support are reliable, ensuring the overall operational stability of the main control unit.

[0037] In some embodiments of the present invention, such as Figure 2 As shown, the FPGA internal functional sequential logic circuit 3-1 includes a top-level module 3-11, an AD acquisition and CCD control module 3-12, an optical switch driver module 3-13, an internal clock divider module 3-14, an FBG peak finding module 3-15, a filtering module 3-20, a peak value calculation module 3-16, a floating-point conversion IP core 3-17, and a division operation IP core 3-18; The top-level module 3-11 is used to coordinate the collaborative work of the various sub-modules under the internal functional timing logic circuit 3-1 of the FPGA, and to schedule timing and data flow. The AD acquisition and CCD control module 3-12 is connected to the external signal processing module 5 and the top-level module 3-11, and is used to control AD ​​conversion and CCD demodulation and acquire digital spectral signals. The optical switch driver module 3-13 is connected to the STM32 auxiliary control unit 4 and the top-level module 3-11, and is used to drive the optical switch to complete multi-channel switching. The internal clock divider module 3-14 is connected to the top-level module 3-11 and is used to provide timing synchronization signals for the system. The FBG peak finding module 3-15 is connected to the top-level module 3-11 and is used for peak finding processing of digital spectral signals; The filtering module 3-20 is connected to the FBG peak finding module 3-15 and is used to perform filtering and noise reduction processing on the digital spectral signal received by the peak finding module. Peak calculation module 3-16 is connected to filter module 3-20 and is used to calculate the center wavelength corresponding to the peak value of the digital spectral signal after filtering and noise reduction. The floating-point conversion IP core 3-17 is connected to the peak calculation module 3-16 and is used to convert the digital spectral signal in the peak region and its product with the corresponding center wavelength into floating-point format respectively. The division operation IP core 3-18 is connected to the peak calculation module 3-16 and the floating-point conversion IP core 3-17. It is used to perform division operations on the sum of the products in floating-point format and the sum of the spectral signals, and feeds back the calculation results to the peak calculation module.

[0038] In some embodiments of the present invention, the high-frequency clock signal in the internal clock divider module 3-14 is obtained from the clock IP core (PLL) of the FPGA main control unit 3; The internal clock divider module 3-14 in the FPGA's internal functional timing logic circuit 3-1 is used to divide the high-frequency clock signal obtained from the FPGA's internal functional timing logic circuit 3-1, outputting three divided clock signals: the first is 5MHz, used as the working clock for the CCD demodulation module 5-1 and ADC converter 5-3, the FIFO read clock, and the communication clock for the 422 control module 3-112; the second is 10MHz, used as the FIFO write clock; and the third is 60MHz, used as the communication clock for the USB control module 3-111. These three divided clock signals are used for signal acquisition, data buffering, and data transmission timing synchronization, respectively. After receiving external signals, the FPGA internal functional timing logic circuit 3-1 outputs the switching control signal of the optical switch 2-3, the exposure control signal of the CCD demodulation module 5-1, and the acquisition control signal of the ADC converter 5-3. At the same time, it performs real-time peak finding processing on the digital spectral signal converted by the ADC converter 5-3 to generate peak centroid coordinate data. Finally, the data is packaged in a predetermined format by the AD acquisition and CCD control module 3-12.

[0039] In this embodiment, the sub-modules of the FPGA internal functional timing logic circuit 3-1 have clear division of labor and unified scheduling. They can independently complete clock frequency division, timing generation, spectrum acquisition, peak finding operation and numerical format conversion. Multi-channel clock frequency division can accurately match the working timing of each device, and the data is packaged in a standardized format, which effectively improves the system timing synchronization and demodulation processing efficiency.

[0040] In some embodiments of the present invention, such as Figure 2 As shown, the FPGA internal functional sequential logic circuit 3-1 also includes a 422 data buffer module 3-19, a USB data buffer module 3-110, a USB control module 3-111, and a 422 control module 3-112; Both the USB data cache module 3-110 and the 422 data cache module 3-19 are connected to the top-level module 3-11 and are used to temporarily store demodulated data. USB control module 3-111 is connected to top-level module 3-11 and USB data cache module 3-110, and is used to control the USB interface communication timing to realize data interaction with external devices; The 422 control module 3-112 is connected to the top-level module 3-11 and the 422 data cache module 3-19, and is used to control the communication timing of the 422 interface to realize data interaction with external devices.

[0041] The specific functions of the sub-module of FPGA internal sequential logic circuit 3-1 are as follows: Top-level module 3-11: As the top-level control core module of FPGA main control unit 3, it realizes the overall working state transition of the multi-channel fiber optic demodulation control system and the scheduling management of all sub-modules through the main state machine; it can receive instructions from USB control module 3-111 or 422 control module 3-112 to complete the entire process of optical channel switching, spectrum acquisition, and data transmission; it supports independent modification of threshold and exposure time parameters, and parameter changes do not affect the operation of the main state machine; it also calls all sub-modules and coordinates the signal and data interaction between modules. AD Acquisition and CCD Control Module 3-12: This module controls the timing of the ADC converter 5-3 and the CCD demodulation module 5-1. It controls the RESET signal according to the operating timing of the CCD demodulation module 5-1 to achieve precise exposure, and generates acquisition trigger signals based on the timing requirements of the CCD demodulation module 5-1 and the ADC converter 5-3. This module uses the single-channel SHA mode of the ADC converter 5-3 to complete the analog-to-digital conversion of the analog spectral signal, controls the timing matching requirements of the ADC converter 5-3 acquisition, and sends the acquired AD data to the USB data buffer module 3-110 or the 422 data buffer module 3-19 to ensure the accuracy of spectral data acquisition. Optical switch driver module 3-13: This module can realize optical channel switching, send channel switching commands to the STM32 auxiliary control unit 4, receive feedback signals for switching completion, ensure the switching time of optical switch 2-3 through the delay of the STM32 auxiliary control unit 4, and complete the state transition after confirming successful channel switching. It can also realize temperature data transmission, receive temperature data from the temperature compensation circuit 5-4 collected by the STM32 auxiliary control unit 4 in real time, and perform format conversion on the temperature data to provide data support for subsequent wavelength correction. Internal clock divider module 3-14: Provides matching clock signals for each hardware component and module. It generates the operating clock for the CCD demodulation module 5-1 and the ADC converter 5-3, configures the write or read clock for the USB data buffer module 3-110 or 422 data buffer module 3-19 of the USB control module 3-111 or 422 control module 3-112, and configures a dedicated read clock for the 422 data buffer module 3-19 for communication with the 422 control module 3-112, ensuring stable operation of each module at the matched clock frequency. Filtering module 3-20: This module performs real-time smoothing of the spectral data acquired from the AD acquisition and CCD control module 3-12 through filtering and interpolation. When the signal of the effective spectrum output by the AD acquisition and CCD control module 3-12 is received, the received spectral data is filtered and smoothed every ten data points, thereby achieving spectral noise reduction at the program level. FBG Peak Finding Module 3-15: This module completes the spectral peak finding processing at the FPGA main control unit 3. When a peak finding command is received, it receives the spectral signal after processing by the filtering module 3-20 in real time, and at the same time judges and stores the coordinates of the FBG peak region that exceeds the threshold and transmits the light intensity of the peak region to the peak calculation module 3-16. Peak calculation module 3-16: Receives the peak-finding region from FBG peak-finding module 3-15 and calls the built-in IP core in Quartus II to calculate the peak coordinates. This module changes the original array storage of peak points to real-time calculation of the numerator and denominator of the centroid formula, reducing the resource consumption of FPGA main control unit 3. The peak-finding results are stored in USB data cache module 3-110 or 422 data cache module 3-19, and uploaded to the host computer 1 along with the original spectral data via USB control module 3-111 or 422 control module 3-112. This also solves the problem of accidental loss of multi-FBG peak-finding results. Floating-point conversion IP core 3-17: Converts integers to IEEE-754 standard floating-point numbers, and can convert signed integers to single-precision, double-precision, or single-precision extended type floating-point numbers; Division IP core 3-18: Implements floating-point division function to improve the accuracy of calculated peak coordinates; 422 Data Buffer Module 3-19: Implements 422 communication data buffering and cross-clock domain data transmission; USB data buffer module 3-110: Implements USB communication data buffering and cross-clock domain data transmission; USB control module 3-111: Responsible for controlling the FT232 chip to realize USB communication, strictly following the synchronous FIFO read and write timing of the FT232 chip to complete USB data read and write between the host computer 1 and the FPGA main control unit 3; 422 Control Module 3-112: Enables 422 serial communication between FPGA main control unit 3 and host computer 1, completes data transmission and reception control, and ensures the transmission of instructions and data through the 422 interface; The system hardware circuit 3-2 in the FPGA main control unit 3 includes 3-21 reset circuit 3-21, 3-22 system power supply circuit 3-22, and 3-23 debugging and configuration circuit 3-23, with the following specific functions; Reset circuit 3-21: Provides a stable external reset signal. It outputs a high level when there is no reset operation and a low level when the reset button is pressed, thus realizing the external reset of FPGA main control unit 3. System power supply circuit 3-22: Ensures stable power supply to FPGA main control unit 3 through power conversion circuit; Debugging configuration circuit 3-23: includes JTAG interface, AS interface and EPCS4SI8 chip. JTAG interface is used for online debugging, AS interface is used for embedding Verilog code. After the FPGA main control unit 3 is powered on, it reads the code from the EPCS4SI8 chip and runs it. To achieve the intended goals, this invention first redesigned and rewired the internal array of the EP4CE10E22C8 according to functional logic using the Quartus II development environment, and redefined the pins. Finally, timing verification was performed using a logic analyzer in the development environment.

[0042] This embodiment adds a dedicated data cache and communication control module, which can realize cross-clock domain data caching and reliable transmission and reception; each functional sub-module can independently complete state scheduling, accurate exposure, spectral smoothing and noise reduction, peak centroid calculation and optimize hardware resource usage; the hardware circuit can ensure reset, stable power supply and online debugging; parameters can be configured independently without affecting the main process; the system flexibility, stability and resource utilization are greatly improved.

[0043] In some embodiments of the present invention Figure 3 This is a schematic diagram of an embodiment of the FPGA top-level module provided by the present invention; the FPGA main control unit 3, as the core device of the present invention, has input and output functions, and its input and output definitions and logic are as follows: (1) Input signal: clk: FPGA main control unit 3 system master clock; sys_rst_n: System reset pin, active low. When reset, it clears the internal registers and state machine of FPGA main control unit 3 and returns to the IDLE initial state. AD_sp: Synchronization signal input between CCD demodulation module 5-1 and ADC converter 5-3. It is the digital start signal converted by ADC converter 5-3. A high signal indicates that CCD demodulation module 5-1 is about to output an electrical signal converted from a valid optical signal. AD_trig: This signal is used to synchronously acquire electrical signals on the rising edge of the AD flip-flop; addata: The converted digital spectral data input to the ADC converter 5-3 is the source of the original spectral data for the multi-channel fiber optic demodulation control system. It also includes temperature data from the temperature compensation circuit 5-4, peak-finding data from the FBG peak-finding module 3-15, frame header and frame tail information, etc. usb_clk_60m: The 60MHz clock output by the USB 2.0 high-speed communication module 6-1 (FT232H) is specifically used for the read and write timing control of the synchronous FIFO of the USB data cache module 3-110 to ensure the synchronization of USB data transmission. usb_rxf_n: The FIFO readable signal of the USB 2.0 high-speed communication module 6-1 (FT232H), active low, indicating that there are demodulation instructions issued by the host computer 1 in the USB data buffer module 3-110, which can be read by the FPGA main control unit 3; usb_txe_n: The FIFO writable signal of the USB 2.0 high-speed communication module 6-1 (FT232H), active low, indicating that the USB data buffer module 3-110 is idle, and the FPGA main control unit 3 can write the demodulation result and upload it to the host computer 1; FPGA_RX: UART receive pin of FPGA main control unit 3 and STM32 auxiliary control unit 4, receiving the current channel number of optical switch 2-3 and temperature compensation data of temperature compensation circuit 5-4 fed back by STM32 auxiliary control unit 4; UART_RX: The UART receive pin of the FPGA main control unit 3 and the 422 serial communication module 6-2, which receives demodulation commands sent by the host computer 1 through the 422 serial communication module 6-2; (2) Output signal: cdsclk2: is the sampling clock of ADC converter 5-3. ADC converter 5-3 samples the input waveform of each channel on its falling edge. adcclk: The operating clock output of ADC converter 5-3, providing a timing reference for ADC converter 5-3; RESET: Exposure control pin of CCD demodulation module 5-1, which controls the exposure time of CCD demodulation module 5-1 and is the core control signal for spectral acquisition; usb_oe_n: Output enable pin of USB 2.0 high-speed communication module 6-1 (FT232H), active low, controls the output enable of the USB data bus to prevent data conflicts; usb_rd_n: FIFO read enable pin of USB 2.0 high-speed communication module 6-1 (FT232H), active low. FPGA main control unit 3 pulls this signal low to read the host computer 1 instruction in USB data buffer module 3-110; usb_wr_n: The FIFO write enable pin of the USB 2.0 high-speed communication module 6-1 (FT232H), active low. When the FPGA main control unit 3 pulls this signal low, the demodulated data is written to the USB data buffer module 3-110. usb_siwu_n: Enables immediate FIFO data transmission in the USB 2.0 high-speed communication module 6-1 (FT232H), active low; clk_5M: The 5MHz clock output by the internal clock divider module 3-14 is used to provide the working clock for the ADC converter 5-3 and the CCD demodulation module 5-1, matching their timing requirements; FPGA_IO2: System idle indicator pin. A high level indicates that the system is idle, and a low level indicates that the system is working. OBE: Output enable of ADC converter 5-3, active low; cf_s2: Conversion efficiency control pin of CCD demodulation module 5-1, set to low level; cdsclk1: CDS reference level sampling clock for ADC converter 5-3; FPGA_TX: The UART transmit pin of the FPGA main control unit 3 and the STM32 auxiliary control unit 4, which sends the switching command of the light-emitting switch 2-3 channel to the STM32 auxiliary control unit 4; UART_TX: The UART transmit pin of the FPGA main control unit 3 and the 422 serial communication module 6-2, used to upload demodulation results or send a 422 response signal; RS485_EN: Transmit / receive enable pin of 422 serial communication module 6-2. A high level indicates that the FPGA main control unit 3 sends data through the 422 serial communication module 6-2, and a low level indicates that the FPGA main control unit 3 receives data to prevent bus conflicts. (3) Two-way signal: usb_data: The bidirectional 8-bit data bus of the USB 2.0 high-speed communication module 6-1 (FT232H), and the instruction or data transmission channel between the FPGA main control unit 3 and the USB 2.0 high-speed communication module 6-1.

[0044] In some embodiments of the present invention, such as Figure 1 As shown, the system hardware circuit 3-2 includes a system power supply circuit 3-22, a reset circuit 3-21, an external clock circuit 3-24, and a debugging and configuration circuit 3-23; Reset circuit 3-21 is used to provide power-on reset and manual reset signals for FPGA main control unit 3 to complete system power-on initialization; System power supply circuit 3-22 is used to output multiple stable voltages to provide stable power supply for FPGA main control unit 3; The debugging and configuration circuit 3-23 is used to support online FPGA program download, firmware configuration, and online system debugging. External clock circuit 3-24 is used to output an external reference clock signal, providing the original clock source for each logic module inside the FPGA.

[0045] In this embodiment, the various circuit units in system hardware circuit 3-2 have clear division of labor, providing reliable power-on and manual reset, multiple stable power supplies, external reference clock output, and online program download and debugging capabilities, providing complete hardware support for the long-term stable operation of the FPGA main control unit, hardware initialization, and function upgrades.

[0046] In some embodiments of the present invention, such as Figure 1 As shown, the system also includes a host computer 1 and a data communication interface module 6; The data communication interface module 6 is electrically connected to the FPGA main control unit 3 and is used to forward the demodulation control commands from the host computer 1 and the demodulation results output by the FPGA main control unit 3. The data communication interface module 6 includes a USB 2.0 high-speed communication module 6-1 and a 422 serial communication module 6-2. The host computer 1 is electrically connected to the data communication interface module 6, which is used to send demodulation control commands to the FPGA main control unit 3, receive the demodulation results output by the FPGA main control unit 3, and perform temperature compensation on the demodulation results based on the digital temperature signal to obtain the temperature-compensated demodulation results.

[0047] In some embodiments of the present invention, the 422 serial communication module 6-2 uses a communication chip of model RSM422, and the USB2.0 high-speed communication module 6-1 uses a communication chip of model FT232H.

[0048] In some embodiments of the present invention, the demodulation control signals in the external signal receiving port 3-3 mainly include USB communication read / write enable signal, 422 communication read / write enable signal, USB communication data signal, 422 communication data signal, system reset signal, CCD exposure signal, acquisition start signal, and acquisition trigger signal.

[0049] The USB 2.0 high-speed communication module 6-1 and the 422 serial communication module 6-2 in the data communication interface module 6 send the collected raw spectral data and peak finding results data to the host computer 1 through the USB or 422 interface, and at the same time output status feedback signals to the STM32 auxiliary control unit 4, including demodulation mode, temperature and channel number. The communication data signals of the USB 2.0 high-speed communication module 6-1 include data from the FPGA main control unit 3 and data from the host computer 1; The communication data signals of the 422 serial communication module 6-2 include data from the STM32 auxiliary control unit 4, data from the FPGA main control unit 3, and data from the host computer 1; The FPGA main control unit 3 data includes frame header, exposure time, transmission frequency mode temperature signal, spectrum, frame tail, peak finding threshold, and peak finding result; The host computer data includes demodulation mode, channel number, and instructions.

[0050] This embodiment uses a dedicated communication chip to build a dual-channel communication architecture, which can stably send demodulation control commands and transmit the original spectrum and peak finding results; various control signals and service data are classified and transmitted in a regular manner, and can synchronously feed back status parameters such as demodulation mode, temperature, and channel number, so as to realize reliable and orderly data interaction between the upper and lower computers and multiple modules.

[0051] To better implement the multi-channel fiber Bragg grating demodulation control system in the embodiments of the present invention, based on the multi-channel fiber Bragg grating demodulation control system, the embodiments of the present invention also provide a multi-channel fiber Bragg grating demodulation control method, such as... Figure 4 As shown, it includes: S401, Provide a light source through an external sensing module, switch the sensing channel to be detected, and acquire the reflectance spectrum signal; S402. The acquired reflectance spectrum signal is filtered and converted from analog to digital by an external signal processing module, and a digital spectrum signal is output. S403: The switching of the sensor channel to be detected is controlled by the STM32 auxiliary control unit; S404 executes system timing synchronization control through the FPGA main control unit, sends the control command for switching the sensor channel to be detected to the STM32 auxiliary control unit, and performs real-time peak finding processing on the digital spectral signal to obtain the demodulation result.

[0052] In some embodiments of the present invention Figure 5 This is a schematic flowchart of another embodiment of the multi-channel fiber Bragg grating demodulation control method provided by the present invention; as shown below. Figure 5 As shown, the control method for the multi-channel fiber Bragg grating demodulation control circuit includes the following steps: 1) System initialization: The STM32 auxiliary control unit 4 enables and resets the FPGA main control unit 3. After power-on, the STM32 auxiliary control unit 4 first configures the ADC converter 5-3, including its working mode and gain. At the same time, the STM32 auxiliary control unit 4 sets the optical channel to the default channel 1, collects the initial temperature data and sends the current channel information to the FPGA main control unit 3. Meanwhile, the internal clock divider module 3-14 of the FPGA main control unit 3 outputs a stable clock signal, and the FPGA main control unit 3 outputs a ready signal, and the system enters the ready state. 2) Receiving control commands: The FPGA main control unit 3 receives the demodulation control commands issued by the host computer 1 through the USB control module 3-111 or the 422 control module 3-112, and parses the commands to obtain the demodulation mode, target channel number, threshold change and exposure time change; 3) Channel switching and status confirmation: After receiving the target channel number, the FPGA main control unit 3 first determines whether switching of optical switches 2-3 is required. If so, it sends a target channel switching command to the STM32 auxiliary control unit 4, and then delays for 0.8ms to ensure stable switching before feeding back the current channel number to the FPGA main control unit 3. After verifying the match, the FPGA main control unit 3 receives temperature data to update the compensation parameters. If not, it directly jumps to step 4). 4) Spectral acquisition and peak finding: The FPGA main control unit 3 acquires and processes the spectrum according to the predetermined instructions; Specifically, step 4) includes the following steps; 41) The FPGA main control unit 3 sends a RESET exposure signal to the CCD demodulation module 5-1 through the AD acquisition and CCD control module 3-12, and controls the exposure of the CCD demodulation module 5-1 according to the preset exposure time; 42) After the CCD demodulation module 5-1 completes the exposure and capture of a frame of spectrum, it outputs the AD_sp signal to indicate that the acquired spectrum signal will be transmitted. At this time, the FPGA main control unit 3 controls the ADC converter 5-3 (AD9826) to acquire the spectrum according to the timing sequence, and converts the spectrum electrical signal after hardware filtering into a digital signal. Hardware filtering refers to using an RC low-pass filter network to filter out high-frequency electromagnetic interference, and then using the ADA4807 active filter amplifier circuit to achieve gain amplification and secondary mid-to-high frequency noise suppression. At the same time, the spectrum signal is sent to the USB data buffer module 3-110 or the 422 data buffer module 3-19. 43) Simultaneously with step 42), the filtering module 3-20 and the FBG peak-finding module 3-15 will also begin operating. The filtering module 3-20 refers to the program block written in the FPGA. This module is used for filtering and interpolating the spectrum. Upon receiving the spectral information, the filtering module 3-20 will first traverse the entire spectrum and perform filtering and interpolation smoothing. The filtering process employs polynomial fitting filtering. The core idea is to use a polynomial to fit the data points within each local window of the data, and then use the value of the polynomial at the center of the window as the smoothed value for that point. Specifically, a third-order 9-point Savitzky-Golay filter is used. The core idea is to approximate the original signal with a low-order polynomial within the sliding window, thereby preserving the higher-order characteristics of the signal. The process is as follows: Figure 6As shown, the processed spectrum is then transmitted to the FBG peak finding module 3-15 in real time. In the FBG peak finding module 3-15, when the signal intensity exceeds the peak finding threshold, it is determined that the spectrum has entered the peak region. The product of the light intensity and the wavelength index value is accumulated in real time, and the sum of the light intensity is added. When the signal intensity is lower than the peak finding threshold, it is determined that the spectrum has left the peak region. The centroid index value can be obtained by using the floating-point conversion IP core 3-17 and the division operation IP core 3-18. Step 43) is repeated until the entire spectrum is traversed. 5) Data transmission: After the spectrum acquisition is completed, the USB control module 3-111 or the 422 control module 3-112 reads the data from the USB data cache module 3-110 or the 422 data cache module 3-19, and transmits the spectral data and peak finding results to the host computer 1. During the transmission, the busy signal is set high, and it is pulled low after the transmission is completed. 6) Loop judgment: If the current demodulation mode is single acquisition mode, the system returns to the ready state. If the current demodulation mode is continuous acquisition mode, repeat steps 3-5 to achieve loop demodulation until the host computer 1 stops the command.

[0053] Figure 6 This describes the implementation flow of Savitzky-Golay filtering, used to smooth and reduce noise in acquired spectral data. It is based on polynomial fitting within a sliding window, solves for the filter coefficients using the least squares method, and then uses a weighted average of the coefficients to calculate the smoothed spectral intensity value, replacing the original data. This process suppresses noise while preserving higher-order spectral features. Specifically, the process of filtering and interpolating the spectrum is as follows: For a window of length 2M+1, the output of the SG filter... It can be represented as points within the window. The weighted sum is shown in Equation 1: (1) Where n is the index of the current filter output point, i.e. the center position of the sliding window, corresponding to the nth sampling point of the spectral data; i is the offset relative to the center n within the window, with a value range of [-M, +M]. The sampled value of the original spectral signal at index n+i, that is, the input light intensity value at each point within the sliding window; This is the smoothed output value at index n after SG filtering, which is the processed spectral intensity value. The filter coefficients corresponding to the i-th offset position are derived by the least squares method from the window length, polynomial order, and point position. The coefficient settings for the 9-point SG filter are shown in Equation 2: (2) The difference equation is shown in Equation 3: (3) Specifically, during the filtering process, the FPGA uses a dual-port BRAM with a depth of 9 to store the input data, forming a sliding window; Furthermore, the interpolation process employs cubic spline interpolation, obtaining the spline function based on the interpolation conditions, the continuity conditions of the first derivative, the continuity conditions of the second derivative, and the natural boundary conditions. The spline interpolation function is a third-order function by default, and its format is shown in Equation 4: (4) in, is the x-coordinate (wavelength value) of the i-th original sampling point; The x-coordinate of the interpolation point (wavelength value to be determined); For interval The cubic spline interpolation function is a third-order polynomial used to fit spectral curves within an interval. It can be used to calculate arbitrary... The light intensity value at that location; This is the constant term of the i-th spline function, which is equal to the original data points. The light intensity value at that location; Let be the coefficient of the linear term of the i-th spline function, and let the corresponding curve be on... The first derivative at that point reflects the slope of the spectral curve at that point; Let be the coefficient of the quadratic term of the i-th spline function, and let the corresponding curve be on... Half of the second derivative (the second derivative is) ), reflecting the curvature of the spectral curve; The coefficient of the cubic term of the i-th spline function corresponds to 1 / 6 of the third derivative of the curve (the third derivative is...). This reflects the rate of change of curvature; The interpolation condition requires the spline function to pass through all given data points, as shown in Equation 5: (5) The continuity condition for the first derivative requires that the first derivatives of cubic polynomials in adjacent subintervals be equal at the nodes, as shown in Equation 6: (6) The continuity condition for the second derivative requires that the second derivatives of cubic polynomials in adjacent subintervals be equal at the nodes, as shown in Equation 7: (7) According to the boundary conditions, the second derivative at the first and last data points is zero, as shown in Equations 8 and 9: (8) (9) The cubic spline function can be obtained by performing the above operations. Then, by substituting the equally spaced values ​​of the center wavelength range as independent variables, the interpolated spectrum can be obtained. In some embodiments of the present invention, the working process of the FBG peak finding module is as follows: Figure 7 As shown, the specific steps include: 1) confirming the peak-finding threshold; 2) confirming the peak-finding interval; 3) accumulating the product of light intensity and wavelength and the light intensity value within the peak-finding interval respectively; 4) taking the sum of the product of light intensity and wavelength and the light intensity value obtained in step 3) to obtain the peak wavelength. Specifically, the formula used by the FBG peak-finding module is shown in Equation 10: (10) in, The center wavelength corresponding to the peak light intensity calculated using the centroid method. This represents the light intensity value at the i-th sampling point. This represents the wavelength corresponding to the i-th sampling point.

[0054] In this embodiment, the multi-channel fiber grating demodulation control method has a rigorous timing sequence and regular steps. Relying on the multi-channel fiber grating demodulation control system's layered conditioning combined with software SG filtering, cubic spline interpolation, and centroid peak finding algorithm, it can realize multi-channel single / continuous automatic demodulation. The filtering and interpolation can preserve the higher-order spectral features and smooth the curve, while the centroid algorithm accurately solves the peak center wavelength, taking into account demodulation real-time performance, spectral smoothness, and peak identification accuracy, making it suitable for multi-channel high-speed and high-precision sensing demodulation applications.

[0055] The multi-channel fiber Bragg grating demodulation control system and method provided by the present invention have been described in detail above. Specific examples have been used to illustrate the principle and implementation of the present invention. The description of the above embodiments is only for the purpose of helping to understand the method and core idea of ​​the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation and application scope based on the idea of ​​the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A multi-channel fiber Bragg grating demodulation control system, characterized in that, include: External sensing module, external signal processing module, STM32 auxiliary control unit and FPGA main control unit; The external sensing module is used to provide a light source, switch the sensing channel to be detected, and acquire reflectance spectrum signals. The external signal processing module is optically connected to the external sensing module and is used to filter and convert the acquired reflectance spectral signal into an analog-to-digital signal, and output a digital spectral signal. The STM32 auxiliary control unit is electrically connected to the external sensing module and is used to control the switching of the sensing channel to be detected. The FPGA main control unit is electrically connected to the external signal processing module and the STM32 auxiliary control unit. It is used to perform system timing synchronization control, issue switching control commands for the sensor channels to be detected to the STM32 auxiliary control unit, and perform real-time peak finding processing on the digital spectral signal to obtain demodulation results.

2. The multi-channel fiber Bragg grating demodulation control system according to claim 1, characterized in that, The external sensing module includes an ASE light source, a circulator, an optical switch, and a multi-channel FBG sensor. The light-emitting end of the ASE light source is connected to the incident end of the circulator to output broadband continuous light and provide a stable reference light source for the sensing optical path. The circulator's output end is connected to an optical switch to unidirectionally guide the light source's optical path into the optical switch; the circulator's reflective end is connected to the optical path of an external signal processing module to unidirectionally send the light signal reflected by the FBG sensor into the external signal processing module for spectral signal processing, while suppressing optical path back-transmission interference. The input end of the optical switch is connected to the output end of the circulator, and the output end is connected to the multi-channel FBG sensor for switching multiple optical paths; each channel of the multi-channel FBG sensor corresponds to a detection point. The multi-channel FBG sensor is used to sense the physical quantity to be detected and generate a reflectance spectrum signal.

3. The multi-channel fiber Bragg grating demodulation control system according to claim 1, characterized in that, The external signal processing module includes a CCD demodulation module, a signal operational amplifier, an ADC converter, and a temperature compensation circuit; The CCD demodulation module is optically connected to the external sensing module and is used to receive the reflection spectrum signal output by the external sensing module and output the original analog spectrum signal. The signal operational amplifier is electrically connected to the CCD demodulation module and is used to filter and reduce noise and amplify the amplitude of the original analog spectral signal, and output the conditioned analog spectral signal. The ADC converter is electrically connected to the signal operational amplifier and is used to convert the conditioned analog spectral signal into a digital spectral signal. The temperature compensation circuit is electrically connected to the CCD demodulation module and is used to acquire the real-time operating temperature of the CCD demodulation module and the real-time operating temperature of the system, and output an analog temperature signal.

4. The multi-channel fiber Bragg grating demodulation control system according to claim 3, characterized in that, The STM32 auxiliary control unit is also connected to the external signal processing module and is used to configure the operating parameters of the ADC converter; the STM32 auxiliary control unit includes an STM32 controller and an STM32 built-in ADC conversion chip. The STM32's built-in ADC conversion chip is used to convert the analog temperature signal into a digital temperature signal. The STM32 controller is connected to the STM32 built-in ADC conversion chip and is used to control the STM32 built-in ADC conversion chip to perform analog-to-digital conversion and send the digital temperature signal to the FPGA main control unit.

5. The multi-channel fiber Bragg grating demodulation control system according to claim 1, characterized in that, The FPGA main control unit includes internal FPGA functional timing logic circuits, system hardware circuits, and external signal receiving ports. The external signal receiving port is used to receive the digital spectral signal output by the external signal processing module and the digital temperature signal output by the STM32 auxiliary control unit. The internal functional timing logic circuit of the FPGA is electrically connected to the external signal receiving port to generate the system working timing and to perform real-time peak finding and demodulation of the spectral signal based on the digital spectral signal. The system hardware circuit is electrically connected to the internal functional timing logic circuit of the FPGA, and is used to provide stable power supply and program configuration and operation support for the FPGA main control unit.

6. The multi-channel fiber Bragg grating demodulation control system according to claim 5, characterized in that, The internal functional timing logic circuit of the FPGA includes a top-level module, an AD acquisition and CCD control module, an optical switch driving module, an internal clock divider module, an FBG peak finding module, a filtering module, a peak value calculation module, a floating-point conversion IP core, and a division operation IP core. The top-level module is used to coordinate the collaborative work of various sub-modules under the internal functional timing logic circuit of the FPGA, and to schedule timing and data flow. The AD acquisition and CCD control module is connected to the external signal processing module and the top-level module, and is used to control AD ​​conversion and CCD demodulation and acquire digital spectral signals. The optical switch driver module is connected to the STM32 auxiliary control unit and the top-level module, and is used to drive the optical switch to complete multi-channel switching. The internal clock divider module is connected to the top-level module and is used to provide timing synchronization signals for the system. The FBG peak finding module is connected to the top-level module and is used for peak finding processing of digital spectral signals; The filtering module is connected to the FBG peak finding module and is used to perform filtering and noise reduction processing on the digital spectral signal received by the peak finding module. The peak calculation module is connected to the filtering module and is used to calculate the center wavelength corresponding to the peak value of the filtered and denoised digital spectral signal. The floating-point conversion IP core is connected to the peak calculation module and is used to convert the digital spectral signal in the peak region and its product with the corresponding center wavelength into floating-point format respectively. The division operation IP core is connected to the peak calculation module and the floating-point conversion IP core, and is used to perform a division operation on the sum of the products in floating-point format and the sum of the spectral signals, and feed the operation result back to the peak calculation module.

7. The multi-channel fiber Bragg grating demodulation control system according to claim 6, characterized in that, The internal functional timing logic circuit of the FPGA also includes a 422 data cache module, a USB data cache module, a USB control module, and a 422 control module; The USB data cache module and the 422 data cache module are both connected to the top-level module and are used to temporarily store demodulated data. The USB control module is connected to the top-level module and the USB data cache module, and is used to control the USB interface communication timing to realize data interaction with external devices. The 422 control module is connected to the top-level module and the 422 data cache module, and is used to control the communication timing of the 422 interface to realize data interaction with external devices.

8. The multi-channel fiber Bragg grating demodulation control system according to claim 5, characterized in that, The system hardware circuit includes a system power supply circuit, a reset circuit, an external clock circuit, and a debugging and configuration circuit. The reset circuit is used to provide power-on reset and manual reset signals to the FPGA main control unit to complete the system power-on initialization. The system power supply circuit is used to output multiple stable voltages to provide stable power supply for the FPGA main control unit; The debugging and configuration circuit is used to support online FPGA program download, firmware configuration, and online system debugging. The external clock circuit is used to output an external reference clock signal, providing the original clock source for each logic module inside the FPGA.

9. The multi-channel fiber Bragg grating demodulation control system according to claim 5, characterized in that, The system also includes a host computer and a data communication interface module; The data communication interface module is electrically connected to the FPGA main control unit and is used to forward the demodulation control commands from the host computer and the demodulation results output by the FPGA main control unit; the data communication interface module includes a USB 2.0 high-speed communication module and a 422 serial port communication module; The host computer is electrically connected to the data communication interface module and is used to send demodulation control commands to the FPGA main control unit, receive the demodulation results output by the FPGA main control unit, and perform temperature compensation on the demodulation results based on the digital temperature signal to obtain the temperature-compensated demodulation results.

10. A multi-channel fiber Bragg grating demodulation control method, based on the multi-channel fiber Bragg grating demodulation control system according to any one of claims 1 to 9, characterized in that, include: The external sensing module provides a light source, switches the sensing channel to be detected, and collects the reflectance spectrum signal. The external signal processing module filters and performs analog-to-digital conversion on the acquired reflectance spectrum signal to output a digital spectrum signal. The switching of the sensor channel to be detected is controlled by the STM32 auxiliary control unit. The FPGA main control unit executes system timing synchronization control, sends the control command for switching the sensor channel to be detected to the STM32 auxiliary control unit, and performs real-time peak finding processing on the digital spectral signal to obtain the demodulation result.

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