A method for correcting the offset of a temperature measurement circuit
By employing chopping technology and automatic zeroing circuitry in the temperature sensing module, R2R-DAC module, and Sar_cmp module of the CMOS temperature sensor, offset is eliminated and average value processing is performed, thus overcoming the shortcomings of CMOS temperature sensors in terms of accuracy and noise suppression and achieving higher-precision temperature measurement.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- NANJING INCODI MICROELECTRONICS TECH CO LTD
- Filing Date
- 2026-03-11
- Publication Date
- 2026-06-12
AI Technical Summary
Existing CMOS temperature sensors suffer from problems such as insufficient accuracy, high cost, high complexity, or limited applicability in offset correction methods. In particular, chopping technology introduces residual ripple and folding noise, while correlated double sampling is sensitive to the non-ideal nature of the sampling switch.
The temperature sensing module based on the bandgap principle and the R2R-DAC module use chopping technology to eliminate the module's own offset. An automatic zeroing circuit is added to the Sar_cmp module, and the offset of the temperature measuring circuit is eliminated by averaging two samples from different directions.
The measurement accuracy of the temperature measuring circuit has been improved, the temperature measurement error has been reduced, the signal-to-noise ratio has been enhanced, and more accurate temperature measurement has been achieved.
Smart Images
Figure CN122192557A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of integrated circuit design technology and relates to an offset correction method for temperature measurement circuits. Background Technology
[0002] Integrated temperature sensors are widely used in consumer electronics, industrial control, automotive electronics, and IoT devices due to their compatibility with standard CMOS processes, ease of monolithic integration with digital systems, small size, and low power consumption. Among them, temperature sensors based on the bipolar junction transistor (BJT) bandgap principle have become the mainstream architecture due to their excellent linearity and stability. This architecture utilizes the base-emitter voltage difference (ΔVBE) of the BJT at two different current densities to generate a positive temperature coefficient (PTAT) voltage, which is combined with the negative temperature coefficient (CTAT) characteristic of the BJT's base-emitter voltage (VBE) to ultimately obtain an output signal proportional to temperature.
[0003] However, inherent device mismatches, process drift, and packaging stress in CMOS processes can lead to significant offset voltage and gain errors in the sensor's front-end circuitry (such as operational amplifiers, current mirrors, and BJT pairs). These errors are directly superimposed on the weak ΔVBE signal (typically only tens of millivolts), severely limiting temperature measurement accuracy. For example, even an input offset voltage of only 1mV in an operational amplifier can introduce temperature measurement errors of up to several degrees Celsius. Furthermore, 1 / f noise also degrades the signal-to-noise ratio at low frequencies. Therefore, effectively correcting or eliminating internal offset and noise within the circuitry becomes a core challenge in the design of high-precision CMOS temperature sensors.
[0004] To address the aforementioned issues, dynamic calibration is a primary method for offset correction. Dynamic calibration techniques mainly include chopper stabilization and correlated double sampling (CDS). Chopper stabilization separates the input signal from low-frequency noise / offset in the frequency spectrum through periodic modulation, followed by demodulation and low-pass filtering to obtain a clean baseband signal, effectively suppressing 1 / f noise and offset of the operational amplifier. However, charge injection and clock feedthrough effects of the chopper switch introduce residual ripple and residual offset at the output, limiting its elimination accuracy. While correlated double sampling can eliminate offset, it introduces folding noise and is sensitive to the non-ideal nature of the sampling switch.
[0005] In summary, existing offset correction methods for CMOS temperature sensors still have shortcomings in terms of accuracy, cost, complexity, and applicability. Summary of the Invention
[0006] To address the problems existing in the above-mentioned traditional methods, this invention proposes an offset correction method for temperature measurement circuits.
[0007] To achieve the above objectives, the embodiments of the present invention adopt the following technical solutions:
[0008] On one hand, an offset correction method for a temperature measurement circuit is provided. The temperature measurement circuit includes: a temperature sensing module based on the bandgap principle, an analog-to-digital converter module, and a temperature calculation module. The temperature sensing module based on the bandgap principle is used to convert the external temperature to be measured into a measurable voltage using the negative temperature coefficient characteristic of a transistor, and provides a reference voltage V to the analog-to-digital converter module. REF The modular quantization module is used to convert the measurable voltage into a digital signal containing temperature information. The modular quantization module includes: the Sar_cmp module, the R2R-DAC module, and the control logic module. The temperature calculation module is used to calculate the current temperature value based on the digital signal containing temperature information.
[0009] Imbalance correction methods include the following steps: Chopper technology is used in the temperature sensing module and R2R-DAC module based on the bandgap principle to eliminate the module's own misalignment.
[0010] An automatic zeroing circuit is added to the Sar_cmp module to correct the offset of the Sar_cmp module itself.
[0011] By using chopper technology, key parameters in the temperature sensing module based on the bandgap principle and the R2R-DAC are sampled twice in different directions, and the values of the two samples are averaged to eliminate the misalignment of the temperature measurement circuit.
[0012] One of the above technical solutions has the following advantages and beneficial effects: The aforementioned offset correction method applied to a temperature measurement circuit includes: a temperature sensing module based on the bandgap principle, a modular quantization module, and a temperature calculation module. The offset correction method includes the following steps: using chopping technology to eliminate the offset of the bandgap-based temperature sensing module and the R2R-DAC module; adding an automatic zeroing circuit to the Sar_cmp module to correct the offset of the Sar_cmp module itself; using chopping technology to sample the key parameters in the bandgap-based temperature sensing module and the R2R-DAC twice in different directions, and averaging the two sampled values to eliminate the offset of the temperature measurement circuit and make the measured temperature value more accurate. Attached Figure Description
[0013] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0014] Figure 1 This is a flowchart illustrating an offset correction method applied to a temperature sensing circuit in one embodiment. Figure 2 This is a block diagram of the temperature measurement circuit in one embodiment; Figure 3 This is a schematic diagram of a temperature sensing module based on the bandgap principle in one embodiment; Figure 4 This is a schematic diagram of the Sar_cmp module in one embodiment; Figure 5 This is a schematic diagram of a unity-gain operational amplifier using chopping technology in one embodiment. Figure 6 This is a block diagram of the control logic module in one embodiment. Detailed Implementation
[0015] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.
[0016] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
[0017] It should be noted that, in this document, the reference to "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of the invention. The presentation of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art will understand that the embodiments described herein can be combined with other embodiments. The term "and / or" as used herein refers to any combination of one or more of the associated listed items, and all possible combinations, including such combinations.
[0018] The embodiments of the present invention will now be described in detail with reference to the accompanying drawings.
[0019] In one embodiment, such as Figure 1 As shown, an offset correction method for a temperature measurement circuit is provided. The temperature measurement circuit includes: a bandgap-based temperature sensing module, an analog-to-digital (ADC) quantization module, and a temperature calculation module. The bandgap-based temperature sensing module utilizes the negative temperature coefficient of a transistor to convert the ambient temperature to be measured into a measurable voltage and provides a reference voltage VREF to the ADC quantization module. The ADC quantization module converts the measurable voltage into a digital signal containing temperature information. The ADC quantization module includes: a Sar_cmp module, an R2R-DAC module, and a control logic module. The temperature calculation module calculates the current temperature value based on the digital signal containing temperature information. The temperature measurement circuit is as follows: Figure 2 As shown.
[0020] Imbalance correction methods may include the following processing steps 1 to 3: Step 1: Use chopping technology to eliminate the module's own offset in the temperature sensing module and R2R-DAC module based on the bandgap principle.
[0021] Specifically, the actual function of a temperature sensing module based on the bandgap principle is as a sensor to convert external temperature into a voltage. Since it's used for temperature measurement, this voltage must be a voltage that changes uniformly and linearly with temperature within the measured temperature range. This is due to the transistor's... Good positive temperature characteristics, here, use The temperature information is converted into voltage. It's important to emphasize that the internal circuitry of the temperature sensing module based on the bandgap principle employs chopper technology to eliminate system-level mismatch.
[0022] The analog-to-digital conversion module converts the analog voltage signal generated by the bandgap-based temperature sensing module into a digital signal. This module mainly includes the Sar_cmp module, the R2R-DAC module, and the control logic module. Similarly, since it's used for temperature measurement, the Sar_cmp and R2R-DAC modules need to eliminate their own offsets. Automatic zeroing is used to ensure minimal offset in the Sar_cmp module. Likewise, the R2R-DAC module uses chopping technology to eliminate its own offset. It's important to note the control logic module, which averages the data compared from the Sar_cmp module, further optimizing the offset at the system level and ensuring measurement accuracy.
[0023] The voltage regulator is an important component of the R2R-DAC module. Because the voltage regulator module uses chopping technology to eliminate its own offset, and the output of the R2R-DAC comes from the voltage of the voltage regulator output divided by resistors, the R2R-DAC uses chopping technology to eliminate its own offset.
[0024] Step 2: Add an automatic zeroing circuit to the Sar_cmp module to correct the offset of the Sar_cmp module itself.
[0025] Specifically, an auto-zeroing circuit is added to the Sar_cmp module circuit (i.e., the sar comparator circuit). When the current comparison begins, after a signal is applied to the comparator, the output current also becomes offset due to the misalignment of the input differential pair. At this time, the auto-zeroing switch is turned on, allowing the current output from the pre-amplifier circuit to charge the capacitor in the auto-zeroing circuit, generating the current offset voltage. When the next comparison begins, the offset voltage stored in the capacitor is converted into a current and added to or subtracted from the output current of the pre-amplifier. The result eliminates the effect of the comparator offset. This result is compared and output through a latch and sent to the next stage.
[0026] Step 3: Use chopping technology to sample the key parameters in the bandgap-based temperature sensing module and R2R-DAC twice in different directions, and average the two sampled values to eliminate the imbalance of the temperature measurement circuit.
[0027] Specifically, taking a temperature sensing module based on the bandgap principle as an example (refer to...) Figure 3 According to the MOSFET voltage-current formula, since PMOS transistors M3 and M4 have the same dimensions and bias voltages (both are the output voltages of the operational amplifiers), the currents in branches I3 and I4 should be equal to the currents in branches I1 and I2. However, due to mismatches in device size and threshold values during actual production, the originally intended equal currents in all four branches are now different from those in I1 and I2. Assuming the current value of I1 and I2 is I, then the current value of I3 and I4 might be I ± δ. Assuming that when A1 is low and A2 is high, the current value of I3 and I4 is I + δ, then the VPTAT voltage is V. PTAT +δV; Conversely, when A1 is high and A2 is low, the currents of I3 and I4 are I - δ, then the voltage VPTAT is V. PTAT -δV; The result obtained by adding the two results (quantitative) and then dividing by 2 (averaging) is still Vptat, which avoids the inaccuracy of temperature measurement results caused by the above mismatch.
[0028] The aforementioned offset correction method applied to a temperature measurement circuit includes: a temperature sensing module based on the bandgap principle, a modular quantization module, and a temperature calculation module. The offset correction method includes the following steps: using chopping technology to eliminate the offset of the bandgap-based temperature sensing module and the R2R-DAC module; adding an automatic zeroing circuit to the Sar_cmp module to correct the offset of the Sar_cmp module itself; using chopping technology to sample the key parameters in the bandgap-based temperature sensing module and the R2R-DAC twice in different directions, and averaging the two sampled values to eliminate the offset of the temperature measurement circuit and make the measured temperature value more accurate.
[0029] In one embodiment, such as Figure 3 As shown, the temperature sensing module based on the bandgap principle includes: a first PMOS transistor M1, a second PMOS transistor M2, a third PMOS transistor M3, a fourth PMOS transistor M4, a first transistor Q1, a second transistor Q2, an operational amplifier, resistors R1, R2, and R3, a first PMOS switch S1, a second PMOS switch S2, a third PMOS switch S3, a fourth PMOS switch S4, a fifth PMOS switch S5, a sixth PMOS switch S6, a seventh PMOS switch S7, and an eighth PMOS switch S8.
[0030] The sources of the first PMOS transistor M1, the second PMOS transistor M2, and the third PMOS transistor M3 are all connected to the source of the fourth PMOS transistor M4, and the gates of the first PMOS transistor M1, the second PMOS transistor M2, the third PMOS transistor M3, and the fourth PMOS transistor M4 are all connected to the output terminal of the operational amplifier.
[0031] The sources of the first PMOS switch S1 and the second PMOS switch S2 are both connected to the drain of the first PMOS transistor M1. The sources of the third PMOS switch S3 and the fourth PMOS switch S4 are both connected to the drain of the first PMOS transistor M1. The sources of the fifth PMOS switch S5 and the sixth PMOS switch S6 are both connected to the drain of the third PMOS transistor M3. The sources of the seventh PMOS switch S7 and the eighth PMOS switch S8 are both connected to the drain of the fourth PMOS transistor M4. The first PMOS switch S1, the third PMOS switch S3, and the sixth PMOS switch S8 are all connected to the drain of the first PMOS switch S1. The drains of PMOS switches S6 and S8 are connected to one end of resistor R1; the drains of PMOS switches S2, S4, S5, and S7 are connected to one end of resistor R3; the gates of PMOS switches S1, S3, S5, and S7 are connected to control signal terminal A1; and the gates of PMOS switches S2, S4, S6, and S8 are connected to control signal terminal A2.
[0032] The other end of resistor R1 and one end of resistor R2 are both connected to the positive input terminal of the operational amplifier. The emitter of the first transistor Q1 is connected to the negative input terminal of the operational amplifier. The other end of resistor R2 is connected to the emitter of the second transistor Q2. The base and collector of the second transistor Q2, the base and collector of the first transistor Q1, and the other end of resistor R3 are all grounded. A reference voltage V is output from one end of resistor R1. REF The voltage V across resistor R3 PTAT .
[0033] In one embodiment, resistor R1 is a variable resistor.
[0034] Specifically, in the structure of the temperature sensing module based on the bandgap principle, due to the mismatch between the current mirror tubes M3 and M4 and M1 and M2, the branch currents, which are ideally equal in magnitude, are... , , , They will no longer be equal. Correspondingly, this offset current will further cause V... PTAT and V REF The imbalance between them. To solve this problem, chopper technology was used to... , The sum of currents and , The sum of the currents is applied alternately across resistors R1 and R3 as the first set of switches (comprising four switches: first PMOS switch S1, third PMOS switch S3, fifth PMOS switch S5, and seventh PMOS switch S7) and the second set of switches (comprising second PMOS switch S2, fourth PMOS switch S4, sixth PMOS switch S6, and eighth PMOS switch S8) are turned on in turn. Thus, voltage V... PTAT and V REF Offset is introduced as the switch is turned on and off. These two voltages, which contain offset factors, are quantized and then averaged to obtain a precise quantized value.
[0035] The principle behind temperature sensing modules based on the bandgap principle for acquiring temperature information: The core structure of a temperature sensing module based on the bandgap principle is a voltage-type bandgap reference generation circuit. Its principle is as follows:
[0036] Among them, V REF For reference voltage, This represents the base and collector voltages of the second transistor Q2. and These are the resistance values of resistors R1 and R2, respectively. This represents the change in base and collector voltage of the second transistor Q2. This is achieved by setting... and By using the ratio, a reference voltage V that does not change with temperature can be obtained. REF . The calculation formula is:
[0037]
[0038] in, Indicates temperature. , , It is a constant. The voltage is proportional to temperature.
[0039] Reference voltage V REF Used as the reference voltage for the R2R-DAC module. Note that the adjustable nature of the circuit is increased because electronic R1 is an adjustable resistor.
[0040] V PTAT It is a positive temperature voltage, meaning that this voltage increases with increasing temperature. Furthermore, this relationship is nearly linear over most of the temperature measurement range. V PTAT The calculation formula is:
[0041] in, q The charge of an electron is often simplified in general calculations to... ; k represents the Boltzmann constant. T represents temperature. n express Figure 3 The ratio of the number of transistors (Q1, Q2) in the two groups; Let R3 be the resistance value.
[0042] Due to V PTAT Since it contains temperature information, the temperature sensing module based on the bandgap principle can acquire temperature.
[0043] In one embodiment, such as Figure 4 As shown, the Sar_cmp module includes: a first-stage amplifier circuit St1, a second-stage amplifier circuit, an automatic zeroing circuit, and a latching circuit.
[0044] The first input terminal of the first-stage amplifier circuit receives voltage V. PTAT The second input terminal of the first-stage amplifier circuit is connected to the output terminal of the R2R-DAC module. The two output terminals of the first-stage amplifier circuit are connected to the two input terminals of the second-stage amplifier circuit. The two output terminals of the second-stage amplifier circuit are connected to the two input terminals of the latch circuit. The output terminal of the latch circuit is connected to the input terminal of the control logic module.
[0045] The automatic zeroing circuit includes: the fifth PMOS transistor PM5, the sixth PMOS transistor PM6, the ninth PMOS switch S9, the tenth PMOS switch S10, the first capacitor C1, the second capacitor C2, and the ninth PMOS transistor PM9.
[0046] One end of the first capacitor C1 and the gate of the fifth PMOS transistor PM5 are both connected to the drain of the ninth PMOS switch S9, and the source of the ninth PMOS switch S9 is connected to the second output terminal of the second stage amplifier circuit; one end of the second capacitor C2 and the gate of the sixth PMOS transistor PM6 are both connected to the drain of the tenth PMOS switch S10, and the source of the tenth PMOS switch S10 is connected to the first output terminal of the second stage amplifier circuit; the other ends of the first capacitor C1 and the second capacitor C2 are grounded.
[0047] The sources of the fifth PMOS transistor PM5 and the sixth PMOS transistor PM6 are both connected to the drain of the ninth PMOS transistor PM9. The source of the ninth PMOS transistor PM9 is connected to VDD, and the gate of the ninth PMOS transistor PM9 is connected to VDD. biasThe voltage terminals are connected, and the drains of the fifth PMOS transistor PM5 and the sixth PMOS transistor PM6 are connected to the first and second output terminals of the first-stage amplifier circuit, respectively; the gates of the ninth PMOS switch S9 and the tenth PMOS switch S10 are both connected to the Auto_en enable voltage. Wherein, V bias The voltage is the bias voltage in the current circuit module.
[0048] Specifically, the Sar_cmp module, also known as the Sar comparator, is one of the core modules of the temperature measurement circuit. Its function is to compare the temperature voltage acquired by the temperature sensing module based on the bandgap principle with the feedback signal converted by the R2R-DAC module. The comparison result is sent to the control logic module for quantization, and the quantized result is sent to the temperature calculation module for calculation. The Sar_cmp module adopts a common fast comparator structure, consisting of a two-stage amplifier and a latch. Automatic zeroing is performed at the input stage amplifier to correct for the inherent offset of the Sar_cmp module.
[0049] The Sar_cmp module is used to quantize voltage V. PTAT It consists of a first-stage amplifier circuit St1, a second-stage amplifier circuit St2, an auto-zero circuit, and a latch circuit. Because this module itself has offset, primarily concentrated in the differential pair of the first-stage amplifier circuit St1, an auto-zero circuit is added to eliminate the offset caused by the differential pair. When the ninth PMOS switch S9 and the tenth PMOS switch S10 are turned on, the offset differential current is injected into capacitors C1 and C2, forming a differential voltage at the terminals of the fifth PMOS transistor PM5 and the sixth PMOS transistor PM6. This voltage further generates a compensation current through the differential pair of the fifth PMOS transistor PM5 and the sixth PMOS transistor PM6, which is sent to the first-stage amplifier circuit St1 to compensate for the input offset caused by the differential pair of the first-stage amplifier circuit St1. Through the correction of the auto-zero circuit, the offset caused by the first-stage amplifier circuit St1 is reduced, thus making the quantization more accurate.
[0050] Figure 4 As shown, the Sar_cmp module includes: a first-stage amplifier circuit St1, a second-stage amplifier circuit St2, an automatic zeroing circuit, and a latching circuit.
[0051] The first-stage amplifier circuit St1 includes: a first PMOS transistor PM1, a second PMOS transistor PM2, an eleventh PMOS transistor PM11, a first NMOS transistor NM1, a second NMOS transistor NM2, a fourth resistor R4, and a fifth resistor R5.
[0052] The second-stage amplifier circuit St2 includes: a third PMOS transistor PM3, a fourth PMOS transistor PM4, a tenth PMOS transistor PM10, a third NMOS transistor NM3, a fourth NMOS transistor NM4, a sixth resistor R6, and a seventh resistor R7.
[0053] The automatic zeroing circuit includes: the fifth PMOS transistor PM5, the sixth PMOS transistor PM6, the ninth PMOS switch S9, the tenth PMOS switch S10, the first capacitor C1, the second capacitor C2, and the ninth PMOS transistor PM9.
[0054] The latching circuit includes: the seventh PMOS transistor PM7, the eighth PMOS transistor PM8, the twelfth PMOS transistor PM12, the thirteenth PMOS transistor PM13, the fifth NMOS transistor NM5, the sixth NMOS transistor NM6, the seventh NMOS transistor NM7, the eighth NMOS transistor NM8, the ninth NMOS transistor NM9, and the RS latch.
[0055] The internal component connections of the Sar_cmp module are as follows: the sources of the eleventh PMOS transistor PM11, the tenth PMOS transistor PM10, and the ninth PMOS transistor PM9 are all connected to the source of the twelfth PMOS transistor PM12; the gates of the eleventh PMOS transistor PM11, the tenth PMOS transistor PM10, and the ninth PMOS transistor PM9 are connected to V. bias With the voltage terminals connected, the sources of both the first PMOS transistor PM1 and the second PMOS transistor PM2 are connected to the drain of the eleventh PMOS transistor PM11. The gate of the first PMOS transistor PM1 receives voltage V. PTAT The gate of the second PMOS transistor PM2 receives the output voltage V from the R2R-DAC module. DAC The drain of the first PMOS transistor PM1, the gate of the third PMOS transistor PM3, the drain of the fifth PMOS transistor PM5, and the drain of the first NMOS transistor NM1 are all connected to one end of resistor R4. The source of the first NMOS transistor NM1 and the source of the second NMOS transistor NM2 are connected to ground. The gates of the first NMOS transistor NM1 and the second NMOS transistor NM2 are all connected to the other end of the fourth resistor R4. The other end of the fourth resistor R4 is connected to one end of the fifth resistor R5. The drain of the second PMOS transistor PM2, the gate of the fourth PMOS transistor PM4, the drain of the sixth PMOS transistor PM6, and the drain of the second NMOS transistor NM2 are all connected to the other end of the fifth resistor R5.
[0056] The sources of the third PMOS transistor PM3 and the fourth PMOS transistor PM4 are both connected to the drain of the tenth PMOS transistor PM10. The drain of the third PMOS transistor PM3, the drain of the fifth NMOS transistor NM5, the source of the tenth PMOS switch S10, and the drain of the third NMOS transistor NM3 are connected to one end of the sixth resistor R6. The source of the third NMOS transistor NM3 and the source of the fourth NMOS transistor NM4 are connected and then grounded. The gate of the third NMOS transistor NM3 and the gate of the fourth NMOS transistor NM4 are connected and then connected to the other end of the sixth resistor R6. The other end of the sixth resistor R6 is connected to one end of the seventh resistor R7. The drain of the fourth PMOS transistor PM4, the drain of the fourth NMOS transistor NM4, the source of the ninth PMOS switch S9, and the source of the thirteenth PMOS transistor PM13 are all connected to the other end of the seventh resistor R7.
[0057] One end of the first capacitor C1 and the gate of the fifth PMOS transistor PM5 are both connected to the drain of the ninth PMOS switch S9. One end of the second capacitor C2 and the gate of the sixth PMOS transistor PM6 are both connected to the drain of the tenth PMOS switch S10. The other ends of the first capacitor C1 and the second capacitor C2 are grounded.
[0058] The sources of the fifth PMOS transistor PM5 and the sixth PMOS transistor PM6 are both connected to the drain of the ninth PMOS transistor PM9, and the gates of the ninth PMOS switch S9 and the tenth PMOS switch S10 are both connected to the Auto_en enable voltage.
[0059] The gates of the thirteenth PMOS transistor PM13, the twelfth PMOS transistor PM12, the fifth NMOS transistor NM5, the sixth NMOS transistor NM6, and the ninth NMOS transistor NM9 all receive the Latch_clk clock signal. The drain of the thirteenth PMOS transistor PM13 is connected to the gate of the seventh PMOS transistor PM7. The sources of the seventh PMOS transistor PM7 and the eighth PMOS transistor PM8 are both connected to the drain of the twelfth PMOS transistor PM12. The drain of the seventh PMOS transistor PM7 and the gate of the sixth NMOS transistor... The drain of transistor NM6, the drain of the seventh NMOS transistor NM7, and the gate of the eighth NMOS transistor NM8 are all connected to the first input terminal of the RS latch. The drain of the eighth PMOS transistor PM8, the gate of the seventh PMOS transistor PM7, and the drain of the eighth NMOS transistor NM8 are all connected to the second input terminal of the RS latch. The output terminal of the RS latch is connected to the input terminal of the control logic module. The sources of the sixth NMOS transistor NM6, the seventh NMOS transistor NM7, the eighth NMOS transistor NM8, and the ninth NMOS transistor NM9 are all grounded.
[0060] In one embodiment, the R2R-DAC module includes a buffer consisting of a resistor string and a unity-gain operational amplifier using chopping technology.
[0061] Specifically, the R2R-DAC module converts the digital signal quantized by the control logic module into an analog signal, which is then sent to the Sar_cmp module for comparison with the temperature voltage output by the bandgap-based temperature sensing module. The R2R-DAC module consists of a series of resistors with values of R and 2R, along with a voltage regulator. Different voltages are obtained by turning on different combinations of switches on the input digital signal.
[0062] The R2R-DAC consists of resistor series and a buffer composed of unity-gain operational amplifiers (op_amps) using chopping technology. The resistor series is offset-free, while the buffer is offset. The offset of the buffer is mainly concentrated at the op_amp input. Similar to the bandgap-based temperature sensing module, chopping technology is used to eliminate the offset at the op_amp input.
[0063] In one embodiment, the unity-gain operational amplifier using chopping technology is a classic unity-gain operational amplifier with an additional set of switching transistors, and clock signals CLk1, CLk2, CLk1b, and CLk2b are used to control the switching on and off; wherein CLk1 and CLk2 are turned on in two consecutive cycles respectively; CLk1 and CLk1b are switching signals with opposite phases, and CLk2 and CLk2b are switching signals with opposite phases.
[0064] Specifically, the schematic diagram of a unity-gain operational amplifier using chopping technology is as follows: Figure 5 As shown, the offset voltage vos of the op-amp is concentrated on the input differential pair transistors M5 and M6. To eliminate the influence of this offset voltage on the subsequent circuit, we added a set of switches and used clock signals CLk1, CLk2, CLk1b, and CLk2b to control the switching on and off. CLk1 and CLk2 are turned on in two consecutive cycles. CLk1 and CLk1b, and CLk2 and CLk2b are switching signals with opposite phases. Assuming vos is negative, when switches S11 and S13 are on and switches S12 and S14 are off, the output voltage out decreases; when switches S11 and S13 are off and switches S12 and S14 are on, the output voltage out increases. Similarly, averaging the two out values reduces the impact of the offset.
[0065] Figure 5 Vbn1 is the bias voltage of the N-type current source of the operational amplifier. This voltage is a fixed DC voltage. Vbn2 and Vbp2 are the bias voltages for the corresponding transistors to conduct, which are also fixed DC voltages.
[0066] Figure 5 In This is a temperature-independent reference voltage from a temperature sensing module based on the bandgap principle. As the output of a unity-gain amplifier, it also exhibits temperature-independent characteristics. <9:0> is used to adjust the voltage division ratio of the resistor series. Let's assume this ratio is... Then the output voltage of the R2R-DAC Having and Same temperature characteristics. Specifically: =
[0067] =
[0068] In one embodiment, the control logic module includes a first D flip-flop, an adder, and a second D flip-flop.
[0069] The input of the first D flip-flop receives the output signal of the Sar_cmp module, and the CK terminal of the first D flip-flop receives the average clock signal Acg_clk. The output of the first D flip-flop is connected to the second input of the adder. The first input of the adder receives the output signal of the Sar_cmp module, and the output of the adder is connected to the input of the second D flip-flop. The CK terminal of the second D flip-flop receives the average clock signal Acg_clk, and the output of the second D flip-flop is connected to the input of the temperature solving module and the input of the R2R-DAC module.
[0070] Specifically, the control logic module quantizes the result obtained from the comparison by the Sar-cmp module into a 10-bit digital signal. It then averages the two 10-bit digital signals obtained through quantization. The control logic includes Sarlogic, adders, and D flip-flops. Figure 4 The result of the latch circuit is fed into Sarlogic, which quantizes the comparison result and outputs a 10-bit digital signal.
[0071] like Figure 6 As shown, a two-step summation and averaging operation is implemented using a flip-flop and an adder. This operation eliminates the influence of inherent offsets in each stage of the circuit, thus providing a more accurate reflection of the temperature data.
[0072] In one embodiment, the temperature calculation module calculates the current temperature based on the relationship between output voltage and temperature:
[0073] Where T is the current temperature. This is the signal output by the modular quantization module.
[0074] Specifically, the temperature calculation module is responsible for calculating the digital signal converted by the analog quantization module, solving for the temperature value, and outputting it to complete the temperature measurement process.
[0075] The temperature sensing module based on the bandgap principle serves as the temperature acquisition module. Its output voltage is a linear function of temperature T, i.e., V = 1.94T + 523. To obtain the current temperature T, simply subtract 523 from the signal output by the analog quantization module and divide by 1.94. The temperature calculation module mainly consists of a series of adders and triggers. By setting fixed values, it achieves the functions of subtracting 523 and dividing by 1.94.
[0076] The temperature measurement circuit applicable to this method comprises three main modules: a bandgap-based temperature sensing module, an analog quantization module, and a temperature calculation module. The bandgap-based temperature sensing module utilizes the positive temperature coefficient of current to generate a voltage that increases with temperature, thus converting the ambient temperature into a measurable voltage. Since the measurable voltage output by the bandgap-based temperature sensing module is an analog signal, which is susceptible to interference from uncontrollable factors such as process conditions, temperature, and voltage, affecting measurement accuracy, an analog quantization module is used to convert the measurable voltage into a digital signal. Using digital signals not only avoids the weaknesses of analog signals but also facilitates arithmetic and logical operations. The analog quantization module includes a Sar_cmp module, a control logic module, and an R2R-DAC module, which respectively implement comparison, conversion, and feedback functions. The measurable voltage is quantized into a 10-bit binary digital signal after entering the analog quantization module. This digital signal, containing temperature information, is then sent to the temperature calculation module to calculate the current temperature value.
[0077] It should be understood that, although the above Figure 1 The steps are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise explicitly stated in this document, there is no strict order in which these steps are executed; they can be performed in other orders. Furthermore, the above... Figure 1 At least some of the steps may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least some of the sub-steps or stages of other steps.
[0078] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0079] The above embodiments are merely illustrative of several implementation methods of this application, and their descriptions are relatively specific and detailed. However, they should not be construed as limiting the scope of protection of this application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and all such modifications and improvements fall within the scope of protection of this application.
Claims
1. An offset correction method applied to a temperature sensing circuit, characterized in that, The temperature measurement circuit includes: a temperature sensing module based on the bandgap principle, a modular quantization module, and a temperature calculation module; the temperature sensing module based on the bandgap principle is used to convert the required ambient temperature into a measurable voltage using the negative temperature coefficient characteristic of a transistor, and provides a reference voltage V to the modular quantization module. REF The modular quantization module is used to convert the measurable voltage into a digital signal containing temperature information; the modular quantization module includes: a Sar_cmp module, an R2R-DAC module, and a control logic module; the temperature calculation module is used to calculate the current temperature value based on the digital signal containing temperature information. The imbalance correction method includes the following steps: In the temperature sensing module based on the bandgap principle and the R2R-DAC module, chopping technology is used to eliminate the module's own misalignment. An automatic zeroing circuit is added to the Sar_cmp module to correct the misalignment of the Sar_cmp module itself. By using chopping technology, the key parameters in the temperature sensing module based on the bandgap principle and the R2R-DAC are sampled twice in different directions, and the values of the two samples are averaged to eliminate the imbalance of the temperature measuring circuit.
2. The offset correction method for temperature measuring circuits according to claim 1, characterized in that, The temperature sensing module based on the bandgap principle includes: a first PMOS transistor M1, a second PMOS transistor M2, a third PMOS transistor M3, a fourth PMOS transistor M4, a first transistor Q1, a second transistor Q2, an operational amplifier, resistors R1, R2, and R3, a first PMOS switch S1, a second PMOS switch S2, a third PMOS switch S3, a fourth PMOS switch S4, a fifth PMOS switch S5, a sixth PMOS switch S6, a seventh PMOS switch S7, and an eighth PMOS switch S8; The sources of the first PMOS transistor M1, the second PMOS transistor M2, and the third PMOS transistor M3 are all connected to the source of the fourth PMOS transistor M4, and the gates of the first PMOS transistor M1, the second PMOS transistor M2, the third PMOS transistor M3, and the fourth PMOS transistor M4 are all connected to the output terminal of the operational amplifier. The sources of the first PMOS switch S1 and the second PMOS switch S2 are both connected to the drain of the first PMOS transistor M1. The sources of the third PMOS switch S3 and the fourth PMOS switch S4 are both connected to the drain of the first PMOS transistor M1. The sources of the fifth PMOS switch S5 and the sixth PMOS switch S6 are both connected to the drain of the third PMOS transistor M3. The sources of the seventh PMOS switch S7 and the eighth PMOS switch S8 are both connected to the drain of the fourth PMOS transistor M4. The first PMOS switch S1, the third PMOS switch S3, and the sixth PMOS switch S8 are all connected to the drain of the first PMOS switch S1. The drains of PMOS switches S6 and S8 are connected to one end of resistor R1; the drains of PMOS switches S2, S4, S5, and S7 are connected to one end of resistor R3; the gates of PMOS switches S1, S3, S5, and S7 are connected to control signal terminal A1; and the gates of PMOS switches S2, S4, S6, and S8 are connected to control signal terminal A2. The other end of resistor R1 and one end of resistor R2 are both connected to the positive input terminal of the operational amplifier. The emitter of the first transistor Q1 is connected to the negative input terminal of the operational amplifier. The other end of resistor R2 is connected to the emitter of the second transistor Q2. The base and collector of the second transistor Q2, the base and collector of the first transistor Q1, and the other end of resistor R3 are all grounded. The reference voltage V is output from one end of resistor R1. REF The voltage V across resistor R3 PTAT .
3. The offset correction method for temperature measuring circuits according to claim 2, characterized in that, Resistor R1 is a variable resistor.
4. The offset correction method for temperature measuring circuits according to claim 1, characterized in that, The Sar_cmp module includes: a first-stage amplifier circuit, a second-stage amplifier circuit, an automatic zeroing circuit, and a latch circuit; The first input terminal of the first stage amplifier circuit receives voltage V PTAT The second input terminal of the first-stage amplifier circuit is connected to the output terminal of the R2R-DAC module. The two output terminals of the first-stage amplifier circuit are connected to the two input terminals of the second-stage amplifier circuit. The two output terminals of the second-stage amplifier circuit are connected to the two input terminals of the latch circuit. The output terminal of the latch circuit is connected to the input terminal of the control logic module. The automatic zeroing circuit includes: a fifth PMOS transistor PM5, a sixth PMOS transistor PM6, a ninth PMOS switch S9, a tenth PMOS switch S10, a first capacitor C1, a second capacitor C2, and a ninth PMOS transistor PM9. One end of the first capacitor C1 and the gate of the fifth PMOS transistor PM5 are both connected to the drain of the ninth PMOS switch S9, and the source of the ninth PMOS switch S9 is connected to the second output terminal of the second stage amplifier circuit; one end of the second capacitor C2 and the gate of the sixth PMOS transistor PM6 are both connected to the drain of the tenth PMOS switch S10, and the source of the tenth PMOS switch S10 is connected to the first output terminal of the second stage amplifier circuit; the other ends of the first capacitor C1 and the second capacitor C2 are grounded. The sources of the fifth PMOS transistor PM5 and the sixth PMOS transistor PM6 are both connected to the drain of the ninth PMOS transistor PM9. The drain of the ninth PMOS transistor PM9 is connected to VDD, and the gate of the ninth PMOS transistor PM9 is connected to VDD. bias The voltage terminals are connected, and the drains of the fifth PMOS transistor PM5 and the sixth PMOS transistor PM6 are connected to the first and second output terminals of the first stage amplifier circuit, respectively; the gates of the ninth PMOS switch S9 and the tenth PMOS switch S10 are both connected to the Auto_en enable voltage.
5. The offset correction method for temperature measuring circuits according to claim 1, characterized in that, The R2R-DAC module includes a buffer consisting of a resistor string and a unity-gain operational amplifier using chopping technology.
6. The offset correction method for temperature measuring circuits according to claim 4, characterized in that, A unity-gain operational amplifier using chopper technology adds a set of switching transistors to a classic unity-gain operational amplifier, and uses clock signals CLk1, CLk2, CLk1b, and CLk2b to control the switching on and off; where CLk1 and CLk2 are turned on in two consecutive cycles. CLk1 and CLk1b are switching signals with opposite phases, and CLk2 and CLk2b are switching signals with opposite phases.
7. The offset correction method for temperature measuring circuits according to claim 1, characterized in that, The control logic module includes a first D flip-flop, an adder, and a second D flip-flop; The input of the first D flip-flop receives the output signal of the Sar_cmp module, and the CK terminal of the first D flip-flop receives the average clock signal Acg_clk. The output of the first D flip-flop is connected to the second input of the adder. The first input of the adder receives the output signal of the Sar_cmp module, and the output of the adder is connected to the input of the second D flip-flop. The CK terminal of the second D flip-flop receives the average clock signal Acg_clk, and the output of the second D flip-flop is connected to the input of the temperature solving module and the input of the R2R-DAC module.
8. The offset correction method for temperature measuring circuits according to claim 1, characterized in that, The temperature calculation module calculates the current temperature based on the relationship between output voltage and temperature: Where T is the current temperature. This is the signal output by the modular quantization module.