Dynamic on-resistance and threshold voltage test circuit and method for GaN devices

Abstract

The application belongs to the technical field of power semiconductor testing, and relates to a dynamic on-resistance and threshold voltage test circuit and method for a GaN device. The application cooperatively integrates a main test circuit, a driving circuit and a clamping circuit to realize dynamic on-resistance tests in four working conditions of first-quadrant hard turn-on, first-quadrant soft turn-on, third-quadrant hard turn-off and third-quadrant soft turn-off on the same set of hardware, and to reuse the first-quadrant hard turn-on process to complete high-precision collection of threshold voltage, thereby breaking through the limitation of single working condition and single parameter measurement in a traditional scheme, and significantly improving measurement resolution, response speed and test consistency. The driving circuit can accurately control the amplitude and the rate of change of voltage of the gate, and the clamping circuit realizes high-speed sampling of the drain-source voltage in the on state, limits the voltage peak value and suppresses high-frequency transient noise in the off state. The overall scheme meets the requirements of device research and development and industrial test, and improves measurement repeatability and stability.

Description

Technical Field

[0001] This invention belongs to the field of power semiconductor testing technology, and relates to a dynamic on-resistance and threshold voltage testing circuit and method for GaN devices. Background Technology

[0002] Gallium nitride (GaN), as a third-generation wide-bandgap semiconductor material, possesses characteristics such as high electron mobility, high saturation drift velocity, wide bandgap, and high critical breakdown field strength. Therefore, it is widely used in high-frequency switching power supplies, electric vehicle inverters, and communication power supplies. Compared with traditional silicon (Si) and silicon carbide (SiC) devices, GaN power devices can achieve higher switching frequencies, lower on-resistance, and smaller chip sizes, thereby improving power density and system efficiency.

[0003] Under high-frequency switching conditions, the dynamic on-resistance (Dynamic RDS(on)) of GaN devices may increase, a phenomenon known as current collapse. This is primarily caused by localized depletion of the two-dimensional electron gas due to the device surface, heterojunction epitaxial layer, or bulk traps, resulting in an on-resistance higher than the static value during the initial turn-on phase. This increase in dynamic resistance significantly enhances conduction losses and impacts system thermal design and overall performance.

[0004] Existing methods for testing dynamic on-resistance typically rely on oscilloscopes to directly measure the drain voltage and calculate the on-resistance based on the current flowing through the device. However, the voltage drop of GaN devices in the on-state is usually only tens of millivolts, making it difficult for oscilloscopes to meet the requirements in terms of quantization accuracy, bandwidth, and sampling speed, thus failing to accurately capture dynamic on-resistance changes on a nanosecond timescale. Furthermore, existing threshold voltage (Vth) tests are significantly affected by the test environment and pre-voltage conditions, resulting in poor measurement repeatability and failing to accurately reflect the electrical characteristics of the device under actual operating conditions.

[0005] Existing testing solutions cannot simultaneously achieve multi-quadrant, multi-condition switching, high-speed sampling of dynamic on-resistance, and high repeatability measurement of threshold voltage on a single hardware device, making it difficult to meet the performance evaluation requirements of GaN devices under real-world operating conditions. Therefore, there is an urgent need for a method and circuit that can achieve high-precision, fast-response dynamic on-resistance and threshold voltage testing for GaN devices under multiple operating conditions to meet the needs of device development, reliability evaluation, and industrial testing. Summary of the Invention

[0006] The present invention aims to overcome the shortcomings of existing technologies that cannot simultaneously achieve adaptability to multiple operating conditions, dynamic measurement accuracy, and threshold voltage test repeatability, and provides an integrated, high-precision, and fast-response GaN device multi-operating condition dynamic on-resistance and threshold voltage test circuit and method.

[0007] The technical solution of this invention is:

[0008] A dynamic on-resistance and threshold voltage test circuit for GaN devices, including a main test circuit, a drive circuit, and a clamping circuit.

[0009] The main test circuit includes a DC voltage source, a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a first switching transistor, a second switching transistor, a third switching transistor, a first current-limiting resistor, a first freewheeling inductor, a first GaN device, and a second GaN device. The positive terminal of the DC voltage source is connected to the positive plates of the first and second capacitors, the drain of the first switching transistor, and the drain of the first GaN device. The negative terminal of the DC voltage source is grounded, and the negative plate of the first capacitor is grounded. The negative plate of the second capacitor is connected to the positive plate of the third capacitor and the drain of the second switching transistor. The positive plate of the third capacitor is grounded. The first and second switching transistors are connected to the DC voltage source and the second switching transistor. The first GaN device's gate is connected to one end of a first current-limiting resistor, the other end of which is connected to one end of a first freewheeling inductor. The other end of the freewheeling inductor is connected to the source of the first GaN device and the drain of the second GaN device. The source of the second GaN device is connected to the drain of the third switch and the positive plate of the fourth capacitor. The source of the third switch and the negative plate of the fourth capacitor are grounded. The driving circuit is connected to the gate of the second GaN device. The clamping circuit is connected between the drain of the second GaN device and ground. The control signal terminals of the first, second, and third switches, as well as the gate of the first GaN device, are connected to external control signals.

[0010] In this scheme, the clamping circuit has two implementation methods, which are defined as the first clamping circuit and the second clamping circuit respectively;

[0011] The first clamping circuit includes a detection circuit and a filtering circuit; the detection circuit consists of a first diode, a second diode, a third diode, a fourth diode, a third resistor, and a fourth resistor; the cathode of the first diode is connected to the drain of the second GAN device, and the anode is connected to one end of the third resistor, one end of the fourth resistor, the cathode of the second diode, and the cathode of the third diode, defining the connection point as the test node; the other end of the third resistor is connected to the power supply VCC; the other end of the fourth resistor and the anode of the second diode are grounded; the anode of the third diode is connected to the anode of the fourth diode; the anode of the fourth diode is grounded.

[0012] The filter circuit consists of a third resistor, a fourth resistor, a fifth capacitor, a sixth capacitor, and a first operational amplifier; the test node is connected to the positive input terminal of the first operational amplifier and one end of the fifth resistor, the other end of the fifth resistor is connected to the positive plate of the fifth capacitor, and the negative plate of the fifth capacitor is grounded; the negative input terminal of the first operational amplifier is connected to the output terminal of the first operational amplifier; the output terminal of the first operational amplifier is connected to one end of the sixth resistor, the other end of the sixth resistor is connected to the positive plate of the sixth capacitor, and the negative plate of the sixth capacitor is grounded;

[0013] The second clamping circuit includes a fifth diode, a sixth diode, a seventh diode, resistors seven through sixteenth, a seventh capacitor, an eighth capacitor, and second, third, and fourth operational amplifiers. The cathode of the fifth diode is connected to the drain of the second GaN device, and the anode is connected to the input node. The input node is connected to one end of the seventh resistor, and the other end of the seventh resistor is connected to the positive input terminal of the second operational amplifier and one end of the eighth resistor. The other end of the eighth resistor is grounded. The positive plate of the seventh capacitor is connected to the input ground, and the negative plate is grounded. The cathode of the sixth diode is connected to the input node. The seventh diode is connected in series with the ninth resistor, and the anode of the seventh diode is connected to the input node. The other end of the ninth resistor is connected to the anode of the sixth diode. The first diode is connected to the power supply VCC through the tenth resistor; the anode of the sixth diode is connected to one end of the eleventh resistor, the other end of the eleventh resistor is connected to the positive input terminal of the third op-amp and one end of the twelfth resistor, and the other end of the twelfth resistor is grounded; the output terminal of the second op-amp is connected to the inverting input terminal of the second op-amp and connected to the positive input terminal of the fourth op-amp through the thirteenth resistor; the output terminal of the third op-amp is connected to the inverting input terminal of the third op-amp and connected to the inverting input terminal of the fourth op-amp through the sixteenth resistor; the output terminal of the fourth op-amp is connected to the inverting input terminal of the fourth op-amp through the fifteenth resistor; the output terminal of the fourth op-amp is connected to one end of the fourteenth resistor, the other end of the fourteenth resistor is connected to the measurement node, and the measurement node is grounded through the eighth capacitor;

[0014] The driving circuit includes a pulse shaping amplifier, a first gate driver, and a second gate driver. The first input terminal of the pulse shaping amplifier is connected to the eighteenth resistor and one end of the ninth capacitor through the seventeenth resistor. The other end of the ninth capacitor is connected to the output terminal of the fifth operational amplifier. The other end of the eighteenth resistor is connected to the positive input terminal of the fifth operational amplifier and the positive plate of the tenth capacitor. The negative plate of the tenth capacitor is grounded. The second input terminal of the pulse shaping amplifier is connected to the negative input terminal of the fifth operational amplifier through the nineteenth resistor. The negative input terminal of the fifth operational amplifier is connected to the output terminal of the fifth operational amplifier through the twentieth resistor. The output terminal of the fifth operational amplifier is connected to the output terminal of the pulse shaping amplifier through the twenty-first resistor. The output terminal of the pulse shaping amplifier is connected to the gate of the second GaN device through a first switch. The positive input terminal of the first gate driver is connected to a first logic control signal, and the positive output terminal is connected to the gate of the second GaN device through the twenty-second resistor. The positive input terminal of the second gate driver is connected to a second logic control signal, and the negative output terminal is connected to the gate of the second GaN device through the twenty-third resistor.

[0015] A method for testing the dynamic on-resistance and threshold voltage of GaN devices includes the following steps:

[0016] S1. Before the test begins, turn off the first switch, turn on the second switch, and turn on the third switch to keep the second GaN device in the off state and maintain a preset voltage for a preset time.

[0017] S2, Test 1: The second GaN device is turned on, and during the first pulse, current flows through the first freewheeling inductor, and the current rises; after the first pulse ends, the second GaN device is turned off, the first GaN device is turned on and forms a freewheeling path to keep the current flowing; then the first GaN device is turned off, and the second GaN device is turned on again. During the second pulse, the clamping circuit measures the node voltage and the drain-source current of the second GaN device, and calculates the on-resistance.

[0018] S3, Test 2: After the first GAN device is turned on for a set time, it is turned off. The reverse current of the first freewheeling inductor discharges the parasitic capacitance of the second GAN device. When the drain-source voltage of the second GAN device drops to zero, the second GAN device is turned on. The clamping circuit measures the node voltage and the drain-source current of the second GaN device, and the on-resistance is calculated.

[0019] S4, Test 3: The first GaN device is turned off after a set time. During the first pulse, the reverse current of the first freewheeling inductor discharges the parasitic capacitance of the second GaN device. When the drain-source voltage of the second GaN device drops to a negative value, a continuous reverse current flows through the channel of the second GaN device, turning on the second GaN device. Then, the second GaN device is turned off before the reverse current of the second GaN device drops to 0. After that, the first GaN device is turned on. During the second pulse, the clamping circuit measures the node voltage and the drain-source current of the second GaN device, and the on-resistance is calculated.

[0020] S5, Test 4: Based on Test 3, adjust the duration of the first pulse so that the current of the first freewheeling inductor is close to 0 when the second GaN device is turned off. Collect the node voltage of the clamping circuit and the drain-source current of the second GaN device, and calculate the on-resistance.

[0021] Furthermore, in step S2, after the second GaN device turns on again and reaches a steady state, the third switch is turned off, allowing current to flow through the second GaN device and charge it through the fourth capacitor, causing the gate-source voltage of the second GaN device to decrease and the current to decrease to a set threshold. The gate-source voltage of the second GaN device is acquired and the threshold voltage is recorded. After the measurement is completed, the second GaN device is turned off, while the first GaN device is turned on, causing the current to gradually decrease to zero. Subsequently, the third GaN device is turned on to discharge the fourth capacitor, causing the source voltage of the second GaN device to return to ground potential, restoring the system to its initial state.

[0022] The beneficial effects of this invention are as follows: Addressing the unique challenges of dynamic characteristic testing for GaN devices, this invention integrates multi-condition current control, multi-functional gate drive, and high-voltage isolation clamping sampling at the architectural level. The drive circuit precisely controls the switching timing, slew rate, and gate potential, providing stable conditions for dynamic sampling. The clamping circuit automatically switches between high-voltage turn-off and low-voltage turn-on, protecting the circuit and improving the signal-to-noise ratio. The test circuit provides a unified current path and pre-stress conditions, enabling the sequential completion of four operating conditions and threshold voltage measurements on the same device. These three components are mutually supportive and indispensable, forming an integrated testing solution that is multi-condition, multi-parameter, high-precision, and highly reusable, possessing outstanding substantive features and significant advancements. Attached Figure Description

[0023] Figure 1 This is a schematic diagram of the test circuit described in this invention.

[0024] Figure 2 This is a schematic diagram of the driving circuit described in this invention.

[0025] Figure 3 This is a schematic diagram of the pulse shaping amplifier described in this invention.

[0026] Figure 4 This is a schematic diagram of the first clamping circuit of the present invention.

[0027] Figure 5 This is a schematic diagram of the second clamping circuit of the present invention.

[0028] Figure 6 This is the waveform of the first quadrant hard-turn-on on-resistance test according to the present invention.

[0029] Figure 7 This is the waveform of the soft-turn-on resistance test in the first quadrant of the present invention.

[0030] Figure 8 This is the waveform of the hard-shutdown on-resistance test in the third quadrant as described in this invention.

[0031] Figure 9 This is the waveform for the soft-shutdown on-resistance test in the third quadrant as described in this invention.

[0032] Figure 10 This is a schematic diagram of the power module health status monitoring in Embodiment 5 of the present invention. Detailed Implementation

[0033] The technical solution of the present invention will now be described in detail with reference to the accompanying drawings and embodiments:

[0034] Example 1

[0035] Using a test circuit, a gate driver and a first clamping circuit are employed to perform dynamic on-resistance measurement under multiple operating conditions, thereby achieving high-precision measurement of M2 under different on- and off operating conditions.

[0036] Test circuit composition and connection:

[0037] Test circuit such as Figure 1 As shown, the circuit includes a DC voltage source Vin, capacitors C1, C2, C3, and C4, switching transistors Q1, Q2, and Q3, a current-limiting resistor R1, a freewheeling inductor L1, and high-voltage GaN devices M1 and M2. M1 and M2 form a half-bridge arm, M2 is the device under test, and Q3 and C4 are used for threshold voltage measurement.

[0038] The positive terminal of Vin is connected to the positive terminal of C1, and also to one end of C2 and the drains of Q1 and M1; the other end of C2 is connected to one end of C3, and the other end of C3 is grounded; the midpoint between C2 and C3 is connected to the drain of Q2; the sources of Q1 and Q2 are connected to R1, and the other end of R1 is connected to L1; the other end of L1 is connected to the source of M1 and the drain of M2; the source of M2 is connected to the drain of Q3 and one end of C4, and the source of Q3 and the other end of C4 are grounded. The gate drive circuit is connected to the gate of M2, and the clamping circuit is connected in parallel between the drain of M2 and ground.

[0039] This configuration enables stable control of the current path under various operating conditions, while providing a safe and reliable working environment for subsequent measurements.

[0040] Gate driver description:

[0041] The drive circuit uses two gate drivers, such as Figure 2 As shown. When S1 is off, the pulse shaping amplifier does not control the gate.

[0042] The gate driver provides a tri-state output, which can make the gate float, pull up, or pull down. The logic input signals VON,Drv and Voff,Drv control the output state. The gate is connected to M2 through RG,ON and RG,off, thereby precisely controlling the turn-on and turn-off times and achieving reliable control for different operating conditions.

[0043] First clamping circuit description:

[0044] The first clamping circuit is as follows: Figure 4 As shown, it consists of a detection circuit and a filter circuit.

[0045] The detection circuit is used to measure the voltage of M2 when it is on and to block the high voltage at the drain when it is off, thus ensuring the safety of the measurement node.

[0046] The filtering circuit eliminates high-frequency ringing and spikes, enabling the detection voltage vm to stabilize rapidly within tens of nanoseconds, thus achieving high-precision sampling of the dynamic on-resistance.

[0047] When M2 is off, D1 blocks the high voltage, and the detected voltage vm is clamped to:

[0048] ,

[0049] When M2 is turned on, the on-state voltage is measured using a detection circuit. D1 is forward biased, and vm is equal to the on-state voltage drop of M2 plus the forward voltage drop of D1.

[0050] To ensure that D1 has a positive bias and accurately measures the dynamic resistance of M2, R7 and R8 need to be set correctly so that the following equation is always satisfied:

[0051] ,

[0052] During the turn-on process of M2, a falling edge dVds / dT will be introduced. The blocking diode D1 is still in reverse bias. The switching effect of dVds / dT will force current to flow, thereby releasing the Vm voltage. The discharge current is determined by the vm junction capacitance and the drain-source voltage change rate of M2.

[0053] The junction capacitance Cvm of the sensing node vm is formed by the junction capacitance of D2 and the junction capacitances of D3 and D4 connected in series.

[0054] The discharge current flows through D2, and the voltage of D3 and D4 connected in series is greater than the voltage of D2. Therefore, vm is clamped to the negative on-state voltage of D2, -Vd2_on.

[0055] The dVds / dT period ends when the voltage Vds,on of M2 meets the following condition:

[0056] ,

[0057] Then D1 is reverse biased, and D2 changes from forward conduction to reverse blocking state.

[0058] The node voltage Vm charges from -Vd2_on to:

[0059]

[0060] The charging time depends on the charging current and junction capacitance at the sensing node vm. Furthermore, D2 should be a Schottky diode with good reverse recovery characteristics to reduce switching time and improve transient response rate.

[0061] To achieve a fast detection speed, the junction capacitance of Vm should be as low as possible. Therefore, choosing a Schottky diode for D2 also offers the advantage of low junction capacitance. The series connection of D3 and D4 helps to further reduce the junction capacitance of Vm. The charging current from VCC accelerates the transition period and also helps to improve the detection speed. Therefore, the values ​​of R7 and VCC should be set appropriately to provide sufficient charging current.

[0062] During the M2 shutdown process, a rising edge dVds / dT will be introduced. This will generate a charging current from D1 to vm, which may cause a large voltage spike at the vm node, thus affecting the measurement resolution.

[0063] Zener diodes D3 and D4 can clamp voltage spikes to a controlled value. The conduction of a Zener diode can introduce reverse recovery; therefore, connecting two Zener diodes in series improves detection speed.

[0064] The first clamping circuit effectively limits the voltage at the measurement node during the high-voltage turn-off phase. During the M2 conduction phase, it can quickly absorb and filter dv / dt spikes, enabling the measurement node vm voltage to stabilize rapidly. The dynamic R_DS(on) can be accurately captured within tens of nanoseconds. Simultaneously, in conjunction with the RC filter circuit, it suppresses switching transient noise, further improving measurement accuracy and ensuring the stability of the conduction voltage.

[0065] Dynamic on-resistance test under four operating conditions:

[0066] The first quadrant hard-opening operation is as follows: Figure 6 As shown:

[0067] Before testing, control switch Q2 is turned on, Q1 is turned off, and Q3 is turned on.

[0068] Before time t0, there is a prestressing preparation period during which the magnitude of the prestress on M2 is 1 / 2 Vin.

[0069] At time t0, M2 is turned on, causing inductor L1 to charge and the current to increase.

[0070] At time t1, when the inductor current reaches the set peak current, the first pulse ends, M2 turns off, M1 turns on and conducts in reverse, and the current continues to flow through the upper tube M1.

[0071] At time t2, M2 turns on again under the given current conditions. During this stage, the on-voltage and current waveforms of the device are observed with an oscilloscope to complete the dynamic resistance test.

[0072] At time t3, the second gate pulse ends, M2 turns off, and the inductor current gradually decreases through M1 until it returns to zero, thus completing the test.

[0073] Setting Vin determines the stress magnitude, setting t1-t2 determines the duration of the off-state stress, setting t0-t1 determines the peak value of the conduction current, and setting t2-t3 determines the observation time for the dynamic resistance test.

[0074] During the experiment, the two different pulse widths of the dual-pulse test can be finely adjusted according to the testing requirements. To avoid overheating, the pulse duration is typically on the order of microseconds. Since the inductor current experiences a significant drop during the freewheeling process t1-t2, the pulse duration of M2 can be slightly extended to approximately twice the duration of the second pulse to ensure a relatively large current value remains during the t2-t3 period.

[0075] The first quadrant soft-opening operation is as follows: Figure 7 As shown:

[0076] Before testing, control switch Q2 is turned on, Q1 is turned off, and Q3 is turned on.

[0077] First, turn on the upper transistor M1 for a short period of time and then turn it off to provide a small reverse current to the inductor.

[0078] During the time interval t0-t1, M1 receives a narrow pulse signal of about 100 ns. During the conduction period, the voltage across the inductor is about -1 / 2 Vin, and the inductor current IL rises in the reverse direction.

[0079] During the dead time from t1 to t2, the inductor current causes the parasitic capacitance of M2 to discharge, reducing the voltage VDS across M2 through resonance. When VDS drops to zero, M2 enters the reverse conduction state.

[0080] At time t2, M2 receives the gate pulse and achieves soft turn-on. During this stage, the on-voltage and current waveforms of the device are observed with an oscilloscope to complete the dynamic resistance test.

[0081] After this, the inductor charges forward, and the inductor voltage rises to 1 / 2 Vin until M2 is turned off at time t3. After a dead time, M1 is turned on again at time t4 and turned off at time t5, and this cycle repeats, causing M2 to be soft-turned on again at time t6.

[0082] Third quadrant hard shutdown condition such as Figure 8 As shown:

[0083] First, before M2 is activated, the upper tube is controlled to conduct for a period of time. Compared with the soft activation mode in the first quadrant, the conduction time in the working mode of the third quadrant is longer.

[0084] Between time t0 and t1, a gate pulse of several microseconds is applied to the upper transistor M1. During this time, the inductor current IL begins to rise in the reverse direction until it reaches a given peak value.

[0085] During the dead time t1-t2, the inductor current discharges the output capacitor of M2, and the voltage VDS across M2 begins to decrease resonantly. When VDS drops to 0, M2 begins to conduct in reverse. Due to the continuous reverse current flowing through the channel of M2, M2 is already in the channel-conducting state before the gate signal arrives. After M2 is turned on, the voltage across the inductor is 1 / 2 Vin, and its current begins to decrease in reverse (gradually approaching zero from a negative value) until M2 is turned off at time t3.

[0086] Since the first pulse time of M1 is approximately twice the first pulse time of M2, a significant reverse current still flows through device M2 until it is turned off, keeping M2 in a conducting state. At time t4, M1 turns on again. Due to the turn-on of the upper transistor, the lower transistor is forcibly turned off. The inductor current undergoes a commutation process, re-establishing a loop through M1, and only then is M2 turned off. This achieves the goal of making M2 operate in the hard-turn-off mode in the third quadrant. During this stage, the on-voltage and current waveforms of the devices are observed using an oscilloscope to complete the dynamic resistance test.

[0087] The third quadrant soft shutdown condition, such as Figure 9 As shown:

[0088] In the third quadrant hard-turn-off test method, by changing the duration of the first pulse of M1 (t0-t1) to be equal to the duration of the gate pulse of M2 (t2-t3), M2 can be controlled to operate in the third quadrant soft-turn-off mode. The inductor current increasing in the reverse direction between t0-t1 is exactly equal to the inverse direction decreasing in the reverse direction between t2-t3; therefore, at t3, the instant the gate signal of M2 disappears, the inductor current drops to zero, and the channel current of the device under test M2 is cut off, thus turning it off. During this stage, the on-voltage and current waveforms of the device are observed with an oscilloscope to complete the dynamic resistance test.

[0089] With this combination, the test circuit can achieve accurate measurement of on-resistance under multiple operating conditions, while ensuring waveform stability, repeatable measurement, and reducing the impact of switching transient noise.

[0090] Example 2:

[0091] Dynamic on-resistance test using pulse-shaping amplifier control:

[0092] Based on Example 1, this example uses a pulse shaping amplifier instead of a gate driver to control the on and off of M2, thereby achieving dynamic on-resistance measurement under different gate drive voltages and charging speeds.

[0093] The test circuit and the first clamping circuit remain unchanged.

[0094] In the driving circuit, Von,Drv inputs are set low and Voff,Drv inputs are set high, so that the gate of M2 is floating. At this time, S1 is turned on to enable the pulse shaping amplifier to control M2.

[0095] Pulse shaping amplifier structure and working principle:

[0096] Pulse shaping amplifier circuit, such as Figure 3 As shown, its output voltage VAMP,GS is controlled by two inputs VAMP,IN and VAMP,OS, both of which are generated by a digital-to-analog converter.

[0097] VAMP,IN first passes through a low-pass filter to smooth the waveform, removing high-frequency noise and spikes; then it passes through a non-inverting amplifier for amplitude amplification and offset adjustment to ensure that the output voltage covers the effective gate range of M2.

[0098] The output terminal VAMP,GS is connected to the gate of M2 via switch S1 to control its on and off states.

[0099] The DC transfer function of the pulse shaping amplifier is:

[0100] ,

[0101] By adjusting VAMP,IN and VAMP,OS, the gate voltage amplitude and slew rate can be precisely controlled. This allows for accurate measurement of dynamic on-resistance under different switching conditions.

[0102] The test method is consistent with the dynamic on-resistance test under four operating conditions in Example 1. During the on or off phase of M2, the pulse shaping amplifier can adjust the gate voltage amplitude and slew rate to observe their influence on the dynamic on-resistance and ensure the repeatability and accuracy of the measurement.

[0103] Example 3:

[0104] Dynamic on-resistance test using the second clamping circuit:

[0105] Based on Example 1, this example replaces the first clamping circuit with the second clamping circuit, while keeping the other test circuits and gate drivers unchanged. The test method remains the dynamic on-resistance test under four operating conditions.

[0106] Second clamping circuit structure and principle:

[0107] The second clamping circuit is as follows: Figure 5As shown, the drain of M2 is connected to the input node vx through a high-voltage diode D5. D6 reverse clamps to prevent high voltage from the drain of M2 from flowing back to VCC. D7 and R13 form an additional protection branch to limit transient current spikes and protect the op-amp input. Because the op-amp's common-mode input range is limited, R11 and R12 proportionally reduce the vx voltage to a safe value. C9 filters out high-frequency spikes at the vx node and suppresses switching transient noise.

[0108] Operational amplifier A3 is a voltage follower structure used for signal sampling and impedance matching, and outputs a low-impedance signal to A5.

[0109] Operational amplifier A4 is a voltage follower structure used for signal sampling and impedance matching. R15~R17 divide VCC and input it to A4 to provide a stable reference level to operational amplifier A5.

[0110] Operational amplifier A5 is a non-inverting proportional amplifier circuit. Resistors R19 and R20 are used to adjust the amplifier gain, and R18 and C10 form a low-pass filter to smooth the vm signal and filter out high-frequency oscillations. Ultimately, this achieves proportional amplification and offset of the signal, resulting in a stable and accurate measured voltage vm.

[0111] Working principle of the second clamping circuit:

[0112] When M2 is turned on, D5 is forward-biased, and the voltage vx is fed into the op-amp through a voltage divider and buffer, ultimately forming a stable and accurate measurement voltage vm.

[0113] When M2 is turned off, D5 cuts off the drain high voltage, and the Vx voltage is clamped through R11, R12, and R15. D6 prevents reverse current, and C9 absorbs transient voltage spikes to protect the op-amp.

[0114] Compared to the first clamping circuit, the second clamping circuit, through a combination of multi-stage buffering, proportional voltage division, and low-pass filtering, can provide higher accuracy and more stable VM measurement under high-frequency switching conditions, and reduce spike interference, thereby improving the repeatability and reliability of dynamic on-resistance testing.

[0115] Example 4:

[0116] Threshold voltage Vth measurement:

[0117] Based on Example 1, this example utilizes a test circuit, a first clamping circuit, and a gate driver to measure the threshold voltage Vth of M2. The test method is based on the first quadrant hard-turn-on dynamic on-resistance test procedure, but the measurement targets are the drain-source current and gate-source voltage of M2.

[0118] In the first quadrant hard-turn-on condition, when M2 turns on again at time t2, Q3 is turned off. Current IL flows through M2 and charges capacitor C4, causing the source voltage of M2 to rise, thereby reducing the VGS voltage of M2. At the same time, the IDS current gradually decreases until it reaches the threshold current Ith. The VGS measured at this time is defined as Vth.

[0119] When VGS drops to Vth, M2 is turned off. Then M1 is turned on, allowing the inductor current IL to gradually decrease to zero through M1. Finally, Q3 is turned on, discharging capacitor C4 and pulling the source voltage down to GND, returning the system to its initial state and preparing it for the next measurement.

[0120] With this configuration, the gate-source voltage change of M2 during the decrease of conduction current can be stably captured, thereby obtaining a threshold voltage measurement result with high repeatability and reliable accuracy. In conjunction with the aforementioned four-condition dynamic on-resistance test, the device performance evaluation under multiple conditions can be realized.

[0121] Example 5:

[0122] Power module health status monitoring:

[0123] like Figure 10 As shown, this embodiment applies the test circuit of the present invention to the health status monitoring of power modules in large power electronic systems, such as GaN power modules in electric vehicle inverters, electric aircraft drive systems, or wind power inverters, to realize online dynamic on-resistance and threshold voltage monitoring of devices during operation.

[0124] The test circuit module is connected to each power module. The data acquisition and monitoring system controls the test circuit to monitor the dynamic on-resistance and threshold voltage of the GaN device in real time. The measurement results are compared with the initial calibration values ​​of the device to analyze the increase of R_DS(on) or the deviation of Vth. When the deviation exceeds the set threshold, the controller can issue an early warning or automatically switch to a backup device to ensure the safe operation of the power module.

[0125] In actual system operation, dynamic on-resistance measurement can be performed online without stopping the system or removing devices. The test method has high accuracy and repeatability, and the collected dynamic on-resistance data can be used to optimize gate drive strategies and system power management, thereby improving overall system efficiency and reliability.

[0126] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A circuit for testing the dynamic on-resistance and threshold voltage of GaN devices, characterized in that, Includes main test circuit, drive circuit and clamping circuit; The main test circuit includes a DC voltage source, a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a first switching transistor, a second switching transistor, a third switching transistor, a first current-limiting resistor, a first freewheeling inductor, a first GaN device, and a second GaN device. The positive terminal of the DC voltage source is connected to the positive plates of the first and second capacitors, the drain of the first switching transistor, and the drain of the first GaN device. The negative terminal of the DC voltage source is grounded, and the negative plate of the first capacitor is grounded. The negative plate of the second capacitor is connected to the positive plate of the third capacitor and the drain of the second switching transistor. The positive plate of the third capacitor is grounded. The first and second switching transistors are connected to the DC voltage source and the second switching transistor. The first GaN device's gate is connected to one end of a first current-limiting resistor, the other end of which is connected to one end of a first freewheeling inductor. The other end of the freewheeling inductor is connected to the source of the first GaN device and the drain of the second GaN device. The source of the second GaN device is connected to the drain of the third switch and the positive plate of the fourth capacitor. The source of the third switch and the negative plate of the fourth capacitor are grounded. The driving circuit is connected to the gate of the second GaN device. The clamping circuit is connected between the drain of the second GaN device and ground. The control signal terminals of the first, second, and third switches, as well as the gate of the first GaN device, are connected to external control signals. The clamping circuit includes a detection circuit and a filtering circuit; the detection circuit consists of a first diode, a second diode, a third diode, a fourth diode, a second resistor, and a third resistor; the cathode of the first diode is connected to the drain of the second GAN device, and the anode is connected to one end of the second resistor, one end of the third resistor, the cathode of the second diode, and the cathode of the third diode, and the connection point is defined as the measurement node; the other end of the second resistor is connected to the power supply VCC; the other end of the third resistor and the anode of the second diode are grounded; the anode of the third diode is connected to the anode of the fourth diode; the anode of the fourth diode is grounded. The filter circuit consists of a fourth resistor, a fifth resistor, a fifth capacitor, a sixth capacitor, and a first operational amplifier. The measurement node is connected to the positive input terminal of the first operational amplifier and one end of the fourth resistor. The other end of the fourth resistor is connected to the positive plate of the fifth capacitor, and the negative plate of the fifth capacitor is grounded. The negative input terminal of the first operational amplifier is connected to the output terminal of the first operational amplifier. The output terminal of the first operational amplifier is connected to one end of the fifth resistor. The other end of the fifth resistor is connected to the positive plate of the sixth capacitor, and the negative plate of the sixth capacitor is grounded. The driving circuit includes a pulse shaping amplifier, a first gate driver, and a second gate driver; the first input terminal of the pulse shaping amplifier is connected to the seventeenth resistor and one end of the ninth capacitor through the sixteenth resistor, the other end of the ninth capacitor is connected to the output terminal of the fifth operational amplifier, the other end of the seventeenth resistor is connected to the positive input terminal of the fifth operational amplifier and the positive plate of the tenth capacitor, and the negative plate of the tenth capacitor is grounded. The second input terminal of the pulse shaping amplifier is connected to the negative input terminal of the fifth op-amp through the eighteenth resistor. The negative input terminal of the fifth op-amp is connected to the output terminal of the fifth op-amp through the nineteenth resistor. The output terminal of the fifth op-amp is connected to the output terminal of the pulse shaping amplifier through the twentieth resistor. The output terminal of the pulse shaping amplifier is connected to the gate of the second GaN device through the first switch. The positive input terminal of the first gate driver is connected to the first logic control signal, and the positive output terminal is connected to the gate of the second GaN device through the twenty-first resistor; the positive input terminal of the second gate driver is connected to the second logic control signal, and the negative output terminal is connected to the gate of the second GaN device through the twenty-second resistor.

2. A method for testing the dynamic on-resistance and threshold voltage of GaN devices, based on the test circuit described in claim 1, characterized in that, Includes the following steps: S1. Before the test begins, turn off the first switch, turn on the second switch, and turn on the third switch to keep the second GaN device in the off state and maintain a preset voltage for a preset time. S2, Test 1: The second GaN device is turned on, and during the first pulse, current flows through the first freewheeling inductor, and the current rises; after the first pulse ends, the second GaN device is turned off, the first GaN device is turned on and forms a freewheeling path to keep the current flowing; then the first GaN device is turned off, and the second GaN device is turned on again. During the second pulse, the clamping circuit measures the node voltage and the drain-source current of the second GaN device, and calculates the on-resistance. S3, Test 2: After the first GAN device is turned on for a set time, it is turned off. The reverse current of the first freewheeling inductor discharges the parasitic capacitance of the second GAN device. When the drain-source voltage of the second GAN device drops to zero, the second GAN device is turned on. The clamping circuit measures the node voltage and the drain-source current of the second GaN device, and the on-resistance is calculated. S4, Test 3: The first GaN device is turned off after a set time. During the first pulse, the reverse current of the first freewheeling inductor discharges the parasitic capacitance of the second GaN device. When the drain-source voltage of the second GaN device drops to a negative value, a continuous reverse current flows through the channel of the second GaN device, turning on the second GaN device. Then, the second GaN device is turned off before the reverse current of the second GaN device drops to 0. After that, the first GaN device is turned on. During the second pulse, the clamping circuit measures the node voltage and the drain-source current of the second GaN device, and the on-resistance is calculated. S5, Test 4: Based on Test 3, adjust the duration of the first pulse so that the current of the first freewheeling inductor is close to 0 when the second GaN device is turned off. Collect the node voltage of the clamping circuit and the drain-source current of the second GaN device, and calculate the on-resistance.

3. A circuit for testing the dynamic on-resistance and threshold voltage of GaN devices, characterized in that, Includes main test circuit, drive circuit and clamping circuit; The main test circuit includes a DC voltage source, a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a first switching transistor, a second switching transistor, a third switching transistor, a first current-limiting resistor, a first freewheeling inductor, a first GaN device, and a second GaN device. The positive terminal of the DC voltage source is connected to the positive plates of the first and second capacitors, the drain of the first switching transistor, and the drain of the first GaN device. The negative terminal of the DC voltage source is grounded, and the negative plate of the first capacitor is grounded. The negative plate of the second capacitor is connected to the positive plate of the third capacitor and the drain of the second switching transistor. The positive plate of the third capacitor is grounded. The first and second switching transistors are connected to the DC voltage source and the second switching transistor. The first GaN device's gate is connected to one end of a first current-limiting resistor, the other end of which is connected to one end of a first freewheeling inductor. The other end of the freewheeling inductor is connected to the source of the first GaN device and the drain of the second GaN device. The source of the second GaN device is connected to the drain of the third switch and the positive plate of the fourth capacitor. The source of the third switch and the negative plate of the fourth capacitor are grounded. The driving circuit is connected to the gate of the second GaN device. The clamping circuit is connected between the drain of the second GaN device and ground. The control signal terminals of the first, second, and third switches, as well as the gate of the first GaN device, are connected to external control signals. The clamping circuit includes a fifth diode, a sixth diode, a seventh diode, sixth to fifteenth resistors, a seventh capacitor, an eighth capacitor, and second, third, and fourth operational amplifiers; The fifth diode's cathode is connected to the drain of the second GaN device, and its anode is connected to one end of the sixth resistor. The other end of the sixth resistor is connected to the positive input of the second operational amplifier and one end of the seventh resistor, with the other end of the seventh resistor grounded. The positive plate of the seventh capacitor is connected to the anode of the fifth diode, and its negative plate is grounded. The sixth diode's cathode is connected to the anode of the fifth diode. The seventh diode is connected in series with the eighth resistor, and the anode of the seventh diode is connected to the anode of the fifth diode. The other end of the eighth resistor is connected to the anode of the sixth diode. The anode of the sixth diode is connected to the power supply VCC through the ninth resistor. The anode of the sixth diode is connected to one end of the tenth resistor, and the other end of the tenth resistor is connected to the positive input of the third operational amplifier and one end of the eleventh resistor, with the other end of the eleventh resistor grounded. The output of the second operational amplifier is connected to the negative input of the second operational amplifier and then to the positive input of the fourth operational amplifier through the twelfth resistor. The output of the third operational amplifier is connected to the negative input of the third operational amplifier and then to the negative input of the fourth operational amplifier through the fifteenth resistor. The output of the fourth operational amplifier is connected to the negative input of the fourth operational amplifier through the fourteenth resistor. The output of the fourth operational amplifier is connected to one end of the thirteenth resistor, and the other end of the thirteenth resistor is connected to the positive plate of the eighth capacitor. The connection point is defined as the measurement node, and the negative plate of the eighth capacitor is grounded. The driving circuit includes a pulse shaping amplifier, a first gate driver, and a second gate driver; the first input terminal of the pulse shaping amplifier is connected to the seventeenth resistor and one end of the ninth capacitor through the sixteenth resistor, the other end of the ninth capacitor is connected to the output terminal of the fifth operational amplifier, the other end of the seventeenth resistor is connected to the positive input terminal of the fifth operational amplifier and the positive plate of the tenth capacitor, and the negative plate of the tenth capacitor is grounded. The second input terminal of the pulse shaping amplifier is connected to the negative input terminal of the fifth op-amp through the eighteenth resistor. The negative input terminal of the fifth op-amp is connected to the output terminal of the fifth op-amp through the nineteenth resistor. The output terminal of the fifth op-amp is connected to the output terminal of the pulse shaping amplifier through the twentieth resistor. The output terminal of the pulse shaping amplifier is connected to the gate of the second GaN device through the first switch. The positive input terminal of the first gate driver is connected to the first logic control signal, and the positive output terminal is connected to the gate of the second GaN device through the twenty-first resistor; the positive input terminal of the second gate driver is connected to the second logic control signal, and the negative output terminal is connected to the gate of the second GaN device through the twenty-second resistor.

4. A method for testing the dynamic on-resistance and threshold voltage of GaN devices, based on the test circuit described in claim 3, characterized in that, Includes the following steps: S1. Before the test begins, turn off the first switch, turn on the second switch, and turn on the third switch to keep the second GaN device in the off state and maintain a preset voltage for a preset time. S2, Test 1: The second GaN device is turned on, and during the first pulse, current flows through the first freewheeling inductor, and the current rises; after the first pulse ends, the second GaN device is turned off, the first GaN device is turned on and forms a freewheeling path to keep the current flowing; then the first GaN device is turned off, and the second GaN device is turned on again. During the second pulse, the clamping circuit measures the node voltage and the drain-source current of the second GaN device, and calculates the on-resistance. S3, Test 2: After the first GAN device is turned on for a set time, it is turned off. The reverse current of the first freewheeling inductor discharges the parasitic capacitance of the second GAN device. When the drain-source voltage of the second GAN device drops to zero, the second GAN device is turned on. The clamping circuit measures the node voltage and the drain-source current of the second GaN device, and the on-resistance is calculated. S4, Test 3: The first GaN device is turned off after a set time. During the first pulse, the reverse current of the first freewheeling inductor discharges the parasitic capacitance of the second GaN device. When the drain-source voltage of the second GaN device drops to a negative value, a continuous reverse current flows through the channel of the second GaN device, turning on the second GaN device. Then, the second GaN device is turned off before the reverse current of the second GaN device drops to 0. After that, the first GaN device is turned on. During the second pulse, the clamping circuit measures the node voltage and the drain-source current of the second GaN device, and the on-resistance is calculated. S5, Test 4: Based on Test 3, adjust the duration of the first pulse so that the current of the first freewheeling inductor is close to 0 when the second GaN device is turned off. Collect the node voltage of the clamping circuit and the drain-source current of the second GaN device, and calculate the on-resistance.

5. The method for testing the dynamic on-resistance and threshold voltage of GaN devices according to claim 4, characterized in that, In step S2, after the second GaN device is turned on again and reaches a steady state, the third switch is turned off, allowing current to flow through the second GaN device and charge it through the fourth capacitor, causing the gate-source voltage of the second GaN device to decrease and the current to decrease to a set threshold. The gate-source voltage of the second GaN device is acquired and the threshold voltage is recorded. After the measurement is completed, the second GaN device is turned off, while the first GaN device is turned on to gradually reduce the current to zero. Then, the third GaN device is turned on to discharge the fourth capacitor, so that the source voltage of the second GaN device returns to ground potential and the system is restored to its initial state.

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