A test circuit for a well logging master control chip
By designing a test circuit for the adjustment, acquisition, and data upload modules of the well logging main control chip, the problems of cumbersome and inefficient testing of traditional well logging main control chips are solved, realizing automated testing and improving efficiency and accuracy.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- CHINA NAT PETROLEUM CORP
- Filing Date
- 2024-12-10
- Publication Date
- 2026-06-12
AI Technical Summary
Traditional logging main control chip testing methods are cumbersome, inefficient, and prone to human error. Existing automated testing circuits still require manual operation, resulting in low efficiency.
Design a test circuit that includes an adjustment module, an acquisition module, a data upload module, and a logic control module. By preprocessing the original analog signal, converting it into a digital signal, and uploading it to the host computer, the test circuit can be automated to test the well logging main control chip.
It improves signal acquisition efficiency and accuracy, provides intuitive test results, simplifies the testing process, and increases testing efficiency while reducing costs.
Smart Images
Figure CN122193886A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of oil well logging technology, and in particular to a test circuit for a well logging master control chip. Background Technology
[0002] As an indispensable core component of logging instruments, the logging master control chip's main function is to manage the transmission of internal data and issue commands. The stable operation of the logging master control chip is crucial to ensuring the normal operation of the logging instrument.
[0003] Traditional well logging control chip testing methods typically rely on manual control and external instrument connections, resulting in a cumbersome, inefficient, and complex data processing process. Furthermore, the manual operation inherently introduces the risk of human error. Therefore, to improve the efficiency and accuracy of well logging control chip testing, there is an urgent need to develop a stable and efficient testing circuit that automates and systematizes the testing process, thereby increasing efficiency and reducing costs.
[0004] Chinese patent application CN114624571B discloses a converter chip testing circuit and system. The converter chip testing circuit includes a logic control unit, a digital-to-analog converter (DAC), and a signal conditioning circuit. The DAC is connected to both the logic control unit and the signal conditioning circuit. The logic control unit receives digital waveform test data from a host computer and sends the digital waveform test data to the DAC. The DAC converts the digital waveform test data into analog waveform test data and sends the analog waveform test data to the signal conditioning circuit. The signal conditioning circuit improves the signal-to-noise ratio of the analog waveform test data and then sends the analog waveform test data to the target chip under test (DUT). The DUT then converts the analog waveform test data into digital waveform test feedback data and sends it to the host computer. The host computer uses the digital waveform test data and the digital waveform test feedback data to obtain the test results of the DUT. This method still requires manual operation of the host computer to send digital waveform test data, resulting in low testing efficiency. Summary of the Invention
[0005] To address the aforementioned problems, the inventors developed this invention, which, through specific implementation methods, provides a test circuit for a well logging master control chip.
[0006] This invention provides a test circuit for a well logging main control chip, comprising:
[0007] The adjustment module is used to preprocess the raw analog signal output by the main control chip of the well logging test and output an optimized signal;
[0008] A data acquisition module is connected to the adjustment module, and the data acquisition module is used to convert the optimized signal into a digital signal;
[0009] A data upload module is connected to the acquisition module, and the data upload module is used to upload the digital signal to the host computer;
[0010] The logic control module is connected to the main control chip, acquisition module and data upload module of the well logging test, respectively. The logic control module is used to generate logic signals to perform logic control on the main control chip, acquisition module and data upload module of the well logging test.
[0011] The beneficial effects of the above-described technical solutions provided in the embodiments of the present invention include at least the following:
[0012] The adjustment module preprocesses the original analog signal output by the logging control chip under test, outputting an optimized signal that more clearly and accurately reflects the performance characteristics of the chip. The acquisition module converts the optimized signal into a digital signal, improving the acquisition efficiency and accuracy. The data upload module uploads the digital signal to the host computer. The logic control module generates logic signals to control the logging control chip, acquisition module, and data upload module. The test results are displayed intuitively on the host computer, improving the efficiency and accuracy of logging control chip testing. This automates and systematizes the testing process, increasing testing efficiency and reducing testing costs.
[0013] Other features and advantages of the invention will be set forth in the following description, or may be learned by practicing the invention. The objects and other advantages of the invention may be realized and obtained by means of the structures particularly pointed out in the written description, claims, and drawings.
[0014] The technical solution of the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description
[0015] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used in conjunction with embodiments of the invention to explain the invention and do not constitute a limitation thereof. In the drawings:
[0016] Figure 1 This is a schematic block diagram of the test circuit according to an embodiment of the present invention;
[0017] Figure 2 This is a circuit diagram of the logic control module in the test circuit of an embodiment of the present invention;
[0018] Figure 3 This is a circuit diagram of the adjustment module in the test circuit of an embodiment of the present invention;
[0019] Figure 4 This is a circuit diagram of the acquisition module in the test circuit of an embodiment of the present invention;
[0020] Figure 5 This is a circuit diagram of the data upload module in the test circuit of an embodiment of the present invention. Detailed Implementation
[0021] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
[0022] To address the problems existing in the prior art, embodiments of the present invention provide a test circuit for a well logging master control chip.
[0023] This invention provides a test circuit for a well logging main control chip, the principle of which is as follows: Figure 1 As shown, including,
[0024] The adjustment module is used to preprocess the raw analog signal output by the main control chip of the well logging test and output an optimized signal;
[0025] A data acquisition module is connected to the adjustment module, and the data acquisition module is used to convert the optimized signal into a digital signal;
[0026] A data upload module is connected to the acquisition module, and the data upload module is used to upload the digital signal to the host computer;
[0027] The logic control module is connected to the main control chip, acquisition module and data upload module of the well logging test, respectively. The logic control module is used to generate logic signals to perform logic control on the main control chip, acquisition module and data upload module of the well logging test.
[0028] Specifically, the adjustment module preprocesses the raw analog signal output by the logging control chip under test to produce an optimized signal. This preprocessing includes at least one of gain adjustment, filtering, and amplification, enabling the signal to more clearly and accurately reflect the performance characteristics of the chip under test. The acquisition module converts the optimized signal into a digital signal, improving acquisition efficiency and accuracy. The data upload module then uploads the digital signal to the host computer. A logic control module generates logic signals, including logic control signals from the adjustment module, acquisition module, and data upload module. These signals are used to logically control the logging control chip, acquisition module, and data upload module, respectively. The test results are displayed intuitively on the host computer, allowing the tester to analyze and judge the data. This achieves efficient testing of the logging control chip and simplifies the testing process.
[0029] In the test circuit described above in this embodiment, such as Figure 2 As shown, the logic control module includes an FPGA device U1 and a crystal oscillator U2; the output terminal of the crystal oscillator U2 is connected to one end of a resistor R1, and the other end of the resistor R1 is connected to the clock input terminal of the FPGA device U1; the power supply terminal of the crystal oscillator U2 is connected to a power supply and one end of a capacitor C1, and the other end of the capacitor C1 is grounded and connected to the ground terminal of the crystal oscillator U2; the logic output terminals A1, A2, A3, and A4 of the FPGA device U1 are respectively connected to the corresponding logging master control chip under test; the logic output terminal CNV, logic input terminal SDO, and logic output terminal SCK of the FPGA device U1 are connected to the acquisition module; and the eighth to twenty-seventh logic output terminals of the FPGA device U1 are connected to the data upload module.
[0030] The power supply terminal of crystal oscillator U2 is connected to the power supply and one end of capacitor C1, respectively. The other end of capacitor C1 is grounded and connected to the ground terminal of crystal oscillator U2, which can filter out high-frequency noise on the power supply.
[0031] In the test circuit described above in this embodiment, such as Figure 3As shown, the adjustment module includes an operational amplifier U3. One end of the input terminal VIN of the adjustment module is connected to the output terminal of the logging main control chip under test. The non-inverting input terminal of the operational amplifier U3 is connected to one end of resistor R3 and capacitor C4 respectively. The other end of resistor R3 is connected to one end of resistor R2 and capacitor C3 respectively. The other end of capacitor C4 is grounded. The output terminal Vout of the operational amplifier U3 is connected to one end of resistor R4 and the other end of capacitor C3 respectively. The inverting input terminal of the operational amplifier U3 is connected to the other end of resistor R4. The other end of resistor R2 is connected to the other end of the input terminal VIN of the adjustment module and one end of capacitor C2 respectively. The other end of capacitor C2 is grounded.
[0032] In the test circuit described above in this embodiment, such as Figure 4 As shown, the acquisition module includes an analog-to-digital converter (ADC) U4; the non-inverting input of the ADC U4 is connected to the output of the adjustment module; the inverting input of the ADC U4 is grounded; the reference voltage input REF of the ADC U4 is connected to the reference power supply VREF and one end of capacitor C5, and the other end of capacitor C5 is grounded; both the logic input and output of the ADC U4 are connected to the logic control module.
[0033] In the test circuit described above in this embodiment, such as Figure 5 As shown, the data upload module includes a communication chip U5 and a crystal oscillator U6; the clock input terminal of the communication chip U5 is connected to both ends of the crystal oscillator U6, and the two ends of the crystal oscillator U6 are grounded through capacitors C7 and C8 respectively; the two data output terminals of the communication chip U5 are connected to the host computer through a USB port; the remaining logic input terminals of the communication chip U5 are connected to the logic control module.
[0034] Preferably, the logic input terminal of the analog-to-digital converter U4 is connected to the logic output terminal CNV and the logic output terminal SCK of the logic control module, respectively; the output terminal of the analog-to-digital converter U4 is connected to the logic input terminal SDO of the logic control module through resistor R5.
[0035] Preferably, the remaining logic input terminals of the communication chip U5 are respectively connected to the eighth to twenty-seventh logic output terminals of the logic control module.
[0036] Preferably, the FPGA device U1 is an A3P1000 series FPGA from ACTEL, which has the advantages of high performance and high stability.
[0037] Preferably, the operational amplifier U3 is an OPA211, which has key characteristics such as low temperature drift and low noise.
[0038] Preferably, the analog-to-digital converter U4 is model AD7981.
[0039] Preferably, the communication chip U5 is model CY7C68013A, which has the advantages of fast transmission rate and high stability.
[0040] Any modifications, additions, and equivalent substitutions made within the scope of the principles of this invention shall still fall within the patent coverage of this invention.
[0041] Unless otherwise stated, the term "connection" as used above refers to a logical relationship of current transmission and does not necessarily indicate a direct electrical connection. Furthermore, terms such as "first" and "second" do not indicate a sequential order but are merely used to identify related units or devices.
Claims
1. A test circuit for a well logging main control chip, characterized in that, The test circuit includes, The adjustment module is used to preprocess the raw analog signal output by the main control chip of the well logging test and output an optimized signal; A data acquisition module is connected to the adjustment module, and the data acquisition module is used to convert the optimized signal into a digital signal; A data upload module is connected to the acquisition module, and the data upload module is used to upload the digital signal to the host computer; The logic control module is connected to the main control chip, acquisition module and data upload module of the well logging test, respectively. The logic control module is used to generate logic signals to perform logic control on the main control chip, acquisition module and data upload module of the well logging test.
2. The test circuit for the well logging main control chip as described in claim 1, characterized in that, The logic control module includes an FPGA device U1 and a crystal oscillator U2; The output terminal of the crystal oscillator U2 is connected to one end of the resistor R1, and the other end of the resistor R1 is connected to the clock input terminal of the FPGA device U1. The power supply terminal of the crystal oscillator U2 is connected to the power supply and one end of the capacitor C1, respectively. The other end of the capacitor C1 is grounded and connected to the ground terminal of the crystal oscillator U2. The logic output terminals A1, A2, A3, and A4 of the FPGA device U1 are respectively connected to the corresponding logging master control chip under test. The logic output terminal CNV, logic input terminal SDO, and logic output terminal SCK of the FPGA device U1 are connected to the acquisition module. The eighth to twenty-seventh logic output terminals of the FPGA device U1 are connected to the data upload module.
3. The test circuit for the well logging main control chip as described in claim 2, characterized in that, The adjustment module includes an operational amplifier U3, and one end of the input terminal VIN of the adjustment module is connected to the output terminal of the logging main control chip to be tested. The non-inverting input terminal of the operational amplifier U3 is connected to one end of resistor R3 and capacitor C4 respectively. The other end of resistor R3 is connected to one end of resistor R2 and capacitor C3 respectively. The other end of capacitor C4 is grounded. The output terminal Vout of the operational amplifier U3 is connected to one end of the resistor R4 and the other end of the capacitor C3, respectively. The inverting input terminal of the operational amplifier U3 is connected to the other end of the resistor R4; The other end of the resistor R2 is connected to the other end of the input terminal VIN of the adjustment module and one end of the capacitor C2, and the other end of the capacitor C2 is grounded.
4. The test circuit for the well logging main control chip as described in claim 2, characterized in that, The acquisition module includes an analog-to-digital converter U4; The non-inverting input terminal of the analog-to-digital converter U4 is connected to the output terminal of the adjustment module; The inverting input terminal of the analog-to-digital converter U4 is grounded; The reference voltage input terminal REF of the analog-to-digital converter U4 is connected to the reference power supply VREF and one end of the capacitor C5, and the other end of the capacitor C5 is grounded. The logic input and output terminals of the analog-to-digital converter U4 are both connected to the logic control module.
5. The test circuit for the well logging main control chip as described in claim 4, characterized in that, The logic input terminals of the analog-to-digital converter U4 are connected to the logic output terminals CNV and SCK of the logic control module, respectively. The output of the analog-to-digital converter U4 is connected to the logic input SDO of the logic control module via resistor R5.
6. The test circuit for the well logging main control chip as described in claim 2, characterized in that, The data upload module includes a communication chip U5 and a crystal oscillator U6; The clock input terminal of the communication chip U5 is connected to both ends of the crystal oscillator U6, and the two ends of the crystal oscillator U6 are grounded through capacitor C7 and capacitor C8, respectively. The two data output terminals of the communication chip U5 are connected to the host computer via a USB port. The remaining logic input terminals of the communication chip U5 are connected to the logic control module.
7. The test circuit for a well logging main control chip as described in claim 6, characterized in that, The remaining logic input terminals of the communication chip U5 are respectively connected to the eighth to twenty-seventh logic output terminals of the logic control module.
8. The test circuit for a well logging main control chip as described in claim 2, characterized in that, The FPGA device U1 is an A3P1000 series FPGA.
9. The test circuit for a well logging main control chip as described in claim 3, characterized in that, The operational amplifier U3 is model OPA211.
10. The test circuit for a well logging main control chip as described in claim 4, characterized in that, The analog-to-digital converter U4 is model AD7981.