Switch IC for testing, capable of setting optimal structure for test environment
By integrating a map information input unit and channel map variable setting unit, the test switch IC dynamically remaps channel configurations to match probe card branches, reducing setup and test times while optimizing manufacturing costs.
Patent Information
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- TECHWIDU CO LTD
- Filing Date
- 2025-12-18
- Publication Date
- 2026-06-25
AI Technical Summary
Existing test switch ICs with fixed channel maps face challenges in efficiently matching the number of branches on probe cards, leading to increased channel setup time and test time, which is costly and inefficient.
Incorporating a map information input unit and a channel map variable setting unit into the switch IC to enable dynamic remapping of channel configurations based on the number of probe card branches, allowing for optimized channel setups.
This approach reduces channel setup time, minimizes test time, and lowers manufacturing costs by enabling switch ICs to adapt to various branch configurations without the need for remanufacturing.
Smart Images
Figure KR2025022250_25062026_PF_FP_ABST
Abstract
Description
Test switch IC capable of optimal structure configuration for test environments
[0001] The present invention relates to a test switch IC capable of setting an optimal structure for a test environment, and more specifically, to a test switch IC capable of setting an optimal structure for a test environment by incorporating a remapping function into the switch IC so that the channel map can be set to an optimal structure according to the number of probe card branches.
[0002] The content described in this section merely provides background information regarding an embodiment of the present invention and does not constitute prior art.
[0003]
[0004] Probe cards for wafer testing utilize various types of PMICs (Power Management ICs) and switch ICs. In particular, as wafer miniaturization progresses, the number of DUTs (Device Under Test) is also increasing. Consequently, as process miniaturization progresses, the DPW (Die Per Wafer) increases, and since the number of ATE (Automated Test Equipment) channels remains fixed, the number of probe cards that need to branch increases accordingly.
[0005]
[0006] Probe cards for wafer testing contain multiple multi-channel switch ICs, and these switch ICs possess a fixed map that internally configures the channels for rapid channel setup. As such, if the channel map of the switch IC is fixed, it becomes difficult to place the switch ICs on cards of various branches. A wafer contains hundreds or thousands of dies. Test time generally takes (number of test items) * (number of branches) * (channel setup time). Since this test time itself is a cost, customers seek to minimize the impact that channel setup time has on test time. However, there was a problem involving a limitation where channel setup time increases if the fixed map does not match the number of branches. Korean Patent Publication No. 10-2006-0094203 is disclosed as a prior art document.
[0007]
[0008] The aforementioned background technology is technical information that the inventor possessed for the derivation of the present invention or acquired during the process of deriving the present invention, and it cannot be considered as publicly known technology disclosed to the general public prior to the filing of the present invention.
[0009] The present invention is proposed to solve the aforementioned problems of previously proposed methods, and aims to provide a test switch IC capable of setting an optimal structure for a test environment by including a map information input unit that receives map information for channel setting and a channel map variable setting unit that sets the channel map to an optimal structure corresponding to the number of probe card branches according to the map information for channel setting input to the map information input unit, thereby enabling the channel map to be set to an optimal structure corresponding to the number of probe card branches by incorporating a remapping function into the switch IC.
[0010]
[0011] In addition, another objective of the present invention is to provide a test switch IC capable of optimizing the structure for a test environment by incorporating a remapping function into the switch IC to enable the optimal structure setting of the channel map to match the number of branches of the probe card, and by inputting variable information regarding the map of the switch IC and enabling the switch IC to change the map configuration of the switch channels according to the input variable information of the map, thereby resolving the problem of increased channel setting time due to mismatch with the number of branches caused by the use of a fixed map and minimizing the increase in test time accordingly.
[0012]
[0013] In addition, another objective of the present invention is to provide a test switch IC capable of setting an optimal structure for a test environment, which enables the switch IC to change the map configuration of switch channels according to input remap information, thereby reducing the manufacturing cost of the customer's switch IC according to various branch numbers of the probe card, eliminating the need to remanufacture the switch IC when the number of branches changes, and enabling the customer to apply and use a switch IC with an optimized structure tailored to various branches.
[0014]
[0015] However, the technical problem that the present invention aims to solve is not limited to the technical problem described above, and other technical problems may exist.
[0016] A test switch IC capable of setting an optimal structure for a test environment according to the features of the present invention for achieving the above-mentioned purpose is,
[0017] As a test switch IC (Integrated Circuit) capable of setting an optimal structure for a test environment,
[0018] A map information input unit provided in a switch integrated circuit for electrical performance testing of DUTs (Device Under Test) connected to a probe card, for receiving map information for channel setting; and
[0019] The configuration is characterized by including a channel map variable setting unit that sets the channel map to an optimal structure corresponding to the number of probe card branches according to the map information for channel setting input to the map information input unit.
[0020]
[0021] Preferably, the map information input unit is,
[0022] It receives map information for channel configuration and can be configured as a Remap function that can change the map configuration of switch channels.
[0023]
[0024] More preferably, the map information input unit is,
[0025] With the Remap function, which allows changing the map configuration of switch channels, information regarding the switch IC map can be received in the form of pins.
[0026]
[0027] More preferably, the map information input unit is,
[0028] It is a remap function that can change the map configuration of switch channels, and can receive information about the switch IC's map in the form of a register.
[0029]
[0030] More preferably, the map information input unit is,
[0031] With the Remap function, which allows changing the map configuration of switch channels, information regarding the switch IC map can be received in the form of OTP (One-Time Programmable).
[0032]
[0033] Preferably, the map information input unit is,
[0034] With a remapping function that allows changing the map configuration of switch channels, it enables the application of optimized switch ICs tailored to various types of branches using a variable map rather than a fixed map.
[0035]
[0036] More preferably, the channel map variable setting unit is,
[0037] According to the map information for channel setting input to the map information input unit, the channel map is set to an optimal structure corresponding to the number of probe card branches, and the channel setting can be varied in response to the remapping function of the map information input unit.
[0038] According to the test switch IC capable of setting an optimal structure for a test environment proposed in the present invention, the switch integrated circuit for electrical performance testing of DUTs (Device Under Test) connected to a probe card is configured to include a map information input unit that receives map information for channel setting and a channel map variable setting unit that sets the channel map to an optimal structure corresponding to the number of probe card branches according to the map information for channel setting input to the map information input unit, thereby enabling the channel map to be set to an optimal structure corresponding to the number of probe card branches by incorporating a remapping function into the switch IC.
[0039]
[0040] In addition, according to the test switch IC capable of setting an optimal structure for the test environment of the present invention, a remapping function is provided to the switch IC to enable the optimal structure setting of the channel map to match the number of branches of the probe card, and variable information regarding the map of the switch IC is input, and the switch IC can change the map configuration of the switch channels according to the variable information of the input map, thereby resolving the problem of increased channel setting time due to mismatch with the number of branches caused by the use of a fixed map, and minimizing the increase in test time accordingly.
[0041]
[0042] In addition, according to the test switch IC capable of setting an optimal structure for the test environment of the present invention, by enabling the switch IC to change the map configuration of the switch channels according to the input remap information, it is possible to reduce the manufacturing cost of the customer's switch IC according to the various number of branches of the probe card, eliminate the need to remanufacture the switch IC when the number of branches changes, and enable the customer to apply and use a switch IC with an optimized structure tailored to various branches.
[0043]
[0044] Furthermore, the various and beneficial advantages and effects of the present invention are not limited to those described above and may be more easily understood in the process of explaining specific embodiments of the present invention.
[0045] FIG. 1 is a diagram illustrating the configuration of a serial connection when controlling a switch IC without a fixed map in the switch IC of a probe card.
[0046] FIG. 2 is a diagram illustrating the configuration of a parallel connection when controlling a switch IC without a fixed map in the switch IC of a probe card.
[0047] Figure 3 is a diagram illustrating the configuration when controlling a switch IC with a fixed map in the switch IC of a probe card.
[0048] FIG. 4 is a diagram illustrating a structure for branching each test port according to the DPW (Die Per Wafer) of the probe card.
[0049] Figure 5 is a diagram illustrating an example structure of a map fixed into four branches in the switch IC of a probe card.
[0050] Figure 6 is a diagram illustrating an example structure of a map fixed into 5 branches in the switch IC of a probe card.
[0051] FIG. 7 is a diagram illustrating the configuration of a test switch IC capable of setting an optimal structure for a test environment according to an embodiment of the present invention in functional blocks.
[0052] FIG. 8 is a diagram illustrating an example structure of a 5-channel branch configuration of a test switch IC capable of setting an optimal structure for a test environment according to an embodiment of the present invention.
[0053] FIG. 9 is a diagram illustrating an example structure of a 6-channel branch configuration of a test switch IC capable of setting an optimal structure for a test environment according to an embodiment of the present invention.
[0054] FIG. 10 is a diagram illustrating an example structure of a 7-channel branch configuration of a test switch IC capable of setting an optimal structure for a test environment according to an embodiment of the present invention.
[0055] FIG. 11 is a diagram illustrating an example structure of an 8-channel branch configuration of a test switch IC capable of setting an optimal structure for a test environment according to an embodiment of the present invention.
[0056] <Explanation of Symbols>
[0057] 100: Test switch IC according to an embodiment of the present invention
[0058] 110: Map Information Input Section
[0059] 120: Channel Map Variable Setting Section
[0060] Embodiments of the present invention are described below with reference to the attached drawings so that those skilled in the art can easily implement the invention. However, the present invention may be embodied in various different forms and is not limited to the embodiments described herein. Furthermore, in order to clearly explain the present invention in the drawings, parts unrelated to the explanation have been omitted, and similar parts throughout the specification are denoted by similar reference numerals.
[0061]
[0062] Throughout the specification, when a part is described as being "connected" to another part, this includes not only cases where they are "directly connected" but also cases where they are "indirectly connected" with other elements interposed between them. Furthermore, when a part is described as "including" a component, this means that, unless specifically stated otherwise, it does not exclude other components but rather allows for the inclusion of additional components; it should be understood that this does not preclude the existence or addition of one or more other features, numbers, steps, actions, components, parts, or combinations thereof.
[0063]
[0064] The following examples are detailed descriptions to aid in understanding the present invention and are not intended to limit the scope of the present invention. Accordingly, inventions within the same scope that perform the same function as the present invention will also fall within the scope of the present invention.
[0065]
[0066] In addition, each component, process, procedure, or method included in each embodiment of the present invention may be shared within a scope that is not technically contradictory to one another.
[0067]
[0068] Generally, probe cards for wafer testing are equipped with multiple multi-channel switch ICs, and these switch ICs have a fixed map that internally configures the channels for fast channel setup.
[0069]
[0070] FIG. 1 is a diagram illustrating the configuration of a serial connection when controlling a switch IC without a fixed map in the switch IC of a probe card, FIG. 2 is a diagram illustrating the configuration of a parallel connection when controlling a switch IC without a fixed map in the switch IC of a probe card, and FIG. 3 is a diagram illustrating the configuration when controlling a switch IC with a fixed map in the switch IC of a probe card.
[0071]
[0072] As shown in Fig. 1, in the configuration of a serial connection when controlling a switch IC without a fixed map in the switch IC of a probe card, when controlling with a switch IC without a fixed map, the CMD must be shifted to control the switch IC, so the setting time increases to 1 CMD * number of switch ICs.
[0073]
[0074] In addition, as shown in Fig. 2, in the configuration of a parallel connection when controlling a switch IC without a fixed map in the switch IC of the probe card, when controlling with a switch IC without a fixed map, multiple switch ICs can be configured at once, but the length of the 1CMD protocol increases by the switch IC identification field, channel identification field, and control field.
[0075]
[0076] In addition, as shown in Fig. 3, in the configuration for controlling the switch IC with a fixed map in the switch IC of the probe card, when controlling the switch IC with a fixed map, the entire channel or the desired core per switch IC can be controlled with a short length of 1 CMD.
[0077]
[0078] FIG. 4 is a diagram illustrating a structure for branching each test port according to the DPW (Die Per Wafer) of the probe card, FIG. 5 is a diagram illustrating an example structure of a map fixed into 4 branches at the switch IC of the probe card, and FIG. 6 is a diagram illustrating an example structure of a map fixed into 5 branches at the switch IC of the probe card.
[0079]
[0080] As shown in Fig. 4, the probe card branches each test port according to the Die Per Wafer (DPW). One channel of the ATE equipment branches out to n channels to transmit signals to the DUT. At this time, as process miniaturization progresses, the number of DPWs increases and the number of ATE channels remains fixed, so the number of channels that the probe card must branch increases.
[0081]
[0082] Consequently, if the channel map of a switch IC is fixed, difficulties arise in deploying the switch IC to probe cards of various branches. A wafer contains hundreds or thousands of dies, and the test time typically takes (number of test items) * (number of branches) * (channel setup time). Since test time itself is a cost, customers seek to minimize the impact of channel setup time on the test time; however, if the fixed map does not match the number of branches, the channel setup time increases.
[0083]
[0084] As illustrated in Fig. 5, for the fourth quarter, regular placement is possible on a fixed map, and the customer can configure the channels to be tested in 1 CMD. For example, to test only the nth DUT of each ATE channel, 1 CMD is required, and the test can be completed with a total of n channel configurations.
[0085]
[0086] On the other hand, as illustrated in Figure 6, in the case of the 5th quarter, using a fixed map results in irregular placement, and multiple CMDs must be sent when the client sets up the channel to be tested. In particular, the advantages of a fixed map cannot be utilized, which leads to an increase in test time and does not meet the client's needs. For example, testing DUT n times for each ATE channel requires 5 CMDs, and the total setup time for the test increases by approximately 5 times compared to the 4th quarter.
[0087]
[0088] FIG. 7 is a diagram illustrating the configuration of a test switch IC capable of setting an optimal structure for a test environment according to an embodiment of the present invention in functional blocks. As shown in FIG. 7, the test switch IC (Integrated Circuit) (100) capable of setting an optimal structure for a test environment according to an embodiment of the present invention may be configured to include a map information input unit (110) for receiving map information for channel setting, provided in a switch integrated circuit for testing the electrical performance of DUTs (Device Under Test) connected to a probe card, and a channel map variable setting unit (120) for setting a channel map to an optimal structure corresponding to the number of probe card branches according to the map information for channel setting input to the map information input unit (110). Hereinafter, the specific configuration of the test switch IC capable of setting an optimal structure for a test environment according to an embodiment of the present invention will be described in detail with reference to the attached drawings.
[0089]
[0090] FIG. 8 is a diagram illustrating an example structure of a 5-channel branch configuration of a test switch IC capable of setting an optimal structure for a test environment according to an embodiment of the present invention, FIG. 9 is a diagram illustrating an example structure of a 6-channel branch configuration of a test switch IC capable of setting an optimal structure for a test environment according to an embodiment of the present invention, FIG. 10 is a diagram illustrating an example structure of a 7-channel branch configuration of a test switch IC capable of setting an optimal structure for a test environment according to an embodiment of the present invention, and FIG. 11 is a diagram illustrating an example structure of an 8-channel branch configuration of a test switch IC capable of setting an optimal structure for a test environment according to an embodiment of the present invention.
[0091]
[0092] The map information input unit (110) is configured to receive map information for channel setting by being provided in a switch integrated circuit for electrical performance testing of DUTs (Device Under Test) connected to a probe card. This map information input unit (110) receives map information for channel setting and can be configured with a remap function that can change the map configuration of the switch channels. Here, the map information input unit (110) is a plurality of multi-channel switch ICs provided in the test switch IC (100), and can function to resolve the problem of increased channel setting time when the existing fixed map does not match the number of branches through the remap function. That is, the map information input unit (110) can function to use map information for channel setting as a variable setting without the need to remanufacture switch ICs according to the various number of branches of the probe card.
[0093]
[0094] Additionally, the map information input unit (110) is a remap function capable of changing the map configuration of switch channels, and can receive information about the map of the switch IC in the form of a pin. Additionally, the map information input unit (110) is a remap function capable of changing the map configuration of switch channels, and can receive information about the map of the switch IC in the form of a register. Additionally, the map information input unit (110) is a remap function capable of changing the map configuration of switch channels, and can receive information about the map of the switch IC in the form of an OTP (One-Time Programmable). As such, the map information input unit (110) receives information about the map of the switch IC, and it can be understood that the input information can be input in various forms including pins, registers, and OTPs.
[0095]
[0096] In addition, the map information input unit (110) can function as a remap function that can change the map configuration of the switch channels, and can enable the application of an optimized switch IC according to various types of branches as a variable map rather than a fixed map.
[0097]
[0098] The channel map variable setting unit (120) is configured to set the channel map to an optimal structure corresponding to the number of probe card branches according to the map information for channel setting input to the map information input unit (110). This channel map variable setting unit (120) sets the channel map to an optimal structure corresponding to the number of probe card branches according to the map information for channel setting input to the map information input unit (110), and can function to make the channel setting variable in response to the remapping function of the map information input unit (110).
[0099]
[0100] FIG. 8 is an example structure of a 5-channel branch configuration of a test switch IC capable of setting an optimal structure for a test environment according to an embodiment of the present invention, showing a case where 1 core is remapped to 5 channels, totaling 11 cores; FIG. 9 is an example structure of a 6-channel branch configuration of a test switch IC capable of setting an optimal structure for a test environment according to an embodiment of the present invention, showing a case where 1 core is remapped to 6 channels, totaling 10 cores; FIG. 10 is an example structure of a 7-channel branch configuration of a test switch IC capable of setting an optimal structure for a test environment according to an embodiment of the present invention, showing a case where 1 core is remapped to 7 channels, totaling 9 cores; and FIG. 11 is an example structure of an 8-channel branch configuration of a test switch IC capable of setting an optimal structure for a test environment according to an embodiment of the present invention, showing a case where 1 core is remapped to 8 channels, totaling 8 cores.
[0101]
[0102] In this way, a test switch IC (100) capable of setting an optimal structure for a test environment is provided in a switch integrated circuit for electrical performance testing of DUTs (Device Under Test) connected to a probe card, and includes a map information input unit (110) for receiving map information for channel setting, and a channel map variable setting unit (120) for setting a channel map into an optimal structure corresponding to the number of probe card branches according to the map information for channel setting input to the map information input unit (110). The switch IC is equipped with a remap function to enable setting an optimal structure for the channel map corresponding to the number of card branches. Additionally, by inputting information regarding the map into the switch IC, the information can be in various forms such as Pin, Register, OTP, etc., and the switch IC can change the map configuration of the switch channels according to the input information. This reduces the manufacturing cost of the switch IC for the customer according to the various number of branches of the probe card, eliminates the need to remanufacture the switch IC when the number of branches changes, and enables the customer to have a structure optimized for various branches. It can function to enable the application and use of switch ICs.
[0103]
[0104] As described above, a test switch IC capable of setting an optimal structure for a test environment according to an embodiment of the present invention is configured to include a switch integrated circuit for electrical performance testing of Device Under Test (DUT) connected to a probe card, a map information input unit that receives map information for channel setting, and a channel map variable setting unit that sets the channel map to an optimal structure corresponding to the number of probe card branches according to the map information for channel setting input to the map information input unit. By doing so, a remapping function can be added to the switch IC to enable the optimal structure setting of the channel map corresponding to the number of probe card branches. In particular, by adding a remapping function to the switch IC to enable the optimal structure setting of the channel map corresponding to the number of probe card branches, and by inputting variable information for the map of the switch IC and enabling the switch IC to change the map configuration of the switch channels according to the input variable information of the map, the problem of increased channel setting time due to mismatch with the number of branches caused by the use of a fixed map can be resolved, and the increase in test time resulting therefrom can be minimized. Furthermore, according to the input remapping information, the switch IC [manipulates] the switch channels By enabling changes to the map configuration, it is possible to reduce the manufacturing cost of the customer's switch IC according to the various number of branches of the probe card, eliminate the need to remanufacture the switch IC when the number of branches changes, and enable the customer to apply and use a switch IC with an optimized structure tailored to various branches.
[0105]
[0106] The foregoing description of the present invention is for illustrative purposes only, and those skilled in the art will understand that other specific forms can be easily modified without altering the technical spirit or essential features of the present invention. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive. For example, each component described as a single unit may be implemented in a distributed manner, and components described as distributed may likewise be implemented in a combined form.
[0107]
[0108] The scope of the present invention is defined by the claims set forth below rather than by the detailed description above, and all modifications or variations derived from the meaning and scope of the claims and equivalent concepts thereof should be interpreted as being included within the scope of the present invention.
Claims
1. A test switch IC (Integrated Circuit) (100) capable of setting an optimal structure for a test environment, A map information input unit (110) provided in a switch integrated circuit for electrical performance testing of DUTs (Device Under Test) connected to a probe card, for receiving map information for channel setting; and A test switch IC capable of setting an optimal structure for a test environment, characterized by including a channel map variable setting unit (120) that sets the channel map to an optimal structure corresponding to the number of probe card branches according to the map information for channel setting input to the map information input unit (110).
2. In paragraph 1, the map information input unit (110) is, A test switch IC capable of configuring an optimal structure for a test environment, characterized by receiving map information for channel configuration and being configured with a remap function that can change the map configuration of switch channels.
3. In paragraph 2, the map information input unit (110) is, A test switch IC capable of setting an optimal structure for a test environment, characterized by a remap function that can change the map configuration of switch channels and receiving information about the switch IC's map in the form of pins.
4. In paragraph 2, the map information input unit (110) is, A test switch IC capable of setting an optimal structure for a test environment, characterized by a remap function that can change the map configuration of switch channels, and receiving information about the map of the switch IC in the form of a register.
5. In paragraph 2, the map information input unit (110) is, A test switch IC capable of setting an optimal structure for a test environment, characterized by a remap function that can change the map configuration of switch channels, and receiving information about the switch IC map in the form of an OTP (One-Time Programmable).
6. In any one of paragraphs 1 to 5, the map information input unit (110) is, A test switch IC capable of configuring an optimal structure for a test environment, characterized by a remap function that can change the map configuration of switch channels, enabling the application of an optimized switch IC tailored to various types of branches using a variable map rather than a fixed map.
7. In paragraph 6, the channel map variable setting unit (120) is, A test switch IC capable of setting an optimal structure for a test environment, characterized by setting a channel map (Map) to an optimal structure corresponding to the number of probe card branches according to map information for channel setting input to the map information input unit (110), and functioning to make the channel setting variable in response to the remapping function of the map information input unit (110).