Intelligent relay response control method and system based on FPGA directly controlling pins

Abstract

The application relates to the technical field of relay response control, and discloses an intelligent relay response control method and system based on FPGA direct control of pins, which comprises the following steps: in response to logical control block configuration instructions and time sequence diagram configuration instructions input by a user in a vehicle-mounted scene, a first control strategy is generated through double-track fusion analysis; a parameter mapping mechanism is configured, the first control strategy is mapped into a first parameter set for FPGA execution; an active area and a standby area of the FPGA are dynamically allocated, and a hardware logic circuit is initialized to obtain a first hardware logic circuit; in combination with input signals, sensor data and synchronous bus signals collected by the FPGA in real time, a control signal corresponding to a relay is generated according to the first hardware logic circuit, and the action of the relay is controlled, so that the intelligent relay can be quickly responded; and the application can shorten a response link and improve response speed.

Description

Technical Field

[0001] This application relates to the field of relay response control technology, and more specifically to an intelligent relay response control method and system based on FPGA direct control pins. Background Technology

[0002] Currently, in the field of vehicle-mounted control, stringent requirements are placed on relay control, including microsecond-level high-speed response and precise coordination of complex logic and timing. Existing solutions based on general-purpose processors, such as MCUs and PLCs, are limited by the latency of the software architecture and cannot meet this requirement. Relying on microcontrollers or programmable logic controllers to implement relay control through software programs results in slow response speed, inflexible development and configuration, rigid resource utilization, and an inability to dynamically optimize allocation according to real-time tasks, leading to low efficiency.

[0003] The existing technology has the following problems: it adopts fixed control logic, and modifications require reprogramming or hardware wiring adjustments, making it difficult to support dynamic configurations with complex timing and multi-condition triggering; the logic control and time axis control are designed separately, which easily leads to timing conflicts and event asynchrony; the control strategy is statically mapped to hardware resources, making it impossible to dynamically allocate computing and I / O resources according to real-time tasks, resulting in low resource utilization and slow response speed; in order to solve at least one of the above problems, this application proposes an intelligent relay response control method and system based on FPGA direct control pins. Summary of the Invention

[0004] To address the shortcomings of existing technologies, the purpose of this application is to provide an intelligent relay response control method and system based on FPGA direct control pins, which can effectively solve the problems in the background technology. The specific technical solution of this application is as follows:

[0005] A smart relay response control method based on FPGA direct control pins includes:

[0006] In response to the logic control block configuration command and timing diagram configuration command input by the user in the vehicle scenario, a first control strategy is generated through dual-track fusion analysis. The dual-track fusion analysis includes parsing the trigger events in the logic control block and the time points in the timing diagram, and constructing a correspondence table between trigger events and time points.

[0007] Configure a parameter mapping mechanism to map the first control strategy to the first set of parameters executed by the FPGA;

[0008] Configure the FPGA according to the first parameter set, dynamically allocate the active area and spare area of ​​the FPGA, and initialize the hardware logic circuit to obtain the first hardware logic circuit.

[0009] By combining the input signals, sensor data, and synchronization bus signals acquired in real time by the FPGA, the control signals of the corresponding relays are generated according to the first hardware logic circuit, and the actions of the relays are controlled to respond to the intelligent relays.

[0010] Specifically, the logic control block configuration command and timing diagram configuration command input by the user in the vehicle scenario are responded to, and a first control strategy is generated through dual-track fusion analysis, including:

[0011] In response to the logic control block configuration command input by the user in the vehicle scenario, the set of trigger events is obtained by parsing the logic topology and extracting the corresponding trigger events. The logic control block configuration command defines the trigger conditions, logical operations and state transition relationships through nodes and connections.

[0012] In response to the timing diagram configuration command input by the user, the time point set is obtained by parsing the time axis and extracting the time points of the corresponding actions. The timing diagram configuration command includes the level change points and timing relationships of the relay output channel.

[0013] Analyze the relationship between triggering events and time points, and dynamically link the set of triggering events and the set of time points to obtain a corresponding table;

[0014] The event time sequence and time parameters are generated according to the corresponding table to obtain the first control strategy.

[0015] Specifically, in response to the user-input logic control block configuration command in the vehicle scenario, a set of trigger events is obtained by parsing the logic topology and extracting the corresponding trigger events, including:

[0016] In response to user input of logic control block configuration commands in vehicle scenarios, nodes and connections are parsed, and the set of labeled nodes and the set of directed edges are obtained through semantic annotation and directed edge analysis.

[0017] Based on the set of labeled nodes and the set of directed edges, the transmission paths between labeled nodes are identified according to the directed edges, and a first path set is constructed.

[0018] Extract the initial node and the termination node from the first path set, construct the corresponding trigger events, and obtain the trigger event set.

[0019] Specifically, in response to the user-inputted sequence diagram configuration command, the timeline is parsed and the corresponding action time points are extracted to obtain a set of time points, including:

[0020] In response to the timing diagram configuration command input by the user, the system scans the multi-channel time axis to identify the transition positions of level change points as the original event points and constructs the first event point sequence.

[0021] Analyze the time corresponding to the event points in the first event point sequence, and merge the event points whose time difference between adjacent event points is less than a preset time difference threshold to obtain the second event point sequence;

[0022] Analyze the timeline of each event point in the second event point sequence, select the event points that are synchronous in time as the synchronization group, and extract the time points corresponding to the events in the synchronization group and the asynchronous group to obtain the time point set.

[0023] Specifically, the analysis of the correlation between triggering events and time points involves dynamically linking the set of triggering events and the set of time points to obtain a corresponding table, including:

[0024] Analyze the semantic matching between the triggering conditions corresponding to the triggering events and the actions corresponding to the time points, match the set of triggering events and the set of time points to obtain the first link result;

[0025] Based on the logical dependencies of events in the trigger event set, the locations in the first link result that have temporal causal conflicts and event resource conflicts are filtered out to obtain the set of conflict link points;

[0026] The updated set of connection points is obtained by replacing the time points of the conflict connection point set or updating the time points of the conflict actions;

[0027] The first link result is updated and optimized based on the updated link point set to obtain the corresponding table.

[0028] Specifically, the parameter mapping mechanism includes:

[0029] Based on the first control strategy, the corresponding logic functional units in the FPGA are parsed out as logic entities. The signal transmission between logic entities is analyzed to construct timing constraints, and a set of logic entities and a set of timing constraints are obtained.

[0030] Based on the set of logical entities and the real-time resource status of the FPGA, a corresponding resource unit is allocated to each logical entity to obtain the first allocation result;

[0031] Combining the first allocation result and the set of timing constraints, the propagation of the signal is simulated and timing analysis is performed. By identifying and optimizing propagation paths whose propagation delay exceeds the timing constraints, a second allocation result is obtained.

[0032] Based on the second allocation result, the first set of parameters for FPGA execution is obtained through a preset parameter generation model.

[0033] Specifically, configuring the FPGA according to the first parameter set, dynamically allocating the active and spare areas of the FPGA, and initializing the hardware logic circuit to obtain the first hardware logic circuit includes:

[0034] Configure the FPGA according to the first parameter set, dynamically allocate the active and spare areas of the FPGA, and generate area allocation instructions;

[0035] The FPGA is subjected to security verification and slice loading according to the area allocation instructions, and the hardware logic circuit is initialized to obtain the first hardware logic circuit.

[0036] Specifically, configuring the FPGA according to the first parameter set, dynamically allocating the active and spare areas of the FPGA, and generating area allocation instructions include:

[0037] Configure the FPGA according to the first parameter set and analyze the real-time resource usage of the FPGA;

[0038] Based on the real-time resource occupancy, the active area and spare area of ​​the FPGA are dynamically allocated, and area allocation instructions are generated. The dynamic allocation process includes erasing the existing configuration of the occupied active area and updating it in real time, or selecting the corresponding area from the spare area for expansion.

[0039] Specifically, the step of performing security verification and slice loading on the FPGA according to the region allocation instruction, and initializing the hardware logic circuit to obtain the first hardware logic circuit includes:

[0040] The FPGA is subjected to security verification and slice loading according to the area allocation instructions. The active area and the spare area are sliced ​​to obtain the first configuration instructions.

[0041] The hardware logic circuit is initialized according to the first configuration instruction to obtain the first hardware logic circuit.

[0042] A smart relay response control system based on FPGA direct control pins, used to implement the aforementioned smart relay response control method based on FPGA direct control pins, includes:

[0043] The instruction parsing module responds to the logic control block configuration instructions and timing diagram configuration instructions input by the user in the vehicle scenario. It generates a first control strategy through dual-track fusion analysis. The dual-track fusion analysis includes parsing the trigger events in the logic control block and the time points in the timing diagram, and constructing a correspondence table between trigger events and time points.

[0044] The parameter mapping module configures the parameter mapping mechanism, mapping the first control strategy to the first set of parameters executed by the FPGA;

[0045] The region allocation module configures the FPGA according to the first parameter set, dynamically allocates the active area and spare area of ​​the FPGA, and initializes the hardware logic circuit to obtain the first hardware logic circuit.

[0046] The relay response module combines the input signals, sensor data, and synchronization bus signals acquired in real time by the FPGA, generates control signals for the corresponding relays according to the first hardware logic circuit, and controls the relays to respond to the intelligent relays.

[0047] The beneficial effects of this application are as follows: By jointly analyzing and dynamically linking logic control blocks and timing diagrams, and constructing a correspondence table, deep collaboration between logic and time is achieved, avoiding timing conflicts; through a parameter mapping mechanism, the control strategy is automatically converted into a set of hardware parameters to be executed by the FPGA, and combined with the dynamic allocation and segmented loading of active and standby areas, real-time optimization of hardware resources is achieved; in dual-track fusion, timing causal conflicts and event resource conflicts are automatically identified, and dynamic optimization is achieved through time-point replacement or updates, improving the feasibility and efficiency of the control strategy; utilizing the parallel processing and pin direct control capabilities of the FPGA, combined with real-time input signals, sensor data, and bus data, drive signals are directly generated, which can shorten the response chain and improve the response speed. Attached Figure Description

[0048] Figure 1 This is a flowchart illustrating the intelligent relay response control method based on FPGA direct control pins in Embodiment 1 of this application.

[0049] Figure 2 This is a schematic diagram of the event point merging process in Embodiment 1 of this application;

[0050] Figure 3 This is a flowchart illustrating the parameter mapping mechanism in Embodiment 1 of this application;

[0051] Figure 4 This is a schematic diagram of the intelligent relay response control system based on FPGA direct control pins in Embodiment 1 of this application. Detailed Implementation

[0052] The present application will be further described in detail below with reference to the accompanying drawings and embodiments.

[0053] In the embodiments of this application, the terms "exemplary" or "for example" are used to indicate that something is an example, illustration, or description. Any embodiment or design that is described as "exemplary" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design. Specifically, the use of the terms "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

[0054] Hereinafter, the terms "first," "second," and other generic terms are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the embodiments of this application, unless otherwise stated, "multiple" means two or more.

[0055] Example 1:

[0056] refer to Figure 1 The image shows a specific implementation of the intelligent relay response control method based on FPGA direct control pins according to this application, including:

[0057] S101. In response to the logic control block configuration command and timing diagram configuration command input by the user in the vehicle scenario, a first control strategy is generated through dual-track fusion analysis. The dual-track fusion analysis includes parsing the trigger events in the logic control block and the time points in the timing diagram, and constructing a correspondence table between trigger events and time points.

[0058] S102. Configure the parameter mapping mechanism to map the first control strategy to the first set of parameters executed by the FPGA;

[0059] S103. Configure the FPGA according to the first parameter set, dynamically allocate the active area and spare area of ​​the FPGA, and initialize the hardware logic circuit to obtain the first hardware logic circuit.

[0060] S104. Combining the input signals, sensor data and synchronization bus signals acquired in real time by the FPGA, the corresponding control signals of the relays are generated according to the first hardware logic circuit and the action of the relays is controlled to respond to the intelligent relays.

[0061] In automated control systems, relays serve as critical actuators, and their response speed and coordination directly impact overall performance. Traditional control architectures utilize microcontrollers or programmable logic controllers as their core, generating control signals by running software programs on the operating system or firmware. This approach inherently suffers from latency, and logic modification and timing debugging are complex processes.

[0062] In this embodiment, based on the logic control block configuration instructions input by the user through the graphical interface, these instructions are internally represented as a data structure of nodes and connections. Through semantic annotation and directed edge analysis, a directed graph reflecting the signal flow is constructed, identifying all transmission paths from input condition nodes to output action nodes. The start and end points of each path are extracted as trigger events, forming a set of trigger events. Simultaneously, based on the timing diagram configuration instructions input by the user, by scanning the multi-channel time axis, all level transition edges are detected as original event points, identifying synchronized action groups and extracting their corresponding times, forming a set of time points. Through dual-track fusion, the set of trigger events and the set of time points are dynamically linked to construct a correspondence table between trigger events and time points, and a first control strategy for the execution time corresponding to each logic event is generated.

[0063] It should be noted that by using dual-track fusion analysis, the input logic design and timing design are automatically and accurately integrated into a conflict-free control strategy. This avoids the problem of repeated manual verification by logic engineers and timing engineers in traditional design, which is prone to oversights, thus improving design efficiency and accuracy. Through automated conflict detection and optimization, the consistency of the control strategy in terms of logical correctness and timing feasibility is ensured, providing accurate strategy support for subsequent conversion to hardware implementation and improving the security and reliability of the entire system.

[0064] Specifically, the first control strategy is parsed into implementable logical functional units in the FPGA, a set of logical entities is constructed, and a set of timing constraints is constructed according to the time requirements in the strategy. Based on the set of logical entities, physical resource units are allocated to each entity to obtain the first allocation result. Timing analysis is performed on the first allocation result to identify and optimize the paths whose propagation delay exceeds the constraints, thereby obtaining the second allocation result that satisfies all timing constraints. The second allocation result is then converted into the first parameter set for FPGA execution.

[0065] It should be noted that the parameter mapping mechanism efficiently converts the control strategy into the underlying hardware configuration. Through automated timing-driven placement and routing optimization, the workload of repeatedly performing timing constraints and iterative compilation manually in traditional FPGA development can be reduced, the development cycle can be shortened, and hardware configuration parameters that have been fully optimized and verified in terms of timing can be generated, ensuring that the control strategy is accurately mapped to the FPGA hardware, and guaranteeing the predictability and optimality of system performance.

[0066] Specifically, based on the first parameter set and combined with the real-time resource occupancy bitmap read from the FPGA's internal status register, the physical coordinates of the active area used to carry the new logic are selected, and the corresponding area boundary and operation type area allocation instructions are generated. Through security verification and slice loading, the configuration data slices of the corresponding area are extracted from the first parameter set. Through the FPGA's internal configuration access port, the slice data is written into the configuration memory corresponding to the active area. After loading is completed, an initialization command is written to the control register of the active area to generate a local hardware initialization pulse, so that all timing elements in the area are reset or set to the initial state, thus obtaining the first hardware logic circuit.

[0067] It should be noted that dynamic partitioning and slice loading initialization technology can improve system flexibility and availability. Specific relay control functions can be dynamically modified, upgraded, or expanded without interrupting the overall system operation. The spare area provides a hardware foundation for fault redundancy and function switching, improving system reliability and maintainability. Local reconfiguration can shorten configuration time and improve response speed.

[0068] Specifically, the FPGA acquires input signals, sensor data, and synchronization bus signals in real time through its programmable I / O pins. Input signals include, but are not limited to, digital inputs such as buttons, switches, and limit signals. Sensor data includes, but is not limited to, analog sensor signals. After being converted into digital signals by an external ADC chip, the data is sent to the FPGA through a parallel or high-speed serial interface. Synchronization bus signals include, but are not limited to, industrial Ethernet and CAN bus data. After being decoded by the FPGA's internal IP core or an external PHY chip, the relevant control words or status words are extracted and sent to the logic circuit.

[0069] Specifically, the first hardware logic circuit continuously and in parallel monitors all input signals. When the collected signal combination meets the trigger event conditions defined in the logic control block, the circuit reacts immediately within one or several FPGA clock cycles. According to the precise timing specified in the corresponding table, it controls the internal timer or counter to send a corresponding control signal to the designated output pin at the corresponding time point, such as a pulse with precise pulse width or a level toggle. This control signal is directly output through the FPGA's I / O pins, undergoes necessary level conversion and power drive circuitry (such as optocoupler isolation and MOSFET drive), and finally acts on the coil control terminal of the smart relay, accurately controlling its closing or opening action. Since the entire decision-making and signal generation chain is implemented by pure hardware logic, the delay from the satisfaction of the input conditions to the action of the output pin is extremely short, avoiding software overhead such as operating system scheduling and task switching, and enabling rapid response to the smart relay.

[0070] It is important to emphasize that through FPGA hardware control, deterministic responses at the microsecond or even nanosecond level can be achieved, enabling rapid responses to instantaneous actions, improving response speed, and providing extremely high real-time performance. During control, it is unaffected by software malfunctions or virus interference, ensuring stable operation and enhancing system reliability. Based on a unified high-precision clock, nanosecond-level precision synchronous or sequential control of multiple relays can be achieved, avoiding timing conflicts and improving system stability and reliability.

[0071] This application performs joint analysis and dynamic linking of logic control blocks and timing diagrams, and constructs a correspondence table to achieve deep coordination between logic and time, avoiding timing conflicts. Through a parameter mapping mechanism, the control strategy is automatically converted into a set of hardware parameters to be executed by the FPGA. Combined with the dynamic allocation and segmented loading of active and standby areas, real-time optimization of hardware resources is achieved. In the dual-track fusion, timing causal conflicts and event resource conflicts are automatically identified, and dynamic optimization is achieved through time point replacement or update, improving the feasibility and efficiency of the control strategy. Utilizing the parallel processing and pin direct control capabilities of the FPGA, combined with real-time input signals, sensor data, and bus data, drive signals are directly generated, which can shorten the response chain and improve the response speed.

[0072] Furthermore, in response to user input of logic control block configuration commands and timing diagram configuration commands in the vehicle scenario, a first control strategy is generated through dual-track fusion analysis, including:

[0073] S201. In response to the logic control block configuration instruction input by the user in the vehicle scenario, the set of trigger events is obtained by parsing the logic topology structure and extracting the corresponding trigger events. The logic control block configuration instruction defines the trigger conditions, logical operations and state transition relationships through nodes and connections.

[0074] S202. In response to the timing diagram configuration instruction input by the user, the time point set is obtained by parsing the time axis and extracting the time points of the corresponding actions. The timing diagram configuration instruction includes the level change points and timing relationships of the relay output channel.

[0075] S203. Analyze the relationship between triggering events and time points, and dynamically link the set of triggering events and the set of time points to obtain a corresponding table;

[0076] S204. Generate the event time sequence and time parameters according to the corresponding table to obtain the first control strategy.

[0077] In this embodiment, in response to user-inputted logic control block configuration commands in an in-vehicle scenario, the logic topology is parsed and corresponding trigger events are extracted to obtain a set of trigger events. The logic control block configuration commands define trigger conditions, logical operations, and state transition relationships through nodes and connections, including a data structure composed of node objects and connection objects. Each node object includes its type attributes and configuration parameters, and each connection object records the source node, target node, and the name of the transmitted signal variable. By parsing the logic topology and extracting the corresponding trigger events, the graphical logic design is quickly and accurately converted into event descriptions, obtaining the corresponding trigger events. This provides accurate input for subsequent integration with the timeline, ensuring the integrity and accuracy of the control strategy.

[0078] Specifically, in response to user-input timing diagram configuration commands, the system parses the time axis and extracts the corresponding action time points. It analyzes time differences and synchronization, then merges these data to obtain a set of time points. The timing diagram configuration commands include the level change points and timing relationships of relay output channels. Data-wise, this is represented as a sequence of level changes across multiple channels on a unified time axis, with each channel corresponding to a different output relay or action. Through merging and optimization, plotting noise can be effectively filtered. Synchronization group identification distinguishes between strictly synchronized actions and sequentially executed actions, providing accurate timing constraints for subsequent links with logical events and a precise data foundation for generating high-precision, implementable timing control strategies.

[0079] Furthermore, the relationship between triggering events and time points is analyzed, and the set of triggering events and the set of time points are dynamically linked. One or more time points are assigned to each triggering event. Through temporal causal conflict detection and event resource conflict detection, conflict locations are detected to form a set of conflict link points. The conflict link points are optimized, and a correspondence table is generated based on the optimization results. The correspondence table includes the precise execution time point corresponding to each triggering event and a list of specific physical actions that need to be performed at that time point.

[0080] It should be noted that by integrating the logic control flow and physical timing flow through conflict detection and optimization, the problems of timing errors and action conflicts caused by human coordination oversights in the traditional separate design pattern can be effectively solved. This improves the consistency and security of the control strategy, enhances the design efficiency and first-time accuracy of complex control systems, and ensures that the final generated hardware control logic meets both functional requirements and strict timing constraints.

[0081] Specifically, each row in the correspondence table defines a logical trigger event and its corresponding execution time point. All rows are sorted according to the chronological order of their time points to obtain an event time sequence list. For multiple events assigned to the same time point, they are marked in the list as having the same timestamp. Detailed time parameters and action parameters are generated for each entry in the list, including but not limited to generating an absolute timestamp based on a unified zero point according to the system design, listing all output channels that need to be controlled at that time point and their target states, and associating them back with the original trigger event logical conditions to obtain a description unit. The time parameters and action parameters are combined to obtain the first control strategy. The fused correspondence table is transformed into a control strategy description. The generated first control strategy includes logical constraints and timing constraints, providing accurate strategy support for the hardware implementation process. The description unit ensures the accuracy and completeness of information transmission from user intent to hardware implementation.

[0082] Furthermore, in response to user input configuration commands for logic control blocks in an in-vehicle scenario, the system parses the logic topology and extracts the corresponding trigger events to obtain a set of trigger events, including:

[0083] S301. In response to the user input of the logic control block configuration command in the vehicle scenario, the nodes and connections are parsed, and the set of labeled nodes and the set of directed edges are obtained through semantic annotation and directed edge analysis.

[0084] S302. Based on the set of labeled nodes and the set of directed edges, identify the transmission paths between labeled nodes according to the directed edges, and construct a first path set;

[0085] S303. Extract the initial node and the termination node from the first path set, construct the corresponding trigger events, and obtain the trigger event set.

[0086] In this embodiment, according to the logic control block configuration instructions input by the user, the logic control block configuration instructions are represented in memory as a data structure of a series of node objects and connection objects; each node object contains its type attributes and related configuration parameters, the type attributes include but are not limited to digital input, analog comparator, logic AND gate, etc., and the configuration parameters include but are not limited to comparison threshold and initial state; each connection object determines the unique identifier of the source node and the unique identifier of the target node, reflecting the direction of signal flow.

[0087] Specifically, semantic annotation is performed by querying a predefined node semantic mapping rule base. This rule base includes, but is not limited to, labeling AND as a logical operation and SENSOR_IN as a sensor input source, thus determining the semantics of each node. Then, directed edge analysis is performed by traversing all connected objects. The annotated nodes are used as vertices of the graph, and directed edges from source nodes to target nodes are established based on the connection information, resulting in a set of annotated nodes and a set of directed edges. Through semantic parsing and directed edge analysis, the potentially ambiguous graphical design input by the user is transformed into an accurate internal computer representation, providing an accurate data foundation for subsequent analysis and reducing the risk of defects introduced by human interpretation errors.

[0088] Specifically, based on the semantic annotation information of the nodes, an initial node set and a termination node set are identified. The initial node set is typically defined as nodes belonging to the input class or with an in-degree of zero, while the termination node set is typically defined as nodes belonging to the output action class or with an out-degree of zero. Using a depth-first search algorithm, starting from each initial node, a recursive traversal is performed along directed edges. During the traversal, all node sequences from the starting point to any termination node are recorded, forming the first path set. A visit state marking mechanism is introduced into the traversal algorithm to prevent getting trapped in infinite recursion caused by circular connections, and the found paths are standardized and stored, for example, each path is stored as an ordered list of node IDs. Through the traversal operation, all complete transmission chains from conditions to actions in the logic control block can be filtered out, ensuring the comprehensiveness and completeness of subsequent trigger event extraction, and providing accurate data input for generating control strategies covering all scenarios.

[0089] Specifically, the first path set is traversed. For each path, the first node on the path is extracted as the initial node of the triggering event, reflecting the logical starting point or condition source of the event. The last node on the path is extracted as the termination node of the triggering event, reflecting the final output action of the event. All intermediate nodes traversed from the initial node to the termination node on the path are analyzed. The types and parameters of these nodes are integrated to generate a formal logical expression to describe the complete triggering condition. For example, if a path sequentially passes through node sensor A (high level), AND gate, and counter C (value >= 5), the generated triggering condition logical expression is: sensor A signal is true AND the current value of counter C is greater than or equal to 5. Each such logical expression is integrated with the action defined by its termination node to obtain a structured triggering event description. The set of all events constitutes the triggering event set. By deconstructing and abstracting the complex control logic, which originally existed in the form of a graphical topology, into a series of discrete and explicit triggering events, the complexity of subsequent steps involving fusion analysis with timing requirements can be reduced, and the modularity and maintainability of the control strategy generation process can be improved.

[0090] Furthermore, in response to user-inputted sequence diagram configuration commands, the timeline is parsed and the corresponding action time points are extracted to obtain a set of time points, including:

[0091] S401. In response to the timing diagram configuration command input by the user, the system scans the multi-channel time axis to identify the transition positions of level change points as the original event points and constructs the first event point sequence.

[0092] S402. Analyze the time corresponding to the event points in the first event point sequence, and merge the event points whose time difference between adjacent event points is less than a preset time difference threshold to obtain the second event point sequence.

[0093] S403. Analyze the time axis of each event point in the second event point sequence, select the event points that are synchronous in time as the synchronization group, extract the time points corresponding to the events in the synchronization group and the asynchronous group, and obtain the time point set.

[0094] In this embodiment, based on the timing diagram configuration instructions input by the user, which include a sequence of level states of multiple output channels on a unified time axis, a time axis scan is performed independently for each channel. A scan time step is determined based on the system's required time control precision and the FPGA's clock reference. For example, if the system needs to achieve microsecond-level control and the FPGA's main clock is 100MHz (i.e., a period of 10 nanoseconds), setting the scan time step to 100 nanoseconds ensures sufficient scan resolution and avoids excessive computational overhead. Starting from the beginning of the time axis, the scan progresses step by step at this time step. At each sampling moment, the theoretical level value of each channel at that moment is read and compared with the value at the previous sampling moment. Once a change in the level state of any channel is detected, such as a transition from low to high representing a relay closing instruction, or a transition from high to low representing a relay opening instruction, an initial event point is immediately recorded.

[0095] Specifically, the original event point records include timestamps, channel identifiers, and action types. After traversing all channels and the entire configured time range, the records are sorted in ascending order by timestamps to obtain a list containing all transition information for all channels, which serves as the first event point sequence. Through high-resolution automatic channel scanning and comparison, the user's timing diagram can be accurately analyzed, reducing errors from manual readings, improving the accuracy and reliability of the timing model, and enhancing the precision of timing control.

[0096] Specifically, the time difference threshold is set based on the timing accuracy and signal jitter resistance requirements of the target control system. For example, in industrial relay control scenarios, the mechanical action time of a relay is typically on the order of milliseconds, while the logic response of an FPGA is on the order of nanoseconds to microseconds. Therefore, the time difference threshold is set to 5 microseconds. The sequence of first event points is traversed, and the time difference between two adjacent event points in the sequence is calculated. Figure 2 As shown, if the difference is less than the preset time difference threshold, the two event points are merged to generate a new event point. The timestamp of the new event point can be the arithmetic mean of the timestamps of the two merged event points. The corresponding action list is the set of the action lists of the merged event points. For example, event point A requires channel 1 to close and event point B requires channel 2 to open. The merged event point requires both actions to be performed simultaneously.

[0097] It should be noted that by traversing the first event point sequence and merging the event points, a second event point sequence with fewer event points is obtained. This can effectively improve the robustness and practicality of the time series model, avoid generating overly complex time series constraints due to drawing errors, and make the generated strategy more consistent with the real situation of engineering implementation. This reduces the computational complexity of subsequent fusion and optimization algorithms and improves the overall processing efficiency.

[0098] Furthermore, based on the synchronization judgment tolerance analysis of the event synchronization status in the second event point sequence, the synchronization judgment tolerance is determined based on the clock network accuracy of the FPGA system and the hold time of the output register. For example, it is set to 1 microsecond, indicating that the timestamp difference of multiple event points is within 1 microsecond, and they are considered as synchronous events in the same clock cycle. All event points in the second event point sequence are analyzed in chronological order. The first event point in the second event point sequence is taken as an initial synchronization group. The next event point is checked sequentially, and the difference between its timestamp and the first event point in the current synchronization group is calculated. Event points with a difference less than or equal to the synchronization judgment tolerance are added to the current synchronization group. If the difference is greater than the tolerance, it indicates the start of a new time point, the current synchronization group is closed, and the next synchronization group is built starting from this new event point.

[0099] After traversal, all events within each synchronization group are considered to be occurring synchronously. For a group containing only a single event point, it represents an independent point in time. The group is represented by the median timestamp of all events within it, and each group is assigned a unique time point identifier. The time point set is composed of all time point identifiers and their corresponding action sets. By constructing a structured timing configuration, the moments of all key actions in the control flow and their accurate synchronization relationships can be determined. This provides accurate hard timing constraints for subsequent integration with logical events, ensuring that the final generated hardware control logic can achieve multi-channel synchronous output at the nanosecond to microsecond level. For collaborative operations requiring strict coordination, it can guarantee high precision and high reliability of complex control tasks from a timing perspective.

[0100] Furthermore, the relationship between triggering events and time points is analyzed, and the set of triggering events and the set of time points are dynamically linked to obtain a corresponding table, including:

[0101] S501. Analyze the semantic matching between the triggering conditions corresponding to the triggering events and the actions corresponding to the time points, match the set of triggering events and the set of time points to obtain the first link result;

[0102] S502. Based on the logical dependencies of events in the trigger event set, filter out the locations in the first link result where there are temporal causal conflicts and event resource conflicts, and obtain the set of conflict link points.

[0103] S503. Obtain the updated set of connection points by replacing the time points of the conflict connection point set or updating the time points of the conflict actions;

[0104] S504. Update and optimize the first link result according to the updated link point set to obtain the corresponding table.

[0105] In this embodiment, a semantic mapping dictionary is configured based on the association between the functional action descriptions used in the logic control block and the physical hardware output channels. The entries in the semantic mapping dictionary are predefined by the system according to the project hardware manifest. Each event in the trigger event set is traversed, and the corresponding field for the execution action is extracted. Simultaneously, each time point in the time point set is traversed, and the corresponding physical channel action list is obtained. For each pair (event E, time point T), the action description of event E is parsed into a set of specific physical channels and desired states by querying the semantic mapping dictionary. For example, starting the main pump channel is DO01, and the state is high. The parsing result is compared with the physical channel action list of time point T. If all channel actions required by event E can be found in the physical channel action list of time point T and the states are consistent, the matching degree is 100%. If there is only a partial match, it is calculated proportionally. If there is a state contradiction, the matching degree is 0.

[0106] Specifically, for each triggered event, all time points with a matching degree exceeding the minimum matching threshold are retained. The minimum matching threshold can be set according to the system's calculation accuracy requirements, such as 80%. The first link result is obtained, which is represented as a list that records each triggered event ID, one or more time point IDs that match it, and the corresponding matching degree score. Through automated preliminary matching based on predefined semantic rules, an initial association framework between logical intent and physical timing can be quickly constructed, reducing the workload of manually specifying the corresponding relationship. This provides a corresponding foundation for subsequent conflict analysis and optimization, and improves the startup efficiency and automation level of the fusion process.

[0107] Furthermore, based on the dependencies between events in the first linking result and the set of triggered events, the sequential dependencies between events are determined by analyzing the topology of the logic control block, thus obtaining the logical dependencies. For each pair of dependent events, the time points allocated in the first linking result are analyzed, and a timing tolerance threshold is set according to the system accuracy requirements. Events whose time point difference is less than or equal to the timing tolerance threshold are selected as events with timing causal conflicts. For each time point, the physical channel actions required by all triggered events linked to that time point are analyzed, and events in the same physical output channel that require them to be in different logical states at that time point are selected as events with event resource conflicts.

[0108] Specifically, all detected temporal causal conflicts and event resource conflicts are integrated to obtain a set of conflict link points, including conflict event ID, time point ID, and conflict type. By filtering temporal causal conflicts and event resource conflicts, deep logical contradictions and hardware resource competition problems can be accurately identified. Timing errors and driving conflicts are handled in the strategy generation stage, providing an accurate data foundation for generating safe and reliable control strategies and reducing the risk of field failures due to design defects.

[0109] Specifically, based on the set of conflicting link points, the set of time points, and the calculated matching degree information, for event resource conflicts, the candidate time points of the conflicting events are selected from the list of time points where the channel actions do not conflict with other events already linked to that point, and the time order of the replaced event and the original dependent events still satisfies the temporal causal constraint. For temporal causal conflicts, the time points of subsequent events are adjusted by adding Δt to the time of the subsequent events, making Δt greater than the temporal tolerance threshold. By replacing time points or updating time points for conflicting actions, a new linking scheme that eliminates all identified conflicts is obtained, which serves as the updated link point set. Through time replacement and time updates, a consistent and contradictory fusion scheme can be generated without deviating from the user's original design intent, improving the automation level, efficiency, and quality of the final result in the design of complex control strategies.

[0110] Specifically, the updated link point set determines the time point associated with each trigger event. Based on the updated link point set, the first link result is updated. Each instruction in the updated link point set is traversed; if the instruction indicates that the link time point of the trigger event needs to be changed from T_old to T_new, the corresponding record for the trigger event is found in the first link result, and its link time point ID is modified to T_new. After all updates are completed, the final first link result is organized, and invalid or duplicate records are removed to obtain a correspondence table. This correspondence table is a clearly structured data table, including the trigger event ID, trigger condition logic expression, link time point ID, time point timestamp, and a list of specific physical channel actions to be executed at that time point. Through dual-track fusion analysis, clear, conflict-free, and accurate correspondence results are obtained. The connection logic design, timing design, and final hardware implementation in the correspondence table provide direct and accurate input for generating specific hardware control strategies that can be loaded onto the FPGA, ensuring accurate and efficient conversion from design intent to implementation code.

[0111] like Figure 3 As shown, the parameter mapping mechanism includes:

[0112] S601. Based on the first control strategy, the corresponding logic functional units in the FPGA are parsed out as logic entities. The signal transmission between logic entities is analyzed to construct timing constraints, and a set of logic entities and a set of timing constraints are obtained.

[0113] S602. Based on the set of logical entities and the real-time resource status of the FPGA, allocate corresponding resource units to each logical entity to obtain the first allocation result;

[0114] S603. Combining the first allocation result and the set of timing constraints, simulate the propagation of the signal and perform timing analysis. By identifying and optimizing propagation paths whose propagation delay exceeds the timing constraints, a second allocation result is obtained.

[0115] S604. According to the second allocation result, the first set of parameters that can be executed by the FPGA is obtained through the preset parameter generation model.

[0116] In this embodiment, deep syntax and semantic analysis is performed on the first control strategy to identify atomic operations, state units, and data flows. For example, the description of waiting for the rising edge of the sensor signal in the first control strategy is parsed and mapped to an edge detector logic entity; the set flag when the temperature exceeds the threshold is mapped to a combined logic entity of a comparator and a set trigger. Integrating all these identified functional modules with clear hardware correspondences yields a set of logic entities. While parsing the functions, explicit or implicit timing requirements are extracted from the first control strategy and transformed into timing constraints for specific signal paths. The logic entities are treated as nodes in a graph, and the transmission of the output signal of one entity to the input of another entity is treated as directed edges, constructing a directed graph model. Each edge is assigned one or more timing attributes. For example, the path from the sensor input entity to the final relay drive entity is marked as having a maximum delay ≤ 100 microseconds. The output consists of a set of logic entities and a set of timing constraints.

[0117] It should be noted that by identifying logical entities and timing constraints, the automatic and accurate conversion from application-oriented control descriptions to circuit netlists and performance indicators for hardware synthesis is achieved. This provides accurate functional and performance specifications for the subsequent hardware implementation process, avoiding the problems of error-prone and inefficient manual translation in traditional methods, and ensuring that the design intent is correctly conveyed to the physical layer.

[0118] Specifically, the real-time resource status of the target FPGA chip is obtained through the configuration query interface provided by the FPGA manufacturer. This includes the bitmap of the occupied resources of all configurable logic blocks, block memory, digital signal processor chips, and routing resources, identifying occupied, protected, and free areas. For each entity in the set of logic entities, based on its type and scale requirements, a greedy placement algorithm based on connectivity and area is used to select a physical location that can accommodate it in the free area of ​​the resource bitmap. The greedy placement algorithm prioritizes placing input / output interface entities to the edge of the FPGA near the physical pins, and according to the tightness of the connections between logic entities, it sequentially places closely connected entities in adjacent or nearby physical areas of the resource bitmap to reduce the length of the initial routing. After finding and marking the specific row and column coordinates of the configurable logic block occupied by each entity, the first allocation result is obtained.

[0119] It should be noted that through automated initial resource allocation and layout, the corresponding chip physical space can be quickly matched, providing initial allocation results for subsequent timing-driven optimizations that require a large amount of computation. This avoids the optimization algorithm starting the search from completely random, which can shorten the time of the entire hardware mapping process and improve execution efficiency.

[0120] Specifically, based on the first allocation result and the timing constraint set, a built-in delay estimation model is invoked. This model integrates the target FPGA's process library data and a placement-based routing delay prediction algorithm. The routing delay prediction algorithm, combined with the Manhattan distance between logic entities, estimates the number of programmable switch nodes required to pass through, calculating the total time for a signal to travel from the source register, through combinational logic and interconnects, to the destination register. The delay estimation model is used to simulate and calculate the estimated propagation delay for each path in the timing constraint set. All paths whose estimated propagation delay exceeds the maximum delay value specified in the constraints are marked as critical paths. The logic entities associated with these critical paths are physically adjusted or repositioned on the resource map. For critical paths that cannot be completely resolved through placement, additional pipeline registers are inserted in the middle of the path, breaking down a long combinational logic segment into multiple clock cycles for optimization. This process continues until all paths satisfy the constraints, and the optimized final placement scheme is used as the second allocation result.

[0121] It should be noted that by using an automatic timing-driven optimization closed loop, the generated hardware logic not only functions correctly, but also reliably meets the high-speed response indicators set in the first control strategy in terms of running speed and response time. This transforms performance assurance from an uncontrollable factor that depends on the engineer's experience into a predictable and verifiable automated process, thereby achieving microsecond-level high-speed response.

[0122] Specifically, the second allocation result includes the precise physical location of each logical entity, configuration details of its internal logical functions, initial values ​​of registers, and interconnection relationships between entities via specific wiring switches and lines. The preset parameter generation model is a bitstream generator for FPGA series. The input of the model is the complete hardware configuration database described by the second allocation result, and the output is the first parameter set conforming to the manufacturer's format. During operation, it is based on the built-in mapping rule library. For example, the rule includes: if LUT 'A' in the SLICE located at coordinates (X,Y) is configured as function F=A&B, then the corresponding configuration memory address offset is Addr_Offset, and the data to be written is 0x8000. Here, A and B in the function represent two input signals of the lookup table LUT. In the configurable logic unit of the FPGA, a LUT has multiple input ports. For example, a 6-input LUT has 6 inputs from A1 to A6. When configuring this LUT to implement a specific two-input AND gate, two physical input ports are selected to carry the actual logic signals, and these two selected ports are identified as A and B in the configuration information. Which two physical input pins of the LUT A and B specifically correspond to are determined by the placement and routing results.

[0123] The parameter generation model traverses the entire hardware configuration database, applying corresponding rules to each logic unit and each wiring connection to calculate its absolute address in the FPGA configuration memory space and the value to be written, thus obtaining the first parameter set. By generating the corresponding parameters, the FPGA can be directly configured to possess predetermined high-speed control functions, completing a fully automated closed loop from user requirements to operable hardware, reducing the hardware development process and cycle.

[0124] Furthermore, the FPGA is configured according to the first parameter set, the active and spare areas of the FPGA are dynamically allocated, and the hardware logic circuit is initialized to obtain the first hardware logic circuit, including:

[0125] S701. Configure the FPGA according to the first parameter set, dynamically allocate the active area and spare area of ​​the FPGA, and generate area allocation instructions;

[0126] S702. Perform security verification and slice loading on the FPGA according to the area allocation instruction, and initialize the hardware logic circuit to obtain the first hardware logic circuit.

[0127] In this embodiment, the FPGA is configured according to the first parameter set, the active area and spare area of ​​the FPGA are dynamically allocated, and area allocation instructions are generated. It can dynamically and optimally adjust the spatial layout of hardware resources according to real-time task requirements without interrupting the overall operation of the system, support the online deployment, update and expansion of control functions, and improve the flexibility and resource utilization of the system.

[0128] Specifically, the FPGA is subjected to security verification and segmented loading according to the area allocation instructions, and the hardware logic circuit is initialized to obtain the first hardware logic circuit. Through security verification, the harm of untrusted or damaged firmware to the system can be avoided, and the system's anti-attack and anti-tampering capabilities can be improved. Through segmented loading and local initialization, function updates or deployments can be completed in milliseconds or even microseconds, with almost zero impact on other parts of the system. While ensuring the highest security, the system's availability, maintainability and rapid response capabilities are improved.

[0129] Furthermore, the FPGA is configured according to the first parameter set, the active and spare areas of the FPGA are dynamically allocated, and area allocation instructions are generated, including:

[0130] S801. Configure the FPGA according to the first parameter set and analyze the real-time resource usage of the FPGA;

[0131] S802. Based on the real-time resource occupancy status, dynamically allocate the active area and spare area of ​​the FPGA and generate area allocation instructions. The dynamic allocation process includes erasing the existing configuration of the occupied active area and updating it in real time, or selecting the corresponding area from the spare area for expansion.

[0132] In this embodiment, by calling the underlying hardware access interface or driver provided by the FPGA manufacturer, the mapping information of the FPGA's internal configuration memory and resource status register are read to generate a real-time resource occupancy bitmap. This bitmap uses the basic management units of the FPGA's reconfigurable region as a grid, with each grid cell recording its current state, such as idle or occupied by functional module A. Simultaneously, the first parameter set is parsed to extract the resource requirements necessary for the hardware implementation of the new control strategy, including the approximate number of lookup tables, the number of triggers, the size and number of block memories, and the number of dedicated digital signal processing units. The topological requirements of these resource requirements on the chip are analyzed, such as whether a continuous, roughly rectangular region is needed. The resource requirements are overlaid with the real-time resource occupancy bitmap for intensity analysis, calculating the idle region that can directly accommodate the new function and the occupied region that can be used after release. This real-time quantitative analysis of FPGA hardware resources provides accurate data support for the subsequent dynamic allocation process, avoiding resource allocation failures, system conflicts, or performance degradation caused by decisions based on outdated information or rough estimates, ensuring the reliability and efficiency of the reconfiguration process.

[0133] Specifically, based on real-time resource occupancy, a dynamic resource allocation decision algorithm analyzes the real-time resource occupancy bitmap, new function resource requirements, and topological constraints to output specific area allocation instructions. The dynamic resource allocation decision algorithm internally includes decision trees with multiple strategies, including: finding a continuous area in idle resources that best matches the required shape and size and designating it as the active area; when a new function is used to upgrade or replace an existing reconfigurable module, analyzing the feasibility of erasing the currently occupied area of ​​the module and directly using it as the new active area, requiring that the area can meet the new requirements in terms of resource type and quantity, and that the erasure operation will not cause other system parts dependent on the module to fail; when existing idle areas are insufficient, selecting an area from a preset reserve area resource pool and integrating it with adjacent scattered idle resources for expansion. The dynamic resource allocation decision algorithm analyzes the number of existing configurations to be erased for each strategy, the wiring distance between the new active area and related I / O or clock resources, and the degree of resource fragmentation generated after the operation, calculates the overall cost, selects the scheme with the lowest overall cost, and generates the corresponding area allocation instructions.

[0134] It should be noted that through dynamic regional allocation, new functional deployment requirements can be responded to flexibly and efficiently without global reset and reconfiguration, optimizing resource utilization. Through the update and standby area integration mechanism, the agility of hardware reconstruction and the online service capability of the system can be improved, providing key infrastructure support for building a smart hardware platform that can evolve over the long term and dynamically add or remove functions.

[0135] Furthermore, based on the region allocation instructions, the FPGA undergoes security verification and slice loading, and the hardware logic circuit is initialized to obtain the first hardware logic circuit, including:

[0136] S901. Perform security verification and slice loading on the FPGA according to the area allocation instruction, slice the active area and the spare area, and obtain the first configuration instruction;

[0137] S902. Initialize the hardware logic circuit according to the first configuration instruction to obtain the first hardware logic circuit.

[0138] In this embodiment, security checks are performed based on the physical boundaries defined by the region allocation instructions. A hash algorithm is used to verify the data integrity of the first parameter set. The system checks whether the configuration data includes a digital signature generated using the authorized party's private key. If the signature verification passes, it proves that the configuration data comes from a legitimate and authorized source, thus verifying the source authenticity. After passing data integrity checks and source authenticity verification, the system enters the fragment loading preparation stage. Based on the physical coordinates of the active area, the system queries the configuration memory address mapping table provided by the FPGA manufacturer. This table defines the start and end addresses of the configuration frames corresponding to each physical unit. The address range of all configuration frames covered by the active area is calculated. From the verified first parameter set, all configuration data whose addresses fall within this range are parsed and extracted to obtain independent configuration data fragments. These fragmented data, their corresponding target addresses, and the written control commands are packaged to generate a first configuration instruction that can be directly executed by the configuration controller.

[0139] It should be noted that the security verification mechanism, which integrates cryptographic methods, constructs a robust security defense for the online reconfiguration of FPGAs. This effectively reduces the risk of firmware tampering, replacement, or injection of malicious logic, thereby improving the system's security and reliability. The precise fragmentation mechanism based on physical addresses ensures accurate writing of the corresponding configuration data, guaranteeing the efficiency and locality of the reconfiguration process.

[0140] Specifically, the first configuration instruction is executed, and frame data from the configuration data slice is written sequentially through the FPGA's internal configuration access port. During the writing process, the FPGA's internal configuration manager automatically latches the data into the target active area, changing the connection relationships and logic functions of all programmable points within that area. After all data is loaded, the hardware logic circuit is initialized by writing a corresponding value to a predefined initialization control register dedicated to the newly configured active area through the internal configuration access port. This write operation is decoded in the FPGA's internal hardware, generating a local initialization pulse that is limited to the physical range of the active area and synchronized with the system master clock. This pulse is connected to the reset or set terminals of all timing elements within the area. According to the constraints defined at the time of design, this pulse forces all user flip-flops to their initial values ​​declared in the hardware description language source code; simultaneously, if an initialization file is specified in the configuration, the pulse also triggers the initialization logic of the block RAM, loading the preset data content into the RAM. The entire initialization process is automatically completed by the hardware logic within a few clock cycles, without software intervention. After the initialization pulse ends, the first hardware logic circuit reaches a defined initial operating point consistent with the simulation behavior, and can immediately respond to the input signal and perform logical operations and signal outputs according to the design specifications.

[0141] It should be noted that hardware initialization can activate hardware functions. Through partial initialization technology, specific functional modules within the FPGA can be independently powered on and started, avoiding service interruptions to other critical functions of the system caused by global reset. This improves the availability, service continuity, and maintainability of the system. The determined initialization state can ensure the predictability and reliability of circuit behavior after each reconfiguration, thereby improving the reliability of the control system operation.

[0142] like Figure 4 As shown, an intelligent relay response control system based on FPGA direct control pins is used to implement an intelligent relay response control method based on FPGA direct control pins, including:

[0143] The instruction parsing module responds to the logic control block configuration instructions and timing diagram configuration instructions input by the user in the vehicle scenario. It generates a first control strategy through dual-track fusion analysis. The dual-track fusion analysis includes parsing the trigger events in the logic control block and the time points in the timing diagram, and constructing a correspondence table between trigger events and time points.

[0144] The parameter mapping module configures the parameter mapping mechanism, mapping the first control strategy to the first set of parameters executed by the FPGA;

[0145] The region allocation module configures the FPGA according to the first parameter set, dynamically allocates the active area and spare area of ​​the FPGA, and initializes the hardware logic circuit to obtain the first hardware logic circuit.

[0146] The relay response module combines the input signals, sensor data, and synchronization bus signals acquired in real time by the FPGA, generates control signals for the corresponding relays according to the first hardware logic circuit, and controls the relays to respond to the intelligent relays.

[0147] In this embodiment, the instruction parsing module receives and processes instructions input by the user through the graphical interface. Using core dual-track fusion analysis technology, it integrates the instructions into a unified, coordinated, and conflict-free first control strategy. It parses the logical topology to extract trigger events and scans the timeline to extract time points. Through intelligent matching, conflict detection, and optimization, it constructs a mapping table between events and time points, achieving visualized and automated collaborative design of control logic and timing requirements. This improves the design efficiency, first-time accuracy, and internal consistency of complex control strategies, ensuring the feasibility and security of the strategy from the source. The parameter mapping module automatically converts the first control strategy into a set of hardware configuration parameters that can be executed on the target FPGA chip through a built-in parameter mapping mechanism. It performs a series of compilation and synthesis operations, from logical entity identification, timing constraint construction, resource allocation and layout planning to timing-driven optimization, greatly shortening the development cycle and ensuring that the generated hardware logic is fully optimized in terms of timing and performance, reliably meeting the design requirements for high-speed response.

[0148] Specifically, the area allocation module allocates FPGA physical resources based on the hardware requirements output by the parameter mapping module, dynamically plans the active area for carrying the current logic and the spare area for future expansion or backup, and completes the security verification of configuration data, slice loading and circuit initialization, realizing dynamic partitioning and partial reconfiguration of FPGA resources. Specific control functions can be dynamically deployed, updated or replaced without interrupting the overall system operation. At the same time, the spare area mechanism provides a hardware foundation for function expansion and fault redundancy, improving the flexibility, maintainability and high availability of the entire control system. The relay response module uses the first hardware logic circuit deployed in the FPGA active area as a dedicated hardware control engine. It processes input signals from external pins, sensors, and communication buses in real time, and directly drives the FPGA's I / O pins to generate control signals at precise moments according to the circuit logic, thereby operating the intelligent relay. It fully utilizes the hardware parallelism and pin direct control capability of the FPGA to achieve microsecond-level or even better deterministic high-speed response. It can eliminate the operating system scheduling and task switching delays in traditional software control architectures, and has extremely high real-time performance and reliability. It can achieve nanosecond-level precise synchronous control between multiple channels, meeting the stringent requirements of high-end industrial applications for instantaneous action and precise timing.

[0149] Example 2:

[0150] This embodiment describes the overall process of the technical solution using window coordination and door interlocking control in a vehicle-mounted scenario as a specific application scenario. The vehicle-mounted scenario includes window A, window B, and one door. The control requirements include: when the start button is pressed and the door closing sensor signal is valid, the system starts; after starting, window A immediately closes (relay KA1 is activated); after rising to the correct position (indicated by the window A position sensor), after a 10-millisecond delay, window B begins to close (relay KA2 is activated); at the same time window B begins to close, the door must be locked immediately (relay KLOCK is activated); the entire action sequence must respond to the trigger event within 200 microseconds.

[0151] Specifically, users design the system through the graphical interface of the configuration software. In the logic control block editing area, users define the control logic by dragging and dropping nodes and connections. Nodes include: input nodes: start button (PB_START), door closing sensor (SENSOR_DOOR), window A position sensor (SENSOR_A_IN); logic operation nodes: AND gate (AND1), rising edge detection (EDGE1); output action nodes: start system (SYS_ON), ​​raise window A (ACTION_A_OUT), raise window B (ACTION_B_ROTATE), lock door (ACTION_LOCK). Connections are defined as follows: PB_START and SENSOR_DOOR are inputs to AND1; the output of AND1 is connected to EDGE1; the output of EDGE1 is connected to SYS_ON; SYS_ON is connected to ACTION_A_OUT; SENSOR_A_IN is connected to ACTION_B_ROTATE; and ACTION_B_ROTATE is directly connected to ACTION_LOCK. After the logical topology is parsed by the system, the key triggering event set extracted includes: Event E1 (triggering condition: PB_START is true and SENSOR_DOOR is true, detect rising edge; action: start system SYS_ON and raise window A on the subsequent link); Event E2 (triggering condition: SENSOR_A_IN is true; action: raise window B); Event E3 (triggering condition: receive command to raise window B; action: lock door).

[0152] In the timing diagram editing area, the user drew waveforms for the output channels (relays KA1, KA2, and KLOCK). The requirements are: at time T0, corresponding to the system response start point, KA1 immediately becomes high (closed); at time T0+10ms, KA2 becomes high (closed); and at the same moment KA2 closes, with a time difference of less than 1 microsecond, KLOCK must also become high (closed). The system, through scanning and parsing, merges adjacent event points to obtain the following time point set: time point T1 (absolute time 0, corresponding action: {KA1: closed}); time point T2 (absolute time 10 milliseconds, corresponding actions: {KA2: closed, KLOCK: closed}).

[0153] Specifically, the instruction parsing module initiates dual-track fusion analysis, performing semantic matching. It matches the action of raising window A in event E1 with the action KA1 at time T1, matches the action of raising window B in event E2 with the action KA2 at time T2, and matches the action of locking the door in event E3 with the action KLOCK at time T2, obtaining the first link result. Simultaneously, conflict detection analysis is performed. Logically, event E2 (raising window B) depends on the completion of event E1 (raising window A), indicated by the window A positioning sensor SENSOR_A_IN. Therefore, time T2 corresponding to event E2 must be later than time T1 corresponding to event E1. This condition is satisfied (10ms > 0). At time T2, KA2 and KLOCK are required to act simultaneously by different events (E2 and E3), but they are on different channels and do not constitute a resource conflict. Therefore, no temporal causal conflict or event resource conflict was found. A correspondence table is generated: E1→T1; E2→T2; E3→T2. The first control strategy generated based on this table is as follows: when the start-up conditions are met, KA1 is immediately closed at time T0; when the window A position signal is valid, KA2 and KLOCK are closed simultaneously at time T0+10ms.

[0154] Correspondingly, the parameter mapping module receives the strategy, parses the functions such as start condition judgment, 10ms delay, and simultaneous output control into corresponding logical entities, including comparators, counters, and multiplexed output drivers, and sets a timing constraint that the total delay from the input event trigger to the KA2 / KLOCK action must not exceed 200 microseconds. The parameter analysis module analyzes the FPGA, such as the real-time resources of a Xilinx Artix-7 XC7A50T, finds an empty area that can accommodate the required logic, performs layout, places the relevant logic entities in the area, and ensures through timing analysis that the critical path, i.e., the delay from the sensor signal input to the counter enable, meets the constraint, and generates a first parameter set containing all lookup table configurations, wiring connections, and timer initial values ​​(the number of clock cycles corresponding to 10ms) for that area.

[0155] Specifically, the region allocation module reads the first parameter set and queries the FPGA's current resource occupancy map. It finds that the logic size specified by the first parameter set is relatively small, while a sufficiently large contiguous free area exists on the FPGA, for example, a rectangular area from CLB coordinates (X10, Y10) to (X15, Y20). This entire area is designated as the active region, and a region allocation instruction is generated, including: the active region boundary coordinates (X10, Y10) to (X15, Y20); the operation type is new configuration; security verification and fragment loading are performed on the active region; the hash value of the first parameter set is calculated and compared with a trusted value to verify the signature; after successful verification, based on the physical address of the active region, configuration data fragments specific to the area at coordinates (X10, Y10) to (X15, Y20) are extracted from the complete bitstream; this fragmented data is accurately written into the configuration memory of the target region via the FPGA's ICAP interface. After writing, the module sends a local initialization pulse to the active region. The pulse resets all flip-flops in the area, clears the 10ms delay counter, and sets the output control register to the default off state. The first hardware logic circuit is then initialized in the designated area of ​​the FPGA.

[0156] Specifically, the relay response module enters the working state, and the FPGA pins monitor the levels of the start button (PB_START), the safety door sensor (SENSOR_DOOR), and the window A positioning sensor (SENSOR_A_IN) in real time. When the operator presses the start button and the safety door is closed, the first hardware logic circuit inside the FPGA immediately detects that the condition of event E1 is met. Within the same clock cycle, for example, if the system clock is 100MHz, the hardware logic makes a judgment within a 10ns cycle and immediately drives the pin corresponding to KA1 to output a high level at time T0 (actually the next clock edge after detection), and window A begins to rise. When window A triggers the positioning sensor, the SENSOR_A_IN signal changes, and the timer in the hardware logic starts counting with 10ns as the reference. When the count value reaches the number of clock cycles corresponding to 10 milliseconds (1,000,000 cycles), the hardware logic synchronously drives the two pins corresponding to KA2 and KLOCK to output a high level at time T2 (i.e., the same clock edge when the counter is full), controlling window B to rise and simultaneously locking the door. The delay from the activation of SENSOR_A_IN to the action of KA2 / KLOCK is only the inherent hardware counting time of the counter (10ms) plus a very small pin output delay (nanosecond level), which fully meets the fast response requirement within 200 microseconds, and KA2 and KLOCK achieve microsecond-level precise synchronization.

[0157] Through the complete process demonstration of the above embodiments, those skilled in the art can clearly understand how the present invention transforms logic and timing design into parallel, deterministic hardware circuits within the FPGA through automated dual-track fusion, parameter mapping, and dynamic hardware resource configuration, thereby achieving microsecond-level high-speed, high-precision synchronous control of the relay system.

[0158] The above description is merely a preferred embodiment of this application. The scope of protection of this application is not limited to the above embodiments. All technical solutions falling within the scope of this application's concept are within the scope of protection of this application. It should be noted that for those skilled in the art, any improvements and modifications made without departing from the principles of this application should also be considered within the scope of protection of this application.

Claims

1. A smart relay response control method based on FPGA direct control pins, characterized in that, include: In response to the logic control block configuration command and timing diagram configuration command input by the user in the vehicle scenario, a first control strategy is generated through dual-track fusion analysis. The dual-track fusion analysis includes parsing the trigger events in the logic control block and the time points in the timing diagram, and constructing a correspondence table between trigger events and time points. Configure a parameter mapping mechanism to map the first control strategy to the first set of parameters executed by the FPGA; Configure the FPGA according to the first parameter set, dynamically allocate the active area and spare area of ​​the FPGA, and initialize the hardware logic circuit to obtain the first hardware logic circuit. By combining the input signals, sensor data, and synchronization bus signals acquired in real time by the FPGA, the control signals of the corresponding relays are generated according to the first hardware logic circuit, and the actions of the relays are controlled to respond to the intelligent relays.

2. The intelligent relay response control method based on FPGA direct control pins according to claim 1, characterized in that, The logic control block configuration instructions and timing diagram configuration instructions, which respond to user input in the vehicle scenario, generate a first control strategy through dual-track fusion analysis, including: In response to the logic control block configuration command input by the user in the vehicle scenario, the set of trigger events is obtained by parsing the logic topology and extracting the corresponding trigger events. The logic control block configuration command defines the trigger conditions, logical operations and state transition relationships through nodes and connections. In response to the timing diagram configuration command input by the user, the time point set is obtained by parsing the time axis and extracting the time points of the corresponding actions. The timing diagram configuration command includes the level change points and timing relationships of the relay output channel. Analyze the relationship between triggering events and time points, and dynamically link the set of triggering events and the set of time points to obtain a corresponding table; The event time sequence and time parameters are generated according to the corresponding table to obtain the first control strategy.

3. The intelligent relay response control method based on FPGA direct control pins according to claim 2, characterized in that, The logic control block configuration command in response to user input in the vehicle scenario is obtained by parsing the logic topology and extracting the corresponding trigger events, resulting in a set of trigger events, including: In response to user input of logic control block configuration commands in vehicle scenarios, nodes and connections are parsed, and the set of labeled nodes and the set of directed edges are obtained through semantic annotation and directed edge analysis. Based on the set of labeled nodes and the set of directed edges, the transmission paths between labeled nodes are identified according to the directed edges, and a first path set is constructed. Extract the initial node and the termination node from the first path set, construct the corresponding trigger events, and obtain the trigger event set.

4. The intelligent relay response control method based on FPGA direct control pins according to claim 3, characterized in that, The sequence diagram configuration command, in response to user input, parses the timeline and extracts the time points of the corresponding actions to obtain a set of time points, including: In response to the timing diagram configuration command input by the user, the system scans the multi-channel time axis to identify the transition positions of level change points as the original event points and constructs the first event point sequence. Analyze the time corresponding to the event points in the first event point sequence, and merge the event points whose time difference between adjacent event points is less than a preset time difference threshold to obtain the second event point sequence; Analyze the timeline of each event point in the second event point sequence, select the event points that are synchronous in time as the synchronization group, and extract the time points corresponding to the events in the synchronization group and the asynchronous group to obtain the time point set.

5. The intelligent relay response control method based on FPGA direct control pins according to claim 4, characterized in that, The analysis of the correlation between triggering events and time points involves dynamically linking the set of triggering events and the set of time points to obtain a corresponding table, including: Analyze the semantic matching between the triggering conditions corresponding to the triggering events and the actions corresponding to the time points, match the set of triggering events and the set of time points to obtain the first link result; Based on the logical dependencies of events in the trigger event set, the locations in the first link result that have temporal causal conflicts and event resource conflicts are filtered out to obtain the set of conflict link points; The updated set of connection points is obtained by replacing the time points of the conflict connection point set or updating the time points of the conflict actions; The first link result is updated and optimized based on the updated link point set to obtain the corresponding table.

6. The intelligent relay response control method based on FPGA direct control pins according to claim 1, characterized in that, The parameter mapping mechanism includes: Based on the first control strategy, the corresponding logic functional units in the FPGA are parsed out as logic entities. The signal transmission between logic entities is analyzed to construct timing constraints, and a set of logic entities and a set of timing constraints are obtained. Based on the set of logical entities and the real-time resource status of the FPGA, a corresponding resource unit is allocated to each logical entity to obtain the first allocation result; Combining the first allocation result and the set of timing constraints, the propagation of the signal is simulated and timing analysis is performed. By identifying and optimizing propagation paths whose propagation delay exceeds the timing constraints, a second allocation result is obtained. Based on the second allocation result, the first set of parameters for FPGA execution is obtained through a preset parameter generation model.

7. The intelligent relay response control method based on FPGA direct control pins according to claim 1, characterized in that, The first hardware logic circuit is obtained by configuring the FPGA according to the first parameter set, dynamically allocating the active and spare areas of the FPGA, and initializing the hardware logic circuit, including: Configure the FPGA according to the first parameter set, dynamically allocate the active and spare areas of the FPGA, and generate area allocation instructions; The FPGA is subjected to security verification and slice loading according to the area allocation instructions, and the hardware logic circuit is initialized to obtain the first hardware logic circuit.

8. The intelligent relay response control method based on FPGA direct control pins according to claim 7, characterized in that, The process of configuring the FPGA according to the first parameter set, dynamically allocating the active and spare areas of the FPGA, and generating area allocation instructions includes: Configure the FPGA according to the first parameter set and analyze the real-time resource usage of the FPGA; Based on the real-time resource occupancy, the active area and spare area of ​​the FPGA are dynamically allocated, and area allocation instructions are generated. The dynamic allocation process includes erasing the existing configuration of the occupied active area and updating it in real time, or selecting the corresponding area from the spare area for expansion.

9. The intelligent relay response control method based on FPGA direct control pins according to claim 8, characterized in that, The first hardware logic circuit, obtained by performing security verification and slice loading on the FPGA according to the region allocation instruction and initializing the hardware logic circuit, includes: The FPGA is subjected to security verification and slice loading according to the area allocation instructions. The active area and the spare area are sliced ​​to obtain the first configuration instructions. The hardware logic circuit is initialized according to the first configuration instruction to obtain the first hardware logic circuit.

10. An intelligent relay response control system based on FPGA direct control pins, characterized in that, The method for implementing the intelligent relay response control method based on FPGA direct control pins as described in any one of claims 1 to 9 includes: The instruction parsing module responds to the logic control block configuration instructions and timing diagram configuration instructions input by the user in the vehicle scenario. It generates a first control strategy through dual-track fusion analysis. The dual-track fusion analysis includes parsing the trigger events in the logic control block and the time points in the timing diagram, and constructing a correspondence table between trigger events and time points. The parameter mapping module configures the parameter mapping mechanism, mapping the first control strategy to the first set of parameters executed by the FPGA; The region allocation module configures the FPGA according to the first parameter set, dynamically allocates the active area and spare area of ​​the FPGA, and initializes the hardware logic circuit to obtain the first hardware logic circuit. The relay response module combines the input signals, sensor data, and synchronization bus signals acquired in real time by the FPGA, generates control signals for the corresponding relays according to the first hardware logic circuit, and controls the relays to respond to the intelligent relays.

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