Digital audio and video integrated stage scheduling intelligent control system

Abstract

The present application relates to the technical field of stage equipment cooperative control, in particular to a digital audio-video integrated stage scheduling intelligent control system, which comprises a synchronization label generated by aligning equipment clock through a time sequence module, a mapping list outputted by an adaptive module to process heterogeneous protocols, a logic issued by a verification module to reconstruct deviation instructions, a recovery module to identify scheduling exceptions to trigger redundant switching and record, and a grouping module to group cooperative equipment, rearrange paths, and integrate into the cloud for unified scheduling. The present application constructs a unified time reference by synthesizing multi-source clocks and frame-level features, refines synchronization identification, matches heterogeneous message structures and semantic differences to form tolerance correspondence to enhance instruction consistency, dynamically shunts sequences according to execution deviation distribution to correct high-deviation objects to maintain low-deviation operation, drives link switching and cooperative replacement scheduling based on exception records to rearrange instruction sequences, groups and reorganizes trajectory overlapping equipment cooperation, integrates into scheduling to improve closed-loop stability.

Description

Technical Field

[0001] This invention relates to the field of stage equipment collaborative control technology, and in particular to a digital audio-visual integrated stage scheduling intelligent control system. Background Technology

[0002] With the rapid development of performing arts technology, stage equipment collaborative control technology has become a core support for modern theaters and large-scale performances. Current stage scheduling involves the linkage of lighting, audio, video, and complex stage machinery, with its core being the high-precision collaborative operation of multiple types of equipment on the same timeline. However, existing digital stage scheduling systems still have many areas for optimization in terms of multi-protocol adaptation, multi-device status feedback verification, and time-sequence consistency management in complex scenarios. A search revealed a digital audio-visual integrated stage scheduling system with publication number CN105657217A. Through the interconnection of camera devices, host computers, and multimedia mobile terminals, it achieves video transcoding, terminal registration, and call scheduling management, demonstrating certain advantages in the technical integration and basic scheduling of centralized control systems. However, this technical solution primarily focuses on the scheduling of audio and video information transmission and communication. When facing stage machinery action sequences and video screen switching linkages requiring microsecond-level synchronization, the lack of a unified time reference driving mechanism leaves room for improvement in ensuring the consistency of action pace among multiple systems. In addition, the system's ability to dynamically adapt to control protocols across different industries is limited, which has a certain impact on its deep integration in cross-brand and multi-type equipment environments.

[0003] On the other hand, a digital audio-visual integrated stage scheduling device with publication number CN109005384A was disclosed. This device aims to control digital stage effects by establishing high-performance client interconnection and utilizing a host as the core for scheduling functions. However, in practical applications, the construction of a closed loop for multi-device status acquisition and feedback verification is still imperfect. Real-time comparison of the execution status of stage equipment (such as lifts and dimming consoles) and correction of command retransmissions still need improvement. Furthermore, the system's description of priority management of signal flow paths and automatic recovery processes under abnormal conditions is relatively simplistic. When facing complex scheduling scenarios with large-scale, high-concurrency command issuance, the system's stability and fault tolerance still have potential for improvement in meeting the high standards of professional performances.

[0004] The above indicates that existing digital audio-visual integrated stage scheduling systems still have room for improvement in terms of collaborative accuracy, closed-loop control mechanisms, protocol integration depth, and high system reliability. Therefore, this invention provides a digital audio-visual integrated stage scheduling intelligent control system, aiming to enhance the deep intelligent linkage and precise scheduling level of audio, video, lighting, and stage machinery by establishing a unified time base, optimizing control protocol adaptation, and improving multi-device status feedback mechanisms. This better meets the demands of modern performing arts for efficient, intelligent, and stable stage control systems. Summary of the Invention

[0005] The purpose of this invention is to overcome the shortcomings of existing technologies and propose a digital audio-visual integrated stage scheduling intelligent control system.

[0006] To achieve the above objectives, the present invention adopts the following technical solution: a digital audio-visual integrated stage scheduling intelligent control system, the system comprising: The timing reference synchronization module acquires the pulse signal of the main control clock source, the frame synchronization characteristics of the audio and video streams, and the sampling clock of the mechanical actuator. It extracts the phase deviation, drift rate, and timing offset, completes the clock alignment of all system devices according to the time axis sequence, defines the device synchronization level based on the alignment results, and generates timing reference synchronization tags. The protocol dynamic adaptation module calls the timing reference synchronization tag to process the message frame structure, baud rate parameters and semantic layers of different controlled terminals, judges the response delay of heterogeneous protocols to instruction parsing, evaluates the impact of cross-platform communication on real-time scheduling, matches protocol conversion tolerance, and outputs a protocol adaptation mapping list. The state closed-loop verification module calls the device task relationship in the protocol adaptation mapping list, adjusts the high deviation device to the correction sequence according to the deviation distribution between the actuator readback data and the preset target instruction, keeps the low deviation device executing, reconstructs the instruction issuance logic, and outputs the state feedback verification distribution map. The fault-tolerant scheduling recovery module reads the instruction execution records in the status feedback verification distribution diagram, identifies signal blocking, feedback timeout and logic conflict situations, triggers redundant link switching requests, broadcasts to nearby controlled terminals, records feedback and identifies and confirms alternative scheduling objects, and generates a scheduling anomaly recovery assignment record after completing instruction rearrangement.

[0007] As a further embodiment of the present invention, the timing reference synchronization tag includes a clock source identifier, a synchronization accuracy level, and timing compensation parameters; the protocol adaptation mapping list includes protocol conversion coefficients, communication link indicators, and instruction parsing delay tolerance; the status feedback verification distribution map includes real-time deviation blocks, instruction correction bands, and closed-loop execution parameters; and the scheduling anomaly recovery assignment record includes a recovery instruction number, a redundancy takeover identifier, and a feedback confirmation time stamp.

[0008] As a further aspect of the present invention, the operation of the timing reference synchronization module includes: The physical layer clock extraction submodule acquires the original pulse records of the master clock source in the digital communication link, divides the continuous sampling segments according to the preset time window, identifies the arrangement pattern of the rising and falling edges of the pulses in the segments, filters them according to the number of jitters and frequency drift of the pulse period, marks the recording segments with clock characteristic fluctuations, and generates clock abnormal segment labeling results. The phase deviation correction submodule, based on the time segment corresponding to the clock abnormal segment annotation result, calls the frame synchronization signal of the audio and video acquisition terminal in the same segment recording, sorts out the alignment rhythm between the video frame start position and the audio sampling point, filters out the segments that have phase shift or sampling loss at the same time as the clock abnormal segment, summarizes them to form a chain of abnormal behavior of timing reaction, and generates a set of timing deviation related segments. The synchronization tag generation submodule calls the set of time deviation associated segments and the clock abnormal segment annotation results, compares the time identifier of the interruption point recorded in the sampling log of the stage machinery actuator, screens the time intersection in the three-dimensional records, identifies the device number with multiple synchronization abnormalities, and classifies the time deviation combination according to the preset synchronization availability standard to generate time reference synchronization tags.

[0009] As a further aspect of the present invention, the protocol dynamic adaptation module includes: The protocol feature identification submodule obtains the message flow records of the link where the device to be scheduled is located. Based on the frame header features and physical layer level characteristics marked on each message, it calls the description content related to the control protocol in the device attribute tag of the corresponding device, establishes the mapping relationship between message features and protocol type, matches according to the combination of message structure complexity level and computational overhead in protocol parsing algorithm, marks the parsing delay impact fragments and organizes their corresponding device numbers, and generates protocol adaptation interference matching results. The semantic conversion mapping submodule calls the device number involved in the protocol adaptation interference matching result, obtains the communication status label of the device in the instruction segment on the task target path, and identifies the intersection range of instruction definition mismatch nodes and control logic conflict points by comparing the semantic definition layers of different brands of devices in the global device library. It sorts and classifies the set of conversion nodes with dual restrictions in the instruction flow and generates a list of protocol restriction node distribution. The adaptation list generation submodule obtains the response time level content in the synchronization tag of each device number corresponding to each node in the protocol-restricted node distribution list, and filters out the device numbers and corresponding task names that can operate within the conversion delay tolerance range by comparing them with the action coordination accuracy requirements set in the task. It then maps the instruction numbers and executable devices one by one to generate a protocol adaptation mapping list.

[0010] As a further aspect of the present invention, the matching based on the combination of message structure complexity level and computational overhead in the protocol parsing algorithm specifically involves: comparing the real-time payload length data and real-time check bit computational overhead in the message stream with the preset processor computing power threshold and memory usage threshold in the protocol attributes; when the real-time payload length data exceeds the computing power threshold or the real-time check bit computational overhead exceeds the memory usage threshold, the matching is completed. The identification instruction definition mismatch node is specifically: the instruction node recorded in the communication status label with an instruction parsing packet loss rate higher than a preset parsing packet loss rate threshold or a semantic mapping delay higher than a preset mapping delay threshold is identified as an instruction definition mismatch node; The identification instruction defines the intersection range of mismatched nodes and control logic conflict points. Specifically, taking each logic conflict point in the semantic definition layer as the logic center, a dynamic logic buffer area is calculated and generated based on the instruction length, maximum response speed, and shortest processing cycle data of the device executing the scheduling task. The instruction definition mismatched nodes falling into the dynamic logic buffer area are determined as nodes within the intersection range.

[0011] As a further aspect of the present invention, the operation of the state closed-loop verification module includes: The execution deviation extraction submodule calls the instruction and device combination information in the protocol adaptation mapping list to obtain the continuous execution feedback records of each execution terminal. According to the continuous repetition frequency and time sequence of the position / status data in the feedback records, the execution segments with close action connections are marked, and the combinations with deviation jumps between execution segments are numbered and grouped to establish the device execution deviation level sorting and generate the execution deviation level distribution results. The instruction correction association submodule extracts the target value data such as spatial position / brightness / gain of the current corresponding instruction based on the device number in the execution deviation level distribution result. According to the feedback deviation area of ​​the instruction number and the classification rules of the correction algorithm, it forms a combination structure with the high deviation level device and the correction instruction retransmission sequence. At the same time, it marks the degree of deviation between the instruction corresponding to the low deviation level device and the high precision area in terms of execution accuracy, and generates a device instruction correction matching combination list. The verification layer update submodule calls the scheduling mapping information in the device instruction correction matching combination list, redirects high deviation level devices to correction instruction path nodes, repositions low deviation level devices to regular scheduling path nodes, and updates the mapping of adjustment paths for all instruction numbers on the execution trajectory, completing the latest correspondence between instruction numbers and device numbers in all regions, and generating a status feedback verification distribution map.

[0012] As a further aspect of the present invention, the fault-tolerant scheduling recovery module includes: The blocking identification submodule reads the task execution process of each controlled terminal in the status feedback verification distribution map, extracts the instruction blocking signal, feedback imbalance behavior and communication interruption record in the task stage in chronological order, sorts them according to the order in which the records appear, determines whether there are two or more consecutive abnormal tag combinations, marks the corresponding instruction number and device number, and generates an abnormal combination instruction label table. The response feedback recording submodule collects the scheduling tags of other redundant controlled terminals in the same scheduling area according to the instruction number of the marked device in the abnormal combination instruction label table, broadcasts takeover requests to these terminals and records the feedback content, extracts the acceptance field and reception time from the feedback response, identifies the device number that has confirmed the takeover intention and sorts them in ascending order of response time, and generates instruction takeover response sorting results. The recovery instruction generation submodule calls the first response device number and corresponding instruction number in the instruction takeover response sorting result, updates the execution device field of the instruction in the status feedback verification distribution diagram, records the target instruction for replacement takeover and the adjustment node of the takeover device in the scheduling configuration, summarizes all instruction information that has been replaced, and generates a scheduling anomaly recovery assignment record.

[0013] As a further aspect of the present invention, the extraction of the instruction blocking signal during the task phase specifically involves: comparing the sequence of instructions sent by the device with the sequence of confirmation receipts fed back by the receiving end in real time; and generating an instruction blocking signal when the missing rate of the confirmation receipt sequence is continuously greater than a first blocking threshold within a preset sliding window. The feedback imbalance behavior during the task extraction phase is specifically as follows: obtain the current execution current of the controlled terminal and calculate the energy consumption change rate. When the energy consumption change rate is continuously higher than the expected energy consumption rate generated based on action planning and load data, and the difference between the two exceeds the preset energy consumption deviation threshold, feedback imbalance behavior is generated. The process of extracting communication interruption records during the task phase specifically involves: determining whether the network heartbeat packets between the controlled terminal and the scheduling host are received within a second preset time period; and generating a communication interruption record if the number of consecutively lost network heartbeat packets exceeds a preset packet loss threshold.

[0014] As a further aspect of the present invention, the system further includes: The equipment collaboration grouping module reads the scheduling anomaly recovery assignment record, screens overlapping action trajectories and scheduling synchronization records, identifies collaborative characteristic equipment and groups it, rearranges its action paths and sequences, integrates them into the cloud for unified scheduling, and outputs a stage equipment collaboration grouping structure diagram. The stage equipment collaborative grouping structure diagram includes collaborative operation group numbers, action overlap measurement indicators, and joint scheduling time axis.

[0015] As a further aspect of the present invention, the device cooperative grouping module includes: The trajectory integration submodule reads the access order and corresponding action trajectory of each instruction execution device in the scheduling anomaly recovery assignment record, extracts the frequency of occurrence of device instruction numbers, overlapping location points and time segments of scheduling areas in the action path, sorts out the number of access times of each device instruction and the number of path intersection nodes, and summarizes the device numbers within the same time period of scheduling time to generate a list of action trajectory intersection features. The collaborative screening module determines whether it simultaneously possesses the characteristics of multiple instruction overlap records and scheduling time overlap based on the device number and path overlap number recorded in the action trajectory intersection feature list. It then groups and classifies the device numbers that meet the conditions, marks them as grouping objects, and establishes a corresponding instruction number set structure for each group to generate a collaborative grouping structure for device instructions. The scheduling and reconfiguration submodule calls the instruction set corresponding to each group in the device instruction collaborative grouping structure, reorders the instruction numbers in each group according to the original execution order, and uniformly specifies the corresponding execution device number as the scheduling entry point in the sorting structure. It updates the order of the corresponding instruction nodes in the platform scheduling arrangement structure and maps the updated content to the regional task distribution layer to generate a stage equipment collaborative grouping structure diagram.

[0016] Compared with the prior art, the advantages and positive effects of the present invention are as follows: In this invention, a unified time reference is constructed by integrating multi-source clock signals and extracting phase and drift parameters from frame-level features, and the synchronization level identifier is refined. Cross-protocol instruction consistency is enhanced by matching heterogeneous message structures and semantic differences to evaluate and resolve latency and form a tolerance correspondence. Targeted correction is implemented for objects with concentrated deviations and low-device objects are maintained in continuous operation by dynamically diverting control sequences based on the deviation distribution of execution readback and target instructions. Alternative scheduling and instruction sequence rearrangement are completed by driving link switching and neighborhood collaboration through anomaly recording. The degree of multi-device action coordination and feedback loop stability are improved by collaboratively grouping and reorganizing overlapping trajectory devices and uniformly merging them into the scheduling sequence. Attached Figure Description

[0017] Figure 1 This is a flowchart illustrating the overall system flow of the present invention. Figure 2 This is a flowchart of the system modules of the present invention. Detailed Implementation

[0018] The technical solution of the present invention will now be described with reference to the accompanying drawings.

[0019] In embodiments of the present invention, words such as "exemplarily," "for example," etc., are used to indicate that something is an example, illustration, or description. Any embodiment or design described as "exemplary" in the present invention should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of the word "exemplary" is intended to present the concept in a concrete manner. Furthermore, in embodiments of the present invention, the meaning expressed by "and / or" can be both, or either one.

[0020] In the embodiments of this invention, the terms "image" and "picture" may sometimes be used interchangeably. It should be noted that, without emphasizing the distinction between them, they convey the same meaning. Similarly, the terms "of," "corresponding (relevant)," and "corresponding" may sometimes be used interchangeably. It should be noted that, without emphasizing the distinction between them, they convey the same meaning.

[0021] In this embodiment of the invention, sometimes a subscript such as W1 may be written in a non-subscript form such as W1. When the difference is not emphasized, the meaning they express is the same.

[0022] To make the technical problems, technical solutions and advantages of the present invention clearer, a detailed description will be given below in conjunction with the accompanying drawings and specific embodiments.

[0023] Please see Figure 1 This invention provides a technical solution: a digital audio-visual integrated stage scheduling intelligent control system, the system comprising: The timing reference synchronization module acquires the pulse signal of the main control clock source, the frame synchronization characteristics of the audio and video streams, and the sampling clock of the mechanical actuator. It extracts the phase deviation, drift rate, and timing offset, completes the clock alignment of all system devices according to the time axis sequence, defines the device synchronization level based on the alignment results, and generates timing reference synchronization tags. The protocol dynamic adaptation module calls the timing reference synchronization tag, processes the message frame structure, baud rate parameters and semantic layers of different controlled terminals, judges the response delay of heterogeneous protocols to instruction parsing, evaluates the impact of cross-platform communication on real-time scheduling, matches protocol conversion tolerance, and outputs a protocol adaptation mapping list. The status closed-loop verification module calls the device task relationship in the protocol adaptation mapping list, adjusts the high deviation devices to the correction sequence according to the deviation distribution between the actuator readback data and the preset target instruction, keeps the low deviation devices executing, reconstructs the instruction issuance logic, and outputs the status feedback verification distribution diagram. The fault-tolerant scheduling recovery module reads the instruction execution record from the status feedback verification distribution diagram, identifies signal blocking, feedback timeout and logical conflict, triggers redundant link switching request, broadcasts to nearby controlled terminals, records feedback and identifies and confirms alternative scheduling objects, and generates scheduling anomaly recovery assignment record after completing instruction rearrangement. The equipment collaboration grouping module reads the scheduling anomaly recovery assignment records, screens overlapping action trajectories and scheduling synchronization records, identifies collaborative characteristic equipment and groups them, rearranges their action paths and sequences, integrates them into the cloud for unified scheduling, and outputs a stage equipment collaboration grouping structure diagram.

[0024] The timing reference synchronization tag includes clock source identifier, synchronization accuracy level and timing compensation parameters; the protocol adaptation mapping list includes protocol conversion coefficient, communication link index and instruction parsing delay tolerance; the status feedback verification distribution diagram includes real-time deviation block, instruction correction band and closed-loop execution parameters; the scheduling anomaly recovery assignment record includes recovery instruction number, redundancy takeover identifier and feedback confirmation time stamp; the stage equipment collaborative grouping structure diagram includes collaborative operation group number, action overlap measurement index and joint scheduling time axis.

[0025] Please see Figure 2 The timing reference synchronization module operation includes: The physical layer clock extraction submodule acquires the original pulse records of the master clock source in the digital communication link, divides the continuous sampling segments according to the preset time window, identifies the arrangement pattern of the rising and falling edges of the pulses in the segments, filters them according to the number of jitters and frequency drift of the pulse period, marks the recording segments with clock characteristic fluctuations, and generates clock abnormal segment labeling results. The original pulse recording dataset of the master clock source in the digital communication link of the stage lift is read. The recorded voltage sample values ​​and corresponding timestamp sequences are extracted from the dataset, and a preset time window parameter of 100 milliseconds is set. According to the timestamp order, the continuous sampling records are divided and truncated into multiple 100-millisecond continuous sampling segment sequences. The voltage sample values ​​within each independent sampling segment sequence are traversed. The timestamps of data points where the voltage sample value changes abruptly from below 0.8 volts to above 3.3 volts are extracted as pulse rising edge variables, and the timestamps of data points where the voltage drops from above 3.3 volts to below 0.8 volts are extracted as pulse falling edge variables. The rising and falling edges within the same sequence are arranged in ascending order of timestamps to generate an arrangement pattern sequence. The timestamps of adjacent pulse rising edge variables are read and substituted into the formula. The pulse period is calculated, and the absolute value of the difference between this period and the standard reference period of 20 milliseconds is used to calculate the jitter parameter. Regarding the threshold for determining the number of jitters, the system was continuously run for 120 hours at 25 degrees Celsius and a constant load of 500 kg, collecting 8,640,000 cycles. The data shows that under normal conditions, the highest frequency of period difference fluctuation is twice every 100 milliseconds; therefore, the threshold is set to 3 times per segment. The actual frequency is calculated and compared with a 50 Hz standard frequency to obtain the frequency drift parameter, with a threshold of 0.5 Hz. Finally, the total count of jitter parameters greater than 0.2 milliseconds within a segment is counted. When the count is greater than or equal to 3 or the frequency drift is greater than 0.5 Hz, the start and end timestamp parameters are extracted and written to the abnormal buffer array, outputting the clock abnormal segment labeling result.

[0026] The phase deviation correction submodule, based on the time segment corresponding to the clock abnormal segment annotation result, calls the frame synchronization signal of the audio and video acquisition terminal in the same segment recording, sorts out the alignment rhythm between the video frame start position and the audio sampling point, filters out the segments that have phase shift or sampling loss at the same time as the clock abnormal segment, summarizes them to form a chain of abnormal behavior of timing reaction, and generates a set of timing deviation related segments. The system retrieves the record nodes with clock anomaly fluctuation identifier codes from the clock anomaly segment annotation results, extracts their corresponding timestamp start and end parameters to establish a target retrieval interval, and retrieves the original media stream data records from the audio and video acquisition terminal within the aforementioned target retrieval interval. It extracts the set of timestamp variables for the start position of video frames from the output stream of the stage panoramic camera and the set of timestamp variables for audio sampling points from the output stream of the main sound reinforcement array microphone. Based on the 30 frames per second working mode set by the video equipment, the standard video frame interval time constant is calculated to be 33.33 milliseconds; based on the 48 kHz sampling rate set by the audio equipment, the standard audio sampling interval time constant is calculated to be 0.02 milliseconds. The system reads the above timestamp variable sets and calculates the time difference sequence of the start positions of actual adjacent video frames and audio sampling points, respectively. It then performs an absolute value operation on the difference with the corresponding standard interval constant to obtain the audio-visual alignment rhythm deviation variable. Regarding the threshold setting for determining the offset, a simulated delay packet is injected during system integration testing. Monitoring reveals that a buffer overflow occurs when the video rhythm deviation reaches 2.0 milliseconds or the audio deviation reaches 0.005 milliseconds. Based on this, the corresponding phase offset judgment threshold is set. By comparing the above variables and thresholds, audio and video time intervals exceeding the thresholds are extracted. Within the extracted audio intervals, audio frames with an audio sampling time difference greater than 0.04 milliseconds are defined as lost sampling data points. The time periods with excessive alignment rhythm deviations are combined with the time periods of lost sampling data points, and their start and end parameters and corresponding hardware addresses are combined and assembled to output a set of time-series deviation-related segments in the form of a one-dimensional relational structure array.

[0027] The synchronization tag generation submodule calls the time deviation associated segment set and the clock abnormal segment annotation results, compares the time identifier of the interruption point recorded in the sampling log of the stage machinery actuator, screens the time intersection in the three dimensions of the record, identifies the device number with multiple synchronization abnormalities, and classifies the time deviation combination according to the preset synchronization availability standard to generate the time reference synchronization tag. The system reads the one-dimensional correlation structure array node parameters from the timing deviation correlation segment set and the exception cache array node parameters from the clock exception segment annotation results, and calls the underlying hardware sampling log file of the stage machinery actuator communication motherboard. It retrieves the hardware interrupt record code from the log file and extracts the accompanying time identifier variable parameters. A three-dimensional comparison is performed between the time span intervals of the above two types of node parameters and the time coordinate axis corresponding to the hardware sampling log time identifier variable parameters, and the intersection range of the time axes is calculated. The process involves determining whether the calculated intersection range parameter is an empty set. If the intersection range is not empty, the MAC address of the terminal with the time intersection record is read, the device number is extracted, and it is marked as having multiple synchronization anomaly characteristics. A synchronization availability standard benchmark value range setting process is introduced: delay interference is applied in the tandem test. Data shows that there is no collision when the delay is below 2.0 milliseconds, slight discontinuity when it is between 2.0 and 5.0 milliseconds, and hardware alarm shutdown when it is 5.0 milliseconds or above. Based on this, the first level range is set to [0, 2.0) milliseconds, the second level to [2.0, 5.0) milliseconds, and the third level to [5.0, 10.0] milliseconds. The absolute value of the actual timing delay difference within the intersection range is extracted and matched with the above benchmark range. If it falls into the first level range, the attribute field of response level one is assigned; if it falls into the second level, level two is assigned; and if it falls into the third level, level three is assigned. The device number is merged with the assigned attribute field, and the timing benchmark synchronization label is output.

[0028] Table 1: Mechanical Equipment Synchronization Tag Classification Record Table As shown in Table 1, the specific allocation results of different mechanical equipment being classified into the corresponding response attribute fields due to time deviation fluctuations were extracted and entered.

[0029] The protocol dynamic adaptation module includes: The protocol feature identification submodule obtains the message flow records of the link where the device to be scheduled is located. Based on the frame header features and physical layer level characteristics marked on each message, it calls the description content related to the control protocol in the device attribute tag of the corresponding device, establishes the mapping relationship between message features and protocol type, matches according to the combination of message structure complexity level and computational overhead in protocol parsing algorithm, marks the parsing delay impact fragments and organizes their corresponding device numbers, and generates protocol adaptation interference matching results. The system retrieves the data link layer packet flow record buffer pool of the network switch port where the task-to-be-scheduled device is located. It sequentially reads the hexadecimal raw data of each packet, extracts the first two bytes of the payload area as the frame header feature identifier, and reads the extreme value variable of the physical layer differential voltage of the current packet's cable, recorded by the underlying hardware digital-to-analog converter. It then calls the device attribute tag corresponding to the device number in the global task database and retrieves the pre-written control protocol description field text to establish a mapping retrieval matching logic: the frame header feature identifier string is compared character-wise with the defined frame header rules, and the voltage extreme value variable is compared with the [1.5, 3.3] volt level standard value range in the protocol library. If the characters match and the voltage falls within the standard range, the current packet is bound to the corresponding underlying protocol type. The system reads the packet structure complexity level quantization parameter for this protocol type. The setting process is as follows: parsing an 8-byte single data type packet consumes 50 clock cycles, set as constant 1; parsing a 64-byte nested dictionary packet consumes 450 cycles, set as constant 2. The system reads the baseline calculation overhead time constant (e.g., 0.02 milliseconds) and calculates the matching combination overhead index. The main control board was selected to send messages concurrently for testing. Monitoring revealed that when the index exceeded 0.05 milliseconds, the timer overflow warning surged to 15%. Therefore, the overhead threshold was set to 0.05 milliseconds. The calculated index was read and determined to be greater than this threshold. When it was greater than 0.05 milliseconds, the timestamp attribute sequence was extracted and labeled as the segment affected by the parsing delay. The device number corresponding to the network port was extracted, and finally, the protocol adaptation interference matching result composed of the two was output.

[0030] The semantic conversion mapping submodule calls the device number involved in the protocol adaptation interference matching result, obtains the communication status label of the device in the instruction segment on the task target path, and compares the semantic definition layers of different brands of devices in the global device library to identify the intersection range of instruction definition mismatch nodes and control logic conflict points. It then organizes and classifies the set of conversion nodes with dual restrictions in the instruction flow and generates a list of protocol restriction node distributions. The system calls the affected device number string recorded in the interference matching results of the protocol adaptation, accesses the routing database of the main control system, queries the instruction distribution node array of the affected device number on the preset action task target path, and reads the communication status label variable parameters in the array. It connects to the global device model asset library server and extracts the semantic definition layer configuration files for the same action control command for different brand and model devices. It reads the instruction definition data type and control logic execution timing array from the configuration files of brand A and brand B devices, and performs a cross-comparison and quantization operation on non-numerical data: it extracts the "16-bit Unsigned Integer" data type field of the brand A lighting control console and the "32-bit Float" receiver data type field of the brand B servo motor; if the full-word matching result is inconsistent, it records the node position and classifies it as an instruction definition mismatch node; it also extracts the control logic execution timing array related to the initialization action. and The execution order is compared, and the coordinate positions are recorded when the order is reversed, categorizing them as control logic conflict points. This result indicates that there are underlying execution obstacles when devices from two brands are used interchangeably in the same area, affecting the execution of the two-dimensional coordinate set intersection calculation logic. Calculate the dual-restriction node variables. Gather the node coordinates and device IDs that satisfy the dual-restriction characteristics, and output a list of protocol-restricted node distributions containing the coordinate distribution of each restricted node.

[0031] The adaptation list generation submodule obtains the response time level content in the synchronization tag of each device number corresponding to each node in the protocol restriction node distribution list, and filters out the device numbers and corresponding task names that can operate within the conversion delay tolerance range by comparing them with the action coordination accuracy requirements set in the task. It then combines the instruction number with the executable device to generate a protocol adaptation mapping list. Read the affected device number string corresponding to each doubly restricted node recorded in the protocol-restricted node distribution list. Call the timing baseline synchronization tag for the corresponding device number generated in step three, and extract the timing delay response level attribute field recorded in the tag string. Access the central task setting parameter library and read the motion coordination accuracy requirement parameter value set for the current performance task, such as the maximum allowed coordination deviation of 15.0 milliseconds for multi-robotic arm synchronous simulation tasks. Read the upper limit of the baseline value range corresponding to the timing delay response level attribute field: 2.0 milliseconds for level one, 5.0 milliseconds for level two, and 10.0 milliseconds for level three. Then calculate the extreme value of the conversion delay tolerance range for this device number in the current state. ,in This represents the upper limit parameter value of each of the aforementioned latency range levels. The extreme value of the conversion latency tolerance range is compared with the inherent fixed latency constant of the protocol conversion determined by the protocol parsing algorithm (e.g., a fixed latency constant of 8.0 milliseconds). If the extreme value of the conversion latency tolerance range is greater than the inherent fixed latency constant of the protocol conversion, the device number variable satisfying this inequality condition is extracted, and the unique identifier string of the corresponding task is read. A dictionary-type data structure is established, using the original instruction feature number requiring conversion as the key and the selected execution device number as the value. Key-value pair data is assembled and merged, outputting a protocol adaptation mapping list consisting of a dictionary of mapped key-value pairs.

[0032] The operation of the state closed-loop verification module includes: The execution deviation extraction submodule calls the instruction and device combination information in the protocol adaptation mapping list to obtain the continuous execution feedback records of each execution terminal. According to the continuous repetition frequency and time sequence of the position / status data in the feedback records, the execution segments with close action connections are marked, and the combinations with deviation jumps between execution segments are numbered and grouped to establish the device execution deviation level sorting and generate the execution deviation level distribution results. The system uses key-value pairs of original instruction feature numbers and execution device numbers from the protocol adaptation mapping list dictionary to connect to the sensor bus interfaces of each underlying execution terminal to extract the continuous execution feedback record dataset. It iterates through the absolute spatial position 3D coordinate variables, hardware status register switch data, and corresponding high-precision time sequence stamp parameters in the dataset. It reads the 3D coordinate variables of adjacent records to calculate the spatial Euclidean distance difference, extracting the number of consecutive occurrences where the difference is less than 0.1 mm. When the number of occurrences exceeds a preset constant by 15 and the time stamp difference is less than 5.0 milliseconds, it extracts the corresponding time start and end interval coordinates and adds a tightly connected execution segment attribute label. It then iterates through the jump connection points between tightly connected segments and calculates the spatial position coordinate distance deviation parameter between the start and end points of the two segments. For the experimental calibration of deviation level classification, a real-world mobile vehicle platform was deployed to perform 100 positioning tests. Rangefinder data showed that when the spatial distance deviation was between 5.0 and 12.0 mm, the track wheels made slight noise but did not derail; when the deviation was greater than or equal to 12.0 mm, anti-collision locking occurred. Based on this, the [5.0, 12.0) mm range was designated as deviation group one, and [12.0, 30.0] mm as deviation group two. The calculated spatial distance deviation variable parameters were read, compared to their corresponding ranges, and assigned group numbers. The device numbers from group one were extracted and assigned to the lower-level deviation parameter variables, while those from group two were extracted and assigned to the higher-level parameter variables. The data was then sorted in reverse order of high to low levels, and the execution deviation level distribution results were output.

[0033] Table 2: Arrangement of Combined Sequences for Execution Terminal Deviation Records As shown in Table 2, based on the physical experimental definition range of the spatial distance deviation parameter, the serial numbers of each execution terminal were segmented and assigned and their levels were quantified and arranged.

[0034] The instruction correction association submodule extracts the target value data such as spatial position / brightness / gain of the current corresponding instruction based on the device number in the execution deviation level distribution results. According to the feedback deviation area of ​​the instruction number and the classification rules of the correction algorithm, it forms a combination structure with the high deviation level device and the correction instruction retransmission sequence. At the same time, it marks the degree of deviation between the instruction corresponding to the low deviation level device and the high precision area in terms of execution accuracy, and generates a device instruction correction matching combination list. The system reads the device number record assigned to the high-level execution deviation parameter variable from the execution deviation level distribution result array, sends the access command to the server, and reads the data packet payload segment corresponding to the control command under the current execution state of the high-level device number. It reads the corresponding target parameter settings from the payload segment by byte offset, including the spatial absolute position target coordinate axis constant, the LED array brightness pulse width modulation duty cycle setting constant, and the audio amplifier circuit voltage gain target parameter constant. It reads the feedback deviation maximum allowable operating boundary region constant bound to the control command number in the global configuration table and calls the correction mode number variable from the control layer correction algorithm classification rule document. It reads the above target parameter settings and determines whether their values ​​fall completely within the numerical space defined by the allowable operating boundary region constant. If they fall completely within this space, it calls the underlying function to generate the corresponding compensation positioning incremental command message sequence and establishes a pointer reference relationship association structure between the generated high-deviation-level device number's identifier variable and the compensation positioning incremental command message sequence data block. Simultaneously, the system reads the device number record assigned to the low-level parameter variable of execution deviation from the array, extracts the actual three-dimensional coordinate values ​​of its control command execution feedback, reads the absolute value parameters of the system's ultra-high precision reference circle center region set in the global coordinate system, and performs Euclidean distance difference calculations on the two sets of coordinate spaces. The obtained distance difference result variable is set as a floating-point variable attribute of deviation degree, appended to the end of the corresponding low-level device structure, and a device command correction matching combination list is output.

[0035] The verification layer update submodule calls the device instruction to correct the scheduling mapping information in the matching combination list, redirects high deviation level devices to the correction instruction path node, repositions low deviation level devices to the regular scheduling path node, and updates the mapping of the adjustment path of all instruction numbers on the execution trajectory, completes the latest correspondence between instruction numbers and device numbers in all areas, and generates a status feedback verification distribution map. The system invokes device instructions to correct the scheduling mapping information nodes in the high-deviation structure data and low-deviation structure data that have established pointer reference associations within the matching combination list, and accesses the system's central scheduling map memory area module. It reads the control instruction memory node block data containing the high-deviation-level device number, erases the memory pointer address that originally pointed to the default execution path node in that memory node block, and re-establishes the memory pointer link for the control instruction memory node containing the high-deviation-level device number, forcibly pointing to the coordinate address of the newly established path node corresponding to the compensation positioning incremental instruction message sequence generated in step eight. It then reads the control instruction memory node block data containing the low-deviation-level device number, verifies the floating-point variable attribute value of the deviation degree contained in that node block, and compares it with the original path node tolerance range constant. It retains the original default regular scheduling path node coordinates, refreshes the execution body parameters of the low-deviation-level device number, and binds them to the port register address corresponding to the default regular scheduling path node. Extract the coordinate sequence parameters of the action path control points stored in the execution trajectory database for all instruction feature numbers. Overwrite these parameters with the updated coordinate addresses of newly established path nodes and the coordinates of regular scheduling path nodes, thereby updating the constant of the mapping matrix constant between the execution device space occupancy and trajectory intersection points in the global 3D mesh. Re-render the node occupancy record array based on the updated mapping matrix constant, and output the status feedback verification distribution map data record.

[0036] The fault-tolerant scheduling and recovery module includes: The blocking identification submodule reads the task execution process of each controlled terminal in the status feedback verification distribution diagram, extracts the instruction blocking signals, feedback imbalance behavior and communication interruption records in the task stage in chronological order, sorts them according to the order in which the records appear, determines whether there are two or more consecutive abnormal tag combinations, marks the corresponding instruction number and device number, and generates an abnormal combination instruction label table. The system retrieves the task action execution process time queue cache of each controlled terminal device number from the status feedback verification distribution map data record. Log record items in the time queue cache are read sequentially from front to back according to the high-precision clock variable of the system operation. Log data classification and extraction operations are performed, extracting hexadecimal instruction blocking hardware level alarm signals with the identifier "ERR_BLOCK", extracting abnormal feedback imbalance floating-point number records where the absolute value of the difference between the actual value and the preset target value of the displacement sensor is greater than 10 mm and the duration exceeds 500 milliseconds, and extracting communication link transmission interruption status register word data with the identifier "TCP_DISCONNECT". The extracted alarm signals, abnormal floating-point number records, and status register word data are read and reassembled in ascending time order according to their respective accompanying system receive timestamp parameters. The adjacent index sequence records of the sorted combined array list elements are traversed, and status comparison and judgment logic is performed: [The text abruptly ends here, likely due to an incomplete translation or source material.] Item element and the first The anomaly type of each element is assigned to a label variable. It is then determined whether two adjacent label variables both belong to the anomaly state type. If both belong to the anomaly state type and the difference in their timestamp interval is less than a constant of 50 milliseconds, the feature number parameter and the terminal device number parameter of the currently invoked instruction at the coordinates of the consecutively occurring nodes are extracted. These two parameters are written in pairs into a two-dimensional association matching table. This result indicates that the physical node has lost its independent recovery capability and there is a cascading risk. Therefore, an anomaly combination instruction label table is output.

[0037] The response feedback recording submodule collects the scheduling tags of other redundant controlled terminals in the same scheduling area based on the instruction numbers of the marked devices in the abnormal combination instruction label table, broadcasts takeover requests to these terminals and records the feedback content, extracts the acceptance field and reception time from the feedback response, identifies the device numbers that have confirmed takeover intentions and sorts them in ascending order of response time, and generates instruction takeover response sorting results. The system reads the marked and confirmed failed controlled terminal device numbers and corresponding pending instruction feature number parameters from the abnormal combination instruction label table. It then retrieves the system area division data table and reads the label string of the physical grid scheduling area where the failed device number is currently located. This label string is used as a search keyword parameter in the redundant controlled terminal configuration database for precise matching. The system extracts the set of device numbers and MAC addresses of other backup redundant controlled terminals with the same function that are completely consistent with the keyword from the returned results. Through the LAN user datagram protocol socket interface, a takeover request multicast control data packet containing the instruction feature number parameter is packaged and sent to the extracted redundant terminal MAC address set. The system synchronously records the start timestamp parameter triggered by the sender's clock counter and starts an asynchronous listening thread to collect the takeover intention response feedback data packets returned by each redundant terminal. The system unpacks and parses the payload content of the feedback data packets, extracting the Boolean-type takeover acceptance field variable data and the local receive timestamp variable data recorded by the underlying network card driver. The system verifies whether the takeover acceptance field variable data is equal to a Boolean true value, filters out invalid response packet data with Boolean false values, and calculates the feedback communication time variable parameter from the filtered valid data. Extract the sequence of redundant device numbers that have been verified and confirmed to have the intention to take over. Then, use a sorting algorithm to sort the sequence in ascending order according to the communication time parameter, and output the sorted set of command takeover response results.

[0038] Table 3: Data Table of Command Takeover Response for Redundant Equipment in the Same Dispatch Area As shown in Table 3, the parameters of the response packets of backup equipment in the same area were sorted out, and the equipment that refused to take over was filtered out. The equipment that met the conditions was then sorted and located in ascending order.

[0039] The recovery instruction generation submodule calls the first responding device number and corresponding instruction number in the instruction takeover response sorting result, updates the execution device field of the instruction in the status feedback verification distribution diagram, records the target instruction for replacement takeover and the adjustment node of the takeover device in the scheduling configuration, and summarizes all instruction information that has been replaced, generating a scheduling anomaly recovery assignment record. The system retrieves the data at the memory address of the first index item in the sorted result set array of the instruction takeover response. It extracts the string parameter of the first responding device number recorded at that memory address, along with the corresponding string parameter of the original abnormal pending instruction feature number. It accesses the linked list structure module of the status feedback verification distribution map stored in the system core control board, retrieving the index node address that matches the feature number of the abnormal pending instruction. It extracts and erases the original MAC address field of the executing device at that index node address, then overwrites and replaces it with the newly extracted string parameter of the first responding device number, forcibly updating the network communication port address record pointed to by the instruction. It calls the global scheduling configuration memory image file block, reading the absolute three-dimensional coordinate node parameter of the replacement takeover location from the memory image file block. Finally, it encapsulates and packages the newly assigned first responding device number, the updated execution instruction feature number, the three-dimensional coordinate node parameter of the replacement occurrence, and the high-precision timestamp data of the replacement time into a dictionary-formatted structure data block, appending and saving it to the system abnormal handling change log record matrix array. The system reads the set of elements from the matrix array of all change log records updated by takeover and replacement events in the system, summarizes the parameters of all elements, and compiles them into a set of XML markup language documents that can be parsed by the underlying device. The output is a scheduling exception recovery assignment record.

[0040] The equipment collaboration and grouping module includes: The trajectory integration submodule reads the access order and corresponding action trajectory of each instruction execution device in the scheduling anomaly recovery assignment record, extracts the frequency of occurrence of device instruction numbers, overlapping location points and time segments of scheduling areas in the action path, sorts out the number of access times of each device instruction and the number of path intersection nodes, and summarizes the device numbers within the same time period of scheduling time to generate a list of action trajectory intersection features. Read the data contained in each tag node of the scheduling anomaly recovery dispatch record file, extract the access execution port timing sequence integer parameters of each execution terminal device number that receives a new instruction dispatch, and simultaneously extract the three-dimensional coordinate path point vector array of the action trajectory corresponding to each device number. Establish a statistical loop structure, using the device instruction feature number as the primary key, to count the total number of times the instruction is repeatedly referenced in the full trajectory three-dimensional coordinate path point vector array. Perform a three-dimensional spatial intersection comparison calculation operation for the execution instructions of different devices: read the coordinate points of the action path point vector array of device A. Coordinates of device B The system performs spatial absolute error distance calculation. If the calculated spatial distance is less than a safety margin constant of 0.05 meters, it extracts this location coordinate record as the coordinate parameters of the intersection node of the overlapping location in the scheduling area, and retrieves the estimated time interval parameters for the two devices to move to the intersection node coordinates. and The extracted total frequency integer parameter is summed with the coordinate parameters of the overlapping intersection nodes to obtain a constant value representing the total number of global path intersection nodes in the entire region. The range of each time segment is read to determine if there are overlapping ranges in the estimated traversed time segments of different devices. If overlap exists, the terminal numbers of conflicting devices within the same concurrent time period in the corresponding time segment are merged and extracted, recorded in a temporary storage structure, and a list of action trajectory intersection features is output.

[0041] The collaborative screening module determines whether the device number and path overlap are simultaneously present based on the device number and path overlap number recorded in the action trajectory intersection feature list. The device numbers that meet the conditions are grouped and classified, marked as group objects, and a corresponding instruction number set structure is established for each group to generate a collaborative grouping structure for device instructions. Read the conflicting terminal device number parameter recorded in the action trajectory intersection feature list, and the global path intersection node count summary constant corresponding to that terminal device number, and extract the specific estimated overlap time difference constant variable for overlaps within the same concurrent time period. Establish a multi-concurrency filtering logic judgment expression module, and call the logic judgment expression module to judge Boolean truth conditions: read judgment condition A (whether the global path intersection node count summary constant is greater than or equal to 2); read judgment condition B (whether the estimated overlap time difference constant variable exceeds the set mechanical avoidance critical reaction time of 5.0 milliseconds). If the Boolean operation results of conditions A and B are both true, extract the set of conflicting terminal device number parameter variables that satisfy the above concurrency control feature constraints, and assign independent grouping sequence number label parameters to different terminal device numbers extracted from this set. Mark the device numbers successfully assigned independent grouping sequence number label parameters with a special cooperative grouping object Boolean flag and place them into the target cooperative device memory pool. For device groups with the same grouping sequence number label parameter in the target collaborative device memory pool, an independent tree-like set data structure is established, and all instruction feature numbers bound to controlled conflicting terminals within this group are pushed into the node memory address stack of this tree-like set data structure. All established group sets are integrated to generate and output multiple sets of combined and mapped device instruction collaborative grouping structure data records.

[0042] The scheduling reconfiguration submodule calls the instruction set corresponding to each group in the device instruction coordination grouping structure, reorders the instruction numbers in each group according to the original execution order, and uniformly specifies the corresponding execution device number as the scheduling entry in the sorting structure, updates the corresponding instruction node order in the platform scheduling arrangement structure, and maps the updated content to the regional task distribution layer to generate a stage equipment coordination grouping structure diagram. The system calls upon the memory addresses of tree-like data structure blocks corresponding to the different independent group sequence number label parameters within the device instruction collaborative grouping structure data record. It then reads the set of restricted control conflict terminal instruction feature number nodes pushed into each tree-like set, and reads and parses the original execution order number constant parameters pre-assigned to the corresponding control instructions in the global script file of the performance process. The system calls the underlying quicksort algorithm function to re-sort the extracted instruction feature number parameters within the same current set group, strictly adhering to the original execution order number constant in an ascending direction. At the first index node position of the re-queueed structure, it locks the first-ranked corresponding action control instruction, reads the MAC address parameter of the corresponding underlying actuator hardware device bound to this first instruction, and forcibly assigns it as the unique scheduling entry route binding point constant for the current collaborative grouping queue's external unified communication. Finally, it accesses the platform's central core scheduling memory structure graph, searches for and replaces the old unordered concurrent instruction memory node sorting connections, and completely overwrites the previous and subsequent order of the re-queueed queue structure nodes into the graph network connection configuration database. The core scheduling memory structure map is overwritten and updated with the new node order logical topology relationship graph network matrix constant. The drawing application programming interface is called, and the pixel-by-pixel coordinate matrix is ​​projected and rendered onto the three-dimensional regional task distribution layer model of the physical performance venue. The above abstract reconstruction relationship is expressed in a concrete way through the mapping data, and the stage equipment collaborative grouping structure diagram is output.

[0043] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A digital audio-visual integrated stage scheduling intelligent control system, characterized in that, The system includes: The timing reference synchronization module acquires the pulse signal of the main control clock source, the frame synchronization characteristics of the audio and video streams, and the sampling clock of the mechanical actuator. It extracts the phase deviation, drift rate, and timing offset, completes the clock alignment of all system devices according to the time axis sequence, defines the device synchronization level based on the alignment results, and generates timing reference synchronization tags. The protocol dynamic adaptation module calls the timing reference synchronization tag to process the message frame structure, baud rate parameters and semantic layers of different controlled terminals, judges the response delay of heterogeneous protocols to instruction parsing, evaluates the impact of cross-platform communication on real-time scheduling, matches protocol conversion tolerance, and outputs a protocol adaptation mapping list. The state closed-loop verification module calls the device task relationship in the protocol adaptation mapping list, adjusts the high deviation device to the correction sequence according to the deviation distribution between the actuator readback data and the preset target instruction, keeps the low deviation device executing, reconstructs the instruction issuance logic, and outputs the state feedback verification distribution map. The fault-tolerant scheduling recovery module reads the instruction execution records in the status feedback verification distribution diagram, identifies signal blocking, feedback timeout and logic conflict situations, triggers redundant link switching requests, broadcasts to nearby controlled terminals, records feedback and identifies and confirms alternative scheduling objects, and generates a scheduling anomaly recovery assignment record after completing instruction rearrangement.

2. The digital audio-visual integrated stage scheduling intelligent control system according to claim 1, characterized in that: The timing reference synchronization tag includes a clock source identifier, synchronization accuracy level, and timing compensation parameters; the protocol adaptation mapping list includes protocol conversion coefficients, communication link indicators, and instruction parsing delay tolerance; the status feedback verification distribution map includes real-time deviation blocks, instruction correction bands, and closed-loop execution parameters; and the scheduling anomaly recovery assignment record includes recovery instruction number, redundancy takeover identifier, and feedback confirmation time stamp.

3. The digital audio-visual integrated stage scheduling intelligent control system according to claim 1, characterized in that, The operation of the timing reference synchronization module includes: The physical layer clock extraction submodule acquires the original pulse records of the master clock source in the digital communication link, divides the continuous sampling segments according to the preset time window, identifies the arrangement pattern of the rising and falling edges of the pulses in the segments, filters them according to the number of jitters and frequency drift of the pulse period, marks the recording segments with clock characteristic fluctuations, and generates clock abnormal segment labeling results. The phase deviation correction submodule, based on the time segment corresponding to the clock abnormal segment annotation result, calls the frame synchronization signal of the audio and video acquisition terminal in the same segment recording, sorts out the alignment rhythm between the video frame start position and the audio sampling point, filters out the segments that have phase shift or sampling loss at the same time as the clock abnormal segment, summarizes them to form a chain of abnormal behavior of timing reaction, and generates a set of timing deviation related segments. The synchronization tag generation submodule calls the set of time deviation associated segments and the clock abnormal segment annotation results, compares the time identifier of the interruption point recorded in the sampling log of the stage machinery actuator, screens the time intersection in the three-dimensional records, identifies the device number with multiple synchronization abnormalities, and classifies the time deviation combination according to the preset synchronization availability standard to generate time reference synchronization tags.

4. The digital audio-visual integrated stage scheduling intelligent control system according to claim 1, characterized in that, The protocol dynamic adaptation module includes: The protocol feature identification submodule obtains the message flow record of the link where the device to be scheduled is located, calls the clock source identifier, synchronization accuracy level and timing compensation parameters corresponding to the device to be scheduled in the timing reference synchronization tag, establishes the mapping relationship between message features and protocol type based on the frame header features and physical layer level characteristics marked in each message, matches according to the combination of message structure complexity level and computational overhead in the protocol parsing algorithm, marks the parsing delay-affected segments and organizes their corresponding device numbers, and generates protocol adaptation interference matching results; The semantic conversion mapping submodule calls the device number involved in the protocol adaptation interference matching result, obtains the communication status label of the device in the instruction segment on the task target path, and identifies the intersection range of instruction definition mismatch nodes and control logic conflict points by comparing the semantic definition layers of different brands of devices in the global device library. It sorts and classifies the set of conversion nodes with dual restrictions in the instruction flow and generates a list of protocol restriction node distribution. The adaptation list generation submodule obtains the response time level content in the synchronization tag of each device number corresponding to each node in the protocol-restricted node distribution list, and filters out the device numbers and corresponding task names that can operate within the conversion delay tolerance range by comparing them with the action coordination accuracy requirements set in the task. It then maps the instruction numbers and executable devices one by one to generate a protocol adaptation mapping list.

5. The digital audio-visual integrated stage scheduling intelligent control system according to claim 4, characterized in that: The matching is performed according to the combination of message structure complexity level and computational overhead in protocol parsing algorithm. Specifically, the real-time payload length data and real-time check bit computational overhead in message stream are compared with the preset processor computing power threshold and memory usage threshold in protocol attributes. When the real-time payload length data exceeds the computing power threshold or the real-time check bit computational overhead exceeds the memory usage threshold, the matching is completed. The identification instruction definition mismatch node is specifically: the instruction node recorded in the communication status label with an instruction parsing packet loss rate higher than a preset parsing packet loss rate threshold or a semantic mapping delay higher than a preset mapping delay threshold is identified as an instruction definition mismatch node; The identification instruction defines the intersection range of mismatched nodes and control logic conflict points. Specifically, taking each logic conflict point in the semantic definition layer as the logic center, a dynamic logic buffer area is calculated and generated based on the instruction length, maximum response speed, and shortest processing cycle data of the device executing the scheduling task. The instruction definition mismatched nodes falling into the dynamic logic buffer area are determined as nodes within the intersection range.

6. The digital audio-visual integrated stage scheduling intelligent control system according to claim 1, characterized in that, The operation of the state closed-loop verification module includes: The execution deviation extraction submodule calls the instruction and device combination information in the protocol adaptation mapping list to obtain the continuous execution feedback records of each execution terminal. According to the continuous repetition frequency and time sequence of the position / status data in the feedback records, the execution segments with close action connections are marked, and the combinations with deviation jumps between execution segments are numbered and grouped to establish the device execution deviation level sorting and generate the execution deviation level distribution results. The instruction correction association submodule extracts the spatial position / brightness / gain target value data of the current corresponding instruction based on the device number in the execution deviation level distribution result. According to the feedback deviation area of ​​the instruction number and the classification rules of the correction algorithm, it forms a combination structure with the high deviation level device and the correction instruction retransmission sequence. At the same time, it marks the degree of deviation between the instruction corresponding to the low deviation level device and the high precision area in terms of execution accuracy, and generates a device instruction correction matching combination list. The verification layer update submodule calls the scheduling mapping information in the device instruction correction matching combination list, redirects high deviation level devices to correction instruction path nodes, repositions low deviation level devices to regular scheduling path nodes, and updates the mapping of adjustment paths for all instruction numbers on the execution trajectory, completing the latest correspondence between instruction numbers and device numbers in all regions, and generating a status feedback verification distribution map.

7. The digital audio-visual integrated stage scheduling intelligent control system according to claim 1, characterized in that, The fault-tolerant scheduling recovery module includes: The blocking identification submodule reads the task execution process of each controlled terminal in the status feedback verification distribution map, extracts the instruction blocking signal, feedback imbalance behavior and communication interruption record in the task stage in chronological order, sorts them according to the order in which the records appear, determines whether there are two or more consecutive abnormal tag combinations, marks the corresponding instruction number and device number, and generates an abnormal combination instruction label table. The response feedback recording submodule collects the scheduling tags of other redundant controlled terminals in the same scheduling area according to the instruction number of the marked device in the abnormal combination instruction label table, broadcasts takeover requests to these terminals and records the feedback content, extracts the acceptance field and reception time from the feedback response, identifies the device number that has confirmed the takeover intention and sorts them in ascending order of response time, and generates instruction takeover response sorting results. The recovery instruction generation submodule calls the first response device number and corresponding instruction number in the instruction takeover response sorting result, updates the execution device field of the instruction in the status feedback verification distribution diagram, records the target instruction for replacement takeover and the adjustment node of the takeover device in the scheduling configuration, summarizes all instruction information that has been replaced, and generates a scheduling anomaly recovery assignment record.

8. The digital audio-visual integrated stage scheduling intelligent control system according to claim 7, characterized in that: The instruction blocking signal during the task extraction phase specifically involves: comparing the sequence of instructions sent by the device with the sequence of confirmation receipts returned by the receiving end in real time; and generating an instruction blocking signal when the missing rate of the confirmation receipt sequence is continuously greater than the first blocking threshold within a preset sliding window. The feedback imbalance behavior during the task extraction phase is specifically as follows: obtain the current execution current of the controlled terminal and calculate the energy consumption change rate. When the energy consumption change rate is continuously higher than the expected energy consumption rate generated based on action planning and load data, and the difference between the two exceeds the preset energy consumption deviation threshold, feedback imbalance behavior is generated. The process of extracting communication interruption records during the task phase specifically involves: determining whether the network heartbeat packets between the controlled terminal and the scheduling host are received within a second preset time period; and generating a communication interruption record if the number of consecutively lost network heartbeat packets exceeds a preset packet loss threshold.

9. The digital audio-visual integrated stage scheduling intelligent control system according to claim 1, characterized in that, The system also includes: The equipment collaboration grouping module reads the scheduling anomaly recovery assignment record, screens overlapping action trajectories and scheduling synchronization records, identifies collaborative characteristic equipment and groups it, rearranges its action paths and sequences, integrates them into the cloud for unified scheduling, and outputs a stage equipment collaboration grouping structure diagram. The stage equipment collaborative grouping structure diagram includes collaborative operation group numbers, action overlap measurement indicators, and joint scheduling time axis.

10. The digital audio-visual integrated stage scheduling intelligent control system according to claim 9, characterized in that, The device collaboration grouping module includes: The trajectory integration submodule reads the access order and corresponding action trajectory of each instruction execution device in the scheduling anomaly recovery assignment record, extracts the frequency of occurrence of device instruction numbers, overlapping location points and time segments of scheduling areas in the action path, sorts out the number of access times of each device instruction and the number of path intersection nodes, and summarizes the device numbers within the same time period of scheduling time to generate a list of action trajectory intersection features. The collaborative screening module determines whether multiple instruction overlap records and scheduling time coincidence characteristics are simultaneously present based on the device number and path overlap count recorded in the action trajectory intersection feature list. Device numbers meeting this condition are grouped and categorized, marked as grouped objects, and a corresponding instruction number set structure is established for each group, generating a collaborative grouping structure for device instructions. The scheduling reconstruction submodule calls the instruction sets corresponding to each group in the collaborative grouping structure for device instructions, reorders the instruction numbers within each group according to the original execution order, and uniformly specifies the corresponding execution device number as the scheduling entry point within the sorting structure. It updates the corresponding instruction node order in the platform scheduling arrangement structure and maps the updated content to the regional task distribution layer, generating a collaborative grouping structure diagram for stage equipment.

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