An adaptive bandwidth scheduling method and device

Abstract

The present specification relates to the field of computer technology, and particularly relates to an adaptive bandwidth scheduling method and device. The method comprises obtaining effective bandwidth information of an instruction dispatch module; and adjusting the number of effective read micro-operations of a UOPQ port according to the effective bandwidth information of the instruction dispatch module. By using the embodiment of the present specification, the power consumption of the UOPQ module, the power consumption of the DISPATCH module, and the power consumption of the execution unit can be reduced without reducing the pipeline efficiency, and the energy efficiency of the processor can be improved.

Description

Technical Field

[0001] This specification relates to the field of computer technology, and in particular to an adaptive bandwidth scheduling method and apparatus. Background Technology

[0002] In CPU microarchitecture, the pipeline is mainly divided into the front end and the back end. As the types and number of back-end execution units continue to increase, the execution capability of the processor's back end continues to improve, and the bandwidth demand for front-end instruction dispatch is growing. However, in traditional designs, the reading and dispatching of front-end micro-operations can no longer match the back end. Undispatched micro-operations will cause hardware energy consumption, leading to an imbalance between performance and power consumption, which restricts the improvement of energy efficiency of high-performance processors.

[0003] Improving processor energy efficiency is an urgent problem that needs to be solved. Summary of the Invention

[0004] To address the problems in the prior art, embodiments of this specification provide an adaptive bandwidth scheduling method and apparatus that can solve the problem of low energy efficiency caused by the mismatch between the number of micro-operations in the micro-operation queue (UOPQ) port and the number of micro-operations in the DISPATCH module in the processor front end. By controlling the effective number of micro-operations in the DISPATCH module, excess micro-operations are prevented from being dispatched to the execution unit, thereby improving the energy efficiency of the execution unit.

[0005] This specification provides an adaptive bandwidth scheduling method, including: Obtain the effective bandwidth information of the Dispatch module; Adjust the number of effective read micro-operations of the UOPQ port based on the effective bandwidth information of the DISPATCH module.

[0006] As a further aspect of this specification, the number of micro-operations effectively read by the UOPQ port includes: the number of micro-operations read by the UOPQ port corresponding to micro-operations that can be effectively dispatched by the DISPATCH module; the effective bandwidth information of the DISPATCH module includes: the number of micro-operations that are effectively dispatched.

[0007] As a further aspect of this specification, the effective bandwidth information of the DISPATCH module also includes: the available resources of the execution unit corresponding to the effectively dispatched micro-operation, and the type of the effectively dispatched micro-operation.

[0008] As a further aspect of this specification, adjusting the number of effective read micro-operations of the UOPQ port based on the effective bandwidth information of the DISPATCH module further includes: When the effective bandwidth information of the DISPATCH module indicates continuous congestion, the number of effective read micro-operations of the UOPQ port is reduced. If the effective bandwidth information of the DISPATCH module indicates continuous idleness, then increase the number of effective read micro-operations of the UOPQ port.

[0009] As a further aspect of this specification, the effective bandwidth information of the DISPATCH module indicating continuous congestion further includes: Based on the type of micro-operation, the key micro-operations that will be effectively dispatched by the DISPATCH module are marked; When the same key micro-operation of the same type is continuously marked with the same flag, it indicates that the effective bandwidth information of the DISPATCH module is continuously congested.

[0010] As a further aspect of this specification, the type includes at least one of the following: Floating-point arithmetic micro-operations, fixed-point arithmetic micro-operations, and memory access micro-operations.

[0011] As a further aspect of this specification, the type further includes a specific operation type for each micro-operation.

[0012] As a further aspect of this specification, micro-operations that meet one or a combination of the following conditions are designated as critical micro-operations: The TOKEN of the execution unit corresponding to the type of micro-operation effectively dispatched by the DISPATCH module is less than the first threshold. The number of micro-operations of this type that are effectively dispatched by the DISPATCH module is less than the second threshold; The difference between the number of micro-operations of this type effectively dispatched by the DISPATCH module and the number of micro-operations effectively read by the UOPQ port is greater than the third threshold.

[0013] As a further aspect of this specification, the effective bandwidth information of the DISPATCH module indicating continuous idle time further includes: Based on the type of micro-operation, non-critical micro-operations that will be effectively dispatched by the DISPATCH module will be marked; When consecutive markers of the same type of non-critical micro-operation reach a specified threshold, it indicates that the effective bandwidth information of the DISPATCH module is continuously idle.

[0014] As another further aspect of this specification, Micro-operations that meet one or a combination of the following conditions are classified as non-critical micro-operations: The TOKEN of the execution unit corresponding to the type of micro-operation effectively dispatched by the DISPATCH module is greater than the first threshold. The number of micro-operations of this type that are effectively dispatched by the DISPATCH module is greater than the second threshold; The difference between the number of micro-operations of this type effectively dispatched by the DISPATCH module and the number of micro-operations effectively read by the UOPQ port is less than the third threshold.

[0015] As a further aspect of this specification, adjusting the number of effective read micro-operations of the UOPQ port includes at least one of the following methods: The number of UOPQ ports can be adjusted by using the UOPQ port enable signal, thereby regulating the number of effective read micro-operations by the UOPQ port; or, By controlling the number of micro-operations written to the UOPQ port by the pipeline front end, and waiting for all micro-operations written to the UOPQ port, the number of UOPQ ports is adjusted, thereby regulating the number of effective micro-operations read by the UOPQ port; or, By controlling the number of micro-operations written to the UOPQ port at the pipeline front end, and waiting for all micro-operations at the pipeline front end to be written to the UOPQ port, and after the micro-operations in the UOPQ have been dispatched, the number of UOPQ ports is adjusted, thereby adjusting the number of micro-operations that the UOPQ port can effectively read; or, By redirecting the REDIRECT action to trigger the FLUSH operation at the front end of the pipeline, the number of UOPQ ports is adjusted, thereby adjusting the number of effective read micro-operations of the UOPQ ports.

[0016] As a further aspect of this specification, after reducing the number of effective read micro-operations for the UOPQ port, it also includes: Monitor the number of micro-operations effectively dispatched by the DISPATCH module; If the number of micro-operations effectively dispatched by the DISPATCH module is consistently lower than a preset threshold, the number of micro-operations effectively read by the UOPQ port will be increased.

[0017] As a further aspect of this specification, after reducing the number of effective read micro-operations for the UOPQ port, it also includes: Monitor changes in processor performance IPC; As the DISPATCH module completes the dispatch of micro-operations, if the IPC remains below a preset threshold, the number of micro-operations effectively read by the UOPQ port will be increased.

[0018] As a further aspect of this specification, after reducing the number of effective read micro-operations for the UOPQ port, it also includes: Monitor the number of execution unit tokens at the back end of the processor pipeline; As the DISPATCH module completes the dispatch of micro-operations, if the number of TOKENs corresponding to a certain type of micro-operation continues to exceed a preset threshold, and if there are still micro-operations of that type in the DISPATCH module, then the number of micro-operations effectively read by the UOPQ port will be increased.

[0019] This specification also provides an adaptive bandwidth scheduling device, comprising: The acquisition unit is configured to acquire the effective bandwidth information of the instruction dispatch DISPATCH module. The decision-maker is configured to adjust the number of effective read micro-operations of the UOPQ port based on the effective bandwidth information of the DISPATCH module.

[0020] This specification also provides an instruction dispatching unit that executes the adaptive bandwidth scheduling method described above.

[0021] This specification also provides a processor, including an instruction dispatch unit for performing the above-described methods.

[0022] This specification also provides a computer device, including a memory and a computer program stored in the memory and executable on a processor, including the processor described above.

[0023] This specification also provides a computer-readable storage medium storing computer instructions that, when executed by a processor, implement the above-described method.

[0024] This specification also provides a computer program product, which includes a computer program that, when executed by a processor, implements the above-described method.

[0025] By utilizing the embodiments in this specification, the power consumption of the UOPQ module can be reduced without decreasing pipeline efficiency, and the power consumption of the DISPATCH module can also be reduced, thereby improving the processor's energy efficiency. Attached Figure Description

[0026] To more clearly illustrate the technical solutions in the embodiments or prior art of this specification, the drawings used in the description of the embodiments or prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this specification. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0027] Figure 1 The diagram shown is a flowchart of an adaptive bandwidth scheduling method according to an embodiment of this specification. Figure 2a The diagram shown is a schematic representation of the distribution history in an embodiment of this specification. Figure 2b The diagram shown is a schematic representation of another distribution history in an embodiment of this specification. Figure 3 The diagram shown is a schematic of the UOPQ port adjustment circuit in an embodiment of this specification. Figure 4 The diagram shown is a schematic diagram of a blocking write operation in an embodiment of this specification; Figure 5 The diagram shown is a schematic of how to clear the front end of the pipeline to adjust the number of UOPQ ports according to an embodiment of this specification; Figure 6 The diagram shown is a structural schematic of the adaptive bandwidth scheduling device according to an embodiment of this specification. Figure 7 The diagram shown is a structural schematic of the instruction dispatch unit in an embodiment of this specification. Figure 8 The diagram shown is a schematic representation of a computer device provided in an embodiment of this specification. Detailed Implementation

[0028] The technical solutions in the embodiments of this specification will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this specification, and not all embodiments. Based on the embodiments in this specification, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this specification.

[0029] like Figure 1 The diagram shows a flowchart of an adaptive bandwidth scheduling method according to an embodiment of this specification. This diagram illustrates that in the pipeline front-end of a high-performance processor, particularly during the process of reading micro-operations from the Unified Operation Queue (UOPQ) to the Dispatch port for micro-operation dispatch, the number of effective micro-operations read by the UOPQ port is dynamically adjusted to match the number of micro-operations at the pipeline front-end and back-end. This reduces ineffective toggle switching of micro-operations between instruction dispatches, reduces the power consumption of execution units caused by excessive instruction dispatch, avoids hardware energy consumption, and improves processor energy efficiency. The method specifically includes: Step 101: Obtain the effective bandwidth information of the instruction dispatching DISPATCH module; Step 102: Adjust the number of effective read micro-operations of the UOPQ port according to the effective bandwidth information of the DISPATCH module.

[0030] The methods described in this specification can reduce the power consumption of the UOPQ module, the power consumption of the DISPATCH module, and the power consumption of the execution unit without reducing pipeline efficiency, thereby improving the energy efficiency of the processor.

[0031] As an embodiment of this specification, the number of micro-operations effectively read by the UOPQ port includes: the number of micro-operations that can be effectively dispatched by the DISPATCH module and read by the UOPQ port.

[0032] In this embodiment, the number of micro-operations read by the UOPQ port can be determined based on the hardware resources of the UOPQ port. For example, if the width of the UOPQ port is 8, it means that 8 micro-operations (SLOT-0~SLOT-7) in the queue can be read at once. Because the number of micro-operations dispatched by the DISPATCH module is limited by the processing resources of the downstream execution unit (e.g., the computing unit ALU), it may only be able to dispatch 4 micro-operations to the downstream execution unit. Alternatively, the dispatching capability of the DISPATCH module may also be limited by its own hardware resources (e.g., the number of channels, the number of ports, etc.), and it may only be able to dispatch 4 micro-operations to the downstream execution unit. As a micro-operation reading end, the UOPQ port (e.g., SLOT-0~SLOT-3) actually outputs only 4 micro-operations that can be effectively dispatched by the DISPATCH module. In the embodiments of the specification, the number of micro-operations read by the UOPQ port corresponding to the micro-operations that can be effectively dispatched by the DISPATCH module is called the number of micro-operations effectively read by the UOPQ port. Since the micro-operations read by the UOPQ port may be parsed into more micro-operations, the number of micro-operations effectively read by the UOPQ port is less than or equal to the number of micro-operations effectively dispatched by the DISPATCH module. By adjusting the number of UOPQ ports, the number of micro-operations read by the UOPQ ports can be matched with the number of micro-operations effectively dispatched by the downstream DISPATCH module (the actual number of UOPQ read micro-operations matches the effective number of UOPQ read micro-operations). This avoids reading micro-operations in UOPQ that far exceed the processing capabilities of the downstream DISPATCH module or execution unit, avoids invalid inversion transitions in UOPQ, and avoids invalid transitions, invalid circuit buffering, and movement in the downstream DISPATCH module and execution unit module, thereby effectively reducing device power consumption.

[0033] As an embodiment of this specification, the effective bandwidth information of the DISPATCH module includes: the number of effectively dispatched micro-operations, the available resource TOKEN of the execution unit corresponding to the effectively dispatched micro-operations, and the type of the effectively dispatched micro-operations.

[0034] In this embodiment, the effective bandwidth information of the DISPATCH module may include the number of micro-operations that are effectively dispatched (i.e., the effective bandwidth of the DISPATCH module hardware). When the hardware bandwidth of the DISPATCH module becomes small due to the large number of micro-operations being processed (i.e., the effective bandwidth resources of the DISPATCH module are tight), the number of micro-operations read by the UOPQ port can be adjusted so that the number of micro-operations effectively read by the UOPQ port matches the number of micro-operations effectively dispatched by the downstream DISPATCH module.

[0035] In another embodiment, the effective bandwidth information of the DISPATCH module may further include the available resources (TOKEN) of the execution unit corresponding to the effectively dispatched micro-operation, and the type of the effectively dispatched micro-operation. The execution unit can execute micro-operations to achieve corresponding functions. The available resources (TOKEN) refer to execution units that have not executed micro-operations, or the ISSUE QUEUE corresponding to the micro-operation execution unit has the capacity to accommodate micro-operations, or the execution unit is not running at full capacity when executing micro-operations and still has resources to process other micro-operations. The value of TOKEN may be the number of micro-operations that the execution unit can accept. The type of micro-operation may include, for example, floating-point arithmetic micro-operations, fixed-point arithmetic micro-operations, memory access micro-operations, etc. The types of micro-operations can also be further subdivided; for example, floating-point arithmetic micro-operations may further include specific operation types such as addition, multiplication, and vector operations.

[0036] When the available resources (TOKEN) of the execution unit corresponding to the effectively dispatched micro-operation are more or less, for example, when the available resources of the execution unit corresponding to the floating-point operation type are more, the number of micro-operations effectively read by the UOPQ port can be adjusted (for example, the number of UOPQ ports can be adjusted) so that the number of micro-operations effectively read by the UOPQ port of a certain type matches the number of TOKENs of the downstream execution unit that processes the corresponding type of micro-operation, thereby improving the processor's processing efficiency and reducing the device's power consumption.

[0037] As an embodiment of this specification, adjusting the number of effective read micro-operations of the UOPQ port based on the effective bandwidth information of the DISPATCH module further includes: When the effective bandwidth information of the DISPATCH module indicates continuous congestion, the number of effective read micro-operations of the UOPQ port is reduced. If the effective bandwidth information of the DISPATCH module indicates continuous idleness, then increase the number of effective read micro-operations of the UOPQ port.

[0038] In this embodiment, the effective bandwidth information of the DISPATCH module indicating continuous congestion can mean that the number of micro-operations dispatched by the DISPATCH module is relatively small over multiple consecutive clock cycles, for example, it can be lower than the maximum number of micro-operations dispatched by the DISPATCH module hardware (or a preset threshold); or, the effective bandwidth information of the DISPATCH module indicating continuous idleness can mean that the number of micro-operations dispatched by the DISPATCH module is relatively large over multiple consecutive clock cycles, for example, it can reach the maximum number of micro-operations dispatched by the DISPATCH module hardware (or a preset threshold).

[0039] The number of valid read micro-operations for the UOPQ port can be reduced or increased. This can be done by reducing the number of valid read micro-operations for the UOPQ port to a minimum, such as reducing it to 0 or 1; or by increasing the number of valid read micro-operations for the UOPQ port to a maximum, such as increasing it to the maximum value of the UOPQ port.

[0040] In other embodiments of this specification, reducing or increasing the number of valid read micro-operations of the UOPQ port may also involve reducing or increasing the number of valid read micro-operations of the UOPQ port to a specified number, continuously determining whether the resources of the effective bandwidth information of the DISPATCH module are continuous or idle during subsequent clock cycles, and gradually adjusting the number of valid read micro-operations of the UOPQ port to increase or decrease until the number of valid read micro-operations of the UOPQ port matches the effective bandwidth information of the DISPATCH module.

[0041] As an embodiment of this specification, the effective bandwidth information of the DISPATCH module indicating continuous congestion further includes: Based on the type of micro-operation, the key micro-operations that will be effectively dispatched by the DISPATCH module are marked; When the same key micro-operation of the same type is continuously marked with the same flag, it indicates that the effective bandwidth information of the DISPATCH module is continuously congested.

[0042] In this embodiment, the critical micro-operation can be determined based on at least one of the following methods: the token of the execution unit corresponding to the type of micro-operation effectively dispatched by the DISPATCH module is less than a corresponding threshold; the number of micro-operations of that type effectively dispatched by the DISPATCH module is less than a corresponding threshold; and the difference between the number of micro-operations of that type effectively dispatched by the DISPATCH module and the number of micro-operations effectively read by the UOPQ port is greater than a corresponding threshold. The corresponding threshold for each determination is different.

[0043] The available resources (TOKEN) of the execution unit corresponding to a certain type of micro-operation at the back end of the pipeline can be obtained through the TOKEN information collector. The number of available TOKENs for each type of execution unit can be collected, such as the execution unit of fixed-point arithmetic micro-operation, the execution unit of memory access arithmetic micro-operation, and the execution unit of scheduling micro-operation. Here, TOKEN is the resource identifier of the execution unit, and the number of available TOKENs represents the degree of resource idleness.

[0044] When dispatching micro-operations in the DISPATCH module, the type of the micro-operation that is effectively dispatched can be obtained.

[0045] When the token corresponding to a certain type of micro-operation is less than the first threshold, and the difference between the number of valid dispatched micro-operations of that type and the number of valid read micro-operations of the UOPQ port is greater than the second threshold, then the micro-operation is determined to be a critical micro-operation.

[0046] If the token corresponding to a certain type of micro-operation is greater than the first threshold, and the difference between the number of valid dispatched micro-operations of that type and the number of valid read micro-operations of the UOPQ port is less than the third threshold, then the micro-operation is determined to be a non-critical micro-operation.

[0047] The first, second, and third thresholds can be generated from simulation experiments or preset, and then these two parameters can be adjusted based on the effect of adaptive bandwidth scheduling.

[0048] The critical and non-critical micro-operations determined when the DISPATCH module dispatches micro-operations are marked. These marks can be recorded and stored in registers or memory. Specifically, when the micro-operation dispatched by the DISPATCH module is a critical micro-operation, the dispatch history is marked as 1 (or 0) to represent continuous congestion in the effective bandwidth information of the DISPATCH module. When the micro-operation dispatched by the DISPATCH module is a non-critical micro-operation (or the mark is recorded separately), the dispatch history is marked as 0 (or 1) to represent continuous idleness in the effective bandwidth information of the DISPATCH module. The historical record information formed by multiple micro-operations dispatched by the DISPATCH module can be... Figure 2a and Figure 2bAs shown, Figure 2a The diagram illustrates the dispatch history of an embodiment of this specification. The diagram describes the type of micro-operation dispatched by the DISPATCH module in each clock cycle (each clock cycle in which a valid DISPATCH exists) (e.g., floating-point operation, fixed-point operation, etc.) and whether it is a critical micro-operation (0 or 1). The length of this history depends on a first threshold. If the same marker 1 is recorded continuously for a period of time, it indicates that there are too many micro-operations in the ISSUE QUEUE of the back-end execution unit for that type of micro-operation (e.g., floating-point operation micro-operation) (i.e., the TOKEN value of the floating-point operation is low). At the same time, the number of valid micro-operations dispatched during the dispatch process is small. Figure 2b The diagram shown is a schematic of another dispatch history in an embodiment of this specification. This diagram describes more detailed micro-operation types. For example, floating-point operation-type 0 and floating-point operation-type 1 in the diagram indicate that the floating-point operation type is further distinguished into type 0 (e.g., addition) and type 1 (e.g., multiplication), which can more accurately analyze the available resources in one or more execution units corresponding to the floating-point operation micro-operation at the pipeline back end to perform floating-point addition and floating-point multiplication operations.

[0049] When a series of consecutive 1s (or 0s) accumulate in the historical record, it indicates that the effective bandwidth information of the DISPATCH module indicates continuous congestion; when a series of consecutive 0s (or 1s) accumulate in the historical record, it indicates that the effective bandwidth information of the DISPATCH module indicates continuous idleness.

[0050] When critical micro-operations recorded in the history are not continuous, for example, when a non-critical operation occurs, the critical micro-operations in the history are recounted.

[0051] As an embodiment of this specification, adjusting the number of effective read micro-operations of the UOPQ port includes at least one of the following methods: The number of UOPQ ports can be adjusted by controlling the enable signal of the UOPQ port, thereby adjusting the number of effective read micro-operations of the UOPQ port; or, By controlling the number of micro-operations written to the UOPQ port by the pipeline front end, and waiting for all micro-operations written to the UOPQ port, the number of UOPQ ports is adjusted, thereby regulating the number of effective micro-operations read by the UOPQ port; or, By controlling the number of micro-operations written to the UOPQ port at the pipeline front end, and waiting for all micro-operations at the pipeline front end to be written to the UOPQ port, and after the micro-operations in the UOPQ have been dispatched, the number of UOPQ ports is adjusted, thereby adjusting the number of micro-operations that the UOPQ port can effectively read; or, By redirecting the REDIRECT action to trigger the FLUSH operation at the front end of the pipeline, the number of UOPQ ports is adjusted, thereby adjusting the number of effective read micro-operations of the UOPQ ports.

[0052] In this embodiment, the number of UOPQ ports can be controlled by the enable signal of the UOPQ port, thereby adjusting the number of effective read micro-operations of the UOPQ port. This method can achieve UOPQ port adjustment without latency. Figure 3 The diagram shown is a schematic of the UOPQ port adjustment circuit according to an embodiment of this specification. This diagram illustrates the adjustment circuit within the UOPQ, such as... Figure 3 The 5-level registers and write / read control logic shown receive the decision-maker instruction for UOPQ port adjustment (reduction or increase) and complete the port width switching within one cycle (or switch directly without delay). When a reverse adjustment is received during the adjustment process, the operation is abandoned to prioritize the adjustment speed.

[0053] UOPQ includes five register levels: register 1, register 2, register 3, register 4, and register 5; the register groups are register 2 and register 3, where: Register 1 is an enable signal, indicating whether to reduce the number of UOPQ ports. The default value is 0 (increasing the number of ports). Register 1 can also indicate whether to reduce the number of valid UOPQ read ports. If the enable signal is 1, the number of UOPQ read ports is directly reduced (i.e., the number of ports in the current UOPQ port that read micro-operations is reduced), which directly reduces the power consumption waste introduced by invalid UOPQ transitions.

[0054] Register 2 is a buffer for reading micro-operations from the UOPQ port, including 8 SLOTs (valid0~7 marks whether it is valid, uops0~7 stores the micro-operation), which directly outputs UOP to subsequent modules, as shown in Table 9.

[0055] Register 3 is the main storage array for UOPQ, as shown in Table 8, which stores more UOPs to be buffered.

[0056] Registers 4 and 5 are RdPtr (read pointer) and RdPtrPlus (read pointer + 1) respectively, which control the range of SLOT read from register 3. Register 5 can solve the timing problem of the circuit.

[0057] Read controls 6, 7, and 12 select valid UOPs in register 3 based on RdPtr / RdPtrPlus and output them to subsequent modules. Specifically, based on registers 4 and 5, the number of valid SLOTs read from UOPQ is updated, and new UOP data information is selected through the updated read controls 6 and 7, as shown in read control 12.

[0058] Upon receiving the read control enable information, the read control 10 outputs the valid UOPs in Table 9 according to the adjusted valid read ports as UOPQs.

[0059] Write control 13 implements the write logic of UOP. Type 1 is: if the number of valid micro-operations in register 3 is less than the number of valid read ports of UOPQ, the micro-operations in register 3 and the newly written micro-operations are both written to register 2. Type 2 is: when the number of valid micro-operations in register 3 is greater than the number of valid read ports of UOPQ, the valid micro-operations in register 3 are selected and written to register 2. At the same time, the valid micro-operation data in write operation 13 will be written to register 3.

[0060] When controlling the number of UOPQ ports to decrease the number of UOPQ ports, the number of UOPQ ports is reduced through the following steps: Step 1: Trigger reduction, set the En signal.

[0061] In this step, when the peripheral circuit determines that the number of valid read micro-operations of the UOPQ port needs to be adjusted, it inputs Enable=1 into register 1 (indicating a reduction in the number of UOPQ ports). At this time, the circuit starts polling to check the status of valid0~7 in register 2 (to determine whether the micro-operations of the current UOPQ port can be cleared).

[0062] Step 2: Enter the emptying state and stop receiving new micro-operations.

[0063] In this step, the circuit control write control 13 pauses writing new micro-operations to register 2 (regardless of the number of valid micro-operations in register 3, register 2 will no longer be filled); at the same time, read control 6, 7, and 12 continue to read the UOPs in register 2 according to the original bandwidth logic until all valid0~7 in register 2 are set to 0, that is, all 8 UOPs in register 2 are dispatched, and the emptying is completed.

[0064] Step 3: Fill in the UOP corresponding to the adjusted UOPQ port.

[0065] In this step, after register 2 is emptied, the circuit switches write control 13 to type 1 or type 2. If the number of valid micro-operations in register 3 is greater than 2, the new micro-operation is first written to register 3; then, only 2 valid UOPs are taken from register 3 and filled into the first 2 SLOTs of register 2 (valid0~1 set to 1, uops0~1 stores UOP), while the last 6 SLOTs (valid2~7) remain invalid. If the number of valid data in register 3 is less than 2, and there is a valid micro-operation in register 3, 1 valid micro-operation in register 3 and the newly written micro-operation are combined to form 2 valid UOPs, which are then filled into the first 2 SLOTs of register 2 (valid0~1 set to 1, uops0~1 stores UOP), while the last 6 SLOTs (valid2~7) remain invalid. If the number of valid data in register 3 is 0, 2 valid UOPs are taken from the newly written micro-operation and filled into the first 2 SLOTs of register 2 (valid0~1 set to 1, uops0~1 stores UOP), while the last 6 SLOTs (valid2~7) remain invalid.

[0066] Step 4: Turn off the unused register clock.

[0067] In this step, the RdPtr / RdPtrPlus range of registers 4 and 5 is reduced to 0~1, and UOP is read only from the first two SLOTs of register 2 to achieve read control update; the circuit turns off the register clock corresponding to SLOT2~7 in register 2, and the registers of these SLOTs stop working and no longer consume power; at this time, register 2 only outputs the UOP of the first two SLOTs to the DISPATCH module, thereby reducing the number of UOPQ ports and thus reducing the number of effective read micro-operations of UOPQ ports.

[0068] When controlling the number of UOPQ ports to increase the number of UOPQ ports, the number of UOPQ ports is increased through the following steps: Step 1: Trigger increase, set the En signal to 0.

[0069] In this step, when the peripheral circuit determines that an additional port needs to be added, it inputs Enable=0 into register 1. The circuit then polls the valid0~1 status of register 2 and waits for it to be cleared.

[0070] Step 2: Empty the micro-operations of the current two ports.

[0071] In this step, write control 13 pauses writing data to register 2, and simultaneously pauses reading data from register 3 and writing it into register 2. Read control continues reading the first two slots of register 2 until valid0~1 is set to 0 (both UOPs are dispatched).

[0072] Step 3: Prefetch 8 UOPs and fill 8 SLOTs in register 2.

[0073] In this step, write control 13 switches back to type 1. If the number of valid micro-operations in register 3 is less than 8, all micro-operations in register 3 and the newly read micro-operations are written to register 2. Eight valid UOPs are taken from register 3 or the input terminal and filled into the eight SLOTs of register 2 (valid0~7 are all set to 1). Alternatively, write control 13 switches back to type 2. Write control 13 writes the latest data into register 3, and at the same time, writes the micro-operations in register 3 into the eight SLOTs of register 2 (valid0~7 are all set to 1).

[0074] Step 4: Turn on the clock and restore the 8 bandwidths to work.

[0075] In this step, RdPtr / RdPtrPlus is restored to the range of 0~7, covering all SLOTs to achieve read control update; the register clock of SLOT2~7 in register 2 is turned on, and all 8 SLOTs resume operation; register 2 outputs the UOP of the 8 SLOTs to the DISPATCH module to increase the number of UOPQ ports, thereby increasing the number of effective read micro-operations of the UOPQ ports.

[0076] Through register 3 in the UOPQ port adjustment circuit of this specification embodiment, and the read / write control logic for reducing and increasing UOPQ ports, new micro-operations can be buffered using register 3. The read control logic reads the micro-operations in register 2 and sends them to the downstream processing logic of the pipeline (e.g., the DISPATCH module) for dispatching micro-operations. When the micro-operations in register 2 are emptied, the write control logic can obtain the adjusted number of valid read micro-operations and write them into register 2, or obtain the adjusted number of valid read micro-operations from register 3 and write them into register 2, or obtain the adjusted number of valid read micro-operations from register 3 and the write control logic and write them into register 2. By controlling the number of UOPQ ports, the number of valid read micro-operations of the UOPQ ports can be adjusted.

[0077] In other embodiments, it may also be as follows: Figure 4The diagram illustrates a blocking write operation in an embodiment of this specification. By controlling the number of micro-operations written to the UOPQ port by the pipeline front end, and waiting for all micro-operations written to the UOPQ port, the number of UOPQ ports is adjusted, thereby adjusting the number of effective micro-operations read by the UOPQ port. When an instruction to adjust the number of effective micro-operations read by the UOPQ port is generated (e.g., reducing the number of effective micro-operations read from 8 to 2), a STALL signal is sent to the instruction decoding channel and the OC (Op Cache) instruction fetch channel; wait for N cycles (e.g., N=3 for a 3-stage pipeline) to ensure that there are no micro-operations not written to UOPQ in the pipeline; then adjust the UOPQ port, switch the read pointer to SLOT0~1, and turn off the clocks of SLOT2~7; after confirming that the UOPQ port configuration is complete, set the STALL signal low, allowing the instruction decoding channel and the OC instruction fetch channel to write new micro-operations to UOPQ; UOPQ reads micro-operations at 2 ports. For example, the decision maker determines that the number of micro-operations read from the UOPQ port needs to be reduced to 2, and sends a STALL signal to the instruction decoding channel; waits for 3 cycles, and all 3 in-flight micro-operations (micro-operations that have not been dispatched) in the pipeline are written to UOPQ and dispatched; adjusts the read pointer to SLOT0~1, and turns off the clock of the remaining 6 SLOTs; sets the STALL signal low, and writes the new micro-operations to UOPQ in 2 ports to avoid conflicts caused by data residue during switching.

[0078] In other embodiments, such as Figure 4 As shown, the number of micro-operations written to the UOPQ port by the pipeline front end can also be controlled. After all the micro-operations at the pipeline front end are written to the UOPQ port, and after the micro-operations in the UOPQ are dispatched, the number of UOPQ ports can be adjusted, thereby adjusting the number of micro-operations effectively read by the UOPQ port. The difference from the previous embodiment is that in this embodiment, after all the micro-operations at the pipeline front end are written to the UOPQ port, it is also necessary to wait for the micro-operations in the UOPQ to be dispatched before adjusting the number of UOPQ ports. For the sake of simplicity, the similarities between this embodiment and the previous embodiment will not be repeated.

[0079] In other embodiments, it may also be as follows: Figure 5The diagram illustrates an embodiment of this specification that uses a pipeline front-end clearing operation to adjust the number of UOPQ ports. A REDIRECT action triggers a FLUSH operation at the pipeline front-end, clearing all micro-operations in the UOPQ ports. The number of UOPQ ports is then adjusted via their enable signals, thereby regulating the number of effective micro-operations read by each UOPQ port. By using the REDIRECT action to FLUSH the pipeline front-end (branch prediction unit, instruction fetch unit, etc.), all unfinished micro-operations read by the UOPQ ports are cleared, and the execution start point is redirected, readjusting the number of UOPQ ports and simplifying the adjustment circuit design. For example, the decision-maker determines that the number of valid micro-operations read from the UOPQ port needs to be increased to 8, triggering the REDIRECT action; the REDIRECT signal triggers FLUSH, clearing any pending micro-operations or instructions in the instruction fetch unit, instruction decoding channel, and OC instruction fetch channel at the front end of the pipeline; while clearing UOPQ, the UOPQ port is adjusted, the read pointer covers slots 0~7, and all SLOT clocks are turned on; REDIRECT specifies a new execution start point (the current program counter PC), and the pipeline fetches and decodes instructions from this address again; the new micro-operations are written to the UOPQ port with an 8-port bandwidth, the system returns to normal, and the port adjustment is completed.

[0080] For example, in the current state: the number of valid micro-operations read by the UOPQ port is 2 (i.e., 2 SLOTs), the historical FLUSH recovery time is 3 cycles, the current IPC is 95% of the baseline value, and the maximum token capacity of the execution unit is 8. The decision-maker determines that the UOPQ port bandwidth needs to be restored for 8 micro-operations, triggering the REDIRECT action; FLUSH clears the 3 pending instructions in the instruction fetch unit and the 2 undisassembled micro-operations in the instruction decoding channel; the UOPQ port is adjusted to 8, the read pointer covers all 8 SLOTs, and the clock is fully enabled; the pipeline fetches instructions again from the current PC value, 8 new micro-operations are written to UOPQ, the DISPATCH module dispatches according to the bandwidth of 8 micro-operations, and the performance is fully restored after 3 cycles, with no data interference during the adjustment process.

[0081] As one embodiment of this specification, after reducing the number of effective read micro-operations of the UOPQ port, the following is also included: Monitor the number of micro-operations effectively dispatched by the DISPATCH module; If the number of micro-operations effectively dispatched by the DISPATCH module is consistently lower than a preset threshold, the number of micro-operations effectively read by the UOPQ port will be increased.

[0082] In this embodiment, when the number of effective micro-operations read by the UOPQ port is reduced, the number of effective micro-operations dispatched by the DISPATCH module remains below a preset threshold. In order to prevent the processor performance from degrading, the number of effective micro-operations read by the UOPQ port can be increased, for example, the full micro-operation read capability of the UOPQ port can be restored.

[0083] In another embodiment, if the difference between the number of micro-operations effectively read by the UOPQ port and the number of micro-operations actually effectively dispatched by the DISPATCH module continuously exceeds a certain preset threshold after the number of micro-operations effectively read by the UOPQ port is reduced, for example, it can be increased to the maximum. Here, "continuously" can be a predetermined time period, multiple consecutive clock cycles, or multiple consecutive effective dispatches. The micro-operations effectively dispatched by the DISPATCH module refer to the micro-operations dispatched by the DISPATCH module to the downstream execution units of the pipeline that can be executed. The micro-operations that the DISPATCH module can dispatch refer to the micro-operations that the downstream execution units of the pipeline can still receive and process, i.e., the available resources of the execution units.

[0084] By monitoring the number of micro-operations effectively dispatched by the DISPATCH module, the number of effective micro-operations read by the UOPQ port can be increased in real time, thereby improving the processor's processing efficiency and avoiding the problem of excessive adjustment of effective micro-operations read by the UOPQ port, which would reduce the processor's processing efficiency.

[0085] As one embodiment of this specification, after reducing the number of effective read micro-operations of the UOPQ port, the following is also included: Monitor changes in processor performance (Instructions Per Cycle, IPC); As the DISPATCH module completes the dispatch of micro-operations, if the IPC remains below a preset threshold, the number of micro-operations effectively read by the UOPQ port will be increased.

[0086] In this step, before bandwidth adjustment, the IPC value under stable processor conditions is recorded in the historical data. For example, an average IPC of 5 over 10 consecutive cycles is used as a preset threshold for judging performance degradation. If the IPC is lower than the preset threshold for a certain duration or clock cycle, performance degradation can be considered, triggering an error correction mechanism to increase the number of valid read micro-operations on the UOPQ port, for example, by increasing it to the maximum.

[0087] In another embodiment, after the number of valid read micro-operations of the UOPQ port is reduced, the number of execution units (TOKENs) at the back end of the processor pipeline is monitored; as the DISPATCH module completes the dispatch of micro-operations, if the number of TOKENs corresponding to a certain type of micro-operation continues to be higher than a preset threshold, and if there are still micro-operations of that type in the DISPATCH module, then the number of valid read micro-operations of the UOPQ port is adjusted to be increased.

[0088] By monitoring changes in processor performance IPC through this embodiment, the number of effective read micro-operations of the UOPQ port can be increased in real time, thereby improving the processor's processing efficiency and avoiding the problem of excessive adjustment of effective read micro-operations of the UOPQ port, which would reduce the processor's processing efficiency.

[0089] like Figure 6 The diagram shown is a schematic representation of the adaptive bandwidth scheduling device according to an embodiment of this specification. This diagram illustrates a device for operating the methods described in the above embodiments. Each functional module can be implemented through circuits, or the functions of each module can be accomplished through a combination of instruction sets and circuits. Specifically, the device includes: The acquisition unit 601 is configured to acquire the effective bandwidth information of the instruction dispatch DISPATCH module; Decision maker 602 is configured to adjust the number of effective read micro-operations of the UOPQ port based on the effective bandwidth information of the DISPATCH module.

[0090] like Figure 7 The diagram shown is a structural schematic of the instruction dispatch unit according to an embodiment of this specification. The internal structure of the instruction dispatch unit is illustrated in this diagram. The functional components can be implemented using hardware circuitry or a combination of instruction sets and hardware circuitry. Not all functional modules are required in this diagram; only a portion of the functional modules are needed to achieve the desired purpose. Specifically, the instruction dispatch unit includes: UOPQ module 701, intermediate processing module 702, dispatch module 703, information collection module 704, TOKEN module 705, type recognition module 706, history record module 707, decision module 708, performance monitoring module 709, execution unit 710.

[0091] The UOPQ module 701 is configured to read a specified number of micro-operations and transmit them to the intermediate processing module 702 according to the control of the decision module 708. The intermediate processing module 702 is configured to send the micro-operations read by the UOPQ module 701 to the dispatch module 703; The dispatch module 703 is configured to dispatch micro-operations to the corresponding execution unit 710; The information collection module 704 is configured to acquire the effective bandwidth information of the dispatch module 703; The TOKEN module 705 is configured to acquire available resources of the execution unit 710; The type identification module 706 is configured to identify the type of micro-operation that has been effectively dispatched; The history recording module 707 is configured to record information about the micro-operations dispatched by the dispatch module 703; The decision module 708 is configured to adjust the number of effective micro-operations read by the UOPQ port of the UOPQ module 701 according to the information collection module 704.

[0092] In another embodiment, the decision module 708 is configured to adjust the number of effective read micro-operations of the UOPQ port of the UOPQ module 701 according to the dispatch module 703, the TOKEN module 705, the type recognition module 706, and the history module 707.

[0093] The performance monitoring module 709 is configured to monitor the system performance of the processor and feed back the changes in system performance to the decision module 708, so that the decision module 708 can adjust the number of effective read micro-operations of the UOPQ port of the UOPQ module 701 according to the changes in system performance.

[0094] Step 1: Collect data from multiple modules.

[0095] In this step, the information collection module 704, the TOKEN module 705, the type recognition module 706, the historical record module 707, and the performance monitoring module 709 work synchronously to output full-dimensional data to the decision-making module 708 to ensure accurate decision-making.

[0096] Specifically, the information collection module 704 collects in real time the effective read bandwidth of the UOPQ module 701 (the number of micro-operations that can be read by the UOPQ port corresponding to the micro-operations that can be effectively dispatched by the DISPATCH module) and the number of micro-operations effectively dispatched by the dispatch module 703. This yields the number of micro-operations effectively read by the UOPQ module 701 and the number of micro-operations effectively dispatched by the dispatch module 703.

[0097] The TOKEN module 705 iterates through fixed-point (EX), floating-point (FP), and memory access (LSU) execution units to count the available TOKENs for each execution unit.

[0098] The type identification module 706 parses the micro-operations of the DISPATCH GROUP of the dispatch module 703, classifies them by function (fixed-point / floating-point / memory access, including subdivision types 0 / 1 / 2), and marks the micro-operation type.

[0099] The history module 707 retrieves the number of valid dispatch micro-operations, the number of TOKENs in each execution unit, the instruction type, and the port adjustment records from the dispatch module 703 for multiple historical cycles (or multiple valid dispatch counts).

[0100] The performance monitoring module 709 collects real-time values ​​of the current IPC (instructions per cycle) and the number of DISPATCH micro-operations, compares them with historical baseline values ​​(stable values ​​before adjustment), and outputs the performance fluctuation status.

[0101] All module output data is synchronously transmitted to decision module 708 via the internal bus.

[0102] Step 2: Decision module 708 determines key micro-operations.

[0103] In this step, the decision module 708 combines the number of micro-operations dispatched by the information collection module 704, the number of tokens in the token module 705, and the type of micro-operation in the type identification module 706 to determine the critical micro-operation (the type of UOP that causes bandwidth limitation).

[0104] Specifically, key operations can be determined using one or a combination of the following methods: Based on the number of micro-operations of this type that are effectively dispatched by the DISPATCH module and output by the information collection module 704, determine whether the number is less than the second threshold. Alternatively, the difference between the number of micro-operations of this type effectively dispatched by the DISPATCH module and the number of micro-operations effectively read by the UOPQ port is greater than the third threshold. Alternatively, based on the TOKEN value of the execution unit corresponding to the type of micro-operation effectively dispatched by the DISPATCH module output by the TOKEN module 705, determine whether the value is less than the first threshold. The decision module 708 marks micro-operations that meet the conditions as critical micro-operations and records them in the history module 707; it starts a counter to record the number of consecutive cycles in which the judgment conditions are met, and if a certain cycle is not met, the counter is cleared to zero.

[0105] Step 3: The decision module 708 determines whether the duration or number of key micro-operations in the history module 707 has reached a specified threshold. If the specified threshold is reached, the number of micro-operations effectively read by the UOPQ port needs to be reduced.

[0106] In this step, if the duration of a critical micro-operation reaches a predetermined threshold, it indicates that the effective bandwidth information of the DISPATCH module is continuously congested, and the number of effective read micro-operations on the UOPQ port needs to be reduced.

[0107] Specifically, based on the key micro-operation judgment results of the decision module 708, historical information is marked periodically. If the judgment condition is met, it is marked as 1 (resource shortage); otherwise, it is marked as 0 (resource abundance). The marking results are stored to form a historical sequence (e.g., cycle0=1, cycle1=1, cycle2=1, cycle3=1), and the sequence length is determined by a first threshold (e.g., first threshold=5, sequence length=5). The decision module 708 triggers a judgment, retrieves the number of consecutive 1 marks from the historical record module 707, and compares it with a specified threshold. If the number of consecutive 1 marks is greater than or equal to the specified threshold, it is determined that the number of UOPQ ports needs to be reduced.

[0108] Step 4: Decision module 708 adjusts the number of ports of UOPQ module 701.

[0109] In this step, the decision module 708 sends an adjustment command to the UOPQ module 701, and the intermediate processing module 702 adapts to the new port width synchronously.

[0110] Specifically, the decision module 708 outputs instructions to synchronously send port adjustments (e.g., read port range is slot0~3) to the intermediate processing module 702.

[0111] The Enable signal of register 1 of UOPQ module 701 is set to 1 (start port reduction); the valid status of register 2 is polled and the emptying stage is entered; the range is adjusted to SLOT0~3 through register 4 / 5, and SLOT4~7 is no longer read; the clock gating module turns off the register clock of SLOT4~7 to reduce invalid power consumption; after emptying is completed, 4 UOPs are prefetched from the main memory array (register 3) to fill SLOT0~3.

[0112] After adjusting the receiving port of the intermediate processing module 702, the working range of the mapping and arbiter is adjusted, processing only the UOPs of SLOT0~3 output by the UOPQ module 701 to avoid data flow outside the range and reduce circuit jumps. The number of ports of the UOPQ module 701 becomes 4, outputting only 4 UOPs / cycle, matching the effective dispatch of the dispatch module 703 and eliminating bandwidth differences.

[0113] Step 5: The decision module 708 restores the UOPQ module 701 port based on the monitoring results of the performance monitoring module 709.

[0114] In this step, the performance monitoring module 709 acquires processor performance data in real time, including IPC and the number of micro-operations effectively dispatched by the dispatch module 703. The decision module 708 decides whether to increase or restore the port resources of the UOPQ module 701 based on the processor performance data.

[0115] Specifically, when the available resources (TOKEN) of the execution unit are continuously greater than a preset threshold, the decision module 708 can adjust the number of ports of the UOPQ module 701. For specific methods, please refer to the aforementioned embodiments.

[0116] The methods and apparatus described in the embodiments of this specification can reduce the power consumption of the processor without changing its performance.

[0117] In one embodiment of this specification, a processor including the above-described instruction dispatch unit can execute the aforementioned adaptive bandwidth scheduling method to reduce the processor's power consumption.

[0118] like Figure 8 The diagram illustrates a computer device according to an embodiment of this specification. The computer device in this embodiment may include the processor described in this specification and utilize the aforementioned inter-chip communication method. This method can also be run on the computer device in this embodiment to execute the methods described in this specification. The computer device 802 may include one or more processors 804, such as one or more central processing units (CPUs), each of which can implement one or more hardware threads. The computer device 802 may also include any memory 806 for storing information of any kind, such as code, settings, data, etc. Non-limitingly, for example, memory 806 may include any type of RAM, any type of ROM, flash memory, hard disk, optical disk, etc. More generally, any memory can use any technology to store information. Further, any memory can provide volatile or non-volatile retention of information. Further, any memory can represent a fixed or removable component of the computer device 802. In one case, when the processor 804 executes associated instructions stored in any memory or combination of memories, the computer device 802 can perform any operation of the associated instructions. The computer device 802 also includes one or more drive mechanisms 808 for interacting with any memory, such as a hard disk drive mechanism, an optical disk drive mechanism, etc.

[0119] Computer device 802 may also include an input / output module 810 (I / O) for receiving various inputs (via input device 812) and providing various outputs (via output device 814). A specific output mechanism may include a presentation device 816 and an associated graphical user interface (GUI) 818. In other embodiments, the input / output module 810 (I / O), input device 812, and output device 814 may be omitted, and the device may function solely as a computer device within a network. Computer device 802 may also include one or more network interfaces 820 for exchanging data with other devices via one or more communication links 822. One or more communication buses 824 couple the components described above together.

[0120] Communication link 822 can be implemented in any way, such as via a local area network, a wide area network (e.g., the Internet), a point-to-point connection, or any combination thereof. Communication link 822 may include any combination of hardwired links, wireless links, routers, gateway functions, name servers, etc., governed by any protocol or combination of protocols.

[0121] This specification also provides a computer-readable instruction that, when executed by a processor, causes the processor to perform the method described above.

[0122] This specification also provides a computer-readable storage medium storing a computer program that, when executed by a processor, performs the methods described above.

[0123] This specification also provides a computer program product, which includes a computer program that, when executed by a processor, implements the above-described method.

[0124] It should be understood that in the various embodiments of this specification, the sequence number of each process does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this specification.

[0125] It should also be understood that, in the embodiments of this specification, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this specification generally indicates that the preceding and following related objects have an "or" relationship.

[0126] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed in this specification can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of each example have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this specification.

[0127] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0128] In the several embodiments provided in this specification, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the couplings or direct couplings or communication connections shown or discussed may be indirect couplings or communication connections through some interfaces, devices, or units, or they may be electrical, mechanical, or other forms of connection.

[0129] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of the embodiments described in this specification, depending on actual needs.

[0130] Furthermore, the functional units in the various embodiments of this specification can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0131] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this specification, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this specification. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0132] This specification uses specific embodiments to illustrate the principles and implementation methods of this specification. The descriptions of the above embodiments are only for the purpose of helping to understand the methods and core ideas of this specification. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this specification. Therefore, the content of this specification should not be construed as a limitation of this specification.

Claims

1. An adaptive bandwidth scheduling method, characterized in that, include: Obtain the effective bandwidth information of the instruction dispatch DISPATCH module; Based on the effective bandwidth information of the DISPATCH module, adjust the number of micro-operations that can be effectively read by the UOPQ port of the micro-operation queue.

2. The method according to claim 1, characterized in that, The number of micro-operations effectively read by the UOPQ port includes: the number of micro-operations that can be effectively dispatched by the DISPATCH module and read by the UOPQ port; the effective bandwidth information of the DISPATCH module includes: the number of micro-operations that are effectively dispatched.

3. The method according to claim 2, characterized in that, The effective bandwidth information of the DISPATCH module also includes: the available resource TOKEN of the execution unit corresponding to the effectively dispatched micro-operation, and the type of the effectively dispatched micro-operation.

4. The method according to claim 3, characterized in that, Adjusting the number of effective read micro-operations of the UOPQ port based on the effective bandwidth information of the DISPATCH module further includes: When the effective bandwidth information of the DISPATCH module indicates continuous congestion, the number of effective read micro-operations of the UOPQ port is reduced. If the effective bandwidth information of the DISPATCH module indicates continuous idleness, then increase the number of effective read micro-operations of the UOPQ port.

5. The method according to claim 4, characterized in that, The effective bandwidth information of the DISPATCH module, indicating persistent congestion, further includes: Based on the type of micro-operation, the key micro-operations that will be effectively dispatched by the DISPATCH module are marked; When the same key micro-operation of the same type is continuously marked with the same flag, it indicates that the effective bandwidth information of the DISPATCH module is continuously congested.

6. The method according to claim 5, characterized in that, The type includes at least one of the following: Floating-point arithmetic micro-operations, fixed-point arithmetic micro-operations, and memory access micro-operations.

7. The method according to claim 6, characterized in that, The type further includes the specific operation type for each micro-operation.

8. The method according to claim 5, characterized in that, Micro-operations that meet one or a combination of the following conditions are designated as critical micro-operations: The TOKEN of the execution unit corresponding to the type of micro-operation effectively dispatched by the DISPATCH module is less than the first threshold. The number of micro-operations of this type that are effectively dispatched by the DISPATCH module is less than the second threshold; The difference between the number of micro-operations of this type effectively dispatched by the DISPATCH module and the number of micro-operations effectively read by the UOPQ port is greater than the third threshold.

9. The method according to claim 8, characterized in that, The effective bandwidth information of the DISPATCH module indicating continuous idleness further includes: Based on the type of micro-operation, non-critical micro-operations that will be effectively dispatched by the DISPATCH module will be marked; When consecutive markers of the same type of non-critical micro-operation reach a specified threshold, it indicates that the effective bandwidth information of the DISPATCH module is continuously idle.

10. The method according to claim 9, characterized in that, Micro-operations that meet one or a combination of the following conditions are classified as non-critical micro-operations: The TOKEN of the execution unit corresponding to the type of micro-operation effectively dispatched by the DISPATCH module is greater than the first threshold. The number of micro-operations of this type that are effectively dispatched by the DISPATCH module is greater than the second threshold; The difference between the number of micro-operations of this type effectively dispatched by the DISPATCH module and the number of micro-operations effectively read by the UOPQ port is less than the third threshold.

11. The method according to claim 1, characterized in that, Adjusting the number of effective read micro-operations of the UOPQ port includes at least one of the following methods: The number of UOPQ ports can be adjusted by using the UOPQ port enable signal, thereby regulating the number of effective read micro-operations by the UOPQ port; or, By controlling the number of micro-operations written to the UOPQ port by the pipeline front end, and waiting for all micro-operations written to the UOPQ port, the number of UOPQ ports is adjusted, thereby regulating the number of effective micro-operations read by the UOPQ port; or, By controlling the number of micro-operations written to the UOPQ port at the pipeline front end, and waiting for all micro-operations at the pipeline front end to be written to the UOPQ port, and after the micro-operations in the UOPQ have been dispatched, the number of UOPQ ports is adjusted, thereby adjusting the number of micro-operations that the UOPQ port can effectively read; or, By redirecting the REDIRECT action to trigger the FLUSH operation at the front end of the pipeline, the number of UOPQ ports is adjusted, thereby adjusting the number of effective read micro-operations of the UOPQ ports.

12. The method according to claim 4, characterized in that, After reducing the number of effective read micro-operations on the UOPQ port, the following are also included: Monitor the number of micro-operations effectively dispatched by the DISPATCH module; If the number of micro-operations effectively dispatched by the DISPATCH module is consistently lower than a preset threshold, the number of micro-operations effectively read by the UOPQ port will be increased.

13. The method according to claim 4, characterized in that, After reducing the number of effective read micro-operations on the UOPQ port, the following are also included: Monitor changes in processor performance IPC; As the DISPATCH module completes the dispatch of micro-operations, if the IPC remains below a preset threshold, the number of micro-operations effectively read by the UOPQ port will be increased.

14. The method according to claim 4, characterized in that, After reducing the number of effective read micro-operations on the UOPQ port, the following are also included: Monitor the number of execution unit tokens at the back end of the processor pipeline; As the DISPATCH module completes the dispatch of micro-operations, if the number of TOKENs corresponding to a certain type of micro-operation continues to exceed a preset threshold, and if there are still micro-operations of that type in the DISPATCH module, then the number of micro-operations effectively read by the UOPQ port will be increased.

15. An adaptive bandwidth scheduling device, characterized in that... include: The acquisition unit is configured to acquire the effective bandwidth information of the instruction dispatch DISPATCH module. The decision-maker is configured to adjust the number of effective read micro-operations of the UOPQ port based on the effective bandwidth information of the DISPATCH module.

16. An instruction dispatching unit, characterized in that, The instruction dispatching unit executes the adaptive bandwidth scheduling method according to any one of claims 1-14.

17. A processor, characterized in that... Includes the instruction dispatching unit as described in claim 16.

18. A computer device comprising a memory and a computer program stored in the memory and executable on a processor, characterized in that, Includes the processor as described in claim 17 above.

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