Display device

Abstract

A display device includes a light emitting diode electrically connected between a driving voltage line and a common voltage line; a driving transistor electrically connected between the driving voltage line and the light emitting diode; a second transistor electrically connected between a first electrode of the driving transistor and a data line, the first electrode of the driving transistor being electrically connected to the driving voltage line; a first scan line electrically connected to a gate electrode of the second transistor; a third transistor electrically connected between a second electrode of the driving transistor and a gate electrode of the driving transistor, the second electrode of the driving transistor being electrically connected to the light emitting diode; a second scan line electrically connected to a gate electrode of the third transistor; and a connection electrode electrically connected to the gate electrode of the driving transistor at a first contact portion and electrically connected to the third transistor at a second contact portion, the connection electrode including a first portion extending in a first direction and a second portion electrically connected to the first portion and extending in a second direction different from the first direction.

Description

[0001] This application is a divisional application of application number 202110575674.4 filed on May 26, 2021, entitled "Display Device". Technical Field

[0002] This disclosure relates to a display device. Background Technology

[0003] An organic light-emitting display device includes two electrodes and an organic light-emitting layer between them. Electrons injected from one electrode and holes injected from the other electrode recombine in the organic light-emitting layer to form excitons. The excitons transition from the excited state to the ground state, releasing energy and emitting light.

[0004] Such an organic light-emitting display device includes multiple pixels, each comprising an organic light-emitting diode (OLED) as a self-emissive element. Each pixel has multiple transistors for driving the OLED and one or more capacitors. The multiple transistors can essentially include switching transistors and driving transistors.

[0005] Each pixel may include a transistor that transmits a compensation voltage. The path for transmitting this compensation voltage overlaps with a portion of the wiring, increasing resistance and potentially preventing proper transmission of the compensation voltage. This results in the detection of horizontal stripes. Summary of the Invention

[0006] The embodiments are intended to provide a display device that can smoothly transmit compensation voltage by reducing the resistance of the path through which the compensation voltage is transmitted.

[0007] The embodiments are intended to provide a display device that can thereby improve horizontal line patterns.

[0008] A display device according to one embodiment includes: a light-emitting diode (LED) electrically connected between a driving voltage line and a common voltage line; a driving transistor electrically connected between the driving voltage line and the LED; a second transistor electrically connected between a first electrode of the driving transistor and a data line, the first electrode of the driving transistor being electrically connected to the driving voltage line; a first scan line electrically connected to the gate electrode of the second transistor; a third transistor electrically connected between a second electrode of the driving transistor and the gate electrode of the driving transistor, the second electrode of the driving transistor being electrically connected to the LED; a second scan line electrically connected to the gate electrode of the third transistor; and a connection electrode electrically connected to the gate electrode of the driving transistor at a first contact portion and electrically connected to the third transistor at a second contact portion, the connection electrode including a first portion extending in a first direction and a second portion electrically connected to the first portion and extending in a second direction different from the first direction.

[0009] A display device according to one embodiment includes: a light-emitting diode (LED) electrically connected between a driving voltage line and a common voltage line; a driving transistor electrically connected between the driving voltage line and the LED; a second transistor electrically connected between a first electrode of the driving transistor and a data line, the first electrode of the driving transistor being electrically connected to the driving voltage line; a first scan line electrically connected to the gate electrode of the second transistor; a third transistor electrically connected between a second electrode of the driving transistor and the gate electrode of the driving transistor, the second electrode of the driving transistor being electrically connected to the LED; a second scan line electrically connected to the gate electrode of the third transistor; and a connecting electrode electrically connected to the gate electrode of the driving transistor at a first contact portion and to the third transistor at a second contact portion, at least a portion of the second contact portion not overlapping the first scan line in a plane.

[0010] A display device according to one embodiment includes: a substrate; a light-emitting diode (LED) on the substrate; a driving transistor electrically connected between a driving voltage line and the LED; a second transistor electrically connected between a first electrode of the driving transistor and a data line, the first electrode of the driving transistor being electrically connected to the driving voltage line; a first scan line electrically connected to the gate electrode of the second transistor; a third transistor electrically connected between a second electrode of the driving transistor and the gate electrode of the driving transistor, the second electrode of the driving transistor being electrically connected to the LED; a second scan line electrically connected to the gate electrode of the third transistor; and a connection electrode electrically connected to the gate electrode of the driving transistor at a first contact portion and electrically connected to the third transistor at a second contact portion, the connection electrode including a first portion extending in a first direction and a second portion connected to the first portion and extending in a second direction different from the first direction.

[0011] A display device according to one embodiment includes: a light-emitting diode (LED) connected between a driving voltage line to which a driving voltage is applied and a common voltage line to which a common voltage is applied; a driving transistor connected between the driving voltage line and the LED; a second transistor connected between a first electrode of the driving transistor connected to the driving voltage line and a data line to which a data voltage is applied; a first scan line connected to the gate electrode of the second transistor and extending in a first direction; a third transistor connected between a second electrode of the driving transistor connected to the LED and the gate electrode of the driving transistor; a second scan line connected to the gate electrode of the third transistor; and a connecting electrode connected to the gate electrode of the driving transistor through a first opening and to the third transistor through a second opening, wherein the second scan line is located in a conductive layer different from the first scan line, and at least a portion of a contact portion of the connecting electrode in contact with the third transistor within the second opening is located in a plane between the first scan line and the second scan line.

[0012] A display device according to one embodiment includes: a light-emitting diode connected between a driving voltage line to which a driving voltage is applied and a common voltage line to which a common voltage is applied; a driving transistor connected between the driving voltage line and the light-emitting diode; a second transistor connected between a first electrode of the driving transistor connected to the driving voltage line and a data line to which a data voltage is applied; a first scan line connected to the gate electrode of the second transistor; a third transistor connected between the second electrode of the driving transistor connected to the light-emitting diode and the gate electrode of the driving transistor; and a connecting electrode connecting the gate electrode of the driving transistor and the third transistor, wherein at least a portion of the contact portion of the connecting electrode and the third transistor in contact with each other does not overlap with the first scan line.

[0013] Alternatively, the contact portion may not overlap with the first scan line.

[0014] The third transistor may include: a first electrode connected to the first electrode of the driving transistor; a second electrode connected to the connection electrode; a channel located between the first electrode and the second electrode; and a gate electrode overlapping the channel, wherein the second electrode of the third transistor overlaps with the connection electrode.

[0015] Alternatively, the display device according to one embodiment may further include: an insulating layer located between the second electrode of the third transistor and the connecting electrode, the insulating layer including an opening that overlaps with the second electrode of the third transistor and the connecting electrode, the second electrode of the third transistor being connected to the connecting electrode through the opening, the opening not overlapping with the first scan line.

[0016] Alternatively, the contact portion may be located within the opening.

[0017] Alternatively, the display device according to one embodiment may further include: a second scan line connected to the gate electrode of the third transistor, wherein the opening is located in a plane between the first scan line and the second scan line.

[0018] Alternatively, one side edge of the opening may coincide with one side edge of the first scan line.

[0019] Alternatively, the connecting electrode may overlap with the first scan line.

[0020] Alternatively, the opening may be separated from the first scan line.

[0021] Alternatively, the connecting electrode may not overlap with the first scan line.

[0022] Alternatively, the driving transistor and the second transistor may comprise polycrystalline semiconductors and be composed of p-type transistors, and the third transistor may comprise oxide semiconductors and be composed of n-type transistors.

[0023] Alternatively, at the same timing, a voltage of opposite polarity to the voltage applied to the first scan line can be applied to the second scan line.

[0024] Alternatively, the display device according to one embodiment may further include: a boost capacitor connected between the gate electrode of the second transistor and the second electrode of the third transistor, wherein the contact portion does not overlap with the boost capacitor.

[0025] Alternatively, a portion of the contact portion may overlap with the first scan line, while the remaining portion of the contact portion may not overlap with the first scan line.

[0026] The third transistor may include: a first electrode connected to the first electrode of the driving transistor; a second electrode connected to the connection electrode; a channel located between the first electrode and the second electrode; and a gate electrode overlapping the channel, wherein the second electrode of the third transistor overlaps with the connection electrode.

[0027] Alternatively, the display device according to one embodiment may further include: an insulating layer located between the second electrode of the third transistor and the connecting electrode, the insulating layer including an opening that overlaps with the second electrode of the third transistor and the connecting electrode, the second electrode of the third transistor being connected to the connecting electrode through the opening, a portion of the opening overlapping with the first scan line, and a remaining portion of the opening not overlapping with the first scan line.

[0028] Alternatively, the contact portion may be located within the opening.

[0029] A display device according to one embodiment includes: a substrate; a first electrode, a channel, and a second electrode of a driving transistor, located on the substrate and comprising a polycrystalline semiconductor; a first gate insulating film located on the first electrode, the channel, and the second electrode of the driving transistor; a gate electrode of the driving transistor located on the first gate insulating film and overlapping the channel of the driving transistor; a first scan line located on the first gate insulating film; a second gate insulating film located on the gate electrode of the driving transistor and the first scan line; a lower second scan line located on the second gate insulating film; and a first interlayer insulating film located between the lower second scan line and the first gate insulating film. Above; a first electrode, channel, and second electrode of a third transistor, located above the first interlayer insulating film, and comprising an oxide semiconductor; a third gate insulating film, located above the first electrode, channel, and second electrode of the third transistor; a gate electrode of the third transistor, located above the third gate insulating film; a second interlayer insulating film, located above the gate electrode of the third transistor; and a connecting electrode, located above the second interlayer insulating film, connecting the gate electrode of the driving transistor and the second electrode of the third transistor, wherein at least a portion of the contact portion of the connecting electrode contacting the second electrode of the third transistor does not overlap with the lower second scan line.

[0030] Alternatively, the second interlayer insulating film and the third gate insulating film may include: an opening that overlaps with the second electrode of the connection electrode and the third transistor, the contact portion being located within the opening, and at least a portion of the opening not overlapping with the first scan line.

[0031] Alternatively, the display device according to one embodiment may further include: an upper second scan line integrally formed with the gate electrode of the third transistor, wherein the opening is located in a plane between the first scan line and the upper second scan line, and the opening does not overlap with the upper second scan line.

[0032] The display device according to one embodiment may further include: a second transistor connected to the first scan line, the driving transistor and the second transistor comprising a polycrystalline semiconductor and being composed of a p-type transistor, the third transistor comprising an oxide semiconductor and being composed of an n-type transistor, and a voltage of opposite polarity to the voltage applied to the upper second scan line at the same timing.

[0033] The display device according to one embodiment may further include: a first boost electrode integrally formed with the first scan line; and a second boost electrode integrally formed with the second electrode of the third transistor, wherein the first boost electrode and the second boost electrode place the second gate insulating film and the first interlayer insulating film between them and overlap each other to form a boost capacitor, and at least a portion of the contact portion does not overlap with the boost capacitor.

[0034] (Invention effect) According to the embodiment, the resistance of the path for transmitting the compensation voltage can be reduced to ensure smooth transmission of the compensation voltage, thereby improving the horizontal stripe pattern. Attached Figure Description

[0035] Figure 1 This is a circuit diagram of a display device according to one embodiment.

[0036] Figure 2 This is a plan view showing a display device according to an embodiment.

[0037] Figure 3 It is along Figure 2 The cross-sectional view shown by line III-III.

[0038] Figure 4 It is along Figure 2 The cross-sectional view shown by line IV-IV.

[0039] Figures 5 to 10 This is a plan view showing the manufacturing sequence of a display device according to one embodiment.

[0040] Figure 11 This is a plan view showing a portion of a display device according to one embodiment.

[0041] Figure 12 This is a plan view showing a display device according to a comparative example.

[0042] Figure 13 It is along Figure 12 The cross-sectional view shown by line XIII-XIII.

[0043] Figure 14 This is a plan view showing a display device according to an embodiment.

[0044] Figure 15 It is along Figure 14 The cross-sectional view is shown by the XV-XV line.

[0045] Figure 16 This is a plan view showing a portion of a display device according to one embodiment.

[0046] Figure 17This is a plan view showing a display device according to an embodiment.

[0047] Figure 18 It is along Figure 17 The cross-sectional view shown by the XVIII-XVIII line.

[0048] Figure 19 This is a plan view showing a portion of a display device according to one embodiment.

[0049] (Explanation of reference numerals in the attached image) 110: Substrate 127: First initialization voltage line 128: Second initialization voltage line 151: First scan line; 151a: First boost electrode 152: Second scan line 153: Initialization control line 154: Bypass control line 155: Illumination control line; 171: Data cable 172: Drive voltage line; 741: Common voltage line 1131: First electrode of the driving transistor; 1133: Second electrode of the driving transistor 1151: Gate electrode of the driving transistor 1165: First opening 1166: Second opening 1175: First connecting electrode; 3151: Gate electrode of the third transistor. 3136: First electrode of the third transistor; 3138: Second electrode of the third transistor 3138a: Second boost electrode Cst: Holding capacitor; Cbt: Boost capacitor Detailed Implementation Hereinafter, with reference to the accompanying drawings, several embodiments of the present invention will be described in detail to enable those skilled in the art to readily implement the invention. The present invention can be implemented in various different forms and is not limited to the embodiments described herein.

[0050] To clearly illustrate the present invention, parts unrelated to the description have been omitted. Throughout the entire specification, the same reference numerals are used to mark the same or similar constituent elements.

[0051] Furthermore, for ease of explanation, the dimensions and thicknesses of the structures shown in the accompanying drawings are arbitrarily illustrated; therefore, the invention is not necessarily limited to the illustrations. In the drawings, the thicknesses are enlarged to clearly show multiple layers and regions. Moreover, in the drawings, the thicknesses of some layers and regions are exaggerated for ease of explanation.

[0052] Furthermore, when it is said that a layer, membrane, region, plate, or other part is "above" or "on" another part, it includes not only the case where it is "directly above" another part, but also the case where there is another part in between. Conversely, when it is said that a part is "directly above" another part, it means that there is no other part in between. In addition, being "above" or "on" the part that serves as a reference means being above or below the part that serves as a reference, and does not mean that it must be "above" or "on" the side opposite to the direction of gravity.

[0053] Furthermore, when it is stated throughout the specification that a certain part "includes" a certain constituent element, unless otherwise stated, it does not exclude other constituent elements, but means that other constituent elements may also be included.

[0054] Additionally, throughout the instruction manual, when it says "on a plane," it means when viewing the object from above; when it says "on a cross section," it means when viewing the object from the side as a vertical section.

[0055] First, refer to Figure 1 The following description pertains to a pixel of a display device according to an embodiment.

[0056] Figure 1 This is a circuit diagram of a display device according to one embodiment.

[0057] like Figure 1 As shown, a pixel PX of a display device according to an embodiment includes a plurality of transistors T1, T2, T3, T4, T5, T6, T7 connected to a plurality of wirings 127, 128, 151, 152, 153, 154, 155, 171, 172, 741, a holding capacitor Cst, a boost capacitor Cbt, and a light-emitting diode LED.

[0058] Multiple wirings 127, 128, 151, 152, 153, 154, 155, 171, 172, and 741 are connected to a pixel PX. These wirings include a first initialization voltage line 127, a second initialization voltage line 128, a first scan line 151, a second scan line 152, an initialization control line 153, a bypass control line 154, an emission control line 155, a data line 171, a drive voltage line 172, and a common voltage line 741.

[0059] The first scan line 151 is connected to the gate drive section (not shown) and transmits the first scan signal GW to the second transistor T2. The second scan line 152 can be applied with a voltage of opposite polarity to the voltage applied to the first scan line 151 at the same timing as the signal of the first scan line 151. For example, when a negative voltage is applied to the first scan line 151, a positive voltage can be applied to the second scan line 152. The second scan line 152 transmits the second scan signal GC to the third transistor T3.

[0060] Initialization control line 153 transmits the initialization control signal GI to the fourth transistor T4. Bypass control line 154 transmits the bypass signal GB to the seventh transistor T7. Bypass control line 154 can be constructed from the first scan line 151 at the front end. Light emission control line 155 transmits the light emission control signal EM to the fifth transistor T5 and the sixth transistor T6.

[0061] Data line 171 serves as a wiring for transmitting the data voltage DATA generated from the data driving unit (not shown). The brightness of the light-emitting diode (LED) changes according to the data voltage DATA applied to the pixel PX.

[0062] The driving voltage line 172 applies the driving voltage ELVDD. The first initialization voltage line 127 transmits the first initialization voltage VINT, and the second initialization voltage line 128 transmits the second initialization voltage AINT. The common voltage line 741 applies the common voltage ELVSS to the cathode electrode of the light-emitting diode (LED). In this embodiment, the voltages applied to the driving voltage line 172, the first and second initialization voltage lines 127 and 128, and the common voltage line 741 can each be a specific voltage.

[0063] The following section provides a detailed explanation of the structure and interconnections of multiple transistors.

[0064] The driving transistor T1 may have p-type transistor characteristics and may contain polycrystalline semiconductor. The driving transistor T1 is a transistor that adjusts the magnitude of the current output to the anode electrode of the light-emitting diode (LED) according to the data voltage DATA applied to its gate electrode. Since the brightness of the LED is adjusted according to the magnitude of the driving current output to the anode electrode of the LED, the brightness of the LED can be adjusted according to the data voltage DATA applied to the pixel PX. For this purpose, the first electrode of the driving transistor T1 is configured to receive the applied driving voltage ELVDD and is connected to the driving voltage line 172 via the fifth transistor T5. Furthermore, the first electrode of the driving transistor T1 is also connected to the second electrode of the second transistor T2 and also receives the applied data voltage DATA. On the other hand, the second electrode of the driving transistor T1 is configured to output current to the LED and is connected to the anode electrode of the LED via the sixth transistor T6. Additionally, the second electrode of the driving transistor T1 transmits the data voltage DATA applied to the first electrode to the third transistor T3. On the other hand, the gate electrode of the driving transistor T1 is connected to one electrode of the holding capacitor Cst (hereinafter referred to as the "second holding electrode"). In response, the voltage at the gate electrode of the driving transistor T1 changes according to the voltage stored in the holding capacitor Cst, thereby changing the drive current output by the driving transistor T1. Furthermore, the holding capacitor Cst also serves to maintain a constant voltage at the gate electrode of the driving transistor T1 throughout a frame.

[0065] The second transistor T2 may have p-type transistor characteristics and may contain polycrystalline semiconductor. The second transistor T2 is the transistor that receives the data voltage DATA into the pixel PX. The gate electrode of the second transistor T2 is connected to the first scan line 151 and one electrode of the boost capacitor Cbt (hereinafter referred to as the "first boost electrode"). The first electrode of the second transistor T2 is connected to the data line 171. The second electrode of the second transistor T2 is connected to the first electrode of the driving transistor T1. If the second transistor T2 is turned on based on the negative voltage in the first scan signal GW transmitted through the first scan line 151, the data voltage DATA transmitted through the data line 171 is transmitted to the first electrode of the driving transistor T1.

[0066] The third transistor T3 may have n-type transistor characteristics and may contain oxide semiconductor. The third transistor T3 electrically connects the second electrode and the gate electrode of the driving transistor T1. As a result, the third transistor T3 is a transistor that transmits a compensation voltage, which changes the data voltage DATA after passing through the driving transistor T1, to the second holding electrode of the holding capacitor Cst. The gate electrode of the third transistor T3 is connected to the second scan line 152, and the first electrode of the third transistor T3 is connected to the second electrode of the driving transistor T1. The second electrode of the third transistor T3 is connected to the second holding electrode of the holding capacitor Cst, the gate electrode of the driving transistor T1, and the other electrode of the boost capacitor Cbt (hereinafter referred to as the "second boost electrode"). The third transistor T3 is turned on based on receiving a positive voltage from the second scan signal GC transmitted through the second scan line 152, connecting the gate electrode of the driving transistor T1 to the second electrode of the driving transistor T1, and transmitting the voltage applied to the gate electrode of the driving transistor T1 to the second holding electrode of the holding capacitor Cst for storage in the holding capacitor Cst.

[0067] The fourth transistor T4 may have n-type transistor characteristics and may contain oxide semiconductor. The fourth transistor T4 initializes the gate electrode of the driving transistor T1 and the second holding electrode of the holding capacitor Cst. The gate electrode of the fourth transistor T4 is connected to the initialization control line 153, and the first electrode of the fourth transistor T4 is connected to the first initialization voltage line 127. The second electrode of the fourth transistor T4 is connected to the second holding electrode of the holding capacitor Cst, the gate electrode of the driving transistor T1, and the second boost electrode via the second electrode of the third transistor T3. The fourth transistor T4 is turned on based on receiving a positive voltage from the initialization control signal GI transmitted via the initialization control line 153. At this time, the first initialization voltage VINT is transmitted to the gate electrode of the driving transistor T1 and the second holding electrode of the holding capacitor Cst. Thus, the voltage at the gate electrode of the driving transistor T1 and the holding capacitor Cst are initialized.

[0068] The fifth transistor T5 may have p-type transistor characteristics and may contain polycrystalline semiconductor. The fifth transistor T5 serves to transmit the driving voltage ELVDD to the driving transistor T1. The gate electrode of the fifth transistor T5 is connected to the light-emitting control line 155, the first electrode of the fifth transistor T5 is connected to the driving voltage line 172, and the second electrode of the fifth transistor T5 is connected to the first electrode of the driving transistor T1.

[0069] The sixth transistor T6 may have p-type transistor characteristics and may contain polycrystalline semiconductor. The sixth transistor T6 serves to transmit the drive current output from the driving transistor T1 to the light-emitting diode (LED). The gate electrode of the sixth transistor T6 is connected to the light-emitting control line 155, the first electrode of the sixth transistor T6 is connected to the second electrode of the driving transistor T1, and the second electrode of the sixth transistor T6 is connected to the positive electrode of the LED.

[0070] The seventh transistor T7 may have p-type transistor characteristics and may contain polycrystalline semiconductor. The seventh transistor T7 initializes the positive electrode of the light-emitting diode (LED). The gate electrode of the seventh transistor T7 is connected to the bypass control line 154, the first electrode of the seventh transistor T7 is connected to the positive electrode of the LED, and the second electrode of the seventh transistor T7 is connected to the second initialization voltage line 128. If the seventh transistor T7 is turned on by a negative voltage in the bypass signal GB, the second initialization voltage AINT is applied to the positive electrode of the LED, thus initializing it.

[0071] The above description indicates that a pixel PX includes seven transistors T1~T7, one holding capacitor Cst, and one boost capacitor Cbt. However, it is not limited to this, and the number of transistors and capacitors, as well as their connection relationships, can be varied.

[0072] In this embodiment, the driving transistor T1 may contain a polycrystalline semiconductor. Additionally, the third transistor T3 and the fourth transistor T4 may contain oxide semiconductors. The second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may contain polycrystalline semiconductors. However, this is not a limitation; at least one of the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may contain oxide semiconductors. In this embodiment, by making the third transistor T3 and the fourth transistor T4 contain semiconductor materials different from those of the driving transistor T1, more stable driving can be achieved, and reliability can be improved.

[0073] As described above, when a positive voltage is applied to the first scan line 151, a negative voltage is applied to the second scan line 152, and vice versa. That is, since the second scan signal GC applied to the second scan line 152 is a signal that is inversely related to the first scan signal GW applied to the first scan line 151, writing data pulls down the gate voltage of the driving transistor T1. Conversely, the first scan signal GW pulls up the gate voltage of the driving transistor T1. Therefore, when writing black voltage, the black voltage may decrease. In this embodiment, by placing the boost capacitor Cbt between the first scan line 151 to which the first scan signal GW is applied and the gate electrode of the driving transistor T1, the gate voltage of the driving transistor T1 can rise, resulting in a stable output of black voltage. As the capacitance of the boost capacitor Cbt increases, the gate voltage of the driving transistor T1 can rise further. By adjusting the capacitance of the boost capacitor Cbt, the gate voltage of the driving transistor T1 can be controlled.

[0074] The following is for reference Figures 2 to 10 The planar and cross-sectional structures of the driving transistor T1, the third transistor T3, the first scan line 151, the boost capacitor Cbt, etc. are further explained.

[0075] Figure 2 This is a plan view showing a display device according to an embodiment. Figure 3 It is along Figure 2 The cross-sectional view shown by line III-III, Figure 4 It is along Figure 2 The cross-sectional view shown by line IV-IV. Figures 5 to 10 This is a plan view showing the manufacturing sequence of a display device according to one embodiment. Figures 2 to 10 Two adjacent pixels are shown, and the two pixels can have symmetrical shapes. However, they are not limited to this; the two pixels can also have substantially the same shape. Hereinafter, the description will mainly focus on the pixel located on the left. In addition, in the case of the seventh transistor T7, since it is connected to the first scan line 151 at the front end, its illustration is omitted, and the seventh transistor T7 at the rear end is shown instead.

[0076] like Figures 2 to 10 The substrate 110 may be configured with a polycrystalline semiconductor including a channel 1132 for driving transistor T1, a first electrode 1131 and a second electrode 1133. Figure 5 The diagram illustrates a polycrystalline semiconductor. The polycrystalline semiconductor may include not only the channel, first electrode, and second electrode of the driving transistor T1, but also the channels, first electrode, and second electrode of each of the second transistor T2, fifth transistor T5, sixth transistor T6, and seventh transistor T7.

[0077] The channel 1132 of the driving transistor T1 can be configured in a curved shape on a plane. However, the shape of the channel 1132 of the driving transistor T1 is not limited to this and can be modified in various ways. For example, the channel 1132 of the driving transistor T1 can also be curved into other shapes, or it can be configured in a rod shape. The first electrode 1131 and the second electrode 1133 of the driving transistor T1 can be located on both sides of the channel 1132 of the driving transistor T1. The first electrode 1131 of the driving transistor T1 extends upward and downward on the plane, and the portion extending downward can be connected to the second electrode of the second transistor T2, and the portion extending upward can be connected to the second electrode of the fifth transistor T5. The second electrode 1133 of the driving transistor T1 can extend upward on the plane and be connected to the first electrode of the sixth transistor T6.

[0078] A buffer layer 111 may be disposed between the substrate 110 and the polycrystalline semiconductor including the channel 1132, the first electrode 1131, and the second electrode 1133 of the driving transistor T1. The buffer layer 111 may have a single-layer or multi-layer structure. The buffer layer 111 may contain organic or inorganic insulating materials.

[0079] A first gate insulating film 141 may be disposed on the polycrystalline semiconductor including the channel 1132, the first electrode 1131, and the second electrode 1133 of the driving transistor T1. The first gate insulating film 141 may contain silicon nitride, silicon oxide, etc.

[0080] A first gate conductor, including the gate electrode 1151 of the driving transistor T1, can be configured on the first gate insulating film 141. Figure 6 The polycrystalline semiconductor and the first gate conductor are shown together. The first gate conductor may include not only the gate electrode of the driving transistor T1, but also the gate electrodes of the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7.

[0081] The gate electrode 1151 of the driving transistor T1 may overlap with the channel 1132 of the driving transistor T1. The channel 1132 of the driving transistor T1 is covered by the gate electrode 1151 of the driving transistor T1.

[0082] The first gate conductor may further include a first scan line 151 and a light emission control line 155. The first scan line 151 and the light emission control line 155 may extend in a generally lateral direction. The first scan line 151 may be connected to the gate electrode of the second transistor T2 and the first boost electrode 151a. The first scan line 151 may be integrally formed with the gate electrode of the second transistor T2. The first scan line 151 may be integrally formed with the first boost electrode 151a. The first scan line 151 may be connected to the gate electrode of the seventh transistor T7 of the pixel located at the next end. That is, the bypass control line connected to the seventh transistor T7 may be formed by the first scan line 151 at the front end. The gate electrodes of the fifth transistor T5 and the sixth transistor T6 may be connected to the light emission control line 155.

[0083] After forming the first gate conductor, including the gate electrode 1151 of the driving transistor T1, a doping process can be performed. Alternatively, the polycrystalline semiconductor covered by the first gate conductor may not be doped, while the portion of the polycrystalline semiconductor not covered by the first gate conductor may be doped to have the same characteristics as the conductor. In this case, a p-type dopant can be used for the doping process, and the driving transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7, including the polycrystalline semiconductor, can have p-type transistor characteristics.

[0084] A second gate insulating film 142 may be disposed on the first gate conductor, including the gate electrode 1151 of the driving transistor T1, and the first gate insulating film 141. The second gate insulating film 142 may contain silicon nitride, silicon oxide, etc.

[0085] A second gate conductor, including a first holding electrode 1153 for holding capacitor Cst, a light blocking layer 3155 for third transistor T3, and a light blocking layer 4155 for fourth transistor T4, can be configured on the second gate insulating film 142. Figure 7 The polycrystalline semiconductor, the first gate conductor, and the second gate conductor are shown together.

[0086] The first holding electrode 1153 overlaps with the gate electrode 1151 of the driving transistor T1 to form a holding capacitor Cst. An opening 1152 is formed in the first holding electrode 1153 of the holding capacitor Cst. The opening 1152 of the first holding electrode 1153 of the holding capacitor Cst can overlap with the gate electrode 1151 of the driving transistor T1. The light blocking layer 3155 of the third transistor T3 can overlap with the channel 3137 and the gate electrode 3151 of the third transistor T3. The light blocking layer 4155 of the fourth transistor T4 can overlap with the channel 4137 and the gate electrode 4151 of the fourth transistor T4.

[0087] The second gate conductor may further include a lower second scan line 152a, a lower initialization control line 153a, and a first initialization voltage line 127. The lower second scan line 152a, lower initialization control line 153a, and first initialization voltage line 127 may extend in a generally lateral direction. The lower second scan line 152a may be connected to the photoblocking layer 3155 of the third transistor T3. The lower second scan line 152a may be integrally formed with the photoblocking layer 3155 of the third transistor T3. The lower initialization control line 153a may be connected to the photoblocking layer 4155 of the fourth transistor T4. The lower initialization control line 153a may be integrally formed with the photoblocking layer 4155 of the fourth transistor T4.

[0088] A first interlayer insulating film 161 may be disposed on the second gate conductor, which includes the first holding electrode 1153 of the holding capacitor Cst, the light blocking layer 3155 of the third transistor T3, and the light blocking layer 4155 of the fourth transistor T4. The first interlayer insulating film 161 may contain silicon nitride, silicon oxide, etc.

[0089] An oxide semiconductor, including a channel 3137, a first electrode 3136 and a second electrode 3138 of a third transistor T3, and a channel 4137, a first electrode 4136 and a second electrode 4138 of a fourth transistor T4, can be disposed on the first interlayer insulating film 161. Figure 8 Together, a polycrystalline semiconductor, a first gate conductor, a second gate conductor, and an oxide semiconductor are shown.

[0090] Oxide semiconductors can include mono-element metal oxides such as indium (In), tin (Sn), or zinc (Zn); di-element metal oxides such as In-Zn oxides, Sn-Zn oxides, Al-Zn oxides, Zn-Mg oxides, Sn-Mg oxides, In-Mg oxides, or In-Ga oxides; In-Ga-Zn oxides; In-Al-Zn oxides; In-Sn-Zn oxides; Sn-Ga-Zn oxides; Al-Ga-Zn oxides; Sn-Al-Zn oxides; In-Hf-Zn oxides; In-La-Zn oxides; In-Ce-Zn oxides; In-Pr-Zn oxides; and In-Nd-Zn oxides. Oxides, including at least one of the following: In-Sm-Zn oxides, In-Eu-Zn oxides, In-Gd-Zn oxides, In-Tb-Zn oxides, In-Dy-Zn oxides, In-Ho-Zn oxides, In-Er-Zn oxides, In-Tm-Zn oxides, In-Yb-Zn oxides, or In-Lu-Zn ​​oxides (tri-element metal oxides); and In-Sn-Ga-Zn oxides, In-Hf-Ga-Zn oxides, In-Al-Ga-Zn oxides, In-Sn-Al-Zn oxides, In-Sn-Hf-Zn oxides, or In-Hf-Al-Zn oxides (quaternary metal oxides). For example, oxide semiconductors may include indium gallium zinc oxide (IGZO) among the In-Ga-Zn oxides.

[0091] The channel 3137, first electrode 3136, and second electrode 3138 of the third transistor T3, and the channel 4137, first electrode 4136, and second electrode 4138 of the fourth transistor T4 can be interconnected and integrally formed. The first electrode 3136 and second electrode 3138 of the third transistor T3 can be located on both sides of the channel 3137 of the third transistor T3. The first electrode 4136 and second electrode 4138 of the fourth transistor T4 can be located on both sides of the channel 4137 of the fourth transistor T4. The second electrode 3138 of the third transistor T3 can be connected to the second electrode 4138 of the fourth transistor T4. The channel 3137 of the third transistor T3 can overlap with the light-blocking layer 3155. The channel 4137 of the fourth transistor T4 can overlap with the light-blocking layer 4155.

[0092] The oxide semiconductor may also include a second boost electrode 3138a. The second boost electrode 3138a may be connected to the second electrode 3138 of the third transistor T3. The second boost electrode 3138a may be integrally formed with the second electrode 3138 of the third transistor T3. The second boost electrode 3138a may be connected to the second electrode 4138 of the fourth transistor T4. The second boost electrode 3138a may be integrally formed with the second electrode 4138 of the fourth transistor T4. The second boost electrode 3138a may overlap with the first boost electrode 151a. The capacitance of the boost capacitor Cbt can be determined by the overlapping region of the first boost electrode 151a and the second boost electrode 3138a, the thickness of the second gate insulating film 142 located between the first boost electrode 151a and the second boost electrode 3138a, and the thickness of the first interlayer insulating film 161.

[0093] A third gate insulating film 143 may be disposed on the oxide semiconductor including the channel 3137, first electrode 3136, and second electrode 3138 of the third transistor T3, and the channel 4137, first electrode 4136, and second electrode 4138 of the fourth transistor T4. The third gate insulating film 143 may be located on the entire surface of the oxide semiconductor and the first interlayer insulating film 161. Therefore, the third gate insulating film 143 may cover the top and side surfaces of the channel 3137, first electrode 3136, and second electrode 3138 of the third transistor T3, and the channel 4137, first electrode 4136, and second electrode 4138 of the fourth transistor T4. However, this embodiment is not limited to this, and the third gate insulating film 143 may not be located on the entire surface of the oxide semiconductor and the first interlayer insulating film 161. For example, the third gate insulating film 143 may overlap with the channel 3137 of the third transistor T3, but not with the first electrode 3136 and the second electrode 3138. In addition, the third gate insulating film 143 may overlap with the channel 4137 of the fourth transistor T4, but not with the first electrode 4136 and the second electrode 4138.

[0094] A third gate conductor, including the gate electrode 3151 of the third transistor T3 and the gate electrode 4151 of the fourth transistor T4, can be disposed on the third gate insulating film 143. Figure 9 Together, a polycrystalline semiconductor, a first gate conductor, a second gate conductor, an oxide semiconductor, and a third gate conductor are shown.

[0095] The gate electrode 3151 of the third transistor T3 may overlap with the channel 3137 of the third transistor T3. The gate electrode 3151 of the third transistor T3 may overlap with the light blocking layer 3155 of the third transistor T3.

[0096] The gate electrode 4151 of the fourth transistor T4 may overlap with the channel 4137 of the fourth transistor T4. The gate electrode 4151 of the fourth transistor T4 may overlap with the light blocking layer 4155 of the fourth transistor T4.

[0097] The third gate conductor may also include an upper second scan line 152b and an upper initialization control line 153b. The upper second scan line 152b and the upper initialization control line 153b may extend in a generally lateral direction. The upper second scan line 152b, together with the lower second scan line 152a, constitutes the second scan line 152. The upper second scan line 152b may be connected to the gate electrode 3151 of the third transistor T3. The upper second scan line 152b may be integrally formed with the gate electrode 3151 of the third transistor T3. The upper initialization control line 153b, together with the lower initialization control line 153a, constitutes the initialization control line 153. The upper initialization control line 153b may be connected to the gate electrode 4151 of the fourth transistor T4. The upper initialization control line 153b may be integrally formed with the gate electrode 4151 of the fourth transistor T4.

[0098] After forming the third gate conductor, including the gate electrode 3151 of the third transistor T3 and the gate electrode 4151 of the fourth transistor T4, a doping process can be performed. This can be done by leaving the portion of the oxide semiconductor covered by the third gate conductor undoped, while doping the portion of the oxide semiconductor not covered by the third gate conductor to achieve the same properties as the conductor. The channel 3137 of the third transistor T3 can be located below the gate electrode 3151, overlapping with it. The first electrode 3136 and the second electrode 3138 of the third transistor T3 may not overlap with the gate electrode 3151. The channel 4137 of the fourth transistor T4 can be located below the gate electrode 4151, overlapping it. The first electrode 4136 and the second electrode 4138 of the fourth transistor T4 may not overlap with the gate electrode 4151. The second boost electrode 3138a may not overlap with the third gate conductor. The doping process of oxide semiconductors can be carried out with n-type dopants, and the third transistor T3 and the fourth transistor T4 containing oxide semiconductors can have n-type transistor characteristics.

[0099] A second interlayer insulating film 162 may be disposed on the third gate conductor, which includes the gate electrode 3151 of the third transistor T3 and the gate electrode 4151 of the fourth transistor T4. The second interlayer insulating film 162 may include a first opening 1165, a second opening 1166, a third opening 3165, and a fourth opening 3166.

[0100] The first opening 1165 may overlap with at least a portion of the gate electrode 1151 of the driving transistor T1. The first opening 1165 may also be formed on the third gate insulating film 143, the first interlayer insulating film 161, and the second gate insulating film 142. The first opening 1165 may overlap with the opening 1152 of the first holding electrode 1153. The first opening 1165 may be located inside the opening 1152 of the first holding electrode 1153.

[0101] The second opening 1166 may at least partially overlap with the second electrode 3138 of the third transistor T3. The second opening 1166 may also be formed on the third gate insulating film 143. The second opening 1166 may be located in a plane between the first scan line 151 and the second scan line 152. The second opening 1166 may not overlap with the first scan line 151. One side edge of the second opening 1166 may coincide with one side edge of the first scan line 151. For example, the lower side edge of the second opening 1166 may coincide with the upper side edge of the first scan line 151. However, this is not a limitation; one side edge of the second opening 1166 may not coincide with one side edge of the first scan line 151. For example, the lower side edge of the second opening 1166 may be configured to be spaced apart from the upper side edge of the first scan line 151, and the lower side edge of the second opening 1166 may be located above the upper side edge of the first scan line 151. The second opening 1166 may not overlap with the second scan line 152. At this time, the second opening 1166 may not overlap with the upper second scan line 152b. The second opening 1166 may also not overlap with the lower second scan line 152a. The second opening 1166 may not overlap with the boost capacitor Cbt. That is, the second opening 1166 may not overlap with the overlapping portion of the first boost electrode 151a and the second boost electrode 3138a.

[0102] The third opening 3165 may overlap with at least a portion of the second electrode 1133 of the driving transistor T1. The third opening 3165 may also be formed on the third gate insulating film 143, the first interlayer insulating film 161, the second gate insulating film 142, and the first gate insulating film 141. The fourth opening 3166 may overlap with at least a portion of the first electrode 3136 of the third transistor T3. The fourth opening 3166 may also be formed on the third gate insulating film 143.

[0103] A first data conductor, including a first connection electrode 1175 and a second connection electrode 3175, can be disposed on the second interlayer insulating film 162. Figure 10 Together, a polycrystalline semiconductor, a first gate conductor, a second gate conductor, an oxide semiconductor, a third gate conductor, and a first data conductor are shown.

[0104] The first connection electrode 1175 can overlap with the gate electrode 1151 of the driving transistor T1. The first connection electrode 1175 can be connected to the gate electrode 1151 of the driving transistor T1 through the first opening 1165 and the opening 1152 of the first holding electrode 1153. The first connection electrode 1175 can overlap with the second electrode 3138 of the third transistor T3. The first connection electrode 1175 can be connected to the second electrode 3138 of the third transistor T3 through the second opening 1166. Therefore, the gate electrode 1151 of the driving transistor T1 and the second electrode 3138 of the third transistor T3 can be connected through the first connection electrode 1175. At this time, the gate electrode 1151 of the driving transistor T1 can also be connected to the second boost electrode 3138a and the second electrode 4138 of the fourth transistor T4 through the first connection electrode 1175.

[0105] The first connecting electrode 1175 can contact the second electrode 3138 of the third transistor T3. The contact portion where the first connecting electrode 1175 and the second electrode 3138 of the third transistor T3 contact each other can be located within the second opening 1166. Since the second opening 1166 does not overlap with the first scan line 151, the contact portion between the first connecting electrode 1175 and the second electrode 3138 of the third transistor T3 may not overlap with the first scan line 151. The first connecting electrode 1175 may overlap with the first scan line 151. A portion of the first connecting electrode 1175 may overlap with the first scan line 151. However, this is not a limitation; the first connecting electrode 1175 may also not overlap with the first scan line 151. Since the second opening 1166 does not overlap with the second scan line 152, at least a portion of the contact portion between the first connecting electrode 1175 and the second electrode 3138 of the third transistor T3 may not overlap with the second scan line 152. The contact portion between the first connecting electrode 1175 and the second electrode 3138 of the third transistor T3 may not overlap with the upper second scan line 152b. The contact portion between the first connecting electrode 1175 and the second electrode 3138 of the third transistor T3 may not overlap with the lower second scan line 152a. The first connecting electrode 1175 may not overlap with the second scan line 152. Since the second opening 1166 does not overlap with the boost capacitor Cbt, the contact portion between the first connecting electrode 1175 and the second electrode 3138 of the third transistor T3 may not overlap with the boost capacitor Cbt.

[0106] The second connection electrode 3175 can overlap with the second electrode 1133 of the driving transistor T1. The second connection electrode 3175 can be connected to the second electrode 1133 of the driving transistor T1 through the third opening 3165. The second connection electrode 3175 can overlap with the first electrode 3136 of the third transistor T3. The second connection electrode 3175 can be connected to the first electrode 3136 of the third transistor T3 through the fourth opening 3166. Therefore, the second electrode 1133 of the driving transistor T1 and the first electrode 3136 of the third transistor T3 can be connected through the second connection electrode 3175.

[0107] The first data conductor may also include a second initialization voltage line 128. The second initialization voltage line 128 may extend in a generally lateral direction.

[0108] A third interlayer insulating film 180 may be disposed on the first data conductor including the first connecting electrode 1175 and the second connecting electrode 3175.

[0109] Data lines 171 and driving voltage lines 172 can be disposed on the third interlayer insulating film 180. Data lines 171 and driving voltage lines 172 can extend in a generally longitudinal direction. Data line 171 can be connected to the second transistor T2. Driving voltage line 172 can be connected to the fifth transistor T5. Additionally, driving voltage line 172 can be connected to the first holding electrode 1153.

[0110] Although the illustration is omitted, a protective film can be disposed on the data line 171 and the drive voltage line 172, and an anode electrode can be disposed on the protective film. The anode electrode can be connected to the sixth transistor T6 and can receive the output current of the drive transistor T1. A partition wall can be disposed on the anode electrode. An opening is formed in the partition wall, and the opening of the partition wall can overlap with the anode electrode. A light-emitting element layer can be disposed within the opening of the partition wall. A cathode electrode can be disposed on the light-emitting element layer and the partition wall. The anode electrode, the light-emitting element layer, and the cathode electrode constitute a light-emitting diode (LED).

[0111] As described above, in a display device according to one embodiment, the driving transistor T1 may contain a polycrystalline semiconductor, and the third transistor T3 and the fourth transistor T4 may contain an oxide semiconductor. As explained above, by making the third transistor T3 and the fourth transistor T4 contain semiconductor materials different from those of the driving transistor T1, more stable driving can be achieved, and reliability can be improved.

[0112] The following is further reference. Figure 11 The path of the compensation voltage being transmitted to the gate electrode of the driving transistor via the third transistor will be explained. Refer to the previous explanation. Figures 1 to 10 Please provide an explanation.

[0113] Figure 11 This is a plan view showing a portion of a display device according to one embodiment. Figure 11 A portion of the first scan line, driving transistor, third transistor, and fourth transistor are shown.

[0114] like Figure 11 As shown, the data voltage DATA applied by the second transistor T2 is transmitted to the third transistor T3 via the driving transistor T1. The third transistor T3 electrically connects the second electrode 1133 of the driving transistor T1 to the gate electrode 1151 of the driving transistor T1. The first electrode 3136 of the third transistor T3 is connected to the second electrode 1133 of the driving transistor T1, and the second electrode 3138 of the third transistor T3 is connected to the gate electrode 1151 of the driving transistor T1. The second electrode 3138 of the third transistor T3 and the gate electrode 1151 of the driving transistor T1 are connected via the first connection electrode 1175. The compensation voltage, which is changed by the data voltage DATA through the third transistor T3, is transmitted to the gate electrode 1151 of the driving transistor T1 via the first connection electrode 1175. The first electrode 3136, channel 3137, and second electrode 3138 of the third transistor T3, which are included in the transmission path CTR of such compensation voltage, are made of oxide semiconductor. The second electrode 3138 of such a third transistor T3 can overlap with the first scan line 151. Because the second electrode 3138 of the third transistor T3 is integrally formed with the second boost electrode 3138a, and the first scan line 151 is integrally formed with the first boost electrode 151a, the first boost electrode 151a and the second boost electrode 3138a overlap each other to form a boost capacitor Cbt.

[0115] As explained above, voltages of opposite polarities are applied to the first scan line 151 and the second scan line 152 at the same timing. The first scan line 151 is connected to the gate electrode of the second transistor T2, and the second scan line 152 is connected to the gate electrode of the third transistor T3. The second transistor T2 is a p-type transistor, and the third transistor T3 is an n-type transistor. Therefore, when a negative voltage is applied to the first scan line 151 and a positive voltage is applied to the second scan line 152, both the second transistor T2 and the third transistor T3 are turned on.

[0116] The portion of the second electrode 3138 of the third transistor T3, which is made of oxide semiconductor, that overlaps with the first scan line 151 may be affected by a negative voltage applied to the first scan line 151. For example, due to the negative voltage applied to the first scan line 151, positive charges may accumulate below the second electrode 3138 of the third transistor T3 adjacent to the first scan line 151. Conversely, negative charges may accumulate above the second electrode 3138 of the third transistor T3 that is relatively far from the first scan line 151. Therefore, in the portion where the second electrode 3138 of the third transistor T3 overlaps with the first scan line 151, the resistance is relatively increased, and voltage transmission may be hindered.

[0117] In a display device according to one embodiment, the contact portion between the first connecting electrode 1175 and the second electrode 3138 of the third transistor T3 may not overlap with the first scan line 151. Therefore, the transmission path CTR of the compensation voltage can avoid the portion where the second electrode 3138 of the third transistor T3 overlaps with the first scan line 151. Thus, an increase in the resistance of the compensation voltage transmission path CTR can be prevented, the compensation voltage can be transmitted smoothly, and horizontal line patterns can be improved.

[0118] The above description addresses the case where the contact portion between the first connecting electrode 1175 and the second electrode 3138 of the third transistor T3 does not overlap with the first scan line 151, but is not limited thereto. By ensuring that the contact portion between the first connecting electrode 1175 and the second electrode 3138 of the third transistor T3 not only does not overlap with the first scan line 151, but also does not overlap with other wiring where a negative voltage is applied, the same or similar effects can be achieved.

[0119] The following is for reference Figure 12 as well as Figure 13 The following description pertains to the display device based on the comparative example.

[0120] Figure 12 This is a plan view showing the display device according to the comparative example. Figure 13 It is along Figure 12 The cross-sectional view shown by line XIII-XIII.

[0121] like Figure 12 as well as Figure 13 The display device according to the comparative example has a structure that is largely the same as that of the display device according to one embodiment. However, the difference lies in that the second opening 1166 overlaps with the first scan line 151.

[0122] In the display device according to the comparative example, the entire second opening 1166 overlaps with the first scan line 151. Therefore, the contact portion between the first connecting electrode 1175 and the second electrode 3138 of the third transistor T3 overlaps with the first scan line 151. In addition, the contact portion between the first connecting electrode 1175 and the second electrode 3138 of the third transistor T3 overlaps with the boost capacitor Cbt.

[0123] In the display device according to the comparative example, the transmission path of the compensation voltage passes through the portion where the second electrode 3138 of the third transistor T3 overlaps with the first scan line 151. Therefore, the resistance of the compensation voltage transmission path increases, causing the transmission of the compensation voltage to be unsuccessful, which may result in it being identified as horizontal stripes.

[0124] In a display device according to one embodiment, by making the transmission path of the compensation voltage avoid the portion where the second electrode 3138 of the third transistor T3 overlaps with the first scan line 151, it is possible to achieve smoother transmission of the compensation voltage compared to the display device according to the comparative example.

[0125] Next, refer to Figures 14 to 16 The following is a description of a display device according to one embodiment.

[0126] Because according to Figures 14 to 16 The display device shown in the embodiment and according to Figures 1 to 11 The same parts of the display device in the illustrated embodiment are omitted from the description. In this embodiment, the difference from the previous embodiment is that the contact portion between the first connecting electrode and the second electrode of the third transistor partially overlaps with the first scan line, which will be further explained below.

[0127] Figure 14 This is a plan view showing a display device according to an embodiment. Figure 15 It is along Figure 14 The cross-sectional view shown by the XV-XV line. Figure 16 This is a plan view showing a portion of a display device according to one embodiment.

[0128] like Figures 14 to 16 As shown, a display device according to one embodiment includes a plurality of wirings 127, 128, 151, 152, 153, 154, 155, 171, 172, a plurality of transistors T1, T2, T3, T4, T5, T6, T7 connected to the wirings, a holding capacitor Cst, a boost capacitor Cbt, and a light-emitting diode (not shown).

[0129] The third transistor T3 includes: a first electrode 3136 connected to the first electrode 1131 of the driving transistor T1; a second electrode 3138 connected to the first connection electrode 1175; a channel 3137 located between the first electrode 3136 and the second electrode 3138; and a gate electrode 3151 overlapping the channel 3137.

[0130] Alternatively, a second interlayer insulating film 162 may be disposed on the gate electrode 3151 of the third transistor T3. The second interlayer insulating film 162 includes a first opening 1165, a second opening 1166, a third opening 3165, and a fourth opening 3166.

[0131] The second opening 1166 may at least partially overlap with the second electrode 3138 of the third transistor T3. The second opening 1166 may also be formed on the third gate insulating film 143. The second opening 1166 may be located in a plane between the first scan line 151 and the second scan line 152. At least a portion of the second opening 1166 may not overlap with the first scan line 151. A portion of the second opening 1166 may overlap with the first scan line 151, while the remaining portion may not overlap with the first scan line 151. For example, half of the second opening 1166 may overlap with the first scan line 151, while the remaining half may not overlap with the first scan line 151. The second opening 1166 may not overlap with the second scan line 152. In this case, the second opening 1166 may not overlap with the upper second scan line 152b. The second opening 1166 may also not overlap with the lower second scan line 152a. At least a portion of the second opening 1166 may not overlap with the boost capacitor Cbt. That is, at least a portion of the second opening 1166 may not overlap with the overlapping portion of the first boost electrode 151a and the second boost electrode 3138a. A portion of the second opening 1166 may overlap with the boost capacitor Cbt, while the remaining portion of the second opening 1166 may not overlap with the boost capacitor Cbt.

[0132] The first connecting electrode 1175 can be connected to the second electrode 3138 of the third transistor T3 through the second opening 1166.

[0133] The first connecting electrode 1175 can contact the second electrode 3138 of the third transistor T3. The contact portion where the first connecting electrode 1175 and the second electrode 3138 of the third transistor T3 contact each other can be located within the second opening 1166. Since at least a portion of the second opening 1166 does not overlap with the first scan line 151, at least a portion of the contact portion between the first connecting electrode 1175 and the second electrode 3138 of the third transistor T3 may not overlap with the first scan line 151. A portion of the contact portion between the first connecting electrode 1175 and the second electrode 3138 of the third transistor T3 may overlap with the first scan line 151, and the remaining portion of the contact portion between the first connecting electrode 1175 and the second electrode 3138 of the third transistor T3 may not overlap with the first scan line 151. The first connecting electrode 1175 may overlap with the first scan line 151. A portion of the first connecting electrode 1175 may overlap with the first scan line 151. Since the second opening 1166 does not overlap with the second scan line 152, at least a portion of the contact between the first connecting electrode 1175 and the second electrode 3138 of the third transistor T3 may not overlap with the second scan line 152. The contact between the first connecting electrode 1175 and the second electrode 3138 of the third transistor T3 may not overlap with the upper second scan line 152b. The contact between the first connecting electrode 1175 and the second electrode 3138 of the third transistor T3 may not overlap with the lower second scan line 152a. The first connecting electrode 1175 may not overlap with the second scan line 152a. Since at least a portion of the second opening 1166 does not overlap with the boost capacitor Cbt, at least a portion of the contact between the first connecting electrode 1175 and the second electrode 3138 of the third transistor T3 may not overlap with the boost capacitor Cbt. A portion of the contact between the first connecting electrode 1175 and the second electrode 3138 of the third transistor T3 may overlap with the boost capacitor Cbt, while the remaining portion of the contact between the first connecting electrode 1175 and the second electrode 3138 of the third transistor T3 may not overlap with the boost capacitor Cbt.

[0134] In a display device according to one embodiment, at least a portion of the contact between the first connecting electrode 1175 and the second electrode 3138 of the third transistor T3 may not overlap with the first scan line 151. Therefore, the compensation voltage transmission path CTR can avoid the portion where the second electrode 3138 of the third transistor T3 overlaps with the first scan line 151. Thus, an increase in the resistance of the compensation voltage transmission path CTR can be prevented, the compensation voltage can be transmitted smoothly, and horizontal line patterns can be improved. The above description addresses the situation where at least a portion of the contact between the first connecting electrode 1175 and the second electrode 3138 of the third transistor T3 does not overlap with the first scan line 151, but is not limited thereto. By ensuring that at least a portion of the contact between the first connecting electrode 1175 and the second electrode 3138 of the third transistor T3 not only does not overlap with the first scan line 151, but also with other wiring where a negative voltage is applied, the same or similar effects can be achieved.

[0135] Next, refer to Figures 17 to 19 The following is a description of a display device according to one embodiment.

[0136] Because according to Figures 17 to 19 The display device shown in the embodiment and according to Figures 1 to 11 The same parts of the display device in the illustrated embodiment are omitted from the description. In this embodiment, the difference from the previous embodiment is that the first connecting electrode and the first scan line do not overlap, which will be further explained below.

[0137] Figure 17 This is a plan view showing a display device according to an embodiment. Figure 18 It is along Figure 17 The cross-sectional view shown by the XVIII-XVIII line is as follows. Figure 19 This is a plan view showing a portion of a display device according to one embodiment.

[0138] like Figures 17 to 19 As shown, a display device according to one embodiment includes a plurality of wirings 127, 128, 151, 152, 153, 154, 155, 171, 172, a plurality of transistors T1, T2, T3, T4, T5, T6, T7 connected to the wirings, a holding capacitor Cst, a boost capacitor Cbt, and a light-emitting diode (not shown).

[0139] The third transistor T3 includes: a first electrode 3136 connected to the first electrode 1131 of the driving transistor T1; a second electrode 3138 connected to the first connection electrode 1175; a channel 3137 located between the first electrode 3136 and the second electrode 3138; and a gate electrode 3151 overlapping the channel 3137.

[0140] Alternatively, a second interlayer insulating film 162 may be disposed on the gate electrode 3151 of the third transistor T3. The second interlayer insulating film 162 includes a first opening 1165, a second opening 1166, a third opening 3165, and a fourth opening 3166.

[0141] The second opening 1166 may at least partially overlap with the second electrode 3138 of the third transistor T3. The second opening 1166 may also be formed on the third gate insulating film 143. The second opening 1166 may be located in a plane between the first scan line 151 and the second scan line 152. The second opening 1166 may not overlap with the first scan line 151. The second opening 1166 may be spaced apart from the first scan line 151. The second opening 1166 may not overlap with the second scan line 152. In this case, the second opening 1166 may not overlap with the upper second scan line 152b. The second opening 1166 may also not overlap with the lower second scan line 152a. The second opening 1166 may not overlap with the boost capacitor Cbt. That is, the second opening 1166 may not overlap with the overlapping portion of the first boost electrode 151a and the second boost electrode 3138a. The second opening 1166 may be spaced apart from the boost capacitor Cbt.

[0142] The first connecting electrode 1175 can be connected to the second electrode 3138 of the third transistor T3 through the second opening 1166.

[0143] The first connecting electrode 1175 can contact the second electrode 3138 of the third transistor T3. The contact portion where the first connecting electrode 1175 and the second electrode 3138 of the third transistor T3 contact each other can be located within the second opening 1166. Since the second opening 1166 does not overlap with the first scan line 151, the contact portion between the first connecting electrode 1175 and the second electrode 3138 of the third transistor T3 may not overlap with the first scan line 151. The first connecting electrode 1175 may not overlap with the first scan line 151. The first connecting electrode 1175 may be spaced apart from the first scan line 151 by a predetermined interval. Since the second opening 1166 does not overlap with the second scan line 152, at least a portion of the contact portion between the first connecting electrode 1175 and the second electrode 3138 of the third transistor T3 may not overlap with the second scan line 152. The contact portion between the first connecting electrode 1175 and the second electrode 3138 of the third transistor T3 may not overlap with the upper second scan line 152b. The contact portion between the first connecting electrode 1175 and the second electrode 3138 of the third transistor T3 may not overlap with the lower second scan line 152a. The first connecting electrode 1175 may not overlap with the second scan line 152a. Since the second opening 1166 does not overlap with the boost capacitor Cbt, the contact portion between the first connecting electrode 1175 and the second electrode 3138 of the third transistor T3 may not overlap with the boost capacitor Cbt.

[0144] In a display device according to one embodiment, the contact portion between the first connecting electrode 1175 and the second electrode 3138 of the third transistor T3 may not overlap with the first scan line 151, and the first connecting electrode 1175 may not overlap with the first scan line 151. Therefore, the transmission path CTR of the compensation voltage can avoid the portion where the second electrode 3138 of the third transistor T3 overlaps with the first scan line 151. Thus, an increase in the resistance of the compensation voltage transmission path CTR can be prevented, the compensation voltage can be transmitted smoothly, and horizontal line patterns can be improved.

[0145] The above description addresses the case where the contact portion between the first connecting electrode 1175 and the second electrode 3138 of the third transistor T3 does not overlap with the first scan line 151, but is not limited to this. By ensuring that the contact portion between the first connecting electrode 1175 and the second electrode 3138 of the third transistor T3 not only does not overlap with the first scan line 151, but also with other wirings to which a negative voltage is applied, the same or similar effects can be achieved. Alternatively, the first connecting electrode 1175 can also be made to not only not overlap with the first scan line 151, but also with other wirings to which a negative voltage is applied.

[0146] The embodiments of the present invention have been described in detail above, but the scope of the present invention is not limited thereto. Various modifications and improvements made by those skilled in the art using the basic concepts of the present invention as defined in the claims also fall within the scope of the present invention.

Claims

1. A display device, wherein, include: The light-emitting diode is electrically connected between the driving voltage line and the common voltage line. A driving transistor is electrically connected between the driving voltage line and the light-emitting diode; The second transistor is electrically connected between the first electrode of the driving transistor and the data line, and the first electrode of the driving transistor is electrically connected to the driving voltage line. The first scan line is electrically connected to the gate electrode of the second transistor; The third transistor is electrically connected between the second electrode of the driving transistor and the gate electrode of the driving transistor, and the second electrode of the driving transistor is electrically connected to the light-emitting diode; The second scan line is electrically connected to the gate electrode of the third transistor; as well as The connecting electrode is electrically connected to the gate electrode of the driving transistor at the first contact portion and to the third transistor at the second contact portion. The connecting electrode includes a first portion extending in a first direction and a second portion electrically connected to the first portion and extending in a second direction different from the first direction.

2. The display device according to claim 1, wherein, At least a portion of the second contact portion does not overlap with the first scan line on the plane.

3. The display device according to claim 2, wherein, The second contact portion is spaced apart from the second scan line on the plane.

4. The display device according to claim 3, wherein, The second contact portion is located on the plane between the first scan line and the second scan line.

5. The display device according to claim 1, wherein, The connecting electrode does not overlap with the first scan line on the plane.

6. The display device according to claim 5, wherein, The connecting electrode intersects the second scan line on the plane.

7. The display device according to claim 1, wherein, The second scan line is located on the plane between the first contact portion and the second contact portion.

8. The display device according to claim 1, wherein, The point where the first part and the second part are connected to each other is located on the plane between the first scan line and the second scan line.

9. The display device according to claim 1, wherein, The display device further includes: Initialize the voltage lines; and The fourth transistor is electrically connected between the initialization voltage line and the second electrode of the third transistor. The third transistor and the fourth transistor include a first semiconductor. The first semiconductor includes the third channel of the third transistor and the fourth channel of the fourth transistor. The second contact portion is on the first semiconductor, and the second contact portion is located in a plane between the third channel and the fourth channel.

10. The display device according to claim 9, wherein, The first semiconductor is an oxide semiconductor. The driving transistor and the second transistor comprise polycrystalline semiconductors.

11. The display device according to claim 1, wherein, The display device further includes: A boost capacitor is electrically connected between the gate electrode of the second transistor and the second electrode of the third transistor. At least a portion of the second contact portion does not overlap with the boost capacitor.

12. The display device according to claim 1, wherein, The third transistor includes: The first electrode is electrically connected to the second electrode of the driving transistor; and The second electrode is electrically connected to the connecting electrode. The second electrode of the third transistor overlaps with the connecting electrode on a plane.

13. The display device according to claim 1, wherein, The display device further includes an insulating layer located between the second electrode of the third transistor and the connecting electrode. The insulating layer defines an opening that overlaps with the second electrode and the connection electrode of the third transistor. The second electrode of the third transistor is electrically connected to the connecting electrode through the opening. The opening does not overlap with the first scan line.

14. The display device according to claim 13, wherein, The second contact portion is located in the opening.

15. A display device, wherein, include: The light-emitting diode is electrically connected between the driving voltage line and the common voltage line. A driving transistor is electrically connected between the driving voltage line and the light-emitting diode; The second transistor is electrically connected between the first electrode of the driving transistor and the data line, and the first electrode of the driving transistor is electrically connected to the driving voltage line. The first scan line is electrically connected to the gate electrode of the second transistor; The third transistor is electrically connected between the second electrode of the driving transistor and the gate electrode of the driving transistor, and the second electrode of the driving transistor is electrically connected to the light-emitting diode; The second scan line is electrically connected to the gate electrode of the third transistor; as well as The connecting electrode is electrically connected to the gate electrode of the driving transistor at the first contact portion and to the third transistor at the second contact portion. At least a portion of the second contact portion does not overlap with the first scan line on the plane.

16. The display device according to claim 15, wherein, The second contact portion is located on the plane between the first scan line and the second scan line.

17. The display device according to claim 15, wherein, The connecting electrode does not overlap with the first scan line on the plane.

18. The display device according to claim 15, wherein, The second scan line is located on the plane between the first contact portion and the second contact portion.

19. The display device according to claim 15, wherein, The connecting electrode includes a first portion extending in a first direction and a second portion connected to the first portion and extending in a second direction different from the first direction. The point where the first part and the second part are connected to each other is located on the plane between the first scan line and the second scan line.

20. A display device, wherein, include: substrate; Light-emitting diodes are mounted on the substrate. A driving transistor is electrically connected between the driving voltage line and the light-emitting diode; The second transistor is electrically connected between the first electrode of the driving transistor and the data line, and the first electrode of the driving transistor is electrically connected to the driving voltage line. The first scan line is electrically connected to the gate electrode of the second transistor; The third transistor is electrically connected between the second electrode of the driving transistor and the gate electrode of the driving transistor, and the second electrode of the driving transistor is electrically connected to the light-emitting diode; The second scan line is electrically connected to the gate electrode of the third transistor; as well as The connecting electrode is electrically connected to the gate electrode of the driving transistor at the first contact portion and to the third transistor at the second contact portion. The connecting electrode includes a first portion extending in a first direction and a second portion connected to the first portion and extending in a second direction different from the first direction.

21. A display device, wherein, include: A light-emitting diode is connected between a driving voltage line to which a driving voltage is applied and a common voltage line to which a common voltage is applied. A driving transistor is connected between the driving voltage line and the light-emitting diode; The second transistor is connected between the first electrode of the driving transistor connected to the driving voltage line and the data line to which the data voltage is applied; The first scan line is connected to the gate electrode of the second transistor and extends in the first direction; The third transistor is connected between the second electrode of the driving transistor connected to the light-emitting diode and the gate electrode of the driving transistor; The second scan line is connected to the gate electrode of the third transistor, and The connecting electrode is connected to the gate electrode of the driving transistor through the first opening and to the third transistor through the second opening. The second scan line is located in a different conductive layer than the first scan line. At least a portion of the contact portion where the connecting electrode contacts the third transistor within the second opening is located on a plane between the first scan line and the second scan line.

22. The display device according to claim 21, wherein, The contact portion does not overlap with the first scan line.

23. The display device according to claim 22, wherein, The third transistor includes: The first electrode is connected to the second electrode of the driving transistor; The second electrode is connected to the connecting electrode; and The channel is located between the first electrode and the second electrode. The gate electrode of the third transistor overlaps with the channel of the third transistor. The second electrode of the third transistor overlaps with the connection electrode.

24. The display device according to claim 23, wherein, The display device further includes an insulating layer located between the second electrode of the third transistor and the connecting electrode. The insulating layer includes the second opening. The second electrode of the third transistor is connected to the connection electrode through the second opening. The second opening does not overlap with the first scan line.

25. The display device according to claim 24, wherein, The contact portion is located inside the second opening.

26. The display device according to claim 24, wherein, The second opening is located on the plane between the first scan line and the second scan line.

27. The display device according to claim 26, wherein, One side edge of the second opening coincides with one side edge of the first scan line.

28. The display device according to claim 27, wherein, The connecting electrode overlaps with the first scan line.

29. The display device according to claim 26, wherein, The second opening is separated from the first scan line.

30. The display device according to claim 29, wherein, The connecting electrode does not overlap with the first scan line.

31. The display device according to claim 26, wherein, The driving transistor and the second transistor comprise polycrystalline semiconductors and are composed of p-type transistors. The third transistor comprises an oxide semiconductor and is composed of an n-type transistor.

32. The display device according to claim 31, wherein, At the same timing, a voltage of opposite polarity to the voltage applied to the first scan line is applied to the second scan line.

33. The display device according to claim 23, wherein, The display device further includes: a boost capacitor connected between the gate electrode of the second transistor and the second electrode of the third transistor. The contact portion does not overlap with the boost capacitor.

34. The display device according to claim 21, wherein, A portion of the contact portion overlaps with the first scan line, while the remaining portion of the contact portion does not overlap with the first scan line.

35. The display device according to claim 34, wherein, The third transistor includes: The first electrode is connected to the second electrode of the driving transistor; The second electrode is connected to the connecting electrode; A channel is located between the first electrode and the second electrode; and The gate electrode overlaps with the channel. The second electrode of the third transistor overlaps with the connection electrode.

36. The display device according to claim 35, wherein, The display device further includes an insulating layer located between the second electrode of the third transistor and the connecting electrode. The insulating layer includes the second opening. The second electrode of the third transistor is connected to the connection electrode through the second opening. A portion of the second opening overlaps with the first scan line, while the remaining portion of the second opening does not overlap with the first scan line.

37. The display device according to claim 36, wherein, The contact portion is located inside the second opening.

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