Gate driving circuit, brush control method and display panel

Abstract

This application belongs to the field of display driving technology, specifically relating to a gate driving circuit, a partial refresh control method, and a display panel. The nth-stage gate driving module includes a pre-charging unit, a partial refresh control unit, and an output unit. The partial refresh control unit, in a full scan frame under partial refresh mode, responds to a first control signal output from a first control signal terminal to form and maintain a partial refresh pre-stored voltage at a voltage pre-stored node. At the refresh start line of the partial refresh frame under partial refresh mode, the drive control node is pre-charged according to the timing coordination of the partial refresh pre-stored voltage, the second control signal output from a second control signal terminal, and the third control signal output from a third control signal terminal. This application improves the problem of erroneous output at the edge of the partial refresh by setting a partial refresh control unit between the pre-charging unit and the drive output unit, allowing the refresh start line of the partial refresh frame to start scanning independently without relying on the preceding stage transmission signal.

Description

Technical Field

[0001] This disclosure belongs to the field of display driving technology, specifically relating to a gate driving circuit, a partial brush control method, and a display panel. Background Technology

[0002] With the increasing demand for large screen sizes, high resolutions, and low power consumption in display devices, progressive scanning using GOA (Gate Driver on Array) technology has become the mainstream driving method. Currently, to reduce display device power consumption, a partial refresh display mode has been proposed, which scans only the area where the image is being updated, rather than refreshing the entire screen, thus significantly reducing the power consumption of the GOA and the driver IC.

[0003] However, in the current partial refresh GOA circuit, under the multi-CK architecture, due to the long timing overlap between adjacent stage transmission signals, erroneous outputs are usually generated at the edge of the refresh area, resulting in display abnormalities and reducing the reliability of partial refresh.

[0004] Therefore, how to improve the erroneous output at the edge of local refresh is an urgent problem to be solved. Summary of the Invention

[0005] This application provides a gate driving circuit, a partial refresh control method, and a display panel. By setting a partial refresh control unit between the pre-charging unit and the driving output unit, cross-frame memory and precise triggering of the refresh start position are realized, so that the refresh start line of the partial refresh frame can start scanning independently without relying on the previous stage transmission signal, thereby improving the problem of erroneous output at the local refresh edge position.

[0006] In a first aspect, this application provides a gate driving circuit, including N cascaded gate driving modules. The nth-stage gate driving module includes: a pre-charge unit connected to the current-stage driving control node, configured to: pre-charge the driving control node in global refresh mode through the cascade transmission signal of the nj-th-stage gate driving module; a local refresh control unit connected to the driving control node, a first control signal terminal, a second control signal terminal, and a third control signal terminal, configured to: in a full scan frame in local refresh mode, in response to a first control signal output by the first control signal terminal, form and maintain a local refresh pre-stored voltage on a voltage pre-stored node; in the refresh start line of a local refresh frame in local refresh mode, pre-charge the driving control node according to the timing coordination of the local refresh pre-stored voltage, the second control signal output by the second control signal terminal, and the third control signal output by the third control signal terminal; wherein the full scan frame is the previous frame of the local refresh frame; and an output unit connected to the driving control node, configured to: output the current-stage cascade transmission signal and the gate driving signal under voltage control on the driving control node.

[0007] Optionally, the local scan control unit includes: a pre-store control subunit connected to the first control signal terminal and the voltage pre-store node of the current stage, configured to: in response to the effective level output by the first control signal terminal in the full scan frame, form and maintain a local scan pre-store voltage on the voltage pre-store node; a trigger enhancement subunit connected to the voltage pre-store node, the second control signal terminal, and the voltage enhancement node, configured to: in response to the second control signal in the local scan frame, generate an enhancement voltage on the voltage enhancement node through capacitive coupling based on the local scan pre-store voltage; and a local scan execution subunit connected to the voltage enhancement node, the third control signal terminal, and the drive control node, configured to: in response to the third control signal in the local scan frame, pre-charge the drive control node based on the enhancement voltage.

[0008] Optionally, the pre-stored control subunit includes: a first transistor, the control terminal of the first transistor being connected to the first control signal terminal, the first terminal of the first transistor being connected to the stage output terminal of the current stage, and the second terminal of the first transistor being connected to the voltage pre-stored node; and a first capacitor, the first terminal of the first capacitor being connected to the voltage pre-stored node, and the second terminal of the first capacitor being connected to the intermediate control node.

[0009] Optionally, the trigger enhancement subunit includes: a second transistor, the control terminal of which is connected to the voltage pre-store node, the first terminal of which is connected to the second control signal terminal, and the second terminal of which is connected to the intermediate control node; a third transistor, the control terminal of which is connected to the intermediate control node, the first terminal of which is connected to the first terminal of the second transistor, and the second terminal of which is connected to the voltage enhancement node; and a second capacitor, the first terminal of which is connected to the voltage enhancement node, and the second terminal of which is connected to the drive control node.

[0010] Optionally, the local brush execution subunit includes: a fourth transistor, the control terminal of the fourth transistor being connected to the third control signal terminal, the first terminal of the fourth transistor being connected to the voltage enhancement node, and the second terminal of the fourth transistor being connected to the drive control node.

[0011] Optionally, the pre-stored control subunit further includes: a fifth transistor, the control terminal of which is connected to the first control signal terminal, the first terminal of which is connected to the stage output terminal of the current stage, and the second terminal of which is connected to the first terminal of the first transistor; and a third capacitor, the first terminal of which is connected to the second terminal of the fifth transistor, and the second terminal of which is connected to a low-level terminal.

[0012] Secondly, this application provides a partial refresh control method applied to a gate drive circuit. The partial refresh control method includes: in a full scan frame in partial refresh mode, in response to a first control signal, forming and maintaining a partial refresh pre-stored voltage on a voltage pre-stored node of a predetermined row; wherein the predetermined row is the refresh start row of the partial refresh frame; in the predetermined row of the partial refresh frame in partial refresh mode, according to the partial refresh pre-stored voltage and the timing coordination of the second and third control signals, pre-charging the drive control node of the current stage through a capacitive coupling network, so that the predetermined row outputs a stage transmission signal and a gate drive signal under the voltage control of the drive control node.

[0013] Optionally, in the full scan frame of the partial refresh mode, forming and maintaining the partial refresh pre-stored voltage on the voltage pre-stored node of the predetermined row includes: during the scanning phase of the full scan frame, making the first control signal active during the pre-charge period of the predetermined row to couple the current stage's transmission signal to the voltage pre-stored node of the predetermined row, and forming and maintaining the partial refresh pre-stored voltage on the voltage pre-stored node.

[0014] Optionally, the predetermined row of the local refresh frame in the local refresh mode, based on the local refresh pre-stored voltage and the timing coordination of the second and third control signals, pre-charges the current-level drive control node through a capacitive coupling network, including: when the predetermined row is reached in the local refresh frame, making the second control signal active, and generating an enhanced voltage at the voltage enhancement node based on the local refresh pre-stored voltage held at the voltage pre-stored node; during the active period of the second control signal, making the third control signal active, and pre-charging the drive control node through capacitive coupling based on the enhanced voltage at the voltage enhancement node.

[0015] Thirdly, this application provides a display panel including a display area and a non-display area, wherein the display area includes multiple scan lines; the non-display area includes the gate driving circuit, and the drive output terminal of the gate driving circuit is electrically connected to at least one scan line.

[0016] The technical solutions provided in this application have at least the following beneficial effects:

[0017] This application adds a partial refresh control unit between the pre-charge unit and the output unit. This unit responds to the first control signal during a full scan frame, forming and maintaining a partial refresh pre-stored voltage corresponding to the refresh start line at the voltage pre-stored node. In the refresh start line of subsequent partial refresh frames, based on this pre-stored voltage and the timing coordination of the second and third control signals, enhanced pre-charging is performed on the drive control node through a capacitive coupling network. This achieves cross-frame memory and precise triggering of the refresh start position, allowing the refresh start line of the partial refresh frame to start scanning independently without relying on the preceding stage transmission signal. This eliminates the erroneous output caused by the timing overlap of adjacent stage transmission signals at the start edge of the local refresh area in multi-CK architectures, ensuring the accuracy and clarity of the image display. This application achieves on-demand startup and precise control of the gate drive signal, effectively reducing scanning power consumption in non-refresh areas while ensuring display quality. It supports efficient execution of multiple consecutive partial refresh frames, significantly improving the energy efficiency ratio and overall reliability of the partial refresh function of the display device. Therefore, this application is a practical application for large-size, multi-CK display devices. Attached Figure Description

[0018] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0019] Figure 1 The diagram shown is a schematic diagram of a display partition provided in an embodiment of this application.

[0020] Figure 2 The diagram shown is a schematic diagram of the gate drive module in the related technology.

[0021] Figure 3 The diagram shown is a circuit schematic of a gate drive module in the related art.

[0022] Figure 4 The diagram shown is a schematic of the driving timing in the related technology.

[0023] Figure 5 The diagram shown is a structural schematic of the first gate driving module provided in an embodiment of this application.

[0024] Figure 6 The diagram shown is a structural schematic of a second gate driving module provided in an embodiment of this application.

[0025] Figure 7 The diagram shown is a circuit diagram of the first type of gate driving module provided in an embodiment of this application.

[0026] Figure 8 The diagram shown is a driving timing diagram of a full scan frame provided in an embodiment of this application.

[0027] Figure 9 The diagram shown is a schematic diagram of the driving timing of a local refresh frame provided in an embodiment of this application.

[0028] Figure 10 The diagram shown is a circuit diagram of a second type of gate driving module provided in an embodiment of this application.

[0029] Figure 11 The diagram shown is a flowchart of a local brush control method provided in an embodiment of this application.

[0030] Explanation of reference numerals in the attached figures:

[0031] 100. Gate drive module; 110. Precharge unit; 120. Partial brush control unit; 121. Pre-store control subunit; 122. Trigger enhancement subunit; 123. Partial brush execution subunit; 130. Output unit; 140. Pull-down unit;

[0032] T1, first transistor; T2, second transistor; T3, third transistor; T4, fourth transistor; T5, fifth transistor; T6, sixth transistor; T7, seventh transistor; T8, eighth transistor; T9, ninth transistor; T10, tenth transistor; C1, first capacitor; C2, second capacitor; C3, third capacitor; C4, fourth capacitor;

[0033] Qn, drive control node; A, voltage pre-store node; B, intermediate control node; C, voltage enhancement node; Fn, stage transmission output terminal; Gn, drive output terminal; Vin1, first control signal terminal; Vin2, second control signal terminal; Vin3, third control signal terminal; VSS, low level terminal; Reset, reset signal terminal; CK, clock signal line. Detailed Implementation

[0034] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided to make this application more comprehensive and complete, and to fully convey the concept of the exemplary embodiments to those skilled in the art.

[0035] Furthermore, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the following description to give a thorough understanding of embodiments of this application. However, those skilled in the art will recognize that the technical solutions of this application can be practiced without one or more of the specific details, or other methods, components, apparatuses, steps, etc., can be employed. In other instances, well-known methods, apparatuses, implementations, or operations are not shown or described in detail to avoid obscuring various aspects of this application.

[0036] The present application will now be described in further detail with reference to the accompanying drawings and specific embodiments. It should be noted that the technical features involved in the various embodiments described below can be combined with each other as long as they do not conflict with each other. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present application, and should not be construed as limiting the present application.

[0037] Most current display devices are active display devices, typically driven by a line-by-line scanning method for pixel setting. Each row of pixels has one scan line, and the scan lines are activated line by line, working in conjunction with data lines to write the target grayscale. The activation of the scan lines is generally achieved using the gate-of-aperture (GOA) method, where the GOA provides the gate drive signal and performs the line-by-line activation function. To save power consumption in display devices, a partial refresh display mode has been proposed, such as... Figure 1 As shown, during normal display, regions A, B, and C all need to be scanned and written line by line. When partial refresh display is used (for example, if only region B has a screen update, region B is partially refreshed), regions A and C are not scanned and written every frame, thereby reducing the output power consumption of GOA and IC. The partial refresh function can be applied to various display devices, such as electronic paper, OLDE, and LCD.

[0038] The inventors of this application have discovered that existing partial refresh GOA technology is generally applied to 2CK circuits in small-sized display devices, and there are no multi-CK GOA circuits. Figure 2 The diagram shows a commonly used basic GOA circuit unit, including a precharge unit, a pull-down unit, an output unit, a noise reduction unit, and a reset unit. The precharge unit and the pull-down unit are responsible for precharging and pulling down the Q point in the circuit, respectively. The precharge and pull-down are controlled by receiving stage transmission signals from the preceding and following stages, respectively. The output unit is turned on with the Q point as the gate and outputs using the clock signal as the gate drive signal. The noise reduction unit performs noise reduction processing on important signals in the circuit. The reset unit pulls down and resets the Q point in each frame. Figure 3 The diagram shows the basic components of the pre-charge unit, pull-down unit, and output unit. The diagram uses the first j-stage for pre-charging and the last i-stage for pull-down.

[0039] The inventors of this application have also discovered that when a multi-CK GOA circuit needs to employ a partial refresh function, the common practice is to trigger the partial refresh start stage using a pre-stored signal, causing the refresh to propagate from the local refresh position. However, in a multi-CK GOA circuit, the Q points and Gout of adjacent stages overlap, making it difficult to conveniently pre-store and activate the local refresh start stage using a signal. This results in erroneous pre-stored signals in adjacent stages above the target position, leading to incorrect output. For example... Figure 4 As shown (hereinafter, 6CK, j=3, i=4 will be used as an example), when the current frame requires local refresh to begin at level n, the Q-points and Gouts of levels n-1 and n-2 overlap with those of level n. Therefore, the current design can only be used with a 2CK GOA circuit and cannot be directly ported to a multiCK GOA circuit to implement local refresh.

[0040] To improve the problem of erroneous output at local refresh edge positions, this application provides a new gate drive circuit, specifically including the following embodiments:

[0041] Figure 5 The diagram shown is a structural schematic of the first type of gate driving module 100 provided in this application embodiment; the gate driving circuit of this embodiment includes N cascaded gate driving modules 100, such as... Figure 5 As shown, the nth stage gate drive module 100 includes a pre-charge unit 110, which is connected to the current stage drive control node Qn and is configured to pre-charge the drive control node Qn through the stage transmission signal of the njth stage gate drive module 100 in global refresh mode; where n≤N.

[0042] It should be noted that before the start of each frame scan or the start of the effective output cycle of the current stage, the pre-charging unit 110, in response to the stage transmission signal from the previous nj stage, pre-charges the drive control node Qn within the current stage, increasing the potential of the drive control node Qn and providing a voltage basis for the control of the output unit 130. In other words, in global refresh mode, the pre-charging unit 110 is responsible for the normal pre-charging of all rows, realizing line-by-line scanning; in local refresh mode, the pre-charging unit 110 is responsible for the pre-charging of the rows before the refresh start row of the local refresh frame, and also responsible for the pre-charging of the rows after the refresh start row of the local refresh frame.

[0043] like Figure 5As shown, the nth-stage gate drive module 100 also includes a partial brush control unit 120, which is connected to the drive control node Qn, the first control signal terminal Vin1, the second control signal terminal Vin2, and the third control signal terminal Vin3. It is configured to: in the full scan frame of the partial refresh mode, in response to the first control signal output by the first control signal terminal Vin1, form and maintain a partial brush pre-stored voltage on the voltage pre-stored node A; and in the refresh start line of the partial brush frame of the partial refresh mode, pre-charge the drive control node Qn according to the timing coordination of the partial brush pre-stored voltage, the second control signal output by the second control signal terminal Vin2, and the third control signal output by the third control signal terminal Vin3.

[0044] It should be noted that the local refresh control unit 120 is a key unit for achieving reliable local refresh under a multi-CK (multi-clock) architecture. Its operation involves two different frames: the full scan frame and the local refresh frame. The two frames have a clear timing relationship, that is, the full scan frame is the frame preceding the local refresh frame. The specific working principle is as follows:

[0045] (1) In a full scan frame: The local brush control unit 120 performs a pre-storage operation. Specifically, during the scanning phase of the full scan frame, the first control signal is set to an active level during the pre-charge period of a predetermined row. At this time, in response to the first control signal, the local brush control unit 120 couples the stage transmission signal from the nk-th stage gate drive module 100 to the voltage pre-storage node A, forming a local brush pre-storage voltage corresponding to the refresh start row position at this node, which is held by an internal capacitor. This process does not affect the normal scan output in the full scan frame, that is, the full scan frame still completes a full scan of all rows. It is worth noting that due to the timing differences of the stage transmission signals, the pre-storage voltages of different rows may have gradient differences.

[0046] (2) At the start of the refresh of the local refresh frame: The local refresh control unit 120 performs triggering and enhancement operations. Specifically, when entering the local refresh frame and reaching the nth line, the second control signal and the third control signal are set to effective levels in sequence according to a preset timing. First, the effective level of the second control signal establishes an initial potential on the internal voltage enhancement node C based on the pre-stored voltage held on the voltage pre-stored node A; subsequently, the effective level of the third control signal conducts the final output path, coupling the potential on the voltage enhancement node C to the drive control node Qn. During this process, the capacitor network inside the local refresh control unit 120 forms two coupling enhancements, thereby forming a positive feedback effect, significantly improving the pre-charging speed and final potential of the drive control node Qn, while effectively reducing the impact caused by the difference in pre-stored voltage gradient. This pre-charging replaces the cascaded pre-charging of the conventional pre-charging unit 110, enabling the nth line to start scanning independently without the preceding stage transmission signal.

[0047] Therefore, the local refresh control unit 120 in this embodiment has the following technical effects: (1) By pre-storing voltage in the full scan frame, the cross-frame storage of refresh start position information is realized, so that the local refresh frame can be refreshed accurately from the predetermined line; (2) The refresh start line of the local refresh frame no longer depends on the previous stage transmission signal, but is started independently by the internally pre-stored voltage, which fundamentally avoids the edge error output problem caused by the overlap of multiple CK timings; (3) Through the timing coordination of the second control signal and the third control signal and the two enhancements of the capacitive coupling network, a positive feedback effect is formed in the local refresh frame, which significantly improves the pre-charging speed and potential stability of the drive control node Qn, and effectively reduces the impact caused by the difference in pre-stored voltage gradient, ensuring the uniformity and reliability of multiple continuous refreshes; (4) Since the pre-stored voltage only exists in the predetermined line (refresh start line and subsequent continuous lines), the adjacent non-refresh lines will not be accidentally triggered, ensuring the clarity and accuracy of the boundary of the local refresh area, and the pre-stored voltage is still maintained after the local refresh frame, supporting the efficient execution of multiple consecutive local refresh frames.

[0048] like Figure 6 As shown, the nth stage gate drive module 100 also includes an output unit 130, which is connected to the drive control node Qn and is configured to output the current stage transmission signal and the gate drive signal under the voltage control of the drive control node Qn.

[0049] It should be noted that the output unit 130 is the final signal output stage, and its operation is directly determined by the potential of the drive control node Qn. When the potential of the drive control node Qn is raised to an effective level, the output unit 130 is turned on, and the received clock signal or other drive signal is output as the cascade signal and / or gate drive signal of this stage. The cascade signal is used to drive the subsequent cascaded modules, and the gate drive signal is used to turn on the pixel TFT of the corresponding row.

[0050] In summary, this embodiment achieves reliable local refresh in a multi-CK architecture through the collaborative operation of the pre-charging unit 110, the local refresh control unit 120, and the output unit 130, using a pre-store-trigger mechanism. The collaborative working principle is as follows:

[0051] 1. Global Refresh Mode: When the first control signal, the second control signal, and the third control signal are all low, the local refresh control unit 120 does not work, and the circuit degenerates into a traditional GOA. The pre-charge unit 110 responds to the previous stage transmission signal and pre-charges the drive control node Qn line by line. Under its control, the output unit 130 outputs the stage transmission signal and the gate drive signal to achieve full-screen scanning.

[0052] 2. Partial Refresh Mode: Partial refresh mode involves full scan frames (pre-stored frames) and partial refresh frames (execution frames), with the full scan frame being the frame preceding the partial refresh frame. Specifically:

[0053] (1) Full scan frame (pre-stored voltage formation)

[0054] During the scanning phase of the full scan frame, the first control signal is at an effective level during the pre-charge period of the predetermined line (i.e., the refresh start line of the subsequent local scan frame); the local scan control unit 120 responds to the first control signal and couples the previous stage transmission signal to the internal voltage pre-store node A, forming and maintaining the pre-stored voltage on the node. This process does not affect the normal scanning output of the full scan frame.

[0055] (2) Local frame refresh (trigger and enhanced precharge)

[0056] In a local area refresh frame, when a predetermined line is reached, the second and third control signals sequentially become active according to a preset timing sequence. After the second control signal becomes active, the local area refresh control unit 120 establishes an initial potential on the internal voltage enhancement node C based on the pre-stored voltage on the voltage pre-stored node A. After the third control signal becomes active, the local area refresh control unit 120 conducts the final output path, coupling the potential on the voltage enhancement node C to the drive control node Qn.

[0057] During this process, the capacitive coupling network inside the local refresh control unit 120 forms two positive feedback enhancements: the potential change of the drive control node Qn is fed back to the voltage pre-store node A and the voltage enhancement node C through capacitors, significantly improving the pre-charging speed and final potential of the drive control node Qn, while reducing the inter-line non-uniformity caused by the difference in pre-stored voltage; after the drive control node Qn is pre-charged to a high level, the output unit 130 outputs the stage transmission signal and the gate drive signal normally, starting the scanning of the local refresh area. Since the pre-stored voltage is maintained after the local refresh frame, it can support the execution of multiple consecutive local refresh frames.

[0058] Therefore, this application adds a partial refresh control unit 120 between the pre-charge unit 110 and the output unit 130. This unit responds to the first control signal in the full scan frame, forming and maintaining a partial refresh pre-stored voltage corresponding to the refresh start line on the voltage pre-stored node A. In the refresh start line of subsequent partial refresh frames, according to the pre-stored voltage and the timing coordination of the second and third control signals, the drive control node Qn is enhanced pre-charged through a capacitive coupling network, thereby realizing cross-frame memory and precise triggering of the refresh start position. This allows the refresh start line of the partial refresh frame to start scanning independently without relying on the previous stage transmission signal, eliminating the erroneous output caused by the timing overlap of adjacent stage transmission signals at the start edge of the local refresh area under the multi-CK architecture, ensuring the accuracy and boundary clarity of the image display. This application realizes on-demand start and precise control of the gate drive signal, effectively reducing the scanning power consumption of the non-refresh area while ensuring display quality, supporting the efficient execution of multiple consecutive partial refresh frames, and significantly improving the energy efficiency ratio and overall reliability of the partial refresh function of the display device. Therefore, this application provides a complete and efficient technical solution for achieving low-power, high-performance partial refresh functionality in large-size, multi-CK display devices.

[0059] Figure 6 The diagram shown is a structural schematic of the second type of gate driving module 100 provided in an embodiment of this application; as shown Figure 6 As shown, the local brush control unit 120 includes a pre-stored control subunit 121, which is connected to the voltage pre-stored node A of the current stage and the first control signal terminal Vin1, and is configured to: in response to the effective level output by the first control signal terminal Vin1 in the full scan frame, form and maintain the local brush pre-stored voltage on the voltage pre-stored node A.

[0060] In this embodiment, the pre-stored control subunit 121 is a position memory module for the local refresh control logic. Specifically, during the scanning phase of the full scan frame, when the first control signal output by the external first control signal terminal Vin1 is at a valid level (e.g., high level) during the pre-charge period of a specific row, this subunit is activated. At this time, by combining the timing of the current level's transmission signal, this subunit forms a local refresh pre-stored voltage on the internal voltage pre-stored node A, representing that the row is a candidate refresh start row, providing a stable control basis for subsequent triggering operations.

[0061] like Figure 6 As shown, the local brush control unit 120 also includes a trigger enhancement subunit 122, which is connected to the voltage pre-stored node A, the second control signal terminal Vin2 and the voltage enhancement node C, and is configured to: in response to the second control signal in the local brush frame, generate an enhanced voltage on the voltage enhancement node C through capacitive coupling according to the local brush pre-stored voltage.

[0062] It should be noted that the trigger enhancement subunit 122 is a voltage enhancement module for the local refresh control logic. Specifically, in a local refresh frame, when a predetermined line is reached, the second control signal terminal Vin2 is set to an effective level (high level) for the output second control signal. At this time, the trigger enhancement subunit 122, based on the local refresh pre-stored voltage held at the voltage pre-stored node A, introduces the high level of the second control signal into the internal path by turning on the internal first-stage switch. During this process, through the capacitive coupling mechanism, an enhanced voltage higher than the initial potential is generated at the voltage enhancement node C. This enhancement effect provides stronger driving capability for subsequent pre-charging.

[0063] like Figure 6 As shown, the local brush control unit 120 also includes a local brush execution subunit 123, which is connected to the voltage enhancement node C, the third control signal terminal Vin3 and the drive control node Qn, and is configured to: in response to the third control signal in the local brush frame, pre-charge the drive control node Qn according to the enhanced voltage.

[0064] It should be noted that the local refresh execution subunit 123 is the final execution module of the local refresh control logic. Specifically, in the local refresh frame, when the third control signal is set to an effective level (high level) at a predetermined time, the local refresh execution subunit 123 conducts the final output path according to the enhanced voltage already established on the voltage enhancement node C. At this time, the enhanced voltage is directly coupled to the drive control node Qn through this path, independently pre-charging the drive control node Qn, causing its potential to rise rapidly to an effective level, thereby activating the output unit 130.

[0065] Therefore, this embodiment further divides the local refresh control unit 120 into a pre-store control subunit 121, a trigger enhancement subunit 122, and a local refresh execution subunit 123, achieving precise three-level control of the refresh start position: pre-store, enhancement, and execution. Specifically, the pre-store control subunit 121 responds to the first control signal during the scanning phase of the full scan frame, forming and maintaining a pre-stored voltage at the voltage pre-stored node A, thereby marking the position information of the refresh start line; the trigger enhancement subunit 122 responds to the second control signal during the local refresh frame, generating an enhanced voltage at the voltage enhancement node C through capacitive coupling based on the pre-stored voltage, thereby converting the static pre-stored voltage into a dynamic strong driving capability, providing sufficient energy reserves for subsequent pre-charging; the local refresh execution subunit 123 responds to the third control signal at the refresh start line of the local refresh frame, independently pre-charging the drive control node Qn based on the enhanced voltage, thereby achieving precise triggering and efficient startup of the refresh start line. Therefore, this application, through the collaborative work of three-level sub-units, not only completely solves the edge output error problem caused by timing overlap in multi-CK architecture, but also significantly improves the pre-charging speed and potential stability of the drive control node Qn through the capacitive coupling enhancement mechanism, effectively compensating for the inter-line non-uniformity caused by the difference in pre-stored voltage gradient, while supporting the efficient execution of multiple consecutive local refresh frames, significantly reducing system power consumption, and providing a high-precision, high-reliability and high-performance solution for large-size, multi-CK display devices.

[0066] Figure 7 The diagram shown is a circuit schematic of the first type of gate driving module 100 provided in an embodiment of this application; as shown Figure 7 As shown, the pre-stored control subunit 121 includes a first transistor T1 and a first capacitor C1; the control terminal of the first transistor T1 is connected to the first control signal terminal Vin1, the first terminal of the first transistor T1 is connected to the stage transmission output terminal of the current stage, and the second terminal of the first transistor T1 is connected to the voltage pre-stored node A; the first terminal of the first capacitor C1 is connected to the voltage pre-stored node A, and the second terminal of the first capacitor C1 is connected to the intermediate control node B.

[0067] like Figure 7 As shown, the trigger enhancement subunit 122 includes a second transistor T2, a third transistor T3, and a second capacitor C2; the control terminal of the second transistor T2 is connected to the voltage pre-store node A, the first terminal of the second transistor T2 is connected to the second control signal terminal Vin2, and the second terminal of the second transistor T2 is connected to the intermediate control node B; the control terminal of the third transistor T3 is connected to the intermediate control node B, the first terminal of the third transistor T3 is connected to the first terminal of the second transistor T2, and the second terminal of the third transistor T3 is connected to the voltage enhancement node C; the first terminal of the second capacitor C2 is connected to the voltage enhancement node C, and the second terminal of the second capacitor C2 is connected to the drive control node Qn.

[0068] like Figure 7 As shown, the local brush execution subunit 123 includes: a fourth transistor T4, the control terminal of the fourth transistor T4 is connected to the third control signal terminal Vin3, the first terminal of the fourth transistor T4 is connected to the voltage enhancement node C, and the second terminal of the fourth transistor T4 is connected to the drive control node Qn.

[0069] like Figure 7 As shown, the pre-charge unit 110 includes a sixth transistor T6. The control terminal of the sixth transistor T6 is connected to the stage transmission output terminal of the nj-th stage gate drive module 100. The first terminal of the sixth transistor T6 is connected to the control terminal of the sixth transistor T6, and the second terminal of the sixth transistor T6 is connected to the drive control node Qn.

[0070] Optionally, the output unit 130 includes a seventh transistor T7, an eighth transistor T8, and a fourth capacitor C4; the control terminal of the seventh transistor T7 is connected to the drive control node Qn, the first terminal of the seventh transistor T7 is connected to the clock signal line CK of the current stage, and the second terminal of the seventh transistor T7 serves as the stage output terminal Fn of the current stage; the control terminal of the eighth transistor T8 is connected to the drive control node Qn, the first terminal of the eighth transistor T8 is connected to the clock signal line CK of the current stage, and the second terminal of the eighth transistor T8 serves as the drive output terminal Gn of the current stage; the first terminal of the fourth capacitor C4 is connected to the drive control node Qn, and the second terminal of the fourth capacitor C4 is connected to the second terminal of the eighth transistor T8.

[0071] like Figure 7 As shown, the nth-stage gate drive module 100 also includes a pull-down unit 140, which is configured to pull down the drive control node Qn and the drive output terminal Gn.

[0072] Optionally, the pull-down unit 140 includes a ninth transistor T9 and a tenth transistor T10; the control terminal of the ninth transistor T9 is connected to the stage output terminal of the (n+i)th stage gate drive module 100, the first terminal of the ninth transistor T9 is connected to the drive output terminal Gn of the output unit 130, and the second terminal of the ninth transistor T9 is connected to the low-level terminal VSS; the control terminal of the tenth transistor T10 is connected to the control terminal of the ninth transistor T9, the first terminal of the tenth transistor T10 is connected to the drive control node Qn, and the second terminal of the tenth transistor T10 is connected to the low-level terminal VSS.

[0073] Here, taking 6CK, j=3, i=4 as an example, combined with Figure 8 and Figure 9 The corresponding timing diagram illustrates the specific working principle of the gate drive circuit in this embodiment as follows:

[0074] I. Global Refresh Mode

[0075] When no partial refresh is required, the first control signal, the second control signal, and the third control signal are all kept at a low level. At this time: the first transistor T1 is turned off, and the pre-stored control subunit 121 does not work; the second transistor T2 is turned off because the voltage pre-stored node A is low; the third transistor T3 is turned off because the intermediate control node B is low; the fourth transistor T4 is turned off because the third control signal is low; and the entire partial refresh control unit 120 is in a bypass state.

[0076] The pre-charge unit 110 operates normally as follows: When the stage transmission signal F(n-3) of stage n-3 is high, the sixth transistor T6 is turned on to pre-charge the drive control node Qn. After the drive control node Qn is pre-charged to a high level, the seventh transistor T7 and the eighth transistor T8 are turned on, outputting the gate drive signal and the stage transmission signal during the high level of the clock signal line CK, completing the row scan. Subsequently, under the action of the stage transmission signal of stage n+4, the drive output terminal Gn and the drive control node Qn are reset through the ninth transistor T9 and the tenth transistor T10 in the pull-down unit.

[0077] In this mode, the circuitry completely degenerates into the traditional GOA, enabling full-screen scanning.

[0078] II. Partial Refresh Mode

[0079] The partial refresh mode involves two frames with a clear temporal relationship: a full scan frame (pre-stored frame) and a partial refresh frame (execution frame), with the full scan frame preceding the partial refresh frame. Assuming that refreshing needs to start from the nth row in the partial refresh frame, the process is as follows.

[0080] (a) Full scan frame (formed by pre-stored voltage)

[0081] The timing sequence during the scanning phase of a full scan frame is as follows: Figure 8 As shown:

[0082] 1. Timing setting of the first control signal: The first control signal is set after the rising edge of the (n-1)th stage transmission signal F(n-1) and before the rising edge of the nth stage transmission signal F(n). Figure 8 At time t1, the signal is pulled high. Further, the first control signal continues until after the rising edge of the (n+2)th stage transmission signal F(n+2) and before the falling edge of the nth stage transmission signal F(n) (e.g., at time t1). Figure 8 The time interval (t1~t2) is pulled low. This period covers the high-level range of F(n), F(n+1), and F(n+2).

[0083] 2. Formation of the pre-stored voltage: During the high level of the first control signal, the first transistor T1 is turned on. Since F(n) is at a high level at this time, this high level charges the voltage pre-stored node A through the first transistor T1, causing the potential of the voltage pre-stored node A to rise.

[0084] Similarly, when F(n+1) and F(n+2) successively go high, An+1 and An+2 are also charged. Due to slight differences in the rise times of F(n), F(n+1), and F(n+2), the final pre-stored potentials of An, An+1, and An+2 are slightly different (e.g., ...). Figure 8 In the voltage storage node A, the voltage values ​​are V1>V2>V3, but all remain at a high level. However, the first capacitor C1 is connected between the voltage pre-stored node A and the intermediate control node B. At this time, the intermediate control node B has not yet been charged (because the second control signal is low). The first capacitor C1 stores the charge of the voltage pre-stored node A, so that the voltage of the voltage pre-stored node A can still be maintained after the first control signal disappears. Here, An represents the voltage pre-stored node in the nth stage gate drive module 100, An+1 represents the voltage pre-stored node in the (n+1)th stage gate drive module 100, and An+2 represents the voltage pre-stored node in the (n+2)th stage gate drive module 100.

[0085] 3. Redundant Row Elimination: For non-target rows (such as rows n-2 and n-1), their transmission signals F(n-2) and F(n-1) occur during the high level of the first control signal, but their falling edges occur while Vin1 is still high. When these signals fall, the first transistor T1 remains on, coupling a low level to the corresponding voltage pre-stored node A, preventing it from forming a valid pre-stored voltage. Therefore, only the target rows An, An+1, and An+2 obtain stable pre-stored voltages.

[0086] 4. Other signal states: During the full scan frame, both the second and third control signals remain low. Therefore, although the voltage pre-store node A is high, turning on the second transistor T2, the second control signal is low, and the intermediate control node B remains low; the third transistor T3 is off, the fourth transistor T4 is off, and other parts of the local brush control unit 120 do not work, thus not affecting normal scan output.

[0087] (ii) Local frame refresh (triggering and enhanced pre-charge): In subsequent local frame refreshes, the timing is as follows Figure 9 As shown, the system uses the pre-stored voltage to start refreshing the nth row.

[0088] 1. Timing settings for the second and third control signals: at the start of local frame refresh ( Figure 9 At time t3, the second control signal is pulled high and remains high for approximately 3 clock cycles. Figure 9 The third control signal is pulled low at time t5. The third control signal is pulled low after the rising edge of the second control signal. Figure 9 The signal is pulled high at time t4 and pulled low slightly before the falling edge of the second control signal.

[0089] 2. First Coupling Enhancement: After the second control signal goes high at time t3, the second transistor T2 turns on because the voltage pre-stored node A in the nth row remains at a high level. The high level of the second control signal charges the intermediate control node B through the second transistor T2, causing the potential of the intermediate control node B to rise. The rise of the intermediate control node B is coupled to the voltage pre-stored node A through the first capacitor C1, further raising the potential of the voltage pre-stored node A, forming the first coupling enhancement. This makes the second transistor T2 conduct more fully, and the potential of the intermediate control node B rises faster.

[0090] 3. Second Coupling Enhancement: The high level of the intermediate control node B turns on the third transistor T3. At this time, the high level of the second control signal reaches the voltage enhancement node C through the third transistor T3, causing the potential of the voltage enhancement node C to rise.

[0091] In addition, the third control signal is pulled high at time t4, the fourth transistor T4 is turned on, and the high level of the voltage enhancement node C starts to charge the drive control node Qn through the fourth transistor T4, causing the potential of the drive control node Qn to rise.

[0092] The rise in the drive control node Qn is coupled back to the voltage enhancement node C through the second capacitor C2, further raising the potential of the voltage enhancement node C, forming a second coupling enhancement. This further rise in the voltage enhancement node C is then fed back to the voltage pre-storage node A through the third transistor T3 (still conducting) and the first capacitor C1, forming a positive feedback loop. This process rapidly raises the potentials of the voltage pre-storage node A, intermediate control node B, voltage enhancement node C, and drive control node Qn to a higher level, significantly improving the pre-charging speed and final potential of the Q point.

[0093] 4. Multi-line continuous triggering: An+1 and An+2 in rows n+1 and n+2 also maintain a pre-stored voltage (albeit slightly lower). They will also undergo the above-mentioned coupling enhancement process within the timing window of the second and third control signals, thus being pre-charged sequentially. Due to the positive feedback effect, the difference in pre-charging effect of each row drive control node Qn is reduced, ensuring the uniformity of multi-line refresh.

[0094] 5. Pre-charge ends: At a certain moment after t4, the third control signal is pulled low first, and the fourth transistor T4 is turned off, stopping the charging of the drive control node Qn. Subsequently, the second control signal is pulled low, and the second transistor T2 and the third transistor T3 are turned off in succession. The intermediate control node B discharges through the second transistor T2, and the voltage enhancement node C discharges through the third transistor T3, but the voltage pre-store node A still maintains the pre-stored voltage (with slight attenuation), providing a basis for subsequent multiple local frame refreshes.

[0095] The high level of the drive control node Qn activates the output unit 130. During the high level of the subsequent clock signal, the signal is transmitted through the output stage of the seventh transistor and the gate drive signal is output by the eighth transistor to start the scanning of the local refresh area.

[0096] (iii) Continuous execution of multiple local refresh frames: Since the pre-stored voltage of voltage pre-store node A remains unchanged after the local refresh frame ends (although slightly attenuated), the system can continuously execute multiple local refresh frames. Each frame starts refreshing from the same starting line, without the need to re-insert a full scan frame. When it is necessary to change the refresh start position or the pre-stored voltage attenuates below the threshold, a new full scan frame is inserted, and the above pre-stored process is repeated.

[0097] (iv) Partial refresh end control: When it is necessary to end the partial refresh at a specific position (e.g., after the m-th row), the system directly controls the clock signal after the m-th row to stop outputting. Since there is no clock pulse, even if there is a step-by-step signal transmission, the output unit 130 cannot output a valid gate drive signal, thereby achieving precise termination of the partial refresh area.

[0098] This embodiment achieves the following technical effects through the coordinated operation of the pre-charging unit 110, the local brush control unit 120, the output unit 130, and the pull-down unit:

[0099] (1) Cross-frame pre-storage and triggering: In the full scan frame, responding to the first control signal, a pre-stored voltage is formed and maintained on the voltage pre-stored node A to realize the cross-frame memory of the refresh start position; in the local scan frame, through the timing coordination of the second and third control signals and the capacitive coupling network, the enhanced pre-charging and precise start of the drive control node Qn are realized, which solves the problem of edge error output caused by timing overlap under the multi-CK architecture.

[0100] (2) Capacitor coupling enhancement mechanism: In the local refresh frame, a positive feedback loop is constructed through the two couplings formed by the first capacitor C1 and the second capacitor C2, which significantly improves the pre-charging speed and final potential of the drive control node Qn, and effectively compensates for the difference in the pre-stored voltage gradient caused by the difference in the timing of the transmission signal, ensuring the uniformity and reliability of the output of multiple continuous refreshes.

[0101] (3) Independent start capability: The refresh start line is started independently by the internally stored voltage and enhanced triggering mechanism, no longer relying on the previous stage transmission signal, ensuring the absolute clarity of the boundary of the local refresh area.

[0102] (4) Multiple consecutive local brushes: The pre-stored voltage remains after the local brush frame ends, supporting the efficient execution of multiple consecutive local brush frames without the need to insert a full scan frame for each frame, which significantly reduces system power consumption.

[0103] (5) Seamless switching: In global refresh mode, the first control signal, the second control signal and the third control signal are all low level, the local refresh control unit 120 is completely bypassed, the circuit degrades to the traditional GOA, and achieves perfect compatibility with the existing display system.

[0104] (6) Complete reset mechanism: The pull-down unit ensures that the drive control nodes Qn and Gn are reliably reset after each line scan, maintaining the determinism of the circuit state and preparing for the next frame.

[0105] Figure 10 The diagram shown is a circuit diagram of the second type of gate driving module 100 provided in an embodiment of this application; Figure 10 The gate drive module 100 shown is in Figure 7 The difference lies in the addition of a fifth transistor T5 and a third capacitor C3; specifically as follows: Figure 10 As shown, the pre-stored control subunit 121 also includes: a fifth transistor T5 and a third capacitor C3; the control terminal of the fifth transistor T5 is connected to the first control signal terminal Vin1, the first terminal of the fifth transistor T5 is connected to the current stage transmission output terminal, and the second terminal of the fifth transistor T5 is connected to the first terminal of the first transistor T1; the first terminal of the third capacitor C3 is connected to the second terminal of the fifth transistor T5, and the second terminal of the third capacitor C3 is connected to the low-level terminal.

[0106] It should be noted that during the pre-storage phase of the full scan frame: when the first control signal is active (high level), the first transistor T1 and the fifth transistor T5 are simultaneously turned on. When the current stage's transmission signal F(n) is high, this high level charges the voltage pre-storage node A through the fifth transistor T5 and the first transistor T1, forming the pre-storage voltage. Simultaneously, the connection node between the fifth transistor T5 and the first transistor T1 is also charged to a high level, and the charge of this node is stored by the third capacitor C3. When the first control signal goes low, the first transistor T1 and the fifth transistor T5 are turned off. At this time, the charge stored in the third capacitor C3 can be compensated for by the fifth transistor T5 (with extremely weak leakage current in the off state) or the first transistor T1, thereby slowing down the decay of the pre-storage voltage at voltage pre-storage node A.

[0107] Therefore, this embodiment, by adding a fifth transistor T5 and a third capacitor C3, forms a charge-holding auxiliary node on the charging path of the voltage pre-stored node A. This auxiliary node stores charge in the third capacitor C3, and after the first control signal is turned off, it can perform charge compensation on the voltage pre-stored node A, effectively reducing the leakage rate of the voltage pre-stored node A, extending the retention time of the pre-stored voltage, further improving the retention capability of the pre-stored voltage and the reliability of the circuit, and providing a more robust implementation scheme for the partial refresh function of the multi-CK GOA circuit.

[0108] Figure 11 The diagram shown is a schematic flowchart of a local swiping control method provided in an embodiment of this application; as follows: Figure 11 As shown, the partial brush control method provided in this embodiment is applied to the gate drive circuit shown in the above embodiment, and specifically includes the following steps:

[0109] Step S100: In a full scan frame in partial refresh mode, in response to a first control signal, a partial refresh pre-stored voltage is formed and maintained on a voltage pre-stored node of a predetermined row; wherein, the predetermined row is the refresh start row of the partial refresh frame.

[0110] Optionally, in the full scan frame of the partial refresh mode, forming and maintaining the partial refresh pre-stored voltage on the voltage pre-stored node of the predetermined row includes: during the scanning phase of the full scan frame, making the first control signal active during the pre-charge period of the predetermined row to couple the current stage's transmission signal to the voltage pre-stored node of the predetermined row, and forming and maintaining the partial refresh pre-stored voltage on the voltage pre-stored node.

[0111] Step S200: In the partial refresh mode, the predetermined row of the partial refresh frame is pre-charged through a capacitive coupling network according to the partial refresh pre-stored voltage and the timing coordination of the second control signal and the third control signal, so that the predetermined row outputs the stage transmission signal and the gate drive signal under the voltage control of the drive control node.

[0112] Optionally, the predetermined row of the local refresh frame in the local refresh mode, based on the local refresh pre-stored voltage and the timing coordination of the second and third control signals, pre-charges the current-level drive control node through a capacitive coupling network, including: when the predetermined row is reached in the local refresh frame, making the second control signal active, and generating an enhanced voltage at the voltage enhancement node based on the local refresh pre-stored voltage held at the voltage pre-stored node; during the active period of the second control signal, making the third control signal active, and pre-charging the drive control node through capacitive coupling based on the enhanced voltage at the voltage enhancement node.

[0113] In one embodiment, the local brush control method further includes: after executing multiple local brush frames consecutively, inserting a new full scan frame, and re-forming and maintaining the updated local brush trigger voltage across frames on the local brush trigger node of the updated predetermined row.

[0114] It should be noted that the working principle of the partial refresh control method provided in this embodiment is essentially the same as that of the gate drive circuit described above. Both are based on the inventive concept of full scan frame pre-storage and partial refresh frame triggering. Through the timing coordination of the first, second, and third control signals and the capacitive coupling network, cross-frame memory and precise enhanced start-up of the refresh start line are achieved. Therefore, the specific workflow, signal timing, and potential changes of each node of this method can be found in the detailed description of the working principle of the gate drive circuit above, and will not be repeated here.

[0115] In one embodiment, this application provides a display panel including a display area and a non-display area. The display area includes multiple scan lines, and the non-display area includes the aforementioned gate driving circuit. The drive output terminal of the gate driving circuit is electrically connected to at least one scan line.

[0116] The gate drive circuit, partial refresh control method, and display panel provided in this application form and maintain a pre-stored voltage corresponding to the refresh start line at the voltage pre-stored node in response to the first control signal in the full scan frame; in subsequent partial refresh frames, the drive control node is enhanced pre-charged through a capacitive coupling network according to the timing coordination of the pre-stored voltage, the second control signal, and the third control signal, thereby realizing cross-frame memory and precise start of the refresh start position.

[0117] Specifically, the gate drive circuit of this application, through the coordinated operation of the pre-charge unit, the partial refresh control unit, and the output unit, is compatible with traditional GOA functions in global refresh mode, and achieves precise partial refresh in partial refresh mode through a three-level control chain of "pre-store-enhancement-execution". Specifically, the pre-store control subunit responds to the first control signal during the scanning phase of the full scan frame, forming and maintaining a pre-stored voltage at the voltage pre-stored node; the trigger enhancement subunit responds to the second control signal in the partial refresh frame, generating an enhanced voltage at the voltage enhancement node through capacitive coupling based on the pre-stored voltage; the partial refresh execution subunit responds to the third control signal at the refresh start line of the partial refresh frame, independently pre-charging the drive control node based on the enhanced voltage and initiating the output of that line. During this process, the two coupled positive feedbacks formed by the first and second capacitors significantly improve the pre-charge speed and potential stability of the drive control node, while effectively reducing the impact of the pre-stored voltage gradient caused by differences in the timing of the transmission signals.

[0118] The beneficial effects of this application are as follows: by using cross-frame pre-storage and capacitive coupling enhancement mechanism, the erroneous output problem caused by the overlapping of signal transmission timing between adjacent stages under the multi-CK architecture is completely eliminated, and the precise control of the refresh boundary is achieved; the positive feedback formed by the capacitive coupling network significantly improves the pre-charge quality and inter-line uniformity; it supports the efficient execution of multiple consecutive local refresh frames, which significantly reduces system power consumption; it is seamlessly compatible with the global refresh mode without changing the workflow of the existing display system; and through modular circuit design, it is easy to integrate and implement in large-size, high-resolution display devices.

[0119] Therefore, this application provides a complete, efficient and easy-to-implement technical solution for achieving low-power, high-reliability local refresh functionality in large-size, multi-CK display devices, which has significant industrial practical value and broad application prospects.

[0120] Furthermore, the terms "first," "second," and "third," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first," "second," or "third" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0121] In the description of this specification, references to terms such as "some embodiments," "exemplarily," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. The illustrative expressions of the above terms in this specification do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in a suitable manner in any one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0122] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application. Therefore, any changes or modifications made in accordance with the claims and description of this application should fall within the scope of this patent application.

Claims

1. A gate drive circuit comprising N cascaded gate drive modules, characterized in that, The nth-stage gate drive module includes: The pre-charge unit, connected to the current stage's drive control node, is configured to pre-charge the drive control node in global refresh mode via the stage transmission signal of the nj-th stage gate drive module. The local refresh control unit, connected to the drive control node, the first control signal terminal, the second control signal terminal, and the third control signal terminal, is configured to: in a full scan frame in local refresh mode, in response to a first control signal output from the first control signal terminal, form and maintain a local refresh pre-stored voltage on the voltage pre-stored node; in the refresh start line of the local refresh frame in local refresh mode, pre-charge the drive control node according to the timing coordination of the local refresh pre-stored voltage, the second control signal output from the second control signal terminal, and the third control signal output from the third control signal terminal; wherein, the full scan frame is the previous frame of the local refresh frame; The output unit, connected to the drive control node, is configured to output the current stage's transmission signal and gate drive signal under voltage control at the drive control node.

2. The gate drive circuit according to claim 1, characterized by The local brush control unit includes: The pre-stored control subunit, connected to the first control signal terminal and the voltage pre-stored node of the current stage, is configured to: in response to the effective level output by the first control signal terminal in the full scan frame, form and maintain the local brush pre-stored voltage on the voltage pre-stored node; The trigger enhancement subunit, connected to the voltage pre-stored node, the second control signal terminal, and the voltage enhancement node, is configured to: in response to the second control signal in the local refresh frame, generate an enhanced voltage on the voltage enhancement node through capacitive coupling based on the local refresh pre-stored voltage; The local brush execution subunit, connected to the voltage enhancement node, the third control signal terminal, and the drive control node, is configured to: in response to the third control signal during the local brush frame, pre-charge the drive control node according to the enhanced voltage.

3. The gate drive circuit according to claim 2, characterized by The pre-stored control subunit includes: The first transistor has a control terminal connected to the first control signal terminal, a first terminal connected to the current stage's output terminal, and a second terminal connected to the voltage pre-store node. A first capacitor, the first end of which is connected to the voltage pre-storage node, and the second end of which is connected to the intermediate control node.

4. The gate drive circuit according to claim 2, characterized by The trigger enhancement subunit includes: The second transistor has a control terminal connected to the voltage pre-store node, a first terminal connected to the second control signal terminal, and a second terminal connected to the intermediate control node. The third transistor has its control terminal connected to the intermediate control node, its first terminal connected to the first terminal of the second transistor, and its second terminal connected to the voltage enhancement node. The second capacitor has its first terminal connected to the voltage enhancement node and its second terminal connected to the drive control node.

5. The gate drive circuit according to claim 2, characterized by The local brush execution subunit includes: The fourth transistor has its control terminal connected to the third control signal terminal, its first terminal connected to the voltage enhancement node, and its second terminal connected to the drive control node.

6. The gate driving circuit according to claim 3, characterized in that, The pre-stored control subunit also includes: The fifth transistor has its control terminal connected to the first control signal terminal, its first terminal connected to the current stage's output terminal, and its second terminal connected to the first terminal of the first transistor. The third capacitor has its first terminal connected to the second terminal of the fifth transistor, and its second terminal connected to the low-level terminal.

7. A method of brush control, characterized in that The partial brush control method, applied to the gate drive circuit according to any one of claims 1-6, comprises: In a full scan frame in partial refresh mode, in response to a first control signal, a partial refresh pre-stored voltage is formed and maintained at a voltage pre-stored node in a predetermined row; wherein, the predetermined row is the refresh start row of the partial refresh frame; In the predetermined row of the local refresh frame in the local refresh mode, according to the local refresh pre-stored voltage and the timing coordination of the second control signal and the third control signal, the current stage drive control node is pre-charged through the capacitive coupling network, so that the predetermined row outputs the stage transmission signal and the gate drive signal under the voltage control of the drive control node.

8. The brush control method according to claim 7, wherein In the full scan frame of the partial refresh mode, forming and maintaining the partial refresh pre-stored voltage at the voltage pre-stored node of the predetermined row includes: During the scanning phase of the full scan frame, the first control signal is made active during the pre-charge period of the predetermined row to couple the current stage's transmission signal to the voltage pre-store node of the predetermined row, and the local brush pre-store voltage is formed and maintained at the voltage pre-store node.

9. The brush control method according to claim 7, wherein The predetermined row of the local refresh frame in the local refresh mode, based on the local refresh pre-stored voltage and the timing coordination of the second and third control signals, pre-charges the current-level drive control node through a capacitive coupling network, including: When the predetermined row is reached in the local refresh frame, the second control signal is made active, and an enhanced voltage is generated at the voltage enhancement node according to the local refresh pre-stored voltage held at the voltage pre-stored node. During the period when the second control signal is active, the third control signal is made active, and the drive control node is pre-charged through capacitive coupling according to the enhanced voltage on the voltage enhancement node.

10. A display panel comprising a display area and a non-display area, the display area comprising a plurality of scan lines; characterized in that, The non-display area includes the gate driving circuit according to any one of claims 1-6, wherein the driving output terminal of the gate driving circuit is electrically connected to at least one scan line.

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