Magnetic storage device

Abstract

A magnetic memory device is provided. The magnetic memory device includes a memory cell including a first magnetic tunnel junction element, a one-time programmable (OTP) cell including a second magnetic tunnel junction element, a switching element between a first bit line connected with the memory cell and a second bit line connected with the OTP cell, and a peripheral circuit configured to control the switching element to disconnect the first bit line and the second bit line from each other in response to a write voltage being applied to the OTP cell.

Description

Cross-reference to related applications

[0001] This application claims priority to Korean Patent Application No. 10-2024-0187007, filed on December 16, 2024, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0002] Some example embodiments involve magnetic storage devices. Background Technology

[0003] As electronic devices become faster and consume less power, the memory devices embedded within them are expected to have fast read / write operations and low operating voltages. Magnetic storage devices are being researched as a solution to meet these requirements. Due to their non-volatility and high-speed operation, magnetic storage devices are attracting attention as a next-generation memory.

[0004] As the integration of magnetic storage devices becomes increasingly sophisticated, STT-MRAM is being researched, which uses the spin-transfer torque (STT) phenomenon to store information. STT-MRAM stores information by directly applying current to the magnetic tunnel junction element to induce magnetization reversal. Highly integrated STT-MRAM enables high-speed and low-current operation.

[0005] In some examples, OTP (One-Time Programmable) memory is a type of non-volatile memory in which data is permanently stored after a single programming. OTP memory is generally used for the purpose of recording specific information only once and allowing continuous reading of that information, and can be used in applications where data stability and security are critical. Because OTP memory can only be programmed once, the information within it cannot be altered, thus ensuring data integrity and stability. OTP memory is primarily used in applications where reliability and security are desired. For example, OTP memory is used to store information; this information may include one or more of digital security tokens, smart cards, keys and passwords, boot codes, and production / manufacturing settings, and can be embedded as part of a semiconductor chip or provided as a standalone chip. When OTP memory is embedded as part of a chip, it can be implemented at low cost, provided that the OTP is fully compatible with logic CMOS processes, and therefore can be used effectively without affecting the performance of the core logic. Summary of the Invention

[0006] Some example embodiments may provide magnetic storage devices with improved product reliability.

[0007] The objectives of the present invention are not limited to those described above. Other objectives and / or advantages not mentioned in the present invention are to be understood based on the following description and may be more clearly understood based on embodiments according to this disclosure. Furthermore, it will be readily understood that the objectives and / or advantages according to some exemplary embodiments can be achieved using the means and combinations thereof shown in the claims.

[0008] A magnetic storage device according to some example embodiments includes: a storage cell including a first magnetic tunnel junction element; an one-time programmable (OTP) cell including a second magnetic tunnel junction element; a switching element between a first bit line connected to the storage cell and a second bit line connected to the OTP cell; and peripheral circuitry configured to control the switching element to disconnect the first bit line and the second bit line from each other in response to a write voltage being applied to the OTP cell.

[0009] Alternatively or additionally, a magnetic storage device according to some example embodiments includes: a memory cell connected to a first bit line and including a first magnetic tunnel junction element; an one-time programmable (OTP) cell connected to a second bit line and including a second magnetic tunnel junction element; a bit line connection transistor located between the first bit line and the second bit line in a first direction in which the first bit line and the second bit line extend; and peripheral circuitry configured to control the bit line connection transistor. The peripheral circuitry is configured to control the bit line connection transistor to turn off in response to a first write voltage being applied to the OTP cell, and to control the bit line connection transistor to turn on in response to a second write voltage being applied to the memory cell.

[0010] Alternatively or additionally, a magnetic storage device including a memory cell and an OTP cell according to some example embodiments includes: a first magnetic tunnel junction element connected to a first bit line; a first cell transistor connecting the first source line and the first magnetic tunnel junction element to each other and connected to a first word line; a second magnetic tunnel junction element connected to a second bit line; a cell array connecting the second source line and the second magnetic tunnel junction element to each other, wherein the cell array includes a second cell transistor, a third cell transistor, and a fourth cell transistor connected to a second word line, a third word line, and a fourth word line, respectively; a switching element located between the first bit line and the second bit line in a first direction in which the first bit line and the second bit line extend; a first via structure on one side of the switching element and adjacent to the memory cell; a second via structure on the other side of the switching element and adjacent to the OTP cell; and peripheral circuitry closer to the OTP cell than to the memory cell in the first direction. The peripheral circuitry is configured to control the switching element to electrically disconnect the first bit line and the second bit line from each other in response to performing a first write operation on the OTP cell.

[0011] Alternatively or additionally, according to some example embodiments, a method of operating a magnetic storage device is provided, the magnetic storage device including a first bit line and a second bit line that can be connected to each other, a memory cell connected to the first bit line, and a one-time programmable (OTP) cell connected to the second bit line, the method including disconnecting the first bit line and the second bit line from each other in response to a write voltage being applied to the OTP cell.

[0012] The method may also include controlling not to apply write voltage to the memory cell.

[0013] The method may also include applying a write voltage to the OTP cell based on the row address supplied to the row decoder and the column address supplied to the column decoder.

[0014] Specific details of the example embodiments are included in the detailed description and accompanying drawings. Attached Figure Description

[0015] The above and other aspects and features will become clearer from the detailed description of the illustrative embodiments with reference to the accompanying drawings, in which:

[0016] Figure 1 These are example block diagrams of magnetic storage devices according to some example embodiments;

[0017] Figure 2 These are example circuit diagrams illustrating magnetic storage devices according to some example embodiments;

[0018] Figure 3 This is an example circuit diagram illustrating a memory cell according to some example embodiments;

[0019] Figure 4 This is an example circuit diagram illustrating an OTP unit according to some example embodiments;

[0020] Figure 5 This is a diagram illustrating the resistance of the memory cell and the OTP cell according to some example embodiments;

[0021] Figure 6 This is an example layout plan view of a magnetic storage device according to some example embodiments;

[0022] Figure 7 It is along Figure 6 Example cross-sectional view taken from line A-A';

[0023] Figure 8 These are example cross-sectional views of magnetic storage devices according to some example embodiments;

[0024] Figures 9 to 11 These are example cross-sectional views of magnetic storage devices according to some example embodiments;

[0025] Figure 12This is a diagram illustrating the cell area and peripheral circuit area of ​​a magnetic storage device according to some example embodiments;

[0026] Figure 13 It is shown Figure 12 A magnified view of region S. Detailed Implementation

[0027] Figure 1 This is an example block diagram of a magnetic storage device according to some example embodiments.

[0028] refer to Figure 1 According to some example embodiments, the magnetic storage device may include a cell array 10, a row selection circuit 20, a column selection circuit 30, a write driver 40, a sensing circuit 50, a source line driver 60, an input / output circuit 70, and control logic 80.

[0029] Cell array 10 may include multiple memory blocks. Each memory block includes a memory cell array 11, an OTP cell array 12, and a switching element array 13. Memory cell array 11 includes multiple memory cells connected to word lines WL1 and BL. OTP cell array 12 includes multiple OTP cells connected to word lines WL21, WL31, and WL41 and the bit line BL. Switching element array 13 includes multiple switching elements connected to word lines WL3 and BL.

[0030] The storage cell and OTP cell can be configured to store data therein. The storage cell and / or OTP cell may include, for example, a variable resistance element, wherein the value of the stored data is determined based on the resistance value. For example, the storage cell and / or OTP cell may include a magnetic tunnel junction (MTJ) element.

[0031] For example, the memory cell and OTP cell may include one or more of resistive RAM (ReRAM), phase change random access memory (PRAM), ferroelectric random access memory (FRAM), etc., or may include magnetic domain memory (MRAM), such as spin-torque transfer MRAM (STT-MRAM), spin-torque transfer magnetized switch RAM (Spin-RAM), spin motion transfer RAM (SMT-RAM), etc.

[0032] Row selection circuit 20 can select (or drive) word lines WL1, WL21, WL31, and WL41 connected to the memory cell and OTP cell performing read or programming operations based on the row address R_ADDR and the row control signal R_CTRL. Alternatively or additionally, row selection circuit 20 can select (or drive) word line WL3 connected to a switching element. Row selection circuit 20 can provide the selected word line WL with a drive voltage VDD received from control logic 80.

[0033] The column selection circuit 30 can select the bit line BL and / or source line SL connected to the memory cell and OTP cell that performs the read operation or programming operation based on the column address C_ADDR and the column control signal C_CTRL. The column selection circuit 30 can connect the selected bit line BL and the selected source line SL to the data line DL.

[0034] During programming operations, write driver 40 can drive a programming voltage (or write current) to store the write data in memory cells and OTP cells selected by row selection circuit 20 and column selection circuit 30. For example, during programming operations, write driver 40 can control the voltage of data line DL based on the write data DATA input from input / output circuit 70 via write input / output line WIO to store the write data DATA in the selected memory cells.

[0035] The sensing circuit 50 can detect the signal output via the data line DL during a read operation and can determine the value of the data stored in the memory cell and the OTP cell based on the detected signal. The sensing circuit 50 can be connected to the column select circuit 30 via the data line DL and to the input / output circuit 70 via the read input / output line RIO. The sensing circuit 50 can input the sensed read data DATA to the input / output circuit 70 via the read input / output line RIO.

[0036] The source line driver 60 can drive the source line SL at a specific voltage level under the control of the control logic 80. For example, the source line driver 60 can receive a voltage from the control logic 80 to drive the source line SL.

[0037] The input / output circuit 70 can send write data DATA input from an external source to the write driver 40, and can output read data DATA input from the sensing circuit 50 to an external component.

[0038] Control logic 80 can generally control the operation of the magnetic storage device. For example, control logic 80 can control row selection circuit 20, column selection circuit 30, write driver 40, sensing circuit 50, source line driver 60, input / output circuit 70, etc. In one example, control logic 80 can operate in response to a command CMD or control signal input from an external source. The command CMD can include read commands, write commands, etc.

[0039] Figure 2 These are example circuit diagrams illustrating magnetic storage devices according to some example embodiments.

[0040] refer to Figure 2According to some example embodiments, the cell array 10 may include a memory cell array 11, an OTP cell array 12, and a switching element array 13. The memory cell array 11 includes a plurality of memory cells MC arranged along the row and column directions. The OTP cell array 12 includes a plurality of OTP cells OTPC arranged along the row and column directions. The switching element array 13 includes a plurality of switching elements SW arranged along the column direction.

[0041] Multiple memory cells MC can be connected to the first word line WL1, the bit line BL, and the source line SL. Each memory cell MC may include a first magnetic tunnel junction element MTJ1 and a first pair of cell transistors CT11 and CT12.

[0042] The memory cell MC can be programmed multiple times. The memory cell MC can switch between two resistive states under an electrical pulse applied to the first magnetic tunnel junction element MTJ1. The memory cell MC can be used as MRAM.

[0043] In some example embodiments, the memory cell MC may have a structure in which multiple unit transistors (e.g., a pair of unit transistors CT11 and CT12) are connected to a magnetic tunnel junction element MTJ1. For example, the memory cell MC may include two unit transistors CT11 and CT12. The number of unit transistors included in the memory cell MC is not limited to this and may vary.

[0044] One end of the first magnetic tunnel junction element MTJ1 is connected to the bit line BL, and the other end of the first magnetic tunnel junction element MTJ1 is connected to one end of the (1-1) unit transistor CT11 and one end of the (1-2) unit transistor CT12. The other ends of the (1-1) unit transistor CT11 and the (1-2) unit transistor CT12 are connected to the source line SL. The gate electrode of the (1-1) unit transistor CT11 and the gate electrode of the (1-2) unit transistor CT12 can be connected to the first word line WL1. The (1-1) unit transistor CT11 and the (1-2) unit transistor CT12 can be turned on or off based on the signal (or voltage) provided through the first word line WL1.

[0045] Multiple OTP cells OTPC can be connected to the second to fourth word lines WL21, WL31, and WL41, the bit line BL, and the source line SL. Each OTP cell OTPC may include a second magnetic tunnel junction element MTJ2, a second pair of cell transistors CT21 and CT22, a third magnetic tunnel junction element MTJ3, a third pair of cell transistors CT31 and CT32, a fourth magnetic tunnel junction element MTJ4, and a fourth pair of cell transistors CT41 and CT42.

[0046] The OTP unit OTPC can only be programmed once. The programmed second magnetic tunnel junction element MTJ2 can have an irreversible resistive state. The OTP unit OTPC can be used as an OTP.

[0047] According to some example embodiments, the OTP unit OTPC can have a structure in which multiple unit transistors CT21, CT22, CT31, CT32, CT41, and CT42 are connected to a magnetic tunnel junction element MTJ2. For example, the OTP unit OTPC may include six unit transistors CT21, CT22, CT31, CT32, CT41, and CT42. A second pair of unit transistors CT21 and CT22, a third pair of unit transistors CT31 and CT32, and a fourth pair of unit transistors CT41 and CT42 may be connected in parallel with each other. The number of unit transistors included in the OTP unit OTPC is not limited to this and can vary.

[0048] One end of the second magnetic tunnel junction element MTJ2 is connected to the bit line BL, and the other end of the second magnetic tunnel junction element MTJ2 is connected to one end of the (2-1) unit transistor CT21 and one end of the (2-2) unit transistor CT22. The other ends of the (2-1) unit transistor CT21 and the (2-2) unit transistor CT22 are connected to the source line SL. The gate electrode of the (2-1) unit transistor CT21 and the gate electrode of the (2-2) unit transistor CT22 can be connected to the second word line WL21. The (2-1) unit transistor CT21 and the (2-2) unit transistor CT22 can be turned on or off based on the signal (or voltage) provided through the second word line WL21.

[0049] One end of the third magnetic tunnel junction element MTJ3 is connected to the bit line BL. The other end of the third magnetic tunnel junction element MTJ3 is not connected to one end of the (3-1) unit transistor CT31 and one end of the (3-2) unit transistor CT32, and the third magnetic tunnel junction element MTJ3 is electrically isolated from the third unit transistors CT31 and CT32. One end of the (3-1) unit transistor CT31 and one end of the (3-2) unit transistor CT32 are connected to the other end of the second magnetic tunnel junction element MTJ2. The other ends of the (3-1) unit transistor CT31 and the (3-2) unit transistor CT32 are connected to the source line SL. The gate electrode of the (3-1) unit transistor CT31 and the gate electrode of the (3-2) unit transistor CT32 can be connected to the third word line WL31. The (3-1) unit transistor CT31 and the (3-2) unit transistor CT32 can be turned on or off based on the signal (or voltage) provided through the third word line WL31.

[0050] One end of the fourth magnetic tunnel junction element MTJ4 is connected to the bit line BL. The other end of the fourth magnetic tunnel junction element MTJ4 is not connected to one end of the (4-1) unit transistor CT41 or one end of the (4-2) unit transistor CT42, and the fourth magnetic tunnel junction element MTJ4 is electrically isolated from the fourth unit transistors CT41 and CT42. One end of the (4-1) unit transistor CT41 and one end of the (4-2) unit transistor CT42 are connected to the other end of the second magnetic tunnel junction element MTJ2. The other ends of the (4-1) unit transistor CT41 and the (4-2) unit transistor CT42 are connected to the source line SL. The gate electrode of the (4-1) unit transistor CT41 and the gate electrode of the (4-2) unit transistor CT42 can be connected to the fourth word line WL41. The (4-1) unit transistor CT41 and the (4-2) unit transistor CT42 can be turned on or off based on the signal (or voltage) provided through the fourth word line WL41.

[0051] Each of the third magnetic tunnel junction element MTJ3 and the fourth magnetic tunnel junction element MTJ4 can act as a dummy magnetic tunnel junction element. Each of the third magnetic tunnel junction element MTJ3 and the fourth magnetic tunnel junction element MTJ4 can be an unused magnetic tunnel junction element.

[0052] In the cell array 10, the combination of the second magnetic tunnel junction element MTJ2 with the second cell transistors CT21 and CT22, the combination of the third magnetic tunnel junction element MTJ3 with the third cell transistors CT31 and CT32, and the combination of the fourth magnetic tunnel junction element MTJ4 with the fourth cell transistors CT41 and CT42 of the OTP cell OTPC can be arranged such that each of the combinations of the second magnetic tunnel junction element MTJ2 with the second cell transistors CT21 and CT22, the third magnetic tunnel junction element MTJ3 with the third cell transistors CT31 and CT32, and the fourth magnetic tunnel junction element MTJ4 with the fourth cell transistors CT41 and CT42 of the OTP cell OTPC has a repetition periodicity equal to that of the combination of the first magnetic tunnel junction element MTJ1 with the first cell transistors CT11 and CT12 of the memory cell MC.

[0053] Each of the first to fourth unit transistors CT11, CT12, CT21, CT22, CT31, CT32, CT41, and CT42 may, for example, include at least one of a diode, a PNP bipolar transistor, an NPN bipolar transistor, an NMOS field-effect transistor, and a PMOS field-effect transistor. Each of the first to fourth unit transistors CT11, CT12, CT21, CT22, CT31, CT32, CT41, and CT42 may include the same or different diodes, PNP bipolar transistors, NPN bipolar transistors, NMOS field-effect transistors, and PMOS field-effect transistors; the exemplary embodiments are not limited thereto.

[0054] In some example embodiments, memory cells MC constituting one column (or included in one column) and memory cells MC constituting another column (or included in another column) may share a source line SL. OTP cells OTPC constituting one column (or included in one column) and OTP cells OTPC constituting another column (or included in another column) may share a source line SL.

[0055] The cell array 10 can be electrically connected to peripheral circuitry. Peripheral circuitry may include, for example, […]. Figure 1 The system includes row selection circuit 20, column selection circuit 30, write driver 40, sensing circuit 50, source line driver 60, input / output circuit 70, control logic 80, etc. The memory cell MC and the OTP cell OTPC can be electrically connected to peripheral circuitry. For example, the memory cell MC and the OTP cell OTPC can share peripheral circuitry.

[0056] In some example embodiments, the OTP unit OTPC can be connected to a specific word line (e.g., one or more of the second to fourth word lines WL21, WL31, WL41).

[0057] The memory cell MC connected to the first word line WL1 can be disposed in the memory cell array 11, and the OTP cell OTPC connected to the second word line WL21, the third word line WL31, and the fourth word line WL41 can be disposed in the OTP cell array 12. Only the memory cell MC can be connected to the first word line WL1, and only the OTP cell OTPC can be connected to the second to fourth word lines WL21, WL31, and WL41. The memory cell MC and the OTP cell OTPC can be connected to a bit line BL.

[0058] The arrangement of the storage cell array 11 and the OTP cell array 12 in the cell array 10 can be varied. For example, the OTP cell array 12 can be arranged around the storage cell array 11.

[0059] Multiple switching elements SW can be connected to the fifth word line WL3, the bit line BL, and the source line SL. The switching elements SW can be positioned between the bit line BL connected to the memory cell MC and the bit line BL connected to the OTP cell OTPC.

[0060] As will be described later, it can be understood that when the switching element SW is turned on, the switching element SW is electrically connected to the first line BL1 (see...). Figure 6 and Figure 7 ) and the second bit line BL2 (see Figure 6 and Figure 7 In each of the following, the memory cells MC and OTP cells OTPC, which share a bit line BL, are electrically connected to each other.

[0061] The number of switching elements SW included in the switching element array 13 is not limited to the number shown, and can vary.

[0062] Alternatively or additionally, in some example embodiments, multiple redundant rows and / or redundant columns of the storage unit MC and / or OTP unit OTPC may exist. Redundant rows and / or redundant columns of the storage unit MC and / or OTP unit OTPC may be used if one or more cells in one or more rows and / or columns of the storage unit MC and / or OTP unit OTPC are defective or deemed defective. The example embodiments are not limited thereto.

[0063] Figure 3 This is an example circuit diagram illustrating a memory cell according to some example embodiments. Figure 4 This is an example circuit diagram illustrating an OTP unit according to some example embodiments. Figure 5 This is a diagram illustrating the resistance of the memory cell and the OTP cell according to some example embodiments.

[0064] refer to Figure 3 and Figure 5 The first magnetic tunnel junction element MTJ1 may include a pinned layer PL, a tunnel layer TL, and a free layer FL. The tunnel layer TL may be located between the pinned layer PL and the free layer FL (e.g., directly or indirectly).

[0065] The pinned layer PL can have a fixed magnetization direction independent of the external magnetic field, and the free layer FL can have a magnetization direction that can be changed to be parallel or antiparallel to the magnetization direction of the pinned layer PL.

[0066] The first magnetic tunnel junction element MTJ1 can store data in the storage cell MC by utilizing the resistance difference based on the magnetization direction of the pinned layer PL and the magnetization direction of the free layer FL.

[0067] For a write operation on the memory cell MC, an on-state voltage can be applied to the first word line WL1, and a write voltage can be applied to the first magnetic tunnel junction element MTJ1. Depending on the direction of the write voltage applied to the first magnetic tunnel junction element MTJ1, a first write current IW1 or a second write current IW2 can flow through the first magnetic tunnel junction element MTJ1.

[0068] For example, when a relatively high voltage level (e.g., write voltage) is applied to the bit line BL and a relatively low voltage level (e.g., ground voltage) is applied to the source line SL, a first write current IW1 flowing from the bit line BL to the source line SL can be provided to the first magnetic tunnel junction element MTJ1. In this case, electrons with the same spin direction as the pinned layer PL can tunnel through the tunnel layer TL to apply torque to the free layer FL. Accordingly, the first magnetic tunnel junction element MTJ1 can be in a parallel state P, where the magnetization direction of the free layer FL is parallel to the magnetization direction of the pinned layer PL, and the first magnetic tunnel junction element MTJ1 has a first resistance value R_P and stores data 0 therein. For example, data corresponding to the parallel state P can be written to the memory cell MC using the first write current IW1.

[0069] When a relatively high voltage level (e.g., write voltage) is applied to the source line SL and a relatively low voltage level (e.g., ground voltage) is applied to the bit line BL, a second write current IW2 flowing from the source line SL to the bit line BL can be provided to the first magnetic tunnel junction element MTJ1. In this case, electrons with spin directions opposite to the spin directions of the pinned layer PL cannot tunnel through the tunnel layer TL, but can be reflected to the free layer FL to apply torque to the free layer FL. Accordingly, the first magnetic tunnel junction element MTJ1 can be changed to an antiparallel state AP, where the magnetization direction of the free layer FL is antiparallel to the magnetization direction of the pinned layer PL, and the first magnetic tunnel junction element MTJ1 has a second resistance value R_AP and can store data 1 therein. The second resistance value R_AP can be greater than the first resistance value R_P. That is, data corresponding to the antiparallel state AP can be written to the memory cell MC using the second write current IW2.

[0070] For example, the memory cell MC can have a first resistance value R_P or a second resistance value R_AP based on the direction of each of the write currents IW1 and IW2 flowing through the first magnetic tunnel junction element MTJ1, thereby enabling it to be implemented as a reprogrammable memory cell.

[0071] A reference resistor value R_m can be determined for the read operation of the memory cell MC. The reference resistor value R_m can have a value between a first resistor value R_P and a second resistor value R_AP.

[0072] Although the example embodiment shows a free layer FL connected to the bit line BL and a pinned layer PL connected to the first cell transistors CT11 and CT12, the embodiment is not limited thereto. Unlike the example shown, the pinned layer PL may be connected to the bit line BL, and the free layer FL may be connected to the first cell transistors CT11 and CT12.

[0073] In some example embodiments, each of the pinned layer PL and the free layer FL may have a magnetization easy axis in a direction perpendicular to the interface between the pinned layer PL and the free layer FL.

[0074] Each of the pinned layer PL and the free layer FL may include a vertically magnetic material (e.g., one or more of CoFeTb, CoFeGd, and CoFeDy), a vertically magnetic material having an L10 structure, CoPt having a hexagonal close-packed lattice structure, and at least one of the vertically magnetic structures. The vertically magnetic material having an L10 structure may, for example, include FePt, FePd, CoPd, and CoPt with an L10 structure. The vertically magnetic structure may include magnetic and non-magnetic layers stacked alternately and repeatedly on top of each other. For example, the vertically magnetic structure may include (Co / Pt)n, (CoFe / Pt)n, (CoFe / Pd)n, (Co / Pd)n, (Co / Ni)n, (CoNi / Pt)n, (CoCr / Pt)n, or (CoCr / Pd)n (where n is the number of stacks).

[0075] In some example embodiments, each of the pinned layer PL and the free layer FL may have a magnetization easy axis in a direction at the level of the interface between the pinned layer PL and the free layer FL.

[0076] Each of the pinned layer PL and the free layer FL may include a ferromagnetic material. In some example embodiments, the pinned layer PL may also include an antiferromagnetic material for fixing the magnetization direction of the ferromagnetic material. For example, the ferromagnetic material may include at least one of CoFeB, Fe, Co, Ni, Gd, Dy, CoFe, NiFe, MnAs, MnBi, MnSb, CrO2, MnOFe2O3, FeOFe2O3, NiOFe2O3, CuOFe2O3, MgOFe2O3, EuO, and Y3Fe5O12. For example, the antiferromagnetic material may include at least one of PtMn, IrMn, MnO, MnS, MnTe, MnF2, FeCl2, FeO, CoCl2, CoO, NiCl2, NiO, and Cr, or at least one selected from noble metals. Precious metals may include ruthenium (Ru), rhodium (Rh), palladium (Pd), osmium (Os), iridium (Ir), platinum (Pt), gold (Au), or silver (Ag). The free layer (FL) can consist of multiple layers.

[0077] The tunnel layer TL may include, for example, at least one selected from oxides of magnesium (Mg), titanium (Ti), aluminum (Al), magnesium zinc (MgZn) and magnesium boron (MgB) and nitrides of titanium (Ti) and vanadium (V).

[0078] refer to Figure 4 and Figure 5 The OTP unit OTPC can have a structure similar to that of the memory unit MC. For example, in Figure 4 In the text, the third unit transistors CT31 and CT32 connected to the third word line WL31 and the fourth unit transistors CT41 and CT42 connected to the fourth word line WL41 are omitted.

[0079] The second magnetic tunnel junction element MTJ2 may include a pinned layer PL, a tunnel layer TL, and a free layer FL. The tunnel layer TL may be located between (e.g., directly or indirectly) the pinned layer PL and the free layer FL. The pinned layer PL, tunnel layer TL, and free layer FL of the second magnetic tunnel junction element MTJ2 may be made of the same material as the pinned layer PL, tunnel layer TL, and free layer FL of the first magnetic tunnel junction element MTJ1. In some example embodiments, the pinned layer PL, tunnel layer TL, and free layer FL of the second magnetic tunnel junction element MTJ2 may be formed simultaneously with the corresponding pinned layer PL, tunnel layer TL, and free layer FL of the first magnetic tunnel junction element MTJ1; however, the example embodiments are not limited thereto. Some OTP cells OTPC may be in a state in which the second magnetic tunnel junction element MTJ2 is in an insulation breakdown state, and each of the remaining OTPC cells OTPC may be in a state in which the second magnetic tunnel junction element MTJ2 is not in an insulation breakdown state.

[0080] In each of some OTP cells OTPC, a breakdown voltage can be applied to the second magnetic tunnel junction element MTJ2 through a single programming operation, and the tunnel layer TL of the second magnetic tunnel junction element MTJ2 can be insulated and broken down. Each of some OTP cells OTPC can have an irreversible resistive state. At the breakdown voltage, a breakdown current can flow through the second magnetic tunnel junction element MTJ2. The breakdown current can be greater than each of the first write current IW1 and the second write current IW2. The insulated and broken-down second magnetic tunnel junction element MTJ2 can be in a short-circuit state. The insulated and broken-down second magnetic tunnel junction element MTJ2 can have a third resistance value R_BD and can store data 0 therein. The un-insulated and broken-down second magnetic tunnel junction element MTJ2 can have a resistance value greater than the third resistance value R_BD and store data 1 therein. The un-insulated and broken-down second magnetic tunnel junction element MTJ2 can be in a parallel state P or an anti-parallel state AP.

[0081] For example, the OTP unit OTPC can only be programmed once, can have a state in which the tunnel layer TL is in an insulation breakdown state or a state in which the tunnel layer TL is not in an insulation breakdown state, and can be used as an OTP.

[0082] As described above, for a write operation of the memory cell MC, a high-level voltage (e.g., write voltage) can be applied to the bit line BL and a low voltage (e.g., ground voltage) can be applied to the source line SL, or a high-level voltage (e.g., write voltage) can be applied to the source line SL and a low voltage (e.g., ground voltage) can be applied to the bit line BL. The write voltage is applied separately to the bit line BL, the first magnetic tunnel junction element MTJ1, the cell transistors CT11 and CT12, the source line SL, etc.

[0083] Since the breakdown voltage should be applied to the second magnetic tunnel junction element MTJ2 for the write operation of the OTP cell OTPC, the magnitude of the write voltage applied for the write operation of the OTP cell OTPC will be greater than the magnitude of the write voltage applied for the write operation of the memory cell MC.

[0084] For example, when memory cell MC and OTP cell OTPC share bit line BL, source line SL and peripheral circuitry, a high-level write voltage may be applied to the cell transistor of memory cell MC that has not been programmed.

[0085] In this situation, the current flowing through the memory cell MC becomes excessive, which may degrade the device's performance. Furthermore, the size of other components required to apply this current may increase, potentially leading to an excessive increase in the overall device size.

[0086] According to some example embodiments, the magnetic storage device may include a switching element SW, which is disposed between and connected to the bit line BL connected to the memory cell MC and the bit line BL connected to the OTP cell OTPC. In some example embodiments, the bit line BL connected to the memory cell MC may be referred to as the first bit line. Figure 6 and Figure 7 BL1), and the bit line BL connected to the OTP unit OTPC can be called the second bit line (BL1). Figure 6 and Figure 7 BL2).

[0087] The switching element SW can be on the first bit line BL1 and the second bit line BL2 (see...) Figure 6 and Figure 7 ) direction of extension ( Figure 6 and Figure 7 The first bit line BL1 and the second bit line BL2 are set on the Y direction (see Figure 6 and Figure 7The switching element SW is connected between the first bit line BL1 and the second bit line BL2. In some example embodiments, the switching element SW may be referred to as a bit line connected transistor.

[0088] When the write voltage is applied to the OTP unit OTPC, the peripheral circuit can control the switching element SW to switch the first bit line BL1 and the second bit line BL2 (see...). Figure 6 and Figure 7 They are disconnected from each other. When a write voltage is applied to the OTP cell OTPC, the external circuitry can control the write voltage not to be applied to the memory cell MC.

[0089] For example, when performing a write operation on the OTP unit OTPC, the peripheral circuit can control the switching element SW to not connect to the first bit line BL1 and the second bit line BL2 (see...). Figure 6 and Figure 7 In some example embodiments, when a write voltage is applied to the OTP cell OTPC, the peripheral circuitry can control the switching element SW to turn off.

[0090] For example, the OTP unit OTPC can correspond to the second word line WL21, and the switching element SW can correspond to the fifth word line WL3. When a write voltage is applied to the OTP unit OTPC, the peripheral circuitry can activate the drive signal for driving the second word line WL21 and deactivate the drive signal for driving the fifth word line WL3. That is, the peripheral circuitry can select the second word line WL21 but not the fifth word line WL3 in order to apply the write voltage to the OTP unit OTPC.

[0091] Therefore, the fifth word line WL3 can be left undriven and the switching element SW can be turned off. Since the switching element SW is turned off, it is possible to prevent high voltage from being applied to the memory cell MC.

[0092] For example, when performing a write operation on the OTP cell OTPC, the write voltage applied to the OTP cell OTPC is applied only to the switching element SW, thereby preventing excessive current from flowing through the bit line BL to the memory cell MC. For example, the write voltage applied to the OTP cell OTPC may be applied only to the drain region of the switching element SW. However, the example embodiment is not limited to this.

[0093] When no write operation is performed on the OTP unit OTPC, for example, when a read operation is performed on the OTP unit OTPC, a write operation is performed on the memory unit MC, or a read operation is performed on the memory unit MC, the peripheral circuit can control the switching element SW to... Figure 6 and Figure 7The first bit line BL1 and the second bit line BL2 are connected to each other. In some example embodiments, when performing a read operation of the OTP unit OTPC, a write operation of the memory unit MC, or a read operation of the memory unit MC, the peripheral circuit can control the switching element SW to turn on.

[0094] For example, when a write voltage is applied to the memory cell MC, the peripheral circuit can control the switching element SW to switch the first bit line BL1 and the second bit line BL2 (see...). Figure 6 and Figure 7 They are electrically connected to each other. In some example embodiments, when a write voltage is applied to the memory cell MC, the peripheral circuitry can control the switching element SW to turn on.

[0095] Figure 6 This is an example layout plan view of a magnetic storage device according to some example embodiments. Figure 7 It is along Figure 6 Example cross-sectional view taken from line A-A'.

[0096] Figure 7 yes Figure 2 This includes a portion of three memory cells (MCs) connected to a bit line, and... Figure 2 This includes an example cross-sectional view of a portion of an OTP unit OTPC connected to a bit line. For ease of illustration, Figure 7 The middle part is omitted Figure 2 The source line SL.

[0097] refer to Figure 6 and Figure 7 According to some example embodiments, the magnetic storage device may include a substrate 100, first to fourth unit transistors CT11, CT12, CT21, CT22, CT31, CT32, CT41 and CT42, an insulating film 101, a wiring structure 210, first to third lower wiring structures 220l, 230l and 240l, first to third upper wiring structures 220u, 230u and 240u, first to fourth lower electrodes BE1, BE2, BE3 and BE4, first to fourth magnetic tunnel junction elements MTJ1, MTJ2, MTJ3 and MTJ4, first to fourth upper electrodes TE1, TE2, TE3 and TE4, a first bit line BL1 and a second bit line BL2, a first via structure V1 and a second via structure V2. Figure 2 The bit line BL may include the first bit line BL1 connected to the memory cell MC and the second bit line BL2 connected to the OTP cell OTPC.

[0098] Storage cells MC can be disposed in storage cell array 11. Each storage cell MC may include a first magnetic tunnel junction element MTJ1. In OTP cell array 12, OTP cells OTPC can be disposed. Each OTP cell OTPC may include a second to a fourth magnetic tunnel junction element MTJ2, MTJ3 and MTJ4.

[0099] A switching element SW can be disposed in the switching element array 13. A first via structure V1 can be disposed between the switching element SW and the memory cell MC. A second via structure V2 can be disposed between the switching element SW and the OTP cell OTPC. That is, the first via structure V1 and the second via structure V2 may not be disposed in the array described later. Figure 12 and Figure 13 Instead of being located in the peripheral circuit area CPR, it is set in Figure 12 and Figure 13 In the cell area CELL.

[0100] Each memory cell MC may include first cell transistors CT11 and CT12, wiring structure 210, first lower electrode BE1, first magnetic tunnel junction element MTJ1, and first upper electrode TE1.

[0101] Each OTP unit OTPC may include second to fourth unit transistors CT21, CT22, CT31, CT32, CT41 and CT42, connection wiring 110, first to third lower wiring structures 220l, 230l and 240l, first to third upper wiring structures 220u, 230u and 240u, second to fourth lower electrodes BE2, BE3 and BE4, second to fourth magnetic tunnel junction elements MTJ2, MTJ3 and MTJ4, and second to fourth upper electrodes TE2, TE3 and TE4.

[0102] The substrate 100 may be, for example, one or more of the following: silicon substrate, gallium arsenide substrate, silicon germanium substrate, ceramic substrate, quartz substrate, display glass substrate, etc., or it may be a semiconductor-on-insulator (SOI) substrate. However, the example embodiments are not limited thereto.

[0103] The substrate 100 may extend in a first horizontal direction X and a second horizontal direction Y that intersect each other. The third direction Z may refer to a height direction perpendicular to each of the first horizontal direction X and the second horizontal direction Y.

[0104] The first to fourth unit transistors CT11, CT12, CT21, CT22, CT31, CT32, CT41, and CT42 can be formed on the substrate 100. A first impurity region (not shown) can be formed in the substrate 100 and on each of the two opposite sides of the first unit transistors CT11 and CT12. The first impurity region can be formed by an implantation process; the example embodiment is not limited thereto. The first impurity region (not shown) can be configured as the source or drain region of the first unit transistors CT11 and CT12. A second impurity region (not shown) can be formed in the substrate 100 and on each of the two opposite sides of each of the second to fourth unit transistors CT21, CT22, CT31, CT32, CT41, and CT42. The second impurity region can be formed by an implantation process; the example embodiment is not limited thereto. The second impurity region (not shown) can be configured as the source or drain region of each of the second to fourth unit transistors CT21, CT22, CT31, CT32, CT41, and CT42. Each of the first impurity region (not shown) and the second impurity region (not shown) may include N-type and / or P-type impurities, such as a first concentration of N-type impurities and a second concentration of P-type impurities that are much higher or lower than the first concentration.

[0105] The switching element SW can be implemented using the cell transistors of the memory cell MC and the OTP cell OTPC. A third impurity region 102e and a fourth impurity region 102f can be formed in the substrate 100 and located on two opposite sides of the switching element SW, respectively. Each of the third impurity region 102e and the fourth impurity region 102f can be configured as a source region or a drain region of the switching element SW. Each of the third impurity region 102e and the fourth impurity region 102f can include N-type or P-type impurities, such as a first concentration of N-type impurities and a second concentration of P-type impurities that is much higher or lower than the first concentration.

[0106] An insulating film 101 may be formed on a substrate 100. The insulating film 101 may cover the first to fourth unit transistors CT11, CT12, CT21, CT22, CT31, CT32, CT41, and CT42, as well as the switching element SW. At least a portion of the wiring structure 210, the first to third lower wiring structures 220l, 230l, and 240l, the connecting wiring 110, at least a portion of each of the first to third upper wiring structures 220u, 230u, and 240u, at least a portion of the first via structure V1, and at least a portion of the second via structure V2 may be formed in the insulating film 101. The insulating film 101 may, for example, comprise silicon oxide, silicon oxynitride, etc. Although not shown in detail, the insulating film 101 may have a multilayer structure.

[0107] The first to fourth magnetic tunnel junction elements MTJ1, MTJ2, MTJ3, and MTJ4 can be formed on the substrate 100. The first to fourth magnetic tunnel junction elements MTJ1, MTJ2, MTJ3, and MTJ4 can be formed at substantially the same vertical height from the substrate 100. In some example embodiments, each of the second to fourth magnetic tunnel junction elements MTJ2, MTJ3, and MTJ4 can have substantially the same dimensions and structure as the first magnetic tunnel junction element MTJ1.

[0108] Wiring structure 210, first to third lower wiring structures 220l, 230l and 240l, first to third upper wiring structures 220u, 230u and 240u, first via structure V1 and second via structure V2 can be formed on substrate 100.

[0109] Wiring structure 210 can connect substrate 100 and first magnetic tunnel junction element MTJ1 to each other. Wiring structure 210 may include via 112a (1-1), wiring 114a (1-1), via 122a (2-1), wiring 124a (2-1), via 132a (3-1), wiring 134a (3-1), via 142a (4-1), first bonding pad LP1, and first lower electrode contact BEC1, which are sequentially stacked on substrate 100. Via 112a (1-1) can be connected to a first impurity region (not shown) located between first unit transistors CT11 and CT12. Via 122a (2-1) can connect wiring 114a (1-1) and wiring 124a (2-1) to each other. Via 132a (3-1) can connect wiring 124a (2-1) and wiring 134a (3-1) to each other. Via 142a (4-1) can connect wiring 134a (3-1) and the first bonding pad LP1 to each other. The first lower electrode contact BEC1 can connect the first bonding pad LP1 and the first magnetic tunnel junction element MTJ1 to each other.

[0110] In some example embodiments, the magnetic storage device may include a storage structure MST. The storage structure MST may be disposed on the first to fourth lower electrode contacts BEC1, BEC2, BEC3, and BEC4. For example, the storage structure MST may include a first lower electrode BE1, a first magnetic tunnel junction element MTJ1, a first intermediate electrode ME1, a first upper electrode TE1, etc. In this regard, the first lower electrode BE1, the first magnetic tunnel junction element MTJ1, the first intermediate electrode ME1, and the first upper electrode TE1 may be stacked sequentially starting from the upper surface of the first lower electrode contact BEC1.

[0111] The memory structure MST may have sloping sidewalls; however, the example embodiments are not limited thereto. For example, in some example embodiments, the area of ​​the lower surface of the memory structure MST may be larger than the area of ​​its upper surface. Alternatively or additionally, in some example embodiments, the area of ​​the lower surface of the memory structure MST may be greater than or equal to the area of ​​the upper surface of the first lower electrode contact BEC1.

[0112] Each of the first to fourth magnetic tunnel junction elements MTJ1, MTJ2, MTJ3, and MTJ4 may include a first magnetic pattern PL, a tunnel blocking pattern TL, and a second magnetic pattern FL. The tunnel blocking pattern TL may be located between the first magnetic pattern PL and the second magnetic pattern FL.

[0113] One of the first magnetic pattern PL and the second magnetic pattern FL can be a reference layer with a fixed magnetization direction that is independent of an external magnetic field, and the other of the first magnetic pattern PL and the second magnetic pattern FL can be a free layer whose magnetization direction is variable between two stable magnetization directions. For example, the first magnetic pattern PL can be a reference layer with a fixed magnetization direction, while the second magnetic pattern FL can be a free layer with a variable magnetization direction. In another example, the first magnetic pattern PL can be a free layer, while the second magnetic pattern FL can be a reference layer.

[0114] In some example embodiments, each of the first magnetic pattern PL and the second magnetic pattern FL may have perpendicular magnetic anisotropy (PMA). Each of the first magnetic pattern PL and the second magnetic pattern FL may have a magnetization easy axis in the vertical direction (a direction perpendicular to the upper surface of the substrate 100).

[0115] Each of the first magnetic pattern PL and the second magnetic pattern FL may include a vertical magnetic material (e.g., CoFeTb, CoFeGd, and CoFeDy), a vertical magnetic material having an L10 structure, CoPt having a hexagonal close-packed lattice structure, and at least one of the following vertical magnetic structures. The vertical magnetic material having an L10 structure may, for example, include FePt, FePd, CoPd, and CoPt with an L10 structure. The vertical magnetic structure may include alternating and repeating magnetic and non-magnetic layers stacked on top of each other. For example, the vertical magnetic structure may include (Co / Pt)n, (CoFe / Pt)n, (CoFe / Pd)n, (Co / Pd)n, (Co / Ni)n, (CoNi / Pt)n, (CoCr / Pt)n, or (CoCr / Pd)n (where n is the number of stacks).

[0116] In some example embodiments, each of the first magnetic pattern PL and the second magnetic pattern FL may have in-plane magnetic anisotropy (IMA). Each of the first magnetic pattern PL and the second magnetic pattern FL may have a magnetization easy axis in the horizontal direction (parallel to the upper surface of the substrate 100).

[0117] Each of the first magnetic pattern PL and the second magnetic pattern FL, having in-plane magnetic anisotropy (IMA), may comprise a ferromagnetic material. In some example embodiments, the magnetic pattern constituting the reference layer in the first magnetic pattern PL and the second magnetic pattern FL may further comprise an antiferromagnetic material for fixing the magnetization direction of the ferromagnetic material. For example, the ferromagnetic material of the reference layer may comprise at least one of CoFeB, Fe, Co, Ni, Gd, Dy, CoFe, NiFe, MnAs, MnBi, MnSb, CrO2, MnOFe2O3, FeOFe2O3, NiOFe2O3, CuOFe2O3, MgOFe2O3, EuO, and Y3Fe5O12. For example, the antiferromagnetic material of the reference layer may comprise at least one of PtMn, IrMn, MnO, MnS, MnTe, MnF2, FeCl2, FeO, CoCl2, CoO, NiCl2, NiO, and Cr, or at least one selected from noble metals. The precious metal may include one or more of ruthenium (Ru), rhodium (Rh), palladium (Pd), osmium (Os), iridium (Ir), platinum (Pt), gold (Au), or silver (Ag). The free layer FL can consist of multiple layers. For example, the ferromagnetic material of the free layer may include at least one of CoFeB, Fe, Co, Ni, Gd, Dy, CoFe, NiFe, MnAs, MnBi, MnSb, CrO2, MnOFe2O3, FeOFe2O3, NiOFe2O3, CuOFe2O3, MgOFe2O3, EuO, and Y3Fe5O12. The magnetic pattern MP, serving as the free layer, may consist of multiple layers.

[0118] Tunnel blocking patterns (TLs) may include, for example, at least one selected from oxides of magnesium (Mg), titanium (Ti), aluminum (Al), magnesium zinc (MgZn), and magnesium boron (MgB), as well as nitrides of titanium (Ti) and vanadium (V).

[0119] The first magnetic tunnel junction element MTJ1 can store data in each storage cell MC based on the resistance difference between the magnetization directions of the first magnetic pattern PL and the magnetization directions of the second magnetic pattern FL.

[0120] For example, when the magnetization directions of the first magnetic pattern PL and the second magnetic pattern FL are parallel to each other, the first magnetic tunnel junction element MTJ1 has a low resistance value. In this case, data "0" can be stored and read. Conversely, when the magnetization directions of the first magnetic pattern PL and the second magnetic pattern FL are antiparallel to each other, the first magnetic tunnel junction element MTJ1 has a high resistance value. In this case, data "1" can be stored and read. In another example, when the magnetization directions of the first magnetic pattern PL and the second magnetic pattern FL are parallel to each other, data "1" can be stored and read from the first magnetic tunnel junction element MTJ1. When the magnetization directions of the first magnetic pattern PL and the second magnetic pattern FL are antiparallel to each other, data "0" can be stored and read from the first magnetic tunnel junction element MTJ1.

[0121] The second magnetic tunnel junction element MTJ2 can have an irreversible resistive state, which is formed by applying a breakdown voltage to the first magnetic pattern PL and the second magnetic pattern FL in a single programming operation to insulate and break down the tunnel blocking pattern TL between the first magnetic pattern PL and the second magnetic pattern FL. The second magnetic tunnel junction element MTJ2 that has undergone insulation breakdown can be in a short-circuit state. The second magnetic tunnel junction element MTJ2 that has undergone insulation breakdown has a low resistance value, and in this case, data DATA can be stored and read as "0". The second magnetic tunnel junction element MTJ2 that has not undergone insulation breakdown has a high resistance value, and in this case, data can be stored and read as "1".

[0122] The cell array 10 of the magnetic storage device according to some example embodiments includes a storage cell MC used as MRAM and an OTP cell OTPC used as OTP. For example, since the storage cell MC and the OTP cell OTPC are implemented in a single cell array 10 without the need for a separate OTP memory, a highly integrated magnetic storage device can be provided.

[0123] During a write operation of the OTP cell OTPC, a breakdown voltage is applied to the second magnetic tunnel junction MTJ2 to insulate the tunnel blocking pattern TL of the second magnetic tunnel junction element MTJ2 from breakdown. The breakdown voltage has a higher value than the write voltage VWR applied to the first magnetic tunnel junction MTJ1 during a write operation of the memory cell MC. Therefore, stress may be applied to the memory cell MC.

[0124] In some examples, in memory devices according to some example embodiments, since the OTP cell OTPC includes second to fourth cell transistors CT21, CT22, CT31, CT32, CT41, and CT42 connected in parallel with each other, a larger voltage can be applied to the second magnetic tunnel junction MTJ2. Therefore, even when the write voltage applied to the OTP cell OTPC is not very high, insulation breakdown of the tunnel blocking pattern TL of the second magnetic tunnel junction MTJ2 can occur more easily. Alternatively or additionally, the stress on the memory cell MC due to the write voltage applied to the OTP cell OTPC can be improved and / or reduced.

[0125] A first lower electrode BE1 may be formed on the first lower electrode contact BEC1. A first magnetic tunnel junction element MTJ1 may be formed on the first lower electrode BE1. A first intermediate electrode ME1 may be formed on the first magnetic tunnel junction element MTJ1. A first upper electrode TE1 may be formed on the first intermediate electrode ME1. The first upper electrode TE1 may be connected to the first magnetic tunnel junction element MTJ1.

[0126] The first lower electrode BE1 may include a metal (e.g., one or more of titanium, tantalum, etc.) and / or a metal nitride (e.g., one or more of titanium nitride, tantalum nitride, etc.). The first intermediate electrode ME1 may include at least one of a metal (e.g., titanium, tantalum, etc.) or a metal nitride (e.g., titanium nitride, tantalum nitride, etc.). The first upper electrode TE1 may include at least one of a metal (e.g., titanium or tantalum) or a metal nitride (e.g., titanium nitride or tantalum nitride). Alternatively, the first upper electrode TE1 may include tungsten, copper, platinum, nickel, silver, gold, etc.

[0127] The first line BL1 can be formed on the first upper electrode TE1. The first line BL1 can be connected to the first upper electrode TE1. The first magnetic tunnel junction element MTJ1 can be electrically connected to the first unit transistors CT11 and CT12 via wiring structure 210, and can be electrically connected to the first line BL1 via the first upper electrode TE1.

[0128] Connection wiring 110 may be disposed on substrate 100. In some example embodiments, connection wiring 110 may be disposed at the lowest metal layer among the wirings. Connection wiring 110 may be the wiring closest to substrate 100. The second to fourth unit transistors CT21, CT22, CT31, CT32, CT41, and CT42 may be electrically connected to each other via connection wiring 110 at the metal layer closest to substrate 100. Connection wiring 110 may be located at the same vertical height from substrate 100 as the (1-1) wiring 114a. In some examples, wirings disposed at the same metal layer as the (1-1) wiring 114a and respectively disposed below the second to fourth magnetic tunnel junction elements MTJ2, MTJ3, and MTJ4 may be directly connected to each other.

[0129] The third magnetic tunnel junction element MTJ3 and the fourth magnetic tunnel junction element MTJ4 can be located at a higher metal level than the metal level of the connection wiring 110, while being isolated from the connection wiring 110. In some example embodiments, between each of the third magnetic tunnel junction element MTJ3 and the fourth magnetic tunnel junction element MTJ4 and the connection wiring 110, vias having the same metal level as the vias that directly contact the connection wiring 110 can be omitted. For example, between the third magnetic tunnel junction element MTJ3 and the connection wiring 110, and between the fourth magnetic tunnel junction element MTJ4 and the connection wiring 110, vias having the same metal level as the metal level of the (2-2) via 122b can be omitted.

[0130] The metal layer in which the connecting wiring 110 is placed, and the metal layer in which the omitted vias (or wiring) between the third magnetic tunnel junction element MTJ3 and the connecting wiring 110, and between the fourth magnetic tunnel junction elements MTJ3 and MTJ4 and the connecting wiring 110 are placed, can vary according to the design of the magnetic storage device.

[0131] The first to third lower wiring structures 220l, 230l and 240l can be spaced apart from each other in the horizontal direction. Each of the first to third lower wiring structures 220l, 230l and 240l can connect the substrate 100 and the connection wiring 110 to each other.

[0132] The first lower wiring structure 220l may include via 112b (1-2). The second lower wiring structure 230l may include via 112c (1-3). The third lower wiring structure 240l may include via 112d (1-4). Each of vias 112b, 112c, and 112d (1-2) can connect each of the second impurity regions (not shown) between the second to fourth unit transistors CT21, CT22, CT31, CT32, CT41, and CT42 to the connection wiring 110. Vias 112a, 112b, 112c, and 112d (1-1) may be located at the same vertical height from the substrate 100.

[0133] The first to third upper wiring structures 220u, 230u, and 240u can be formed on the connecting wiring 110. The first to third upper wiring structures 220u, 230u, and 240u can be spaced apart from each other in the horizontal direction. Each of the first to third upper wiring structures 220u, 230u, and 240u can be connected to a corresponding one of the second to fourth magnetic tunnel junction elements MTJ2, MTJ3, and MTJ4.

[0134] A first upper wiring structure 220u can be disposed between the connecting wiring 110 and the second magnetic tunnel junction element MTJ2. The first upper wiring structure 220u can connect the connecting wiring 110 and the second magnetic tunnel junction element MTJ2 to each other. The first upper wiring structure 220u may include a second (2-2) via 122b, a second (2-2) wiring 124b, a third (3-2) via 132b, a third (3-2) wiring 134b, a fourth (4-2) via 142b, a second bonding pad LP2, and a second lower electrode contact BEC2, which are sequentially stacked on the connecting wiring 110. The second (2-2) via 122b can connect the connecting wiring 110 and the second (2-2) wiring 124b to each other. The third (3-2) via 132b can connect the second (2-2) wiring 124b and the third (3-2) wiring 134b to each other. Via 142b (4-2) can connect wiring 134b (3-2) and the second bonding pad LP2 to each other. The second lower electrode contact BEC2 can connect the second bonding pad LP2 and the second magnetic tunnel junction element MTJ2 to each other.

[0135] The second upper wiring structure 230u can be disposed between the connecting wiring 110 and the third magnetic tunnel junction element MTJ3. The second upper wiring structure 230u can be spaced apart from the connecting wiring 110 and can be connected to the third magnetic tunnel junction element MTJ3. The second upper wiring structure 230u may include a second (3rd) wiring 124c, a third (3rd) via 132c, a third (3rd) wiring 134c, a fourth (4th) via 142c, a third bonding pad LP3, and a third lower electrode contact BEC3, which are sequentially stacked on the connecting wiring 110. The second (3rd) wiring 124c can be spaced apart from the connecting wiring 110. The second (3rd) wiring 124c may not be in direct contact with the connecting wiring 110. The third (3rd) via 132c can connect the second (3rd) wiring 124c and the third (3rd) wiring 134c. Via 142c (4-3) connects wiring 134c (3-3) and the third bonding pad LP3 to each other. The third lower electrode contact BEC3 connects the third bonding pad LP3 and the third magnetic tunnel junction element MTJ3 to each other.

[0136] The third upper wiring structure 240u can be disposed between the connection wiring 110 and the fourth magnetic tunnel junction element MTJ4. The third upper wiring structure 240u can be spaced apart from the connection wiring 110 and can be connected to the fourth magnetic tunnel junction element MTJ4. The third upper wiring structure 240u may include a second-fourth wiring 124d, a third-fourth via 132d, a third-fourth wiring 134d, a fourth via 142d, a fourth bonding pad LP4, and a fourth lower electrode contact BEC4, which are sequentially stacked on the connection wiring 110. The second-fourth wiring 124d can be spaced apart from the connection wiring 110. The second-fourth wiring 124d may not be in direct contact with the connection wiring 110. The third-fourth via 132d can connect the second-fourth wiring 124d and the third-fourth wiring 134d to each other. Via 142d (4-4) connects via 134d (3-4) and the fourth bonding pad LP4 to each other. The fourth lower electrode contact BEC4 connects the fourth bonding pad LP4 and the fourth magnetic tunnel junction element MTJ4 to each other.

[0137] Vias 122a (2-1) and 122b (2-2) can be located at the same vertical height from the substrate 100. Routing from (2-1) to (2-4) 124a, 124b, 124c, and 124d can be located at the same vertical height from the substrate 100. Vias 132a, 132b, 132c, and 132d (3-1) to (3-4) can be located at the same vertical height from the substrate 100. Routing from (3-1) to (3-4) 134a, 134b, 134c, and 134d can be located at the same vertical height from the substrate 100. Vias 142a, 142b, 142c, and 142d (4-1) can be located at the same vertical height from the substrate 100. The first to fourth bonding pads LP1, LP2, LP3 and LP4 can be located at the same vertical height from the substrate 100. The first to fourth lower electrode contacts BEC1, BEC2, BEC3 and BEC4 can be located at the same vertical height from the substrate 100.

[0138] Each of the second to fourth lower electrodes BE2, BE3, and BE4 can be formed on a corresponding one of the second to fourth lower electrode contacts BEC2, BEC3, and BEC4. Each of the second to fourth magnetic tunnel junction elements MTJ2, MTJ3, and MTJ4 can be formed on a corresponding one of the second to fourth lower electrodes BE2, BE3, and BE4. Each of the second to fourth intermediate electrodes ME2, ME3, and ME4 can be formed on a corresponding one of the second to fourth magnetic tunnel junction elements MTJ2, MTJ3, and MTJ4. Each of the second to fourth upper electrodes TE2, TE3, and TE4 can be formed on a corresponding one of the second to fourth intermediate electrodes ME2, ME3, and ME4. Each of the second to fourth upper electrodes TE2, TE3, and TE4 can be connected to a corresponding one of the second to fourth magnetic tunnel junction elements MTJ2, MTJ3, and MTJ4. The first to fourth upper electrodes TE1, TE2, TE3, and TE4 can be located at the same vertical height 100 from the substrate.

[0139] Each of the second to fourth lower electrodes BE2, BE3, and BE4 may independently or simultaneously include a metal (e.g., titanium, tantalum, etc.) or a metal nitride (e.g., titanium nitride, tantalum nitride, etc.). Each of the second to fourth intermediate electrodes ME2, ME3, and ME4 may independently or simultaneously include at least one of a metal (e.g., titanium or tantalum) or a metal nitride (e.g., titanium nitride and / or tantalum nitride). Each of the second to fourth upper electrodes TE2, TE3, and TE4 may include at least one of a metal (e.g., titanium, tantalum, etc.) or a metal nitride (e.g., titanium nitride, tantalum nitride, etc.). Alternatively or additionally, each of the second to fourth upper electrodes TE2, TE3, and TE4 may independently or simultaneously include one or more of tungsten, copper, platinum, nickel, silver, gold, etc.

[0140] The second bit line BL2 can be formed on the second to fourth upper electrodes TE2, TE3, and TE4. The second bit line BL2 can be connected to the second to fourth upper electrodes TE2, TE3, and TE4. The first bit line BL1 and the second bit line BL2 can be located at the same vertical height 100 from the substrate.

[0141] The second magnetic tunnel junction element MTJ2 can be electrically connected to the second to fourth unit transistors CT21, CT22, CT31, CT32, CT41 and CT42 via the first upper wiring structure 220u, the connecting wiring 110, and the first to third lower wiring structures 220l, 230l and 240l, and can be electrically connected to the second bit line BL2 via the second upper electrode TE2.

[0142] The vias and wiring of each of the wiring structure 210, the first to third lower wiring structures 220l, 230l and 240l, and the first to third upper wiring structures 220u, 230u and 240u may include at least one of a metal (e.g., copper) and a conductive metal nitride (e.g., titanium nitride, tantalum nitride and / or tungsten nitride).

[0143] Each of the first to fourth bonding pads LP1, LP2, LP3 and LP4 may include at least one of a doped semiconductor material (e.g., doped silicon), a metal (e.g., tungsten, titanium and / or tantalum), a metal semiconductor compound (e.g., a metal silicide), and a conductive metal nitride (e.g., titanium nitride, tantalum nitride and / or tungsten nitride).

[0144] Although not shown in detail, each of the first to fourth lower electrode contacts BEC1, BEC2, BEC3, and BEC4 may include a blocking pattern (not shown) and / or a conductive pattern (not shown). The blocking pattern (not shown) may include a metal nitride (e.g., tungsten nitride, tantalum nitride, titanium nitride, etc.) and / or a metal (e.g., tantalum, titanium, etc.), and the conductive pattern (not shown) may include a conductive material (e.g., copper, etc.).

[0145] The first via structure V1 and the second via structure V2 can be spaced apart from each other in the second horizontal direction Y, and can be disposed between the storage cell MC and the OTP cell OTPC.

[0146] The first via structure V1 can be disposed on one side of the switching element SW along the second horizontal direction Y. The first via structure V1 can be disposed adjacent to the first magnetic tunnel junction element MTJ1. The first via structure V1 can be disposed between the first magnetic tunnel junction element MTJ1 and the switching element SW.

[0147] The second via structure V2 can be disposed on the other side of the switching element SW along the second horizontal direction Y. The second via structure V2 can be disposed adjacent to the second magnetic tunnel junction element MTJ2. The second via structure V2 can be disposed between the second magnetic tunnel junction element MTJ2 and the switching element SW.

[0148] The first bit line BL1 and the second bit line BL2 can be respectively disposed on the first via structure V1 and the second via structure V2. The first bit line BL1 and the second bit line BL2 can be disposed on the first via structure V1 and the second via structure V2, while being spaced apart from each other in the second horizontal direction Y. For example, the bit line BL can be physically discontinuous between the first via structure V1 and the second via structure V2.

[0149] When the write operation of the OTP unit OTPC is performed, the peripheral circuit can control the switching element SW to electrically disconnect the first bit line BL1 and the second bit line BL2 from each other via the first via structure V1 and the second via structure V2.

[0150] When a write operation is performed on the memory cell MC, the peripheral circuitry can control the switching element SW to electrically connect the first bit line BL1 and the second bit line BL2 to each other via the first via structure V1 and the second via structure V2. When the write operation is performed on the memory cell MC, the peripheral circuitry can turn on the switching element SW to form an electrical path P1 consisting of the first bit line BL1, the first via structure V1, the switching element SW, the second via structure V2, and the second bit line BL2. Therefore, the switching element SW can electrically connect the first bit line BL1 and the second bit line BL2 to each other through the first via structure V1 and the second via structure V2.

[0151] In this configuration, one end of the switching element SW can be connected to the first bit line BL1 via the first via structure V1, and the other end of the switching element SW can be connected to the second bit line BL2 via the second via structure V2. The third impurity region 102e of the switching element SW can be connected to the first bit line BL1 via the first via structure V1. The fourth impurity region 102f of the switching element SW can be connected to the second bit line BL2 via the second via structure V2.

[0152] At least a portion of each of the first via structure V1 and the second via structure V2 may be disposed in the insulating film 101, and another portion of each of the first via structure V1 and the second via structure V2 may be disposed on the insulating film 101.

[0153] The first via structure V1 may include a first-e via 112e, a first-e wiring 114e, a second-e via 122e, a second-e wiring 124e, a third-e via 132e, a third-e wiring 134e, a fourth-e via 142e, a fourth-e wiring 144e, and a fifth-e via 154e, which are sequentially stacked on the substrate 100.

[0154] Via 112e (1e) can be connected to the third impurity region 102e of the switching element SW. Via 122e (2e) can connect wiring 114e (1e) and wiring 124e (2e). Via 132e (3e) can connect wiring 124e (2e) and wiring 134e (3e) to each other. Via 142e (4e) can connect wiring 134e (3e) and wiring 144e (4e) to each other. Via 154e (5e) can connect wiring 144e (4e) to the first line BL1.

[0155] The second via structure V2 may include a first f via 112f, a first f wiring 114f, a second f via 122f, a second f wiring 124f, a third f via 132f, a third f wiring 134f, a fourth f via 142f, a fourth f wiring 144f, and a fifth f via 154f, which are sequentially stacked on the substrate 100.

[0156] Via 112f (1f) can be connected to the fourth impurity region 102f of the switching element SW. Via 122f (2f) can connect wiring 114f (1f) and wiring 124f (2f). Via 132f (3f) can connect wiring 124f (2f) and wiring 134f (3f) to each other. Via 142f (4f) can connect wiring 134f (3f) to wiring 144f (4f). Via 154f (5f) can connect wiring 144f (4f) to the second bit line BL2.

[0157] Via 112e (1e) and via 112f (1f) can be located at the same vertical height from substrate 100 as each of vias 112a, 112b, 112c, and 112d (1-1) and (1-4). Wiring 114e (1e) and wiring 114f (1f) can be located at the same vertical height from substrate 100 as wiring 114a (1-1) and connection wiring 110.

[0158] Vias 122e and 122f can be located at the same distance from the substrate 100 and at the same vertical height as each of vias 122a (2-1) and 122b (2-2). Wiring 124e and 124f can be located at the same distance from the substrate 100 and at the same vertical height as each of wirings 124a, 124b, 124c, and 124d (2-1) to (2-4).

[0159] Vias 132e and 132f (3e and 3f) can be located at the same vertical height as the substrate 100 and the same vertical height as each of vias 132a, 132b, 132c and 132d (3-1 and 3-4). Wiring 134e (3e) and 134f (3f) can be located at the same vertical height as the substrate 100 and the same vertical height as each of wirings 134a, 134b, 134c and 134d (3-1 and 3-4).

[0160] Vias 142e and 142f (4e and 4f respectively) can be located at the same distance from substrate 100 and at the same vertical height as each of vias 142a, 142b, 142c and 142d (4-1 to 4-4). Wiring 144e (4e and 4f) can be located at the same distance from substrate 100 and at the same vertical height as each of the first bonding pads LP1, LP2, LP3 and LP4.

[0161] The upper surfaces of vias 154e (5e) and 154f (5f) may be located at a vertical height equal to the distance from substrate 100 and the same as the vertical height of the upper surfaces of each of the first to fourth magnetic tunnel junction elements MTJ1, MTJ2, MTJ3, and MTJ4. Each of vias 154e (5e) and 154f (5f) may extend at least partially into the barrier layer BR, the first molded insulating layer M1, the capping layer EN, and the second molded insulating layer M2, which will be described later. Each of vias 154e (5e) and 154f (5f) may extend in a third direction (Z) through at least a portion of each of the barrier layer BR, the first molded insulating layer M1, the capping layer EN, and the second molded insulating layer M2, which will be described later.

[0162] Each of the vias and wiring in the first via structure V1 and the second via structure V2 may independently or simultaneously include at least one of a metal (e.g., copper) and a conductive metal nitride (e.g., one or more of titanium nitride, tantalum nitride, or tungsten nitride).

[0163] According to some example embodiments, the magnetic storage device may also include a barrier film BR, a first molded insulating film M1, a capping film EN, and a second molded insulating film M2.

[0164] A barrier layer BR can be formed on the upper surface of the insulating film 101 of the memory cell array 11, the OTP cell array 12, and the switching element array 13. The barrier layer BR can be formed on the first bonding pad LP1, the fourth e wiring 144e, the fourth f wiring 144f, and the second to fourth bonding pads LP2, LP3, and LP4.

[0165] The barrier layer BR may include at least one of carbon (C), nitrogen (N), and silicon (Si). The barrier layer BR may include a silicon (Si)-based material comprising at least one of carbon (C) and nitrogen (N). For example, the barrier layer BR may include SiCN.

[0166] A first molded insulating layer M1 may be formed on the insulating film 101 of the memory cell array 11, the OTP cell array 12, and the switching element array 13. The first molded insulating layer M1 may also be formed on the barrier layer BR of the memory cell array 11, the OTP cell array 12, and the switching element array 13. The first molded insulating layer M1 may include an oxide such as silicon oxide.

[0167] The first to fourth lower electrode contacts BEC1, BEC2, BEC3, and BEC4 can be formed within the barrier film BR and the first molded insulating film M1. The first to fourth lower electrode contacts BEC1, BEC2, BEC3, and BEC4 can extend through the barrier film BR and the first molded insulating film M1. Each of the sidewalls of the first to fourth lower electrode contacts BEC1, BEC2, BEC3, and BEC4 can be surrounded by the barrier film BR and the first molded insulating film M1.

[0168] The upper surface of the first molded insulating layer M1 can be recessed. That is, the thickness of the portion of the first molded insulating film M1 adjacent to the first to fourth lower electrode contact portions BEC1, BEC2, BEC3 and BEC4 can be greater than the thickness of the portion of the first molded insulating film M1 away from the first to fourth lower electrode contact portions BEC1, BEC2, BEC3 and BEC4.

[0169] The capping layer EN can be formed along the sidewalls of the storage structure MST on the first molded insulating layer M1 of the storage cell array 11, the OTP cell array 12, and the switching element array 13. The capping layer EN can be conformally formed on the surfaces of the first molded insulating layer M1 and the storage structure MST. The capping layer EN can have a substantially uniform thickness.

[0170] The capping film EN can contact the sidewalls of the memory structure MST to protect the memory structure MST. The capping film EN can be disposed on the sidewalls of the first to fourth lower electrodes BE1, BE2, BE3, and BE4. The capping film EN can be disposed on the sidewalls of the first to fourth intermediate electrodes ME1, ME2, ME3, and ME4. The capping film EN can be disposed on the sidewalls of the first to fourth upper electrodes TE1, TE2, TE3, and TE4. The upper surface of the capping layer EN can have a recessed shape similar to the upper surface of the first molded insulating layer M1. The capping layer EN can comprise silicon nitride or silicon oxynitride.

[0171] A second molded insulating layer M2 can be formed on the capping layer EN of the memory cell array 11, the OTP cell array 12, and the switching element array 13. The second molded insulating layer M2 can be disposed on the sidewalls of the memory structure MST and the capping layer EN. The second molded insulating layer M2 can fill or at least partially fill the space between the memory structures MST.

[0172] The second molded insulating layer M2 may include an oxide such as silicon oxide. For example, the first molded insulating film M1 may include an oxide such as LK (low k). However, the second molded insulating layer M2 may include a high-density plasma chemical vapor deposition (HDP-CVD) oxide. That is, the first molded insulating film M1 and the second molded insulating film M2 may include different materials. However, the example embodiments are not limited thereto.

[0173] In the second horizontal direction Y extending from the first bit line BL1 and the second bit line BL2, the number of switching elements arranged between the first bit line BL1 and the second bit line BL2 can be one. However, the technical idea of ​​the example embodiment is not limited thereto.

[0174] Figure 8 This is an example cross-sectional view of a magnetic storage device according to some example embodiments. For ease of description, a brief description will be provided in conjunction with the above references. Figures 1 to 7 The description contains repeated content, or the description is omitted.

[0175] refer to Figure 8 According to some example embodiments, the magnetic storage device may include a first switching element SW1 and a second switching element SW2 disposed between a first via structure V1 and a second via structure V2. That is, in the second horizontal direction Y extending from the first bit line BL1 and the second bit line BL2, the number of switching elements arranged between the first bit line BL1 and the second bit line BL2 may be two or more.

[0176] One end of the first switching element SW1 can be connected to the first bit line BL1 through the first via structure V1, and one end of the second switching element SW2 can be connected to the second bit line BL2 through the second via structure V2.

[0177] The first via structure V1 can be connected to the impurity region 102c1 of the first switching element SW1. The second via structure V2 can be connected to the impurity region 102c2 of the second switching element SW2.

[0178] Figures 9 to 11 This is an example cross-sectional view of a magnetic storage device according to some example embodiments. For ease of description, a brief description will be provided in conjunction with the above references. Figures 1 to 8 The description repeats itself, or omits its description. For ease of explanation, Figures 9 to 11 The middle part is omitted Figure 2 The source line SL.

[0179] refer to Figure 9 According to some example embodiments, the connection wiring 110 of the magnetic storage device may be located at the same distance from the substrate 100 and the same as the (3-1) wiring 134a (see Figure 7At the same vertical height as the vertical height of ), that is, at the same vertical height as the (3-1) wiring 134a (see Figure 7 Wiring at the same metal level and located below the second to fourth magnetic tunnel junction elements MT2, MTJ3 and MT4 respectively can be directly connected to each other.

[0180] Between the third magnetic tunnel junction element MTJ3 and the connection wiring 110, and between the fourth magnetic tunnel junction element MTJ4 and the connection wiring 110, vias having the same metal level as the metal level of the (4-2) via 142b can be omitted.

[0181] The first lower wiring structure 220l may include vias 112b, 114b, 122b, 124b, and 132b sequentially stacked on the substrate 100. The second lower wiring structure 230l may include vias 112c, 114c, 122c, 124c, and 132c sequentially stacked on the substrate 100. The third lower wiring structure 240l may include vias 112d, 114d, 122d, 124d, and 132d sequentially stacked on the substrate 100. Each of vias 122b, 122c, and 122d from (2-2) to (2-4) can connect each of the routing from (1-2) to (1-4) 114b, 114c, and 114d to each of the routing from (2-2) to (2-4) 124b, 124c, and 124d. Each of vias 132b, 132c, and 132d from (3-2) to (3-4) can connect each of the routing from (2-2) to (2-4) 124b, 124c, and 124d to the connection wiring 110.

[0182] The first upper wiring structure 220u may include a first (4-2) via 142b, a second bonding pad LP2, and a second lower electrode contact BEC2, sequentially stacked on the connection wiring 110. The second (4-2) via 142b can connect the connection wiring 110 and the second bonding pad LP2 to each other. The second upper wiring structure 230u may include a third bonding pad LP3 and a third lower electrode contact BEC3, sequentially stacked on the connection wiring 110. The third bonding pad LP3 may be spaced apart from the connection wiring 110. The third bonding pad LP3 may not be in direct contact with the connection wiring 110. The third upper wiring structure 240u may include a fourth bonding pad LP4 and a fourth lower electrode contact BEC4, sequentially stacked on the connection wiring 110. The fourth bonding pad LP4 may be spaced apart from the connection wiring 110. The fourth bonding pad LP4 may not be in direct contact with the connection wiring 110.

[0183] refer to Figure 10 According to some example embodiments, the connection wiring 110 of the magnetic storage device may be located at the same distance from the substrate 100 and adjacent to the first bonding pad LP1 (see...). Figure 7 At the same vertical height as the first bonding pad LP1 (see...). Figure 7 Wiring at the same metal level and located below the second to fourth magnetic tunnel junction elements MT2, MTJ3 and MT4 respectively can be directly connected to each other.

[0184] Between the third magnetic tunnel junction element MTJ3 and the connecting wiring 110, and between the fourth magnetic tunnel junction element MTJ4 and the connecting wiring 110, vias having the same metal level as the metal level of the second lower electrode contact portion BEC2 can be omitted.

[0185] The first lower wiring structure 220l may include vias 112b (1-2), 114b (1-2), 122b (2-2), 124b (2-2), 132b (3-2), 134b (3-2), and 142b (4-2) sequentially stacked on the substrate 100. The second lower wiring structure 230l may include vias 112c (1-3), 114c (1-3), 122c (2-3), 124c (2-3), 132c (3-3), 134c (3-3), and 142c (4-3) sequentially stacked on the substrate 100. The third lower wiring structure 240l may include vias 112d (1-4), wiring 114d (1-4), vias 122d (2-4), wiring 124d (2-4), vias 132d (3-4), wiring 134d (3-4), and via 142d (4-4) sequentially stacked on the substrate 100. Each of vias 142b, 142c, and 142d (4-2) can connect each of wirings 134b, 134c, and 134d (3-2) to the connection wiring 110.

[0186] The first upper wiring structure 220u may include a second lower electrode BE2. The second lower electrode contact portion BEC2 connects the connecting wiring 110 and the second magnetic tunnel junction element MTJ2 to each other. The third magnetic tunnel junction element MTJ3 and the fourth magnetic tunnel junction element MTJ4 may be spaced apart from the connecting wiring 110. The third magnetic tunnel junction element MTJ3 and the fourth magnetic tunnel junction element MTJ4 may not be in direct contact with the connecting wiring 110.

[0187] The OTP unit OTPC may include second to fourth unit transistors CT21, CT22, CT31, CT32, CT41 and CT42, connection wiring 110, first to third lower wiring structures 220l, 230l and 240l, first upper wiring structure 220u, second to fourth magnetic tunnel junction elements MTJ2, MTJ3 and MTJ4, and second to fourth upper electrodes TE2, TE3 and TE4.

[0188] refer to Figure 11According to some example embodiments, vias having the same metal level as the vias that do not directly contact the connection wiring 110 can be omitted between the third magnetic tunnel junction element MTJ3 and the fourth magnetic tunnel junction element MTJ4 of the magnetic storage device and the connection wiring 110. For example, vias having the same metal level as the metal level of the (3-2) via 132b can be omitted between the third magnetic tunnel junction element MTJ3 and the connection wiring 110, and between the fourth magnetic tunnel junction elements MTJ3 and MTJ4 and the connection wiring 110.

[0189] The first sub-wiring structure 230u1 and the second sub-wiring structure 230u2 can be disposed between the connecting wiring 110 and the third magnetic tunnel junction element MTJ3. The first sub-wiring structure 230u1 can be connected to the connecting wiring 110. The second sub-wiring structure 230u2 can be connected to the third magnetic tunnel junction element MTJ3. The first sub-wiring structure 230u1 and the second sub-wiring structure 230u2 can be spaced apart from each other in the vertical direction. The first sub-wiring structure 230u1 and the second sub-wiring structure 230u2 do not need to be in direct contact with each other.

[0190] The first sub-wiring structure 230u1 may include a second (2-3) via 122c and a second (2-3) wiring 124c sequentially stacked on the connection wiring 110. The second sub-wiring structure 230u2 may include a third lower electrode contact BEC3, a third bonding pad LP3, a fourth (4-3) via 142c, and a third (3-3) wiring 134c sequentially stacked and disposed below the third magnetic tunnel junction element MTJ3. The second (2-3) wiring 124c and the third (3-3) wiring 134c may be spaced apart from each other. The second (2-3) wiring 124c and the third (3-3) wiring 134c may not be in direct contact with each other.

[0191] The third sub-wiring structure 240u1 and the fourth sub-wiring structure 240u2 can be disposed between the connecting wiring 110 and the fourth magnetic tunnel junction element MTJ4. The third sub-wiring structure 240u1 can be connected to the connecting wiring 110. The fourth sub-wiring structure 240u2 can be connected to the fourth magnetic tunnel junction element MTJ4. The third sub-wiring structure 240u1 and the fourth sub-wiring structure 240u2 can be spaced apart from each other in the vertical direction. The third sub-wiring structure 240u1 and the fourth sub-wiring structure 240u2 do not need to be in direct contact with each other.

[0192] The third sub-wiring structure 240u1 may include a (2-4) via 122d and a (2-4) wiring 124d sequentially stacked on the connection wiring 110. The fourth sub-wiring structure 240u2 may include a fourth lower electrode contact BEC4, a fourth bonding pad LP4, a (4-4) via 142d, and a (3-4) wiring 134d sequentially stacked and disposed below the fourth magnetic tunnel junction element MTJ4. The (2-4) wiring 124d and the (3-4) wiring 134d may be spaced apart from each other. The (2-4) wiring 124d and the (3-4) wiring 134d may not be in direct contact with each other.

[0193] Figure 12 This is a diagram illustrating the cell area and peripheral circuit area of ​​a magnetic storage device according to some example embodiments. Figure 13 It is shown Figure 12 A magnified view of region S. For ease of description, a brief description will be provided in conjunction with the above reference. Figures 1 to 11 The description contains repeated content, or the description is omitted.

[0194] refer to Figure 12 According to some example embodiments, the magnetic storage device may include a cell area (CELL) and a peripheral circuit area (CPR). The memory cell array 11, OTP cell array 12, and switching element array 13 described above may be disposed in the cell area (CELL). The aforementioned peripheral circuitry may be disposed in the peripheral circuit area (CPR).

[0195] Cell regions (CELL) and peripheral circuit regions (CPR) can be adjacent to each other in a first direction DR1 and a second direction DR2 that intersect each other. Cell regions (CELL) can be spaced apart from each other in the first direction DR1 and the second direction DR2, while peripheral circuit regions (CPR) are located between cell regions (CELL). The first direction DR1 can be the direction in which the bit line BL extends. The second direction DR2 can be a direction perpendicular to the first direction DR1.

[0196] refer to Figure 13 The peripheral circuitry PERI may include row selection circuitry 20, column selection circuitry 30, write driver 40, and sensing circuitry 50. Although not shown in detail, the peripheral circuitry may also include reference circuitry. Figure 1 The source line driver 60, input / output circuitry 70, and control logic 80 are described.

[0197] The row selection circuit 20 may include a row decoder 21, and the column selection circuit 30 may include a column decoder 31.

[0198] Figure 13 The contents of the row selection circuit 20, column selection circuit 30, write driver 40, and sensing circuit 50 can be similarly applied to the reference. Figure 1The description includes the row selection circuit 20, column selection circuit 30, write driver 40, and sensing circuit 50.

[0199] The line decoder 21 can be based on the line address R_ADDR (see...) Figure 1 To select the storage unit MC (see) Figure 2 ) and OTP unit OTPC (see Figure 2 The word lines are connected. The column decoder 31 can be based on... Figure 1 The column address C_ADDR is used to select and Figure 2 storage unit MC and Figure 2 The bit lines and / or source lines connected to the OTP unit OTPC.

[0200] The write driver 40 can drive the write voltage to the memory cell selected by the row decoder 21 and the column decoder 31. Figure 2 MC) and OTP unit ( Figure 2 OTPC). The sensing circuit 50 can be used to determine the contents stored in the memory cell (OTPC). Figure 2 MC) and OTP unit ( Figure 2 The value of each of the data in the OTPC.

[0201] In the first direction DR1, the peripheral circuitry PERI can be positioned closer to the OTP cell array 12 than to the memory cell array 11. That is, the peripheral circuitry region CPR can be connected to the bit line closer to the OTP cell array 12 than to the memory cell array 11. The OTP cell array 12 can be positioned between the memory cell array 11 and the peripheral circuitry region CPR in the first direction DR1.

[0202] For example, in the first direction DR1, the column decoder 31 can be positioned closer to the OTP cell array 12 than to the memory cell array 11. In this case, the OTP cell array 12 can be positioned between the memory cell array 11 and the column decoder 31.

[0203] although Figure 13 The example shows column decoder 31 being closer to the cell region than row decoder 21, but the example embodiment is not limited to this. In some example embodiments, row decoder 21 may be configured to be closer to the cell region than column decoder 31.

[0204] Any elements and / or functional blocks disclosed above may include or be implemented in processing circuitry, such as: hardware including logic circuitry; hardware / software combinations such as processors executing software; or combinations thereof. For example, processing circuitry may more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field-programmable gate array (FPGA), a system-on-a-chip (SoC), a programmable logic unit, a microprocessor, an application-specific integrated circuit (ASIC), etc. Processing circuitry may include electrical components, such as at least one of transistors, resistors, capacitors, etc. Processing circuitry may include electrical components, such as logic gates including at least one of AND gates, OR gates, NAND gates, NOT gates, etc.

[0205] Although some exemplary embodiments have been described above with reference to the accompanying drawings, the inventive concept is not limited to these embodiments and can be implemented in various different forms. Those skilled in the art to which this inventive concept pertains will understand that the inventive concept can be implemented in other specific forms without altering its technical idea or essential characteristics. Therefore, it should be understood that the embodiments described above are illustrative in all respects and are not limiting. Furthermore, the exemplary embodiments are not necessarily mutually exclusive. For example, some exemplary embodiments may include one or more features described with reference to one or more of the accompanying drawings, and may also include one or more other features described with reference to one or more other of the accompanying drawings.

Claims

1. A magnetic storage device, comprising: The storage cell includes a first magnetic tunnel junction element; A one-time programmable OTP unit, including a second magnetic tunnel junction element; A switching element is located between the first bit line connected to the memory cell and the second bit line connected to the OTP cell; as well as The peripheral circuitry is configured to control the switching element to disconnect the first bit line and the second bit line from each other in response to a write voltage being applied to the OTP unit.

2. The magnetic storage device according to claim 1, wherein, The peripheral circuitry is configured to control the non-application of the write voltage to the memory cell in response to the write voltage being applied to the OTP cell.

3. The magnetic storage device according to claim 1, further comprising: A first via structure is located on one side of the switching element and adjacent to the first magnetic tunnel junction element; as well as The second via structure is located on the other side of the switching element and adjacent to the second magnetic tunnel junction element.

4. The magnetic storage device according to claim 3, wherein, The first bit line and the second bit line are respectively arranged on the first via structure and the second via structure, and are spaced apart from each other.

5. The magnetic storage device according to claim 3, wherein, The first via structure is located between the first magnetic tunnel junction element and the switching element. The second via structure is located between the second magnetic tunnel junction element and the switching element, and The first via structure and the second via structure are spaced apart from each other.

6. The magnetic storage device according to claim 3, wherein, The switching element includes a plurality of switching elements between the first via structure and the second via structure.

7. The magnetic storage device according to claim 3, wherein, The peripheral circuitry is configured to control the switching element to electrically connect the first bit line and the second bit line to each other by using the first via structure and the second via structure in response to the write voltage being applied to the memory cell.

8. The magnetic storage device according to claim 7, wherein, One end of the switching element is electrically connected to the first bit line through the first via structure, and The other end of the switching element is electrically connected to the second bit line through the second via structure.

9. The magnetic storage device according to claim 1, wherein, In the direction in which the first bit line and the second bit line extend, the peripheral circuit is closer to the OTP cell than to the memory cell.

10. The magnetic storage device according to claim 1, wherein, The storage unit and the OTP unit share the peripheral circuitry.

11. The magnetic storage device according to claim 1, wherein, The peripheral circuit includes: The line decoder is configured to select the word line connected to the OTP unit based on the line address; The column decoder is configured to select the second bit line connected to the OTP unit based on the column address; and The write driver is configured to apply the write voltage to the OTP unit selected by the row decoder and the column decoder.

12. A magnetic storage device, comprising: A storage unit, connected to the first bit line and including a first magnetic tunnel junction element; A one-time programmable OTP unit is connected to a second bit line and includes a second magnetic tunnel junction element; Bit line connection transistor, located between the first bit line and the second bit line in a first direction extending from the first bit line and the second bit line; and The peripheral circuitry is configured to control the bit-line connected transistor. The peripheral circuit is configured as follows: In response to a first write voltage being applied to the OTP cell, the bit line connection transistor is controlled to turn off; and In response to a second write voltage being applied to the memory cell, the bit line connection transistor is controlled to turn on.

13. The magnetic storage device according to claim 12, wherein, The OTP unit corresponds to the first word line. The bit line connection transistor corresponds to the second word line. The peripheral circuitry is also configured to activate a first drive signal driving the first word line and deactivate a second drive signal driving the second word line in response to the first write voltage or the second write voltage being applied to the OTP unit.

14. The magnetic storage device according to claim 12, wherein, In the first direction, the peripheral circuit is closer to the OTP unit than to the storage unit.

15. The magnetic storage device according to claim 12, wherein, In the first direction, the OTP unit is located between the bit line connection transistor and the peripheral circuit.

16. A magnetic storage device, comprising a storage unit and a one-time programmable (OTP) unit, in, The storage unit includes: The first magnetic tunnel junction element is connected to the first bit line; and The first unit transistor connects the first source line and the first magnetic tunnel junction element to each other, and is also connected to the first word line. The OTP unit includes: The second magnetic tunnel junction element is connected to the second bit line; A cell array connects a second source line and a second magnetic tunnel junction element to each other, wherein the cell array includes a second cell transistor, a third cell transistor, and a fourth cell transistor connected to a second word line, a third word line, and a fourth word line, respectively; A switching element is located between the first bit line and the second bit line in a first direction in which the first bit line and the second bit line extend; A first via structure is located on one side of the switching element and adjacent to the storage cell; A second via structure is located on the other side of the switching element and adjacent to the OTP unit; and The peripheral circuitry is closer to the OTP unit than to the memory unit in the first direction. The peripheral circuitry is configured to control the switching element to electrically disconnect the first bit line and the second bit line from each other in response to performing a first write operation on the OTP unit.

17. The magnetic storage device according to claim 16, wherein, The peripheral circuitry is also configured to control the switching element to turn on in response to at least one of performing a second write operation on the storage cell, performing a first read operation on the storage cell, or performing a second read operation on the OTP cell.

18. The magnetic storage device according to claim 16, wherein, The peripheral circuitry is also configured to control the switching element to turn off in response to a write voltage being applied to the OTP unit.

19. The magnetic storage device according to claim 18, wherein, The peripheral circuitry is also configured to control the write voltage from being applied to the memory cell.

20. The magnetic storage device according to claim 16, wherein, The peripheral circuitry is also configured to select the second word line and not the third word line to apply a write voltage to the OTP cell.

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