Light load pfc efficiency improvement and pf optimization circuit

Abstract

The application discloses a light-load PFC efficiency improvement and PF optimization circuit, relates to the field of switching power supplies, and comprises an interleaved PFC master control unit which generates two complementary driving signals and carries out closed-loop control according to a feedback signal; a Boost main power unit which completes voltage step-up and power factor correction according to the driving signals; a sampling unit which collects output voltage and input current and feeds back to the interleaved PFC master control unit; a Comp sampling and filtering compensation unit which samples the voltage of a Comp pin and adjusts compensation parameters of a voltage loop and a current loop according to a load state; and a switching phase-off unit which judges the load state according to the output signal of the Comp sampling and filtering compensation unit and judges whether to turn off a PFC driving signal of one phase according to the load state. The application overcomes the defects of low light-load efficiency, poor PF value and unstable work in the prior PFC control technology and can adaptively adjust control parameters and optimize light-load performance.

Description

Technical Field

[0001] This application relates to the field of switching power supply technology, and in particular to a circuit for improving PFC efficiency and optimizing PF under light load. Background Technology

[0002] In medium-to-high power AC-DC power supplies, interleaved Boost PFC is the mainstream topology. By interleaving two or more Boost units in parallel, input current ripple can be significantly reduced and power density increased. With increasingly stringent energy conservation and emission reduction requirements, power supply equipment not only needs to have a high power factor and low input current harmonics under full load conditions, but also needs to meet stringent energy efficiency standards under light load conditions, and harmonic standards (such as IEC 61000-3-2).

[0003] To optimize efficiency under light loads, existing technologies typically employ methods such as frequency reduction and phase switching (phase stopping), but these methods have the following drawbacks: (1) PF value decrease and current distortion: Simple phase stop will cause distortion of the input current waveform and a significant decrease in PF value. When the load is light, the inductor current enters discontinuous mode, and there is a deviation between the sampled current and the actual input current. If not corrected, it will lead to current tracking deviation, affecting the power factor and total harmonic distortion (THDi). At the same time, the peak value of the inductor current is small under light load. The zero-crossing detector (ZCD) delay and dead zone effect will cause the current waveform to have a "dead zone", further increasing the input current distortion rate, reducing the PF value, and making it difficult to meet the harmonic standard.

[0004] (2) Low efficiency under light load: Traditional PFC controllers are usually designed for full-load conditions. Under light load conditions, the switching frequency is still relatively high, which leads to an increase in the proportion of switching losses and a significant decrease in efficiency. If the frequency is too low, audio noise will be introduced and the dynamic response will deteriorate. Under light load, switching losses, drive losses and core losses dominate in multiphase PFC. The parallel operation of multiple phases will amplify these losses, resulting in a significant decline in the overall efficiency.

[0005] (3) The compensation network is complex and has poor stability: The existing compensation network design is complex and it is difficult to simultaneously achieve both efficiency and power factor (PF). Insufficient phase margin under light load may lead to system instability, while excessive bandwidth under heavy load may affect control accuracy. Traditional phase-stop control requires complex logic judgment and compensation algorithm, which can easily lead to increased output voltage ripple and slower dynamic response.

[0006] (4) Single / Dual-phase switching disturbance: Interleaved PFC switches to single-phase operation mode under light load to improve efficiency, but the switching process is prone to disturbance to the controller, resulting in output voltage fluctuation. Long-term multi-phase operation will also lead to inconsistent aging of devices in each phase, reducing system reliability. Summary of the Invention

[0007] The purpose of this application is to provide a light-load PFC efficiency improvement and PF optimization circuit to solve the above-mentioned problems existing in the prior art.

[0008] To achieve the above objectives, this application provides a light-load PFC efficiency improvement and PF optimization circuit, comprising: The interleaved PFC main control unit is used to generate two complementary drive signals and perform closed-loop control based on the feedback signal. The Boost main power unit, connected to the interleaved PFC main control unit, is used to perform boost and power factor correction based on the drive signal; The sampling unit, connected to the Boost main power unit and the interleaved PFC main control unit, is used to collect the output voltage and input current and feed them back to the interleaved PFC main control unit. The Comp sampling and filtering compensation unit is connected to the Comp pin of the interleaved PFC main control unit. It is used to sample the voltage of the Comp pin and adjust the compensation parameters of the voltage loop and current loop according to the load status. The phase-stop switching unit is connected to the interleaved PFC main control unit and the Comp sampling and filtering compensation unit. It is used to determine the load status based on the output signal of the Comp sampling and filtering compensation unit, and to determine whether to turn off the PFC drive signal of one phase based on the load status.

[0009] Preferably, the Boost main power unit includes two-phase interleaved parallel Boost circuits. Each phase circuit includes an inductor, a switching transistor, a boost diode, and an output capacitor. The output terminals of the two phase circuits are connected in parallel.

[0010] Preferably, the Comp sampling and filtering compensation unit includes a voltage follower and an RC low-pass filter network. The input of the voltage follower is connected to the Comp pin of the interleaved PFC main control unit, and the output is connected to the input of the RC low-pass filter network.

[0011] Preferably, the sampling unit includes an output voltage sampling circuit and an input current sampling circuit. The output voltage sampling circuit is composed of voltage divider resistors connected in series, and the input current sampling circuit is composed of a sampling resistor and a filter capacitor.

[0012] Preferably, the phase-stop unit includes a load detection circuit and a switch execution circuit; the load detection circuit is used to sample the output current or load power in real time, and the switch execution circuit includes a first transistor, a second transistor, and a resistor; when the sampled output current or load power is lower than a set threshold, the second transistor is turned off, the first transistor is turned on, and the phase-stop pin of the interleaved PFC main control unit is pulled to a low level, turning off the drive signal of one phase; when the sampled output current or load power is higher than the set threshold, the second transistor is turned on, the first transistor is turned off, the phase-stop pin is pulled to a high level, and all-phase operation is restored.

[0013] Preferably, it also includes a zero-crossing detection optimization circuit, which consists of a fast diode and at least two stages of RC filter network connected in series. The input terminal of the fast diode is connected to the inductively coupled signal terminal of the Boost main power unit, and the output terminal is connected to the zero-crossing detection signal input terminal of the interleaved PFC main control unit through a multi-stage RC filter network.

[0014] Preferably, it further includes a voltage comparison unit, which consists of a second operational amplifier, a resistor divider network, a feedback resistor, and a capacitor; wherein, the output terminal of the Comp sampling and filtering compensation unit is connected to the inverting input terminal of the second operational amplifier after being filtered by the resistor and capacitor, the non-inverting input terminal of the second operational amplifier is connected to the reference voltage formed by the resistor divider and capacitor filtering, and the feedback resistor and capacitor are connected in parallel between the output terminal and the non-inverting input terminal of the second operational amplifier to form a hysteresis comparator.

[0015] Preferably, the phase-stopping unit includes a resistor and a first transistor; the output of the second operational amplifier is connected to the base of the first transistor after being divided by the resistor; when the second operational amplifier outputs a high level, the first transistor is turned on, pulling the phase-stopping pin of the interleaved PFC main control unit to a low level, and turning off the driving signal of the corresponding phase; when the second operational amplifier outputs a low level, the first transistor is turned off, the phase-stopping pin is pulled to a high level, and the full-phase operation is restored.

[0016] Preferably, the voltage comparison unit forms a positive feedback network through a feedback resistor and a capacitor: when the second operational amplifier outputs a high level to latch the phase-stop state, the positive feedback network raises the reference voltage at the non-inverting input terminal, increasing the phase-start threshold; when the second operational amplifier outputs a low level to latch the phase-start state, the positive feedback network lowers the reference voltage at the non-inverting input terminal, increasing the phase-stop threshold; thereby forming a hysteresis latching mechanism to avoid repeated switching of the phase-stop state due to load fluctuations at the light load boundary.

[0017] Preferably, the Comp sampling and filtering compensation unit further includes a Comp sampling compensation network, which consists of resistors and capacitors and is connected to the signal path of the voltage comparison unit. It is used to sample and filter the Comp compensation signal, monitor the loop status in real time, and adaptively adjust the compensation parameters during phase stop, so as to decouple the phase stop control from the main power loop and avoid the phase stop action from impacting the output voltage stability and system dynamic response.

[0018] Therefore, the light-load PFC efficiency improvement and PF optimization circuit described above has the following advantages compared with the prior art: (1) Significantly improved efficiency under light load: By stopping the phase under light load, the PFC of one phase is turned off, and the losses of the switching transistor, drive circuit and inductor core of the turned-off phase are completely eliminated, which greatly reduces the dominant switching losses, drive losses and core losses under light load. The measured efficiency under light load can be improved by 3%~8%.

[0019] (2) PF value and THD performance optimization: Zero-crossing detection is optimized by fast diodes and multi-level RC compensation network, shortening the response time, eliminating the zero-crossing distortion of inductor current, making the input current waveform closer to a sine wave, and the PF value under light load can be maintained above 0.98, and the THD meets the requirements of IEC 61000-3-2 standard.

[0020] (3) High system stability and no switching disturbance: Through the positive feedback network of the voltage comparison unit, the reference voltage is adaptively compensated, forming a hysteresis latching mechanism, avoiding repeated switching of the phase stop state due to load fluctuation at the light load boundary, completely eliminating the oscillation phenomenon of "sometimes stopping and sometimes not stopping", improving stability and reliability, and can be widely used in various power supplies.

[0021] The technical solution of this application will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0022] Figure 1 This is a circuit schematic diagram of the basic scheme for a light-load PFC efficiency improvement and PF optimization circuit in this application; Figure 2 This is a circuit schematic diagram of the improved scheme in the embodiments of this application; Figure 3 This is a basic circuit block diagram of the embodiments of this application; Figure 4 This is a circuit block diagram of the improved scheme in the embodiments of this application. Detailed Implementation

[0023] The following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0024] Unless otherwise defined, the technical or scientific terms used in this application shall have the ordinary meaning as understood by a person of ordinary skill in the art to which this application pertains.

[0025] The terms "comprising" or "including," as used in this application, mean that the element preceding the term encompasses the element listed after the term, and do not exclude the possibility of encompassing other elements as well. The terms "inner," "outer," "upper," and "lower," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. When the absolute position of the described object changes, the relative positional relationship may also change accordingly. In this application, unless otherwise expressly specified and limited, the term "attached," etc., should be interpreted broadly. For example, it can refer to a fixed connection, a detachable connection, or an integral part; it can refer to a direct connection or an indirect connection through an intermediate medium; it can refer to the internal communication of two elements or the interaction relationship between two elements. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0026] Example 1: A light-load PFC efficiency improvement and PF optimization circuit includes: The interleaved PFC main control unit is used to generate two complementary drive signals and perform closed-loop control based on the feedback signal. The Boost main power unit, connected to the interleaved PFC main control unit, is used to perform boost and power factor correction based on the drive signal; The Boost main power unit includes two-phase interleaved parallel Boost circuits. Each phase circuit includes an inductor, a switching transistor, a boost diode, and an output capacitor. The output terminals of the two phase circuits are connected in parallel.

[0027] The sampling unit, connected to the Boost main power unit and the interleaved PFC main control unit, is used to collect the output voltage and input current and feed them back to the interleaved PFC main control unit. The sampling unit includes an output voltage sampling circuit and an input current sampling circuit. The output voltage sampling circuit is composed of voltage divider resistors connected in series, and the input current sampling circuit is composed of a sampling resistor and a filter capacitor.

[0028] The Comp sampling and filtering compensation unit is connected to the Comp pin of the interleaved PFC main control unit. It is used to sample the voltage of the Comp pin and adjust the compensation parameters of the voltage loop and current loop according to the load status. The Comp sampling and filtering compensation unit includes a voltage follower and an RC low-pass filter network. The input of the voltage follower is connected to the Comp pin of the interleaved PFC main control unit, and the output is connected to the input of the RC low-pass filter network.

[0029] The phase-stop switching unit is connected to the interleaved PFC main control unit and the Comp sampling and filtering compensation unit. It is used to determine the load status based on the output signal of the Comp sampling and filtering compensation unit, and to determine whether to turn off the PFC drive signal of one phase based on the load status.

[0030] The phase-stop unit includes a load detection circuit and a switch execution circuit. The load detection circuit is used to sample the output current or load power in real time. The switch execution circuit includes a first transistor, a second transistor, and a resistor. When the sampled output current or load power is lower than a set threshold, the second transistor is turned off and the first transistor is turned on, pulling the phase-stop pin of the interleaved PFC main control unit to a low level and turning off the drive signal of one phase. When the sampled output current or load power is higher than the set threshold, the second transistor is turned on and the first transistor is turned off, the phase-stop pin is pulled to a high level, and all-phase operation is restored.

[0031] It also includes a zero-crossing detection optimization circuit, which consists of a fast diode and at least two stages of RC filter network connected in series. The input of the fast diode is connected to the inductively coupled signal terminal of the Boost main power unit, and the output is connected to the zero-crossing detection signal input terminal of the interleaved PFC main control unit through a multi-stage RC filter network.

[0032] Specifically, such as Figure 1 and Figure 3 As shown, this basic solution is designed for applications with less demanding requirements and consists of five main functional modules: Phase-stopping switching section: composed of Q5 / Q6, operational amplifier U1, etc., which determines whether to turn off one phase of the PFC based on the load current; Interleaved PFC main control section: the core control chip U3 generates two complementary drive signals (ZCDA / ZCDB) to achieve interleaved control and phase-stopping logic; Boost main power section: composed of T1 / T1A inductors, Q1 / Q3 switching transistors, D1 / D2 diodes, and output capacitor EC1, which completes voltage boosting and power factor correction; Sampling section: collects output voltage and input current signals to provide feedback for the control loop; Comp sampling and filtering compensation section: composed of an R / C network and operational amplifiers, which achieves voltage and current loop compensation to ensure system stability and dynamic performance.

[0033] The working mechanism is as follows: After power-on, the interleaved control chip U3 starts working, and Q1 and Q3 start working alternately. At this time, the feedback signal after coupling of the boost main power section step-up transformer enters the interleaved PFC main control section through R1 and R4 for zero-crossing detection. At the same time, ZCDA / ZCDB is sampled by diode Q7 and then filtered by the filter compensation circuit composed of C6 filter, R8, and C3 RC filter network. The Comp sampling and compensation part composed of R / C network compensates the Comp of the interleaved PFC main control chip according to the load state (light load / The voltage difference across C6 under heavy load indicates the load state of the PFC circuit. The compensation parameters of the voltage and current loops are adjusted to improve the power factor (PF). Under light load, the PFC main control chip has a higher frequency and smaller duty cycle. When ZCDA / ZCDB is sampled by diode Q7, the voltage across C6 decreases, the filter compensation decreases, and the Comp level rises (the Comp voltage is higher than before compensation), thus increasing the PF. Under heavy load, the PFC main control chip has a lower frequency and larger duty cycle. When ZCDA / ZCDB is sampled by diode Q7, the voltage across C6 rises, the filter compensation increases, the Comp level is very high, and the PF increases. Accurate ZCDA / ZCDB signals are generated by quickly detecting the zero-crossing point of the inductor current, controlling the switching transistor to turn on / off when the current is zero. Traditional light-load ZCD delay leads to a "dead zone" in the current waveform. This circuit shortens the ZCD response time and eliminates current zero-crossing distortion through fast diodes and precise RC compensation, making the input current closer to a sine wave, thereby improving the PF and reducing THD. Simultaneously, the ZCD signal is sent to the main control unit U3 to ensure that the inductor current of the remaining working phases smoothly crosses zero in each half-cycle, avoiding phase misalignment and achieving synchronous control. Under the effect of loop compensation, stability and waveform quality are guaranteed. The Comp sampling section, composed of operational amplifier U1 and an R / C network, adjusts the compensation parameters of the voltage and current loops according to the load state (light load / heavy load). Light load adaptation: After phase stoppage, the compensation network automatically adapts to the loop gain of single-phase operation to avoid system oscillation, while maintaining stable output voltage and ensuring the sinusoidal nature of the input current waveform. At the same time, multi-stage RC filters C3, C4, C5, and C6 are used to suppress high-frequency noise, improving the reliability and anti-interference capability of the ZCD and sampling signals.

[0034] The working principle of the light-load PFC efficiency improvement and PF value optimization circuit is as follows: Light load phase-stop: When the load current is below the threshold, the phase-stop section of the switch shuts off one PFC drive signal (such as ZCDB), keeping only one phase running, which greatly reduces switching and drive losses; ZCD optimization: By quickly detecting the zero-crossing point of the inductor current through Q7, the timing of the ZCD signal is optimized, reducing the current zero-crossing distortion and improving the light load PF value. Adaptive compensation: The Comp sampling section adjusts the compensation network parameters according to the load condition, maintaining good voltage regulation and current waveform quality even after phase stoppage.

[0035] In the phase-stop section, the voltage across the Comp pin is sampled by operational amplifier U1 and fed into the positive terminal of the operational amplifier via R9. Under the action of the operational amplifier follower, U1 outputs a voltage identical to the voltage at the Comp pin, which is then supplied to the phase-stop switching circuit. This circuit consists of R11, R13, Q6, R7, Q5, R6, and R20. When the sampled voltage at the Comp pin causes the voltage across R13 to be less than 0.7V, Q6 is cut off. The voltage across R20 and R7, after voltage division, is greater than 0.7V, and Q5 is turned on. The phase-stop pin of the PFC main control chip is pulled low, and the PFC main control chip stops the gate output for one phase, achieving phase-stop. This improves PFC efficiency under light load. Actual measurements show that phase-stop under light load reduces switching and drive losses by approximately 50%, and efficiency can be improved by 3% to 8%.

[0036] When the sampled Comp pin voltage makes the voltage across R13 greater than 0.7V, Q6 turns on, and the voltage after voltage division by R20 and R7 is less than 0.7V, Q5 turns off. The PFC main control chip's phase-stop pin is pulled high, and the PFC main control chip starts to work in full phase and outputs dual or multiple GATE channels.

[0037] Example 2: This embodiment is an improvement upon Embodiment 1.

[0038] The voltage comparator unit consists of a second operational amplifier, a resistor divider network, a feedback resistor, and a capacitor. The output of the Comp sampling and filtering compensation unit is connected to the inverting input of the second operational amplifier after being filtered by the resistor and capacitor. The non-inverting input of the second operational amplifier is connected to the reference voltage formed by the resistor divider and capacitor filtering. The feedback resistor and capacitor are connected in parallel between the output and non-inverting input of the second operational amplifier to form a hysteresis comparator.

[0039] The phase-stop unit includes a resistor and a first transistor; the output of the second operational amplifier is connected to the base of the first transistor after being divided by the resistor; when the second operational amplifier outputs a high level, the first transistor is turned on, pulling the phase-stop pin of the interleaved PFC main control unit to a low level, turning off the drive signal of the corresponding phase; when the second operational amplifier outputs a low level, the first transistor is turned off, the phase-stop pin is pulled to a high level, and the full-phase operation is restored.

[0040] The voltage comparator unit forms a positive feedback network through a feedback resistor and a capacitor: when the second operational amplifier outputs a high level to latch the phase-stop state, the positive feedback network raises the reference voltage at the non-inverting input terminal, increasing the phase-start threshold; when the second operational amplifier outputs a low level to latch the phase-start state, the positive feedback network lowers the reference voltage at the non-inverting input terminal, increasing the phase-stop threshold; thus forming a hysteresis latching mechanism to avoid repeated switching of the phase-stop state due to load fluctuations at the light load boundary.

[0041] The Comp sampling and filtering compensation unit also includes a Comp sampling compensation network, which consists of resistors and capacitors and is connected to the signal path of the voltage comparison unit. It is used to sample and filter the Comp compensation signal, monitor the loop status in real time, and adaptively adjust the compensation parameters during phase stoppage. This decouples the phase stoppage control from the main power loop and avoids the impact of phase stoppage on the output voltage stability and system dynamic response.

[0042] Specifically, such as Figure 2 and Figure 4 As shown, the system is divided into six functional modules: Phase-stopping switching section: composed of Q5, R6, R11, R13, operational amplifier U2, etc., which determines whether to turn off one phase of the PFC based on the load current; Interleaved PFC main control section: the core control chip U3 generates two complementary drive signals (ZCDA / ZCDB) to realize interleaved control and phase-stopping logic; Boost main power section: composed of T1 / T1A inductors, Q1 / Q3 switching transistors, D1 / D2 diodes, and output capacitor EC1, which completes voltage boost and power factor correction; Sampling section: Q7 collects output voltage and input current signals to provide feedback for the control loop; Filtering and compensation section: composed of R12, C6, R8, C3, R / C network, and operational amplifier, which realizes voltage and current loop compensation to ensure system stability and dynamic performance; Comp sampling section: composed of R9 and U1; Voltage comparison section: composed of R15, R16, C8, R17, and C9, with R14 and C8 as the feedback section.

[0043] Compared to the basic solution, the improved solution in this embodiment makes key improvements to the phase-stopping circuit, solving the problem of the other switching transistor easily entering the linear region and exhibiting "intermittent" jitter during phase-stopping, thus significantly improving the stability and reliability of phase-stopping control. The original phase-stopping circuit consists of Q5, Q6, and operational amplifier U1, and has the following problems: Linear Region Risks: When a phase stops, the simple transistor turn-off drive makes the control signal susceptible to load fluctuations and noise interference. This can cause the phase-stopping drive signal (such as GDB) to not be fully pulled back, resulting in the switching transistor Q3 entering the linear region and exhibiting an incomplete on / off state. Intermittent Interruptions: Operation in the linear region introduces additional losses and current distortion. Simultaneously, the feedback loop misjudges the load state, causing the phase-stopping logic to be repeatedly triggered, resulting in intermittent oscillations that degrade system stability. Insufficient Control Accuracy: The phase-stopping threshold judgment relies on simple current sampling, lacking voltage comparison and hysteresis mechanisms, making it prone to malfunctions at light load boundaries. For applications with higher requirements, an improved mechanism is used. The optimized phase-stopping circuit adds a voltage comparison section (op-amp U2, resistors R11 / R13 / R14) and a Comp sampling compensation section (R15 / R16 / C7 / C8 / C9), solving the original problems from both control logic and signal stability perspectives. 1. Voltage comparison and hysteresis control: Operational amplifier U2 and surrounding resistors form a voltage comparator with hysteresis to perform threshold judgment on the load current / power sampling signal, avoiding false triggering at the light load boundary.

[0044] When the load is below the threshold, U2 outputs a stable low level, directly latching the phase-stop state; when the load recovers to above the threshold, the phase-stop is released, completely eliminating the "intermittent" oscillation.

[0045] 2. Drive signal hard-pull mechanism: When a phase stops, the optimization circuit, through the coordinated control of Q5 / Q6 and U2, will forcefully pull the drive signal (gdb) of the stopped phase to ground or the power rail, ensuring that the switching transistor Q3 is completely turned off and completely avoiding entering the linear region.

[0046] Compared to the original circuit's "soft shutdown," the optimized "hard shutdown" makes the drive signal level jump steeper, with no intermediate transition state, thus eliminating the possibility of incomplete conduction.

[0047] 3. Comp sampling and compensation optimization: The newly added R15 / R16 / C7 / C8 / C9 networks sample and filter the Comp compensation signal, monitor the loop status in real time, and adaptively adjust the compensation parameters during phase stoppage to ensure the stable operation of the remaining working phases, while preventing the phase stoppage logic from being falsely triggered by interference signals.

[0048] This part decouples the phase-stop control from the main power loop, avoiding the impact of phase-stop action on system stability.

[0049] The PF value compensation and optimization part is the same as the basic scheme.

[0050] In the phase-stopping section, the Comp sampling section uses op-amp U1 to input the Comp voltage through R9 to the positive terminal of the op-amp. Under the action of the op-amp follower, U1 outputs a voltage that is the same as the voltage at the Comp pin. The U1 output signal is filtered by R17 and C9 and then sent to the negative terminal of U2. The positive terminal of U2 is a stable reference voltage after being filtered by R15 and C7. The voltage comparison section is composed of R15, R16, C8, R17, and C9, with the feedback section consisting of R14 and C8. The two voltages are compared. The phase-stopping switching circuit is composed of R6, Q5, R11, and R13. When the sampled Comp pin voltage is less than the U2 reference voltage, U2 outputs a high level. After being divided by R13 and R11, the high level voltage is greater than 0.7V, Q5 turns on, and the PFC main control chip's phase stop pin is pulled to a low level. Under the action of R14 and C8 in the feedback section, the high level output of U2 compensates for the reference at the positive end of U2, causing the reference voltage to rise, and the PFC main control chip stops the GATE output of one phase.

[0051] When the sampled voltage at the Comp pin is greater than the reference voltage of U2, U2 outputs a low level. After being divided by R13 and R11, the low level voltage is less than 0.7V, Q5 is cut off, and the PFC main control chip pulls the phase-stopping signal to the low level. Under the action of R14 and C8 in the feedback section, the low level output by U2 compensates for the reference voltage at the positive terminal of U2, further reducing the reference voltage. The PFC main control chip then starts to operate in full phase and outputs dual or multiple gates. Under the action of R14 and C8 in the feedback section, the control signal of the receiving voltage comparison section is enabled to realize hard turn-off / turn-on control of the target phase drive signal, achieving stable phase-stopping / phase-starting logic switching. U2 outputs a stable low-level control signal through hysteresis comparison logic to latch the "phase-stopping" state. When the load power rises back above the threshold, U2 switches to a high level, releasing the phase-stopping state. This hysteresis mechanism avoids false triggering at the light load boundary, eliminating the "intermittent" oscillation at its source.

[0052] The improved scheme in this embodiment completely eliminates the risk of linear region. When a phase stops, the target phase switch is completely turned off, eliminating conduction losses and current distortion in the linear region, resulting in a 3%~8% improvement in light-load efficiency. It achieves stable, oscillation-free operation in the phase-stop state. The voltage comparison hysteresis mechanism latches the phase-stop state, avoiding intermittent jitter at the light-load boundary, resulting in smoother system operation. Simultaneously, the power factor (PF) and total current (THD) performance are optimized: after eliminating linear region distortion, the input current waveform is closer to a sine wave, the PF value can be maintained above 0.98 under light load, and the THD meets the requirements of the IEC 61000-3-2 standard. Enhanced anti-interference capability is also achieved: Comp sampling compensation and multi-stage filtering design significantly improve the circuit's immunity to load fluctuations and power supply noise, making it suitable for demanding applications such as server power supplies and industrial power supplies.

[0053] Therefore, this application adopts the above-mentioned light-load PFC efficiency improvement and PF optimization circuit. By using the phase-stopping unit to adaptively turn off the PFC drive signal of one phase according to the load state, the switching loss, drive loss and core loss under light load are greatly reduced, thereby improving the efficiency under light load. By using the zero-crossing detection optimization circuit to shorten the zero-crossing detection response time and eliminate the inductor current zero-crossing distortion, the input current waveform is made close to a sine wave, thereby improving the power factor. By using the Comp sampling and filtering compensation unit to adaptively adjust the compensation parameters during the phase-stopping period, the output voltage is stable and shock-free.

[0054] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application and not to limit them. Although this application has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can still be made to the technical solutions of this application, and these modifications or equivalent substitutions cannot cause the modified technical solutions to deviate from the spirit and scope of the technical solutions of this application.

Claims

1. A circuit for improving PFC efficiency and optimizing PF under light load, characterized in that, include: The interleaved PFC main control unit is used to generate two complementary drive signals and perform closed-loop control based on the feedback signal. The Boost main power unit, connected to the interleaved PFC main control unit, is used to perform boost and power factor correction based on the drive signal; The sampling unit, connected to the Boost main power unit and the interleaved PFC main control unit, is used to collect the output voltage and input current and feed them back to the interleaved PFC main control unit. The Comp sampling and filtering compensation unit is connected to the Comp pin of the interleaved PFC main control unit. It is used to sample the voltage of the Comp pin and adjust the compensation parameters of the voltage loop and current loop according to the load status. The phase-stop switching unit is connected to the interleaved PFC main control unit and the Comp sampling and filtering compensation unit. It is used to determine the load status based on the output signal of the Comp sampling and filtering compensation unit, and to determine whether to turn off the PFC drive signal of one phase based on the load status.

2. The light-load PFC efficiency improvement and PF optimization circuit according to claim 1, characterized in that, The Boost main power unit includes two-phase interleaved parallel Boost circuits. Each phase circuit includes an inductor, a switching transistor, a boost diode, and an output capacitor. The output terminals of the two phase circuits are connected in parallel.

3. The light-load PFC efficiency improvement and PF optimization circuit according to claim 2, characterized in that, The Comp sampling and filtering compensation unit includes a voltage follower and an RC low-pass filter network. The input of the voltage follower is connected to the Comp pin of the interleaved PFC main control unit, and the output is connected to the input of the RC low-pass filter network.

4. The light-load PFC efficiency improvement and PF optimization circuit according to claim 3, characterized in that, The sampling unit includes an output voltage sampling circuit and an input current sampling circuit. The output voltage sampling circuit is composed of voltage divider resistors connected in series, and the input current sampling circuit is composed of a sampling resistor and a filter capacitor.

5. The light-load PFC efficiency improvement and PF optimization circuit according to claim 4, characterized in that, The phase-stop unit includes a load detection circuit and a switch execution circuit. The load detection circuit is used to sample the output current or load power in real time. The switch execution circuit includes a first transistor, a second transistor, and a resistor. When the sampled output current or load power is lower than a set threshold, the second transistor is turned off and the first transistor is turned on, pulling the phase-stop pin of the interleaved PFC main control unit to a low level and turning off the drive signal of one phase. When the sampled output current or load power is higher than the set threshold, the second transistor is turned on and the first transistor is turned off, the phase-stop pin is pulled to a high level, and all-phase operation is restored.

6. The light-load PFC efficiency improvement and PF optimization circuit according to claim 5, characterized in that, It also includes a zero-crossing detection optimization circuit, which consists of a fast diode and at least two stages of RC filter network connected in series. The input of the fast diode is connected to the inductively coupled signal terminal of the Boost main power unit, and the output is connected to the zero-crossing detection signal input terminal of the interleaved PFC main control unit through a multi-stage RC filter network.

7. The light-load PFC efficiency improvement and PF optimization circuit according to claim 1, characterized in that, It also includes a voltage comparison unit, which consists of a second operational amplifier, a resistor divider network, a feedback resistor, and a capacitor. The output of the Comp sampling and filtering compensation unit is connected to the inverting input of the second operational amplifier after being filtered by the resistor and capacitor. The non-inverting input of the second operational amplifier is connected to the reference voltage formed by the resistor divider and capacitor filtering. The feedback resistor and capacitor are connected in parallel between the output and non-inverting input of the second operational amplifier to form a hysteresis comparator.

8. The light-load PFC efficiency improvement and PF optimization circuit according to claim 7, characterized in that, The phase-stopping switch unit includes a resistor and a first transistor; the output of the second operational amplifier is connected to the base of the first transistor after being divided by a resistor; When the second operational amplifier outputs a high level, the first transistor is turned on, pulling the phase-stop pin of the interleaved PFC main control unit to a low level and turning off the drive signal of the corresponding phase; when the second operational amplifier outputs a low level, the first transistor is turned off, the phase-stop pin is pulled to a high level, and the full-phase operation is restored.

9. The light-load PFC efficiency improvement and PF optimization circuit according to claim 8, characterized in that, The voltage comparison unit forms a positive feedback network through a feedback resistor and a capacitor: when the second operational amplifier outputs a high level to latch the phase-stop state, the positive feedback network raises the reference voltage at the non-inverting input terminal and increases the phase-start threshold; when the second operational amplifier outputs a low level to latch the phase-start state, the positive feedback network lowers the reference voltage at the non-inverting input terminal and increases the phase-stop threshold. This creates a hysteresis latching mechanism, preventing repeated switching of the phase-stop state due to load fluctuations at the light load boundary.

10. The light-load PFC efficiency improvement and PF optimization circuit according to claim 9, characterized in that, The Comp sampling and filtering compensation unit also includes a Comp sampling compensation network, which consists of resistors and capacitors and is connected to the signal path of the voltage comparison unit. It is used to sample and filter the Comp compensation signal, monitor the loop status in real time, and adaptively adjust the compensation parameters during phase stoppage. This decouples the phase stoppage control from the main power loop and avoids the impact of phase stoppage on the output voltage stability and system dynamic response.

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