Resonant charge pump circuit

Abstract

A resonant charge pump circuit includes a resonant circuit having a series connection of a bucket capacitor and a bucket inductor, and a switching circuit connected to the resonant circuit. The switching circuit switches to a first state that enables current to flow from an input terminal into the resonant circuit to charge the bucket capacitor and the bucket inductor, and to a second state that enables current to flow from the resonant circuit to discharge the bucket capacitor and the bucket inductor to an output terminal. The resonant circuit controls current flow into and out of the resonant circuit as the switching circuit switches between the states. The resonant charge pump circuit further includes a timing circuit that controls when the switching circuit switches between the states.

Description

[0001] Cross-references to related applications

[0002] This application claims the benefit of provisional patent application serial number 63 / 734,226, filed on December 16, 2024, the full disclosure of which is incorporated herein by reference. Technical Field

[0003] This invention generally relates to charge pumps, and more specifically to a high-power and high-efficiency resonant charge pump. Background Technology

[0004] A very common requirement in electronic circuits is to convert an available direct current (DC) voltage source to a lower or higher DC voltage. One way to do this is by using a charge pump circuit. A charge pump uses capacitors as energy storage elements. During operation, current (charge) alternately switches and is directed between two capacitors arranged such that the circuit output is twice the input, thus acting as a voltage doubler boost converter. In other configurations, the charge pump acts as a “voltage divider” in a half-converter or step-down converter.

[0005] Unfortunately, traditional charge pump circuits, despite their well-known high conversion efficiency, may not be suitable for high-power applications. For example, during the switching operation of a charge pump, a large amount of current flows through the components for a very short period of time. This is known as inrush current and can potentially damage circuit components (e.g., cause fuses to blow or apply high stress to the device).

[0006] Therefore, there is a need for a high-efficiency charge pump circuit that is suitable for high-power applications and overcomes the problems associated with conventional circuits. Summary of the Invention

[0007] In various embodiments, a high-power and high-efficiency resonant charge pump circuit is provided. The resonant charge pump overcomes the problems associated with the large inrush currents experienced by conventional circuits. Therefore, embodiments of the resonant charge pump are suitable for applications requiring high power and high efficiency. As an additional benefit, the resonant charge pump operates with very low electromagnetic interference (EMI).

[0008] Example 1. A resonant charge pump circuit comprising: a resonant circuit having a barrel capacitor and a barrel inductor connected in series; a first transistor configured to be off and on, the first transistor being connected to allow current to flow from an input terminal into the resonant circuit to charge the barrel capacitor and the barrel inductor when the first transistor is on, and to prevent current from flowing from the input terminal into the resonant circuit when the first transistor is off; a second transistor configured to be off and on, the second transistor being configured to allow current to flow from the resonant circuit to discharge the barrel capacitor and the barrel inductor to an output terminal when the second transistor is on, and to prevent current from flowing from the resonant circuit to the output terminal when the second transistor is off; and a synchronization circuit configured to generate a clock signal such that the off and on states of the first transistor and the second transistor are synchronized according to the clock signal, wherein the synchronization circuit is configured to detect activation of a first body diode of the first transistor and activation of a second body diode of the second transistor, and to adjust the frequency of the clock signal in response to activation of either the first body diode or the second body diode.

[0009] Example 2. The resonant charge pump circuit according to Example 1, wherein: the first transistor is a first field-effect transistor (FET); and the second transistor is a second FET.

[0010] Example 3. The resonant charge pump circuit according to Example 1, wherein the synchronization circuit is configured to: increase the frequency of the clock signal in response to the detection of activation of the first body diode; and decrease the frequency of the clock signal in response to the detection of activation of the second body diode.

[0011] Example 4. The resonant charge pump circuit according to Example 1, wherein the synchronization circuit is configured to: decrease the frequency of the clock signal in response to the detection of activation of the first body diode; and increase the frequency of the clock signal in response to the detection of activation of the second body diode.

[0012] Example 5. The resonant charge pump circuit according to Example 1, wherein the synchronization circuit is configured to operate the first transistor and the second transistor to turn on and off according to the clock signal, such that: in a first state, the first transistor is on and the second transistor is off; in a second state, the second transistor is on and the first transistor is off; and in a third state, both the first transistor and the second transistor are off.

[0013] Example 6. The resonant charge pump circuit according to Example 5, wherein the synchronization circuit is configured to detect the activation of the first body diode of the first transistor and the activation of the second body diode of the second transistor when both the first transistor and the second transistor are turned off in the third state.

[0014] Example 7. The resonant charge pump circuit according to Example 6, wherein the synchronization circuit comprises: a comparator receiving an intermediate voltage from an intermediate node between the first transistor and the second transistor, the comparator being configured to generate a detection signal in a detection state in response to the intermediate voltage being higher than a threshold voltage level, the threshold voltage level being higher than an input voltage level at an input terminal; an AND gate being configured to receive a stagnation signal in a stagnation state in response to the third state, the AND gate being configured to generate a frequency adjustment signal in a frequency adjustment state in response to the detection signal being in the detection state and the stagnation signal being in the stagnation state; and a one-shot being configured to adjust the clock frequency in response to the frequency adjustment signal being in the frequency adjustment state.

[0015] Example 8. The resonant charge pump circuit according to Example 6, wherein the synchronization circuit comprises: a comparator receiving an intermediate voltage from an intermediate node between the first transistor and the second transistor, the comparator being configured to generate a detection signal in a detection state in response to the intermediate voltage being lower than a threshold voltage level, the threshold voltage level being lower than ground; an AND gate being configured to receive a stagnation signal in a stagnation state in response to the third state, the AND gate being configured to generate a frequency adjustment signal in a frequency adjustment state in response to the detection signal being in the detection state and the stagnation signal being in the stagnation state; and a single-transmitter being configured to adjust the clock frequency in response to the frequency adjustment signal being in the frequency adjustment state.

[0016] Example 9. The resonant charge pump circuit according to Example 1 further includes a switching circuit connected to the resonant circuit, wherein the switching circuit is configured to: switch to a first state, the first state allowing current to flow from the input terminal to the resonant circuit to charge the barrel capacitor and barrel inductor; switch to a second state, the second state allowing current to flow from the resonant circuit to discharge the barrel capacitor and barrel inductor to the output terminal; and switch to a third state, the third state preventing current from flowing from the input terminal to the resonant circuit and preventing current from flowing from the resonant circuit to discharge the barrel capacitor and barrel inductor to the output terminal.

[0017] Example 10. The resonant charge pump circuit according to Example 9, wherein the switching circuit includes the first transistor and the second transistor.

[0018] Example 11. The resonant charge pump circuit according to Example 9, wherein: when the switching circuit is in the first state, the first transistor connects the input terminal to the resonant circuit, and when the switching circuit is in the second and third states, the first transistor disconnects the input terminal from the resonant circuit, and the first transistor is outside the switching circuit; and when the switching circuit is in the second state, the second transistor connects the resonant circuit to the output terminal, and when the switching circuit is in the first and third states, the second transistor disconnects the output terminal from the resonant circuit, and the second transistor is outside the switching circuit.

[0019] Example 12. A method for operating a resonant charge pump, the method comprising: in a first state, turning on a first transistor to allow current to flow from an input terminal to a resonant circuit to charge a barrel capacitor and a barrel inductor, and turning off a second transistor to prevent current from flowing from the resonant circuit to discharge the barrel capacitor and barrel inductor to an output terminal; in a second state, turning off the first transistor to prevent current from flowing from the input terminal to the resonant circuit to charge the barrel capacitor, and turning off the second transistor to prevent current from flowing from the resonant circuit to discharge the barrel capacitor and barrel inductor to the output terminal; and in a third state, turning off the first transistor... A transistor prevents current from flowing from the input terminal to the resonant circuit to charge the barrel capacitor and barrel inductor, and turns on the second transistor to allow current to flow from the resonant circuit to discharge the barrel capacitor and barrel inductor to the output terminal; generates a clock signal such that the opening and closing of the first transistor and the second transistor are synchronized according to the clock signal; detects that either the activation of the first body diode of the first transistor or the activation of the second body diode of the second transistor is in a second state; and adjusts the frequency of the clock signal in response to the activation of the first body diode or the activation of the second body diode.

[0020] Example 13. According to the method of Example 12, adjusting the frequency of the clock signal in response to the activation of the first body diode or the activation of the second body diode includes: increasing the frequency of the clock signal in response to detecting the activation of the first body diode; and decreasing the frequency of the clock signal in response to detecting the activation of the second body diode.

[0021] Example 14. According to the method of Example 12, adjusting the frequency of the clock signal in response to the activation of the first body diode or the activation of the second body diode includes: decreasing the frequency of the clock signal in response to detecting the activation of the first body diode; and increasing the frequency of the clock signal in response to detecting the activation of the second body diode.

[0022] Example 15. The method according to Example 12, wherein detecting either the activation of the first body diode of the first transistor or the activation of the second body diode of the second transistor in a second state comprises: receiving an intermediate voltage from an intermediate node between the first transistor and the second transistor; generating a detection signal in a detection state in response to the intermediate voltage being higher than a threshold voltage level, the threshold voltage level being higher than an input voltage level at the input terminal; and receiving a stagnation signal in a stagnation state in response to the second state.

[0023] Example 16. According to the method of Example 15, adjusting the frequency of the clock signal in response to the activation of the first body diode or the activation of the second body diode includes: generating a frequency adjustment signal in a frequency adjustment state in response to the detection signal being in the detection state and the stagnation signal being in the stagnation state; and adjusting the clock frequency in response to the frequency adjustment signal being in the frequency adjustment state.

[0024] Example 17. According to the method of Example 12, detecting that either the activation of the first body diode of the first transistor is activated or the activation of the second body diode of the second transistor is in the second state includes: receiving an intermediate voltage from an intermediate node between the first transistor and the second transistor; generating a detection signal in a detection state, the threshold voltage level being lower than ground, in response to the intermediate voltage being lower than a threshold voltage level; and receiving a stagnation signal in a stagnation state in response to the second state.

[0025] Example 18. The method according to Example 17, wherein adjusting the frequency of the clock signal in response to the activation of the first body diode or the activation of the second body diode comprises: generating a frequency adjustment signal in a frequency adjustment state in response to the detection signal being in the detection state and the stagnation signal being in the stagnation state; and adjusting the clock frequency in response to the frequency adjustment signal being in the frequency adjustment state.

[0026] Example 19. A power system including a resonant charge pump circuit, the resonant charge pump circuit comprising: a resonant circuit having a barrel capacitor and a barrel inductor connected in series; a first transistor configured to be off and on, the first transistor being connected to allow current to flow from an input terminal into the resonant circuit to charge the barrel capacitor and the barrel inductor when the first transistor is on, and to prevent current from flowing from the input terminal into the resonant circuit to charge the barrel capacitor and the barrel inductor when the first transistor is off; a second transistor configured to be off and on, the second transistor being configured to... When the first transistor is turned on, current can flow from the resonant circuit to discharge the barrel capacitor and barrel inductor to the output terminal, and when the second transistor is turned off, current cannot flow from the resonant circuit to discharge the barrel capacitor and barrel inductor to the output terminal; and a synchronization circuit configured to generate a clock signal such that the opening and closing of the first transistor and the second transistor are synchronized according to the clock signal, wherein the synchronization circuit is configured to detect the activation of the first body diode of the first transistor and the activation of the second body diode of the second transistor, and adjust the frequency of the clock signal in response to the activation of the first body diode or the activation of the second body diode.

[0027] Example 20. The power system according to Example 19, wherein the synchronization circuit is configured to: increase the frequency of the clock signal in response to the detection of activation of the first body diode; and decrease the frequency of the clock signal in response to the detection of activation of the second body diode.

[0028] Example 21. The power system according to Example 19, wherein the synchronization circuit is configured to: decrease the frequency of the clock signal in response to the detection of activation of the first body diode; and increase the frequency of the clock signal in response to the detection of activation of the second body diode.

[0029] Further details and embodiments are described in the following detailed description. This invention is not intended to be limited in scope. The invention is defined by the claims. Attached Figure Description

[0030] The accompanying drawings illustrate embodiments of the invention, with the same reference numerals indicating the same components.

[0031] Figure 1A An embodiment of a charge pump circuit is shown.

[0032] Figure 1B An embodiment of a charge pump circuit is shown.

[0033] Figure 2A The diagram shows the flow. Figure 1A The diagram shows the current in the charge pump circuit.

[0034] Figure 2B Demonstrates the ability to reduce surge current Figure 1A An alternative embodiment of the charge pump circuit shown.

[0035] Figure 2C This demonstrates the effect of adding a resistor. Figure 1A The diagram shows the operation of the charge pump circuit.

[0036] Figure 3A An embodiment of a resonant charge pump circuit is shown.

[0037] Figure 3B An embodiment of a resonant charge pump circuit is shown.

[0038] Figure 4 Demonstrated simulation Figure 3A An embodiment of the operation of the resonant charge pump circuit shown.

[0039] Figure 5 Showing the comparison with Figure 4 The diagram shows the voltage and current waveforms associated with the synchronous operation of the resonant charge pump circuit.

[0040] Figure 6 Showing the comparison with Figure 4 The diagram shows the voltage and current waveforms associated with asynchronous operation of the resonant charge pump circuit.

[0041] Figure 7 An embodiment of a resonant charge pump circuit including a synchronization circuit is shown.

[0042] Figure 8 An embodiment of a synchronous resonant charge pump circuit is shown.

[0043] Figure 9 Showing the comparison with Figure 8 The diagram shows the voltage and current waveforms associated with the resonant charge pump circuit.

[0044] Figure 10 Demonstrated simulation Figure 3A Another embodiment of the operation of the resonant charge pump circuit shown.

[0045] Figure 11 An example of intermediate node voltage is shown.

[0046] Figure 12 The synchronization circuit was demonstrated. Detailed Implementation

[0047] Reference will now be made in detail to some exemplary embodiments of the present invention, examples of which are shown in the accompanying drawings.

[0048] Figure 1A An embodiment of a charge pump circuit 100 is shown. The charge pump circuit 100 charges a low voltage (V) LOW ) converted to a higher voltage (V HIGH ), where V HIGH =V LOW x 2. The buffer (BUF1) receives a clock signal that causes the buffer output to V. LOW It switches between the first level at ground and the second level at ground. When the BUF1 output is at ground, the barrel current i BKT Flow to the barrel capacitor (C BKT In ) and C BKT Charge to V LOW The level. When the output of BUF1 switches to V LOW At that time, C BKT The voltage is added to the output of BUF1, making the voltage level at the output of diode D2 equal to (2 x V). LOW Therefore, the charge pump circuit 100 acts as a voltage multiplier.

[0049] Figure 1B An embodiment of a charge pump circuit 102 is shown. The charge pump circuit 102 will charge V... HIGH Convert to V LOW V LOW =V HIGH / 2. Charge pump circuit 102 is connected with Figure 1A The charge pump circuit 100 shown is implemented in a similar manner, but operates to transfer voltage Vt. HIGH Reduce to output voltage V LOW Therefore, charge pump circuit 102 acts as a voltage divider or step charge pump. The two charge pump circuits 100 and 102 are symmetrical and have similar drawbacks when used in high-power applications. For example, when BUF1 switches states, both charge pump circuits 100 and 102 experience large inrush currents. These large inrush currents can damage circuit components. This problem is explained in more detail below.

[0050] Figure 2A The diagram shows the flow. Figure 1A Figure 200 shows the current of the charge pump circuit 100. Figure 200 illustrates the clock signal and the barrel current i. BKT As can be seen from Figure 200, when the clock signal switches states, the barrel current i BKTLarge current spikes are experienced. These current spikes have very large amplitudes (I0) and occur within a very short duration (T0). In high-power applications, these current spikes can become extremely large. If the charge pump circuit 100 is used in high-power applications, additional circuitry will be required to prevent large inrush currents that could otherwise damage circuit components (fuse or apply high stress to the device), potentially shortening product life. Therefore, a way to control or reduce inrush current spikes is desirable.

[0051] Figure 2B Demonstrates the ability to reduce surge current Figure 1A An alternative embodiment of the charge pump circuit 100 is shown. For example, a resistor is added to the charge pump circuit 100 to control or reduce inrush current spikes. For example, circuit 202 shows how a resistor R0 is added to the output of BUF1. Resistor R0 reduces the inrush current because the inrush current passing through resistor R0 generates a reduced surge current across C. BKT The voltage drop is due to the voltage. However, the use of resistor R0 also reduces the conversion efficiency.

[0052] Figure 2C This demonstrates the effect of adding resistor R0. Figure 1A Figure 204 shows the operation of circuit 100. Figure 204 illustrates the clock signal and the barrel current i. BKT As can be seen from Figure 204, when the clock signal switches states, the barrel current i BKT Experiencing reduced current spikes. For example, current spikes have amplitudes (I1) smaller than I0 and are less likely to damage circuit components. These smaller spikes occur when there are resistors R0 and C... BKT The current spikes occur within the duration (T1) of the time constant, which is longer than T0. Therefore, with the addition of resistor R0, it is possible to use the charge pump circuit 100 in high-voltage applications. However, it should be noted that resistor R0 also reduces the conversion efficiency of the charge pump circuit 100. Therefore, it is desirable to have a way to control or reduce current spikes without affecting the efficiency of the charge pump circuit 100.

[0053] Resonant charge pump circuit

[0054] Figure 3A An embodiment of a resonant charge pump circuit 300 is illustrated. The resonant charge pump circuit 300 will V LOW Convert to V HIGH V HIGH =V LOW x 2. The resonant charge pump circuit 300 is similar to Figure 1A The charge pump circuit 100 shown is simply an inductor (or coil) L BKT 302 has been added to the output of BUF1. Inductor LBKT 302 and C BKT These components are combined to form a resonant circuit that operates to control or reduce current spikes. In an exemplary embodiment, the LC resonant circuit generates a sinusoidal current flow, thus mitigating inrush current problems. Because the resonant circuit has no resistance or power loss, it is suitable for controlling or reducing current spikes in charge pump circuits, even in high-power applications.

[0055] Figure 3B An embodiment of the resonant charge pump circuit 304 is illustrated. The resonant charge pump circuit 304 will V HIGH Convert to V LOW V LOW =V HIGH / 2. The resonant charge pump circuit 304 is similar to... Figure 1B The charge pump circuit 102 shown is simply an inductor (or coil) L BKT 306 has been added at the output of the buffer (BUF2). It should be noted that although inductor L... BKT 306 is located in C BKT On the opposite side, however, the effect of the resonant circuit is the same as that in the resonant charge pump circuit 300.

[0056] Figure 4 Demonstrated simulation Figure 3A The illustrated resonant charge pump circuit 300 is an embodiment of the resonant charge pump circuit 400. Considering the target of high-power applications, the resonant charge pump circuit 400 includes transistors SW3 and SW4 replacing diodes D1 and D2. The resonant charge pump circuit 400 also includes a switching circuit 410, which includes a buffer 416; transistor switches SW1 and SW2; and resistors R1 and R2. The resonant charge pump circuit 400 also includes an output load capacitor CL and a resistor RL.

[0057] Transistors SW3 and SW4 are synchronized with the control clock signal 412. The resonant charge pump circuit 400 also includes a barrel capacitor (C). BKT )406 and barrel inductors (L BKT 408, which form an LC resonant circuit 414, maintain its self-oscillation (ideally, permanent oscillation) over a long period until parasitic resistance converts the resonant energy into heat. Switching circuit 410 acts as BUF1 to receive control clock signal 412 and generates a switch in response to control clock signal 412 at V... LOW Output (SW) that switches between states with and from ground.

[0058] The LC resonant circuit 414 delivers energy to and from node VM. To maintain the direction of energy delivery, the switching timing needs to be synchronized with the LC resonant frequency. Therefore, the resonant charge pump circuit 400 receives a low input voltage (VIN) (e.g., 12 volts) and generates a high output voltage (VOUT) that is approximately twice VIN (2 x VIN). Synchronous and asynchronous operation of the resonant charge pump circuit 400 are respectively... Figure 5 and 6 It is displayed in the middle.

[0059] Figure 5 Showing the comparison with Figure 4 The diagram 500 shows the voltage and current waveforms associated with the synchronous operation of the resonant charge pump circuit 400. For example, diagram 500 includes a representation of the barrel current i. BKT Graph 502 shows the input current (iin), and graph 504 shows the cross-barrel capacitor C. BKT Graph 506 shows the voltage of 406, and graph 508 shows VOUT. As shown in graph 502, the resonant circuit (barrel capacitor C) BKT 406. Barrel-type inductor L BKT 408) Bucket current i has been eliminated BKT The large current spikes on the surface. For example, graph 502 shows the barrel current i BKT A perfect sine wave example. Therefore, when BUF1 (the switching circuit) switches between the first and second states, the resonant circuit suppresses current spikes. It should also be noted that graph 508 shows the output voltage (e.g., 24 volts) remaining constant at (2 x V). LOW These results demonstrate that the synchronous resonant circuit reduces or eliminates large inrush currents, thus allowing the resonant charge pump circuit 400 to be used in high-power applications.

[0060] Figure 6 Showing the comparison with Figure 4 The diagram 600 shows the voltage and current waveforms associated with the asynchronous operation of the resonant charge pump circuit 400. For example, diagram 600 includes a representation of the barrel current i. BKT Graph 602 shows the curve of iin; Graph 604 shows the cross-barrel capacitor C. BKT The voltage curve 606 shows the voltage of 406, and the curve 608 shows VOUT. As can be seen from curve 608, due to the asynchronous energy delivery of the LC circuit, the output "dashed line" 610 is below 20V (instead of 24V). Therefore, a way to maintain synchronization of the resonant charge pump circuit 400 for proper operation is desired, such as... Figure 5 As shown.

[0061] Resonant charge pump synchronization

[0062] Figure 7 An embodiment of a resonant charge pump circuit 700, including a synchronization circuit 714, is illustrated. In one embodiment, a current sensor 712 senses the current at the output of BUF1. The sensed current is input to a zero-current detector 702, which detects a zero-current event at the output of BUF1. A detection pulse associated with the detected zero-current event is input to an "OR" device 706, which also receives a clock signal from an alternating clock generator 704 (discussed in more detail below). During normal operation, the detection pulse output from the zero-current detector 702 flows through the OR device 706 and is input to an inverting flip-flop (FF) 708. The output of the inverting FF 708 is used to generate complementary synchronization clock signals S1 and S2 for the transistor switches SW1, SW2 and transistors SW3, SW4 that drive the resonant charge pump circuit 700. In another operating mode, if the zero-current detector 702 fails to detect a zero-current event, the alternating clock generator 704 generates an alternating clock 716, which reaches the input of the inverting FF 708 via the OR device 706. Therefore, in the absence of a detected zero-current event due to the low current flowing through the LC circuit, the alternating clock generator 704 generates a clock signal used by the resonant charge pump circuit 700. In one embodiment, the synchronization circuit 714 is implemented on an integrated circuit.

[0063] During operation of the resonant charge pump circuit 700, the direction of energy delivery is maintained by detecting the zero-current flow timing of the LC resonant circuit 718. In one embodiment, when a zero-current event is detected in the LC resonant circuit 718, the complementary synchronization clock signals S1 and S2 change state from high to low or from low to high. Appropriately changing the state of the complementary synchronization clock signals S1 and S2 causes the current to flow in one direction.

[0064] Alternating clock generator

[0065] When the load on the resonant charge pump circuit 700 becomes very small, the zero-current detector 702 may become difficult to detect "zero-current" events because the current delivered by the LC resonant circuit 718 may drop below the detection threshold. In this case, the alternating clock generator 704 operates to maintain circuit pumping. In one embodiment, a simple logic timing circuit can be used to generate the alternating clock 716. When the zero-current detector 702 does not output a detection pulse, the alternating clock generator 704 starts its timer and maintains the periodic toggling of the complementary synchronous clock signals S1 / S2. In this case, the load current is very small, and whether the alternating clock timing is synchronized or asynchronous has little effect. Preferably, this alternating clock period is set to be approximately equal to or slightly longer than the LC resonant design target.

[0066] In various embodiments, the "zero current sensing" circuit may have a certain limitation on its detection range. This depends on the step-down or step-up pumping operation, and is determined from the output side (V). LOW or V HIGH (any one of them) light to zero load current case.

[0067] Under light load conditions, since the current flow between the input and output sides is negligible, it is not necessary to maintain accurate LC resonant frequency timing on the complementary synchronous control clock signals S1 and S2. It is desirable to provide approximate timing on the complementary synchronous clock signals S1 and S2 to maintain the output voltage. Therefore, when the zero-current sensing circuit is not operating (sensing), the alternating clock generator 704 maintains the timing of the complementary synchronous clock signals S1 and S2.

[0068] Figure 8 An embodiment with a synchronized resonant charge pump circuit 800 is shown. In one embodiment, the resonant charge pump circuit 800 is Figure 7 An embodiment of the resonant charge pump circuit 700 is shown. The resonant charge pump circuit 800 includes... Figure 7 The zero-current detector 702, alternating clock generator 704, and inverting FF 708 are used. The operation of the resonant charge pump circuit 800 results in... Figure 9 As shown. In one embodiment, the zero-current detector 702, alternating clock generator 704, and inverting FF 708 are implemented on an integrated circuit.

[0069] As discussed above, if a very small current enters the LC circuit, the zero-current detector 702 may not be able to properly detect a zero-current event. In one embodiment, two diodes 802 and 804 are inserted across transistors SW3 and SW4, which act as... Figure 1A and Figure 4 The diodes D1 and D2 are shown. In one embodiment, it may be preferred that when Figure 7 When the alternating clock 716 positively drives the complementary synchronization clock signals S1 and S2, transistors SW3 and SW4 are deactivated. Diodes 802 and 804 maintain the output voltage during this period. Since this is a light load condition, there is no need to worry about power loss. Diodes 802 and 804 can suppress unwanted LC resonant ringing during light load conditions. In one embodiment, diodes 802 and 804 are body diodes, which are part of the field-effect transistors (FETs) used as transistors SW3 and SW4.

[0070] like Figure 8As shown, the zero-current detector 702 includes a sensing resistor Rs, a comparator 806, a rising-edge triggered singleton 808, a negative-edge triggered singleton 810, and an OR gate 812. During operation, a zero-current event is detected as a change in voltage input to the sensing resistor Rs of the comparator 806. The comparator 806 responds by outputting a rising-edge or falling-edge signal that triggers one of the singletons 808 or 810 to output a pulse to the OR gate 812. The OR gate 812 passes this pulse as a trigger pulse 822 to the alternating clock generator 704.

[0071] like Figure 8 As shown, the alternating clock generator 704 includes a timer circuit 816, a single-transmitter circuit 818, and an OR gate 814. The timing period 826 of the timer circuit 816 is set to be longer than the expected LC resonant frequency (including the coil and capacitor tolerances). Whenever the zero-current detector 702 outputs a trigger pulse 822 when the current direction changes (e.g., zero-current sensing), the timer circuit 816 is reset, and the timing of the complementary synchronization clock signals S1 and S2 remains under the control of the zero-current detector 702.

[0072] When under light load conditions, the zero-current detector 702 fails to detect a zero-current event and stops sending trigger pulse 822. At this time, the timer circuit 816 is allowed to complete its timing cycle (timer expires) and trigger pulse 822 is initiated from the single-transmitter circuit 818. The output of the single-transmitter circuit 818 forms an alternating clock 716, which flows through the OR gate 814 to invert FF 820 and the complementary synchronization clock signals S1, S2, thereby maintaining the charge pump output. The pulse output of the OR gate 814 also restarts the timer circuit 816, causing the complementary synchronization clock signals S1, S2 to repeat cyclically. Since the timing period 826 provided by the timer circuit 816 is set to be longer than the main LC resonant timing, once the resonant charge pump circuit 800 exits the light load condition, the zero-current detector 702 takes over control of the timing of the complementary synchronization clock signals S1, S2.

[0073] Figure 9 Showing the comparison with Figure 8 The diagram 900 shows the voltage and current waveforms associated with the resonant charge pump circuit 800. For example, diagram 900 includes... Figure 7 The graph 902 showing the alternating clock 716 illustrates the barrel current i. BKT Graph 904 shows the curve of iin; Graph 906 shows the curve across C. BKT The voltage curve 908 and the VOUT curve 910 showing the resonant charge pump circuit 800 are shown.

[0074] As shown in graph 902, when the load current is small (e.g., as indicated by the input current shown in graph 906), the alternating clock 716 provides a clock pulse signal. When the load current increases and a zero-current event begins to occur (shown at time indicator 912), the zero-current detector 702 and the LC resonant circuit 718 take over to generate a synchronous clock signal. This can be seen from the clean sine wave following time indicator 912, which is generated by the zero-current event detected by the zero-current detector 702. It should be noted that regardless of whether the synchronous clock generated by the zero-current detector 702 or multiple clocks from the alternating clock 716 generated by the alternating clock generator 704 are used, the resonant charge pump circuit 800 continues to output a stable 24-volt output, as shown in graph 910.

[0075] Low EMI circuit operation

[0076] In various embodiments, the resonant charge pump circuit operates with very low noise. For example, during low load current conditions, the resonant charge pump is asynchronous and operates based on an alternating clock. Because the energy flowing is so low, the circuit emits low EMI. During synchronous operation of the resonant charge pump circuit, the circuit operates using zero-current switching (ZCS). This operating mode is known to provide very good noise performance because the high-power transistor is switching when no current is flowing. Typically, EMI noise power comes from sudden changes in current flow, but the resonant charge pump circuit utilizes ZCS, which results in low EMI.

[0077] Resonant charge pump with alternative synchronization circuit

[0078] Figure 10 Demonstrated simulation Figure 3A Another embodiment of the operation of the resonant charge pump circuit 1000 shown in the diagram is the operation of the resonant charge pump circuit 300.

[0079] Resonant charge pump circuit 1000 and Figure 4 The resonant charge pump circuit 400 shown is the same, except that transistor switch SW1 is specifically a FET with a body diode, transistor switch SW2 is specifically a FET with a body diode, transistor SW3 is specifically a FET with a body diode, and transistor SW4 is specifically a FET with a body diode. Furthermore, with... Figure 4 Unlike the resonant charge pump circuit 400 shown, the resonant charge pump circuit 1000 includes another embodiment of the synchronization circuit 1002. It should be noted that other embodiments of the resonant charge pump circuit 1000 may include multiple pairs of transistor switches SW1, SW2 and multiple pairs of transistors SW3, SW4 arranged in parallel connected to the output terminals, such that the output voltage can be charged to a higher voltage via VIN.

[0080] exist Figure 10 In this circuit, the resonant charge pump circuit 1000 is included in the power circuit 1004. The resonant charge pump circuit 1000 is compared to... Figure 4 The improvement to the resonant charge pump circuit 400 shown is that... Figure 8 The sensing resistor Rs in the zero-current detector 702 is not used, resulting in less resistance and providing higher conversion efficiency. In some embodiments, transistor switches SW1, SW2 and transistors SW3, SW4 may each be complementary metal-oxide-semiconductor (CMOS) or bipolar CMOS (BiCMOS) silicon transistors, or transistor switches SW1, SW2 and transistors SW3, SW4 may each be gallium nitride (GaN) or silicon carbide (SiC) transistors. Transistor switch SW2 is configured to be off (i.e., in a non-conducting state, open) and on (i.e., in a conducting state, closed). As explained above, transistor switch SW2 is connected to allow current to flow from the input terminal to the LC resonant circuit 414 to the barrel capacitor C when transistor switch SW2 is on. BKT 406 and barrel inductor L BKT 408 is charged, and when transistor switch SW2 is turned off, current cannot flow from the input terminal to the LC resonant circuit 414. Transistor switch SW1 is configured to be turned off and on. Transistor switch SW1 is configured to allow current to flow from the LC resonant circuit 414 when transistor switch SW1 is turned on to charge the barrel capacitor C. BKT 406 and barrel inductor L BKT 408 discharges to the output terminal and prevents current from flowing from the LC resonant circuit 414 to the output terminal when transistor switch SW1 is off. Transistor switches SW1 and SW2 are located inside the switching circuit 410. Transistor SW3 is also connected to allow current to flow from the input terminal to the LC resonant circuit 414 to the barrel capacitor C when transistor SW3 is on. BKT 406 and barrel inductor L BKT 408 is charged, and when transistor SW3 is turned off, current cannot flow from the input terminal to the LC resonant circuit 414. Transistor SW4 is configured to be turned off and on. Transistor SW4 is configured to allow current to flow from the LC resonant circuit 414 when transistor SW4 is on to charge the barrel capacitor C. BKT 406 and barrel inductor L BKT 408 discharges to the output terminal and prevents current from flowing from the LC resonant circuit 414 to the output terminal when transistor SW4 is turned off. Transistors SW3 and SW4 are located outside the switching circuit 410.

[0081] In this example, transistor switch SW1 is connected between the input terminal and intermediate node 1006. Intermediate node 1006 is connected to SW. Transistor switch SW2 is connected between intermediate node 1006 and ground. Transistor SW3 is connected between the input terminal and intermediate node 1008. Intermediate node 1008 is directly connected to node VM. Transistor SW4 is connected between intermediate node 1008 and the output terminal.

[0082] Synchronization circuit 1002 is configured to generate a control clock signal 412, such that the turning off and turning on of transistor switches SW1, SW2 and transistors SW3, SW4 are synchronized according to the control clock signal 412, as explained above. Synchronization circuit 1002 utilizes the fact that when the clock frequency is synchronized with the barrel current i BKT When the frequencies are out of sync, the body diodes of transistor switches SW1 and SW3, or transistor switches SW2 and SW4, will be switched on. Whether the body diodes of transistor switches SW1 and SW3, or transistor switches SW2 and SW4, are switched on depends on the clock frequency and the barrel current i. BKT The frequency is either too fast or too slow compared to the operating frequency. This depends on which phase of the control clock signal 412 (i.e., CLK, XCLK) is activated; it can be any situation. For example, if the clock frequency is not synchronized with the frequencies of transistor switches SW1 and SW3, and transistor switches SW2 and SW4, then the lack of synchronization will cause issues with the barrel current i. BKT Deformation occurs in the middle, therefore the barrel current i BKT It is not a clean sine wave.

[0083] In some embodiments, the synchronization circuit 1002 is configured to detect the activation of the body diodes of transistor switch SW1 and transistor switch SW2, and adjust the frequency of the control clock signal 412 in response to the activation of either the body diode of transistor switch SW1 or the body diode of transistor switch SW2. In some embodiments, the synchronization circuit 1002 is configured to increase the clock frequency of the control clock signal 412 in response to the detection of activation of the body diode of transistor switch SW1, and decrease the clock frequency of the control clock signal 412 in response to the detection of activation of the body diode of transistor switch SW2. In other embodiments, the synchronization circuit 1002 is configured to decrease the clock frequency of the control clock signal 412 in response to the detection of activation of the body diode of transistor switch SW1, and increase the clock frequency of the control clock signal 412 in response to the detection of activation of the body diode of transistor switch SW2. Similarly, whether the detection of activation of the body diode of transistor switch SW1 or the body diode of transistor switch SW2 causes the synchronization circuit 1002 to increase or decrease the clock frequency depends on the relationship between which phase (CLK, XCLK) turns transistor switches SW1 and SW2 on and off. Synchronization circuit 1002 is configured to adjust the clock frequency in such a way that the clock frequency and the barrel current i BKT The frequency is synchronized, so the body diode is not turned on during oscillation. In some embodiments, the synchronization circuit 1002 can detect whether the body diode of transistor switch SW1 or transistor switch SW2 is turned on by detecting the voltage at intermediate node 1006, as explained below.

[0084] In some embodiments, the synchronization circuit 1002 is configured to detect the activation of the body diode of transistor SW3 and the body diode of transistor SW4, and adjust the frequency of the control clock signal 412 in response to the activation of either the body diode of transistor SW3 or the body diode of transistor SW4. In some embodiments, the synchronization circuit 1002 is configured to increase the clock frequency of the control clock signal 412 in response to the detection of the activation of the body diode of transistor SW3, and decrease the clock frequency of the control clock signal 412 in response to the detection of the activation of the body diode of transistor SW4. In other embodiments, the synchronization circuit 1002 is configured to decrease the clock frequency of the control clock signal 412 in response to the detection of the activation of the body diode of transistor SW3, and increase the clock frequency of the control clock signal 412 in response to the detection of the activation of the body diode of transistor SW4. Similarly, whether the activation of the body diode of transistor SW3 or the body diode of transistor SW4 causes the synchronization circuit 1002 to increase or decrease the clock frequency depends on which phase (CLK, XCLK) turns transistors SW3 and SW4 on and off. Synchronization circuit 1002 is configured to adjust the clock frequency in such a way that the clock frequency and the barrel current i BKT The frequency is synchronized, so the body diode is not turned on during oscillation. In some embodiments, the synchronization circuit 1002 can detect whether the body diode of transistor SW3 or transistor SW4 is turned on by detecting the voltage at intermediate node 1008, as explained below.

[0085] It should be noted that other embodiments of the synchronization circuit 1002 may detect whether the body diode of transistor switch SW2 or the body diode of transistor SW3 is turned on to adjust the clock frequency. Other embodiments of the synchronization circuit 1002 may detect whether the body diode of transistor switch SW1 or the body diode of transistor SW4 is turned on to adjust the clock frequency.

[0086] Figure 11 An example of an intermediate node voltage of 1100 is shown.

[0087] In some embodiments, the intermediate node voltage 1100 may be Figure 10The voltage at intermediate node 1006. When the intermediate node voltage 1100 can be the voltage at intermediate node 1006, the synchronization circuit 1002 is configured to detect whether the body diode of transistor switch SW1 or transistor switch SW2 is activated when both transistor switches SW1 and SW2 are off. In response to detecting that the body diode of transistor switch SW1 or transistor switch SW2 is activated when both transistor switches SW1 and SW2 are off, the synchronization circuit 1002 is configured to adjust the clock frequency of the control clock signal 412. In some embodiments, the clock frequency is increased in response to detecting that the body diode of transistor switch SW1 has been activated when both transistor switches SW1 and SW2 are off, and the clock frequency is decreased in response to detecting that the body diode of transistor switch SW2 has been activated when both transistor switches SW1 and SW2 are off. In other embodiments, the clock frequency is reduced in response to detecting that the body diode of transistor switch SW1 has been activated when both transistor switches SW1 and SW2 are turned off, and the clock frequency is increased in response to detecting that the body diode of transistor switch SW2 has been activated when both transistor switches SW1 and SW2 are turned off.

[0088] In some embodiments, the intermediate node voltage 1100 may be Figure 10 The voltage at intermediate node 1008. When the intermediate node voltage 1100 can be the voltage at intermediate node 1008, the synchronization circuit 1002 is configured to detect whether the body diode of transistor SW3 or transistor SW4 is activated when both transistors SW3 and SW4 are off. In response to detecting that the body diode of transistor SW3 or transistor SW4 is activated when both transistors SW3 and SW4 are off, the synchronization circuit 1002 is configured to adjust the clock frequency of the control clock signal 412. In some embodiments, the clock frequency is increased in response to detecting that the body diode of transistor SW3 has been activated when both transistors SW3 and SW4 are off, and the clock frequency is decreased in response to detecting that the body diode of transistor SW4 has been activated when both transistors SW3 and SW4 are off. In other embodiments, the clock frequency is reduced in response to detecting that the body diode of transistor SW3 has been activated when both transistors SW3 and SW4 are turned off, and the clock frequency is increased in response to detecting that the body diode of transistor SW4 has been activated when both transistors SW3 and SW4 are turned off.

[0089] In this example, it is assumed that VIN is at a 4-volt DC voltage level. Additionally, it is assumed that ground is at a 0-volt DC voltage level. In one example, if the clock frequency of the control clock signal 412 is related to the barrel current i... BKT If the frequencies are out of sync, the intermediate node voltage 1100 will increase above VIN. This is indicated by the hump 1102 in the intermediate node voltage 1100. If the synchronization circuit 1002 is configured to detect the intermediate node voltage 1100 as the voltage at intermediate node 1006, then once the intermediate node voltage 1100 exceeds the threshold voltage 1103, the synchronization circuit 1002 detects that the body diode of transistor switch SW1 is activated. The threshold voltage 1103 has a DC threshold voltage level higher than VIN. In this embodiment, the DC threshold voltage level is 4.1 volts. In response to the intermediate node voltage 1100 exceeding the threshold voltage, the synchronization circuit 1002 responds by adjusting the clock frequency. In some embodiments, the clock frequency is increased. In some embodiments, the clock frequency is decreased.

[0090] On the other hand, if the synchronization circuit 1002 is configured to detect the intermediate node voltage 1100 as the voltage at the intermediate node 1008, then once the intermediate node voltage 1100 is higher than the threshold voltage 1103, the synchronization circuit 1002 detects that the body diode of transistor SW3 is activated. In response to the intermediate node voltage 1100 being higher than the threshold voltage, the synchronization circuit 1002 responds by adjusting the clock frequency. In some embodiments, the clock frequency is increased. In some embodiments, the clock frequency is decreased.

[0091] In another example, if the clock frequency of the control clock signal 412 is related to the barrel current i BKT If the frequencies are out of sync, the intermediate node voltage will decrease below ground. This is indicated by the hump 1104 in the intermediate node voltage 1100. If the synchronization circuit 1002 is configured to detect the intermediate node voltage 1100 as the voltage at intermediate node 1006, then once the intermediate node voltage 1100 falls below the threshold voltage 1106, the synchronization circuit 1002 detects that the body diode of transistor switch SW2 is activated. The threshold voltage 1106 has a DC threshold voltage level below ground. In this embodiment, the DC threshold voltage level is -0.1 volts. In response to the intermediate node voltage 1100 falling below the threshold voltage, the synchronization circuit 1002 responds by adjusting the clock frequency. In some embodiments, the clock frequency is increased. In some embodiments, the clock frequency is decreased.

[0092] On the other hand, if the synchronization circuit 1002 is configured to detect the intermediate node voltage 1100 as the voltage at the intermediate node 1008, then once the intermediate node voltage 1100 falls below the threshold voltage 1106, the synchronization circuit 1002 detects that the body diode of transistor SW4 is activated. In response to the intermediate node voltage 1100 falling below the threshold voltage, the synchronization circuit 1002 responds by adjusting the clock frequency. In some embodiments, the clock frequency is increased. In some embodiments, the clock frequency is decreased.

[0093] Detecting the activation of the body diodes of transistor switches SW1, SW2 and transistors SW3, SW4 simplifies the relationship between clock frequency and barrel current i. BKT The frequency is synchronized. This increases the conversion efficiency of the resonant charge pump circuit 1000.

[0094] Figure 12 Showcase the 1200 synchronous circuit.

[0095] In some embodiments, Figure 10 The synchronization circuit 1002 shown is used in conjunction with Figure 12 The synchronization circuit 1200 shown is configured in the same manner. The synchronization circuit 1200 includes a first detection circuit 1202 and a second detection circuit 1204. The first detection circuit 1202 is configured to detect whether the intermediate node voltage IV is lower than a threshold voltage TH1. In some embodiments, the intermediate node voltage IV is... Figure 10 The voltage at intermediate node 1006. In other embodiments, the intermediate node voltage IV is... Figure 10 The voltage at intermediate node 1008. The threshold voltage TH1 has a DC threshold voltage level that is lower than the DC voltage level of ground. Therefore, the threshold voltage TH1 is related to... Figure 11 The threshold voltage 1106 corresponds to this.

[0096] The first detection circuit 1202 includes a comparator 1206, an AND gate 1208, and a single-transmitter 1210. In this example, the non-inverting terminal of the comparator 1206 is configured to receive a threshold voltage TH1, and the inverting terminal of the comparator 1206 is configured to receive an intermediate voltage IV. Therefore, in response to the intermediate voltage IV being higher than the threshold voltage TH1, the output CO1 of the comparator 1206 is low. In response to the intermediate voltage IV being lower than the threshold voltage TH1, the output CO1 of the comparator 1206 is high. Note that the threshold voltage TH1 is a negative voltage because the threshold voltage TH1 is received at the non-inverting terminal, while the intermediate voltage IV is received at the inverting terminal.

[0097] AND gate 1208 is configured to receive output CO1 and a stagnation control signal tdead. The stagnation control signal tdead is low when either transistor switch SW1 or SW2 is turned on. Conversely, the stagnation control signal tdead is high when either transistor switch SW1 or SW2, or transistors SW3 or SW4, is turned on. Therefore, when output CO1 is high and when the stagnation control signal tdead is high, the corresponding transistor (i.e., ...) Figure 10 The body diode of transistor switch SW2 or transistor SW4 in the circuit has been activated, which means that the clock frequency is related to the barrel current i. BKT Frequency asynchrony (see) Figure 10 When the output CO1 is low or the stagnation control signal tdead is low, the output AD1 of the AND gate 1208 is low. However, when the output CO1 is high and the stagnation control signal tdead is high, the output AD1 of the AND gate 1208 is high.

[0098] When output AD1 is low, the single-transmitter 1210 does not generate output fUP. However, when output AD1 is high, the single-transmitter 1210 generates output fUP. In response to output fUP, the clock frequency of the control clock signal 412 (see...) Figure 10 The clock frequency of the control clock signal 412 decreases in response to the output AD1 being high.

[0099] The second detection circuit 1204 is configured to detect whether the intermediate node voltage IV is higher than the threshold voltage TH2. In some embodiments, the intermediate node voltage IV is Figure 10 The voltage at intermediate node 1006. In other embodiments, the intermediate node voltage IV is... Figure 10 The voltage at intermediate node 1008. The threshold voltage TH1 has a DC threshold voltage level higher than the DC voltage level of VIN. Therefore, the threshold voltage TH1 is related to... Figure 11 The threshold voltage 1103 corresponds to this.

[0100] The second detection circuit 1204 includes a comparator 1212, an AND gate 1214, and a single-transmitter 1216. In this example, the non-inverting terminal of comparator 1206 is configured to receive an intermediate voltage IV, and the inverting terminal of comparator 1206 is configured to receive a threshold voltage TH2. Therefore, in response to the intermediate voltage IV being lower than the threshold voltage TH2, the output CO2 of comparator 1206 is low. In response to the intermediate voltage IV being higher than the threshold voltage TH2, the output CO1 of comparator 1206 is high. Therefore, in response to the intermediate voltage IV being higher than the threshold voltage TH2, the output CO2 is high. Note that since the intermediate voltage IV is received at the non-inverting terminal and the threshold voltage TH2 is received at the inverting terminal, the threshold voltage TH2 is positive.

[0101] AND gate 1214 is configured to receive the output CO2 and the stagnation control signal tdead. Therefore, when the output CO2 is high and the stagnation control signal tdead is high, this means that the body diode of the corresponding transistor (i.e., transistor switch SW1 or transistor SW3) has been activated, which in turn means that the clock frequency and the barrel current i... BKT Frequency asynchrony (see) Figure 10 When the output CO2 is low or the stagnation control signal tdead is low, the output AD2 of the AND gate 1208 is low. However, when the output CO2 is high and the stagnation control signal tdead is high, the output AD2 of the AND gate 1208 is high.

[0102] In response to output AD2 being low, the single-transmitter 1216 does not generate output fDOWN. However, in response to output AD2 being high, the single-transmitter 1216 generates output fDOWN. In response to output fDOWN, the clock frequency of control clock signal 412 (see...) Figure 10 The clock frequency of the control clock signal 412 increases in response to the output AD2 being high.

[0103] Although certain specific embodiments have been described above for guiding purposes, the teachings of this patent document are generally applicable and not limited to the specific embodiments described above. The functionality of the hardware circuitry system shown in the figures can be implemented in the hardware circuitry system shown, or in a combination of dedicated hardware circuitry systems and software, or primarily in software. Therefore, various modifications, adaptations, and combinations of the features of the described embodiments can be practiced without departing from the scope of the invention as set forth in the claims.

Claims

1. A resonant charge pump circuit, comprising: A resonant circuit having a barrel capacitor and a barrel inductor connected in series; A first transistor is configured to be off and on, and is connected such that when the first transistor is on, current can flow from the input terminal to the resonant circuit to charge the barrel capacitor and the barrel inductor, and when the first transistor is off, current cannot flow from the input terminal to the resonant circuit. The second transistor is configured to be turned off and on, wherein when the second transistor is turned on, it allows current to flow from the resonant circuit to discharge the barrel capacitor and the barrel inductor to the output terminal, and when the second transistor is turned off, it prevents current from flowing from the resonant circuit to the output terminal. as well as A synchronization circuit is configured to generate a clock signal such that the switching off and on of the first transistor and the second transistor are synchronized according to the clock signal, wherein the synchronization circuit is configured to detect the activation of a first body diode of the first transistor and the activation of a second body diode of the second transistor, and adjust the frequency of the clock signal in response to the activation of the first body diode or the activation of the second body diode.

2. The resonant charge pump circuit according to claim 1, wherein: The first transistor is a first field-effect transistor (FET); and The second transistor is a second FET.

3. The resonant charge pump circuit according to claim 1, wherein the synchronization circuit is configured to: The frequency of the clock signal is increased in response to the detection of activation of the first body diode; and The frequency of the clock signal is reduced in response to the detection of activation of the second body diode.

4. The resonant charge pump circuit of claim 1, wherein the synchronization circuit is configured to: The frequency of the clock signal is reduced in response to the detection of activation of the first body diode; and The frequency of the clock signal is increased in response to the detection of activation of the second body diode.

5. The resonant charge pump circuit of claim 1, wherein the synchronization circuit is configured to operate the first transistor and the second transistor on and off according to the clock signal, such that: In the first state, the first transistor is turned on and the second transistor is turned off; In the second state, the second transistor is turned on and the first transistor is turned off; and In the third state, both the first transistor and the second transistor are turned off.

6. The resonant charge pump circuit of claim 5, wherein the synchronization circuit is configured to detect the activation of the first body diode of the first transistor and the activation of the second body diode of the second transistor when both the first transistor and the second transistor are turned off in the third state.

7. The resonant charge pump circuit according to claim 6, wherein the synchronization circuit comprises: A comparator receives an intermediate voltage from an intermediate node between the first transistor and the second transistor, the comparator being configured to generate a detection signal in a detection state in response to the intermediate voltage being higher than a threshold voltage level, the threshold voltage level being higher than an input voltage level at the input terminal; An AND gate is configured to receive a stagnation signal in a stagnation state in response to the third state, and the AND gate is configured to generate a frequency adjustment signal in a frequency adjustment state in response to the detection signal being in the detection state and the stagnation signal being in the stagnation state. as well as A single transmitter configured to adjust the clock frequency in response to the frequency adjustment signal being in the frequency adjustment state.

8. The resonant charge pump circuit according to claim 6, wherein the synchronization circuit comprises: A comparator that receives an intermediate voltage from an intermediate node between the first transistor and the second transistor, the comparator being configured to generate a detection signal in a detection state in response to the intermediate voltage being lower than a threshold voltage level, the threshold voltage level being lower than ground; An AND gate is configured to receive a stagnation signal in a stagnation state in response to the third state, and the AND gate is configured to generate a frequency adjustment signal in a frequency adjustment state in response to the detection signal being in the detection state and the stagnation signal being in the stagnation state. as well as A single transmitter configured to adjust the clock frequency in response to the frequency adjustment signal being in the frequency adjustment state.

9. The resonant charge pump circuit of claim 1, further comprising a switching circuit connected to the resonant circuit, wherein the switching circuit is configured to: Switch to a first state, which allows current to flow from the input terminal to the resonant circuit to charge the barrel capacitor and the barrel inductor; Switching to a second state, the second state allows current to flow from the resonant circuit to discharge the barrel capacitor and the barrel inductor to the output terminal; and Switching to a third state, which prevents the current from flowing from the input terminal to the resonant circuit and prevents the current from flowing from the resonant circuit to discharge the barrel capacitor and the barrel inductor to the output terminal.

10. The resonant charge pump circuit according to claim 9, wherein the switching circuit includes the first transistor and the second transistor.

11. The resonant charge pump circuit according to claim 9, wherein: When the switching circuit is in the first state, the first transistor connects the input terminal to the resonant circuit, and when the switching circuit is in the second and third states, the first transistor disconnects the input terminal from the resonant circuit. The first transistor is located outside the switching circuit. and When the switching circuit is in the second state, the second transistor connects the resonant circuit to the output terminal, and when the switching circuit is in the first state and the third state, the second transistor disconnects the output terminal from the resonant circuit. The second transistor is located outside the switching circuit.

12. A method for operating a resonant charge pump, the method comprising: In the first state, the first transistor is turned on to allow current to flow from the input terminal to the resonant circuit to charge the barrel capacitor and the barrel inductor, and the second transistor is turned off to prevent current from flowing from the resonant circuit to discharge the barrel capacitor and the barrel inductor to the output terminal. In the second state, the first transistor is turned off so that the current cannot flow from the input terminal to the resonant circuit to charge the barrel capacitor, and the second transistor is turned off so that the current cannot flow from the resonant circuit to discharge the barrel capacitor and the barrel inductor to the output terminal. In the third state, the first transistor is turned off so that the current cannot flow from the input terminal to the resonant circuit to charge the barrel capacitor and the barrel inductor, and the second transistor is turned on so that the current can flow from the resonant circuit to discharge the barrel capacitor and the barrel inductor to the output terminal. A clock signal is generated so that the opening and closing of the first transistor and the second transistor are synchronized according to the clock signal; The activation of either the first body diode of the first transistor or the activation of the second body diode of the second transistor is detected to be in the second state. as well as The frequency of the clock signal is adjusted in response to the activation of the first body diode or the activation of the second body diode.

13. The method of claim 12, wherein adjusting the frequency of the clock signal in response to the activation of the first body diode or the activation of the second body diode comprises: The frequency of the clock signal is increased in response to the detection of activation of the first body diode; as well as The frequency of the clock signal is reduced in response to the detection of activation of the second body diode.

14. The method of claim 12, wherein adjusting the frequency of the clock signal in response to the activation of the first body diode or the activation of the second body diode comprises: The frequency of the clock signal is reduced in response to the detection of activation of the first body diode; as well as The frequency of the clock signal is increased in response to the detection of activation of the second body diode.

15. The method of claim 12, wherein detecting that either the activation of the first body diode of the first transistor is activated or the activation of the second body diode of the second transistor is in the second state comprises: Receive intermediate voltage from the intermediate node between the first transistor and the second transistor; A detection signal is generated in response to the intermediate voltage being higher than a threshold voltage level, wherein the threshold voltage level is higher than the input voltage level of the input voltage at the input terminal; as well as In response to the second state, a stagnation signal in a stagnation state is received.

16. The method of claim 15, wherein adjusting the frequency of the clock signal in response to the activation of the first body diode or the activation of the second body diode comprises: A frequency adjustment signal in a frequency adjustment state is generated in response to the detection signal being in the detection state and the stagnation signal being in the stagnation state. as well as The clock frequency is adjusted in response to the frequency adjustment signal being in the frequency adjustment state.

17. The method of claim 12, wherein detecting that either the activation of the first body diode of the first transistor is activated or the activation of the second body diode of the second transistor is in the second state comprises: Receive intermediate voltage from the intermediate node between the first transistor and the second transistor; A detection signal in a detection state is generated in response to the intermediate voltage being lower than a threshold voltage level, wherein the threshold voltage level is lower than ground; as well as In response to the second state, a stagnation signal in a stagnation state is received.

18. The method of claim 17, wherein adjusting the frequency of the clock signal in response to the activation of the first body diode or the activation of the second body diode comprises: A frequency adjustment signal in a frequency adjustment state is generated in response to the detection signal being in the detection state and the stagnation signal being in the stagnation state. as well as The clock frequency is adjusted in response to the frequency adjustment signal being in the frequency adjustment state.

19. A power system including a resonant charge pump circuit, the resonant charge pump circuit comprising: A resonant circuit having a barrel capacitor and a barrel inductor connected in series; A first transistor is configured to be off and on, and is connected such that when the first transistor is on, current can flow from the input terminal to the resonant circuit to charge the barrel capacitor and the barrel inductor, and when the first transistor is off, the current cannot flow from the input terminal to the resonant circuit to charge the barrel capacitor and the barrel inductor. A second transistor is configured to be turned off and on, wherein when the second transistor is turned on, the current is allowed to flow from the resonant circuit to discharge the barrel capacitor and the barrel inductor to the output terminal, and when the second transistor is turned off, the current is prevented from flowing from the resonant circuit to discharge the barrel capacitor and the barrel inductor to the output terminal. as well as A synchronization circuit is configured to generate a clock signal such that the opening and closing of the first transistor and the second transistor are synchronized according to the clock signal, wherein the synchronization circuit is configured to detect the activation of a first body diode of the first transistor and the activation of a second body diode of the second transistor, and adjust the frequency of the clock signal in response to the activation of the first body diode or the activation of the second body diode.

20. The power system of claim 19, wherein the synchronization circuit is configured to: The frequency of the clock signal is increased in response to the detection of activation of the first body diode; and The frequency of the clock signal is reduced in response to the detection of activation of the second body diode.

21. The power system of claim 19, wherein the synchronization circuit is configured to: The frequency of the clock signal is reduced in response to the detection of activation of the first body diode; and The frequency of the clock signal is increased in response to the detection of activation of the second body diode.

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