A step-down converter circuit

Abstract

The application discloses a step-down converter circuit. The step-down converter circuit comprises a multi-phase slope generation module, a parallel comparator module and a control module. The multi-phase slope generation module is used for outputting N sawtooth wave signals, and the parallel comparator module is used for receiving the sawtooth wave signals to output N PWM waves. After an error signal is suddenly changed, the step-down converter circuit is in a transient state, the control module selects a PWM wave output by a comparator which first jumps in the parallel comparator module as an optimal PWM wave signal as an output of an output end of the control module. Through the scheme, when the step-down converter encounters a transient current jump, the equivalent switching frequency can be improved by increasing the sampling frequency, so that the dynamic response speed is improved. At the same time, the original switching frequency is maintained when the converter is in a steady state, the switching loss is effectively controlled, and the conversion efficiency is improved, so that the problem that the aging condition of a power semiconductor in the prior art is difficult to be monitored is solved.

Description

Technical Field

[0001] This invention relates to the field of buck converters, and more specifically to a buck converter circuit. Background Technology

[0002] In low-voltage power supply systems, the buck converter is the core power supply unit, and its dynamic response performance directly determines the stability and reliability of the power supply system. When a large load current transient occurs in the power supply system, in order to avoid excessive voltage drop in the output voltage, which could lead to abnormal operation or even damage to downstream electrical equipment, the buck converter must have a fast dynamic response capability to minimize the voltage drop.

[0003] Existing technologies employ voltage-mode pulse-width modulation (PWM) control schemes to control buck converters. However, traditional PWM-controlled buck converters have inherent limitations, with their transient response speed restricted by the switching frequency. The duty cycle update of such converters can only be completed at the level crossing moment between the error amplifier output signal and the single sawtooth wave signal, fundamentally limiting the potential for improving transient response performance. Increasing the switching frequency would significantly increase switching losses in the power supply, thereby drastically reducing the power system's energy conversion efficiency and contradicting the trend towards energy-saving power systems. Using a hysteresis-mode control scheme would result in output voltage overshoot during the transient response. This overshoot would subject the power devices inside the power supply to voltage stress exceeding their rated withstand voltage, potentially causing device damage and severely impacting the power supply's reliability and lifespan. Summary of the Invention

[0004] The main technical problem solved by this invention is the difficulty in improving the transient response speed of existing buck converters.

[0005] According to a first aspect, one embodiment provides a buck converter circuit, comprising:

[0006] A power stage circuit includes a signal input terminal, a voltage input terminal, and a voltage output terminal; the signal input terminal of the power stage is connected to the output terminal of the control module, the voltage input terminal of the power stage is connected to the power supply, and the voltage output terminal of the power stage is used to output a first voltage signal.

[0007] An error amplifier is provided, comprising a first input terminal, a second input terminal, and an output terminal. The first input terminal of the error amplifier is used to receive a reference voltage; the second input terminal of the error amplifier is used to receive a first voltage signal output by the buck converter circuit; and the output terminal of the error amplifier outputs an error signal, which reflects the degree to which the voltage signal output by the buck converter circuit deviates from the reference voltage.

[0008] A multiphase ramp generation module includes N output terminals for outputting N sawtooth wave signals. The N sawtooth wave signals have the same frequency but different phases.

[0009] The parallel comparator module has N comparators. Each comparator includes a first input terminal, a second input terminal, and an output terminal. The first input terminal of each comparator is connected to the output terminal of the error amplifier. The second input terminal of each comparator is connected to each output terminal of the multiphase ramp generation module. The output terminal of each comparator is used to output N PWM waves.

[0010] The control module receives N PWM wave signals and determines the state of the buck converter circuit. If the buck converter circuit is in a steady state, the control module selects any one PWM wave signal as the output of the control module. If the buck converter circuit is in a transient state, the control module selects the PWM wave output by the comparator that first jumps after the buck converter circuit transitions from a steady state to a transient state as the output of the control module.

[0011] In a further embodiment of the present invention, the control module includes:

[0012] A sampling circuit, the sampling circuit including an error signal input terminal and a status output terminal;

[0013] The error signal input terminal is used to receive the error signal, and the status output terminal is used to output a first level or a second level, indicating that the buck converter circuit is in a steady state or a transient state.

[0014] The sampling circuit determines whether the error signal undergoes a sudden change, in order to determine whether the buck converter circuit is in a steady state or a transient state.

[0015] In a further embodiment of the present invention, the sampling circuit further includes a sampling capacitor, a sampling voltage output terminal, a sampling selection unit, and a sampling switch;

[0016] The sampling switch includes a first terminal, a second terminal, and a control terminal. The first terminal of the sampling switch is connected to the error signal input terminal; the second terminal of the sampling switch is connected to the first terminal of the sampling capacitor; and the control terminal of the sampling switch is connected to the output terminal of the sampling selection unit to control the switching on and off of the sampling switch.

[0017] The first terminal of the sampling capacitor is connected to the sampling voltage output terminal, and the second terminal of the sampling capacitor is connected to ground;

[0018] The sampling selection unit includes an input terminal and an output terminal. The input terminal of the sampling selection unit is used to receive the signal from the status output terminal. When the status output terminal outputs a first level, the output terminal of the sampling selection unit outputs a high-frequency clock signal. When the status output terminal outputs a second level, the output terminal of the sampling selection unit outputs a low-frequency clock signal.

[0019] The sampling voltage output terminal is used to output the voltage of the sampling capacitor. Each time the sampling circuit performs a sampling, it is represented by the sampling switch being turned on and off once. The current output voltage of the sampling voltage output terminal is compared with the output voltage of the sampling voltage output terminal during the previous sampling. When the difference between the two is greater than a preset threshold, it is determined that the buck converter circuit is in a transient state, and the status output terminal outputs a first level; otherwise, it is determined that the buck converter circuit is in a steady state, and the status output terminal outputs a second level.

[0020] In a further embodiment of the present invention, the sampling circuit further includes a sampling voltage register and a sampling voltage comparator;

[0021] The sampling voltage register is connected to the sampling voltage output terminal and the sampling voltage comparator. The sampling voltage register is used to receive and store the output voltage of the sampling voltage output terminal after the sampling circuit performs one sampling, and to provide the sampling voltage comparator with the output voltage of the sampling voltage output terminal during the previous sampling when the sampling circuit performs one sampling.

[0022] The sampling voltage comparator includes a first input terminal, a second input terminal, and an output terminal. The first input terminal of the sampling voltage comparator is connected to the sampling voltage output terminal, the second input terminal of the sampling voltage comparator is connected to the sampling voltage register, and the output terminal of the sampling voltage comparator is connected to the status output terminal.

[0023] The sampling voltage comparator is used to compare the output voltage of the sampling voltage output terminal with the output voltage of the sampling voltage register whenever the sampling circuit performs a sampling. If the difference between the two is greater than a preset threshold, it is determined that the buck converter circuit is in a transient state, and the status output terminal outputs a first level; otherwise, it is determined that the buck converter circuit is in a steady state, and the status output terminal outputs a second level.

[0024] In a further embodiment of the present invention, the multiphase slope generation module includes:

[0025] There are N ramp generation modules, each ramp generation module includes an input terminal and an output terminal. The input terminal of the ramp generation module is used to receive a clock signal, and the output terminal of the ramp generation module is used to output a sawtooth wave signal.

[0026] There are N delay generation modules. Each delay generation module includes an input terminal and an output terminal. The input terminal of each delay generation module is used to receive the same clock signal, and the output terminal of each delay generation module is used to output clock signals with different delays.

[0027] The output of each delay generation module is connected to the input of a ramp generation module, providing the multiphase ramp generation module with N sawtooth wave signals with the same frequency and different phases.

[0028] In a further embodiment of the present invention, the ramp generation module includes a pulse generator, a first switching unit, a first capacitor, and a current source:

[0029] The pulse generator includes an input terminal and an output terminal. The pulse generator is used to receive a clock signal and output a pulse signal of fixed width.

[0030] The first switching unit includes a first terminal, a second terminal, and a control terminal. The first terminal of the first switching unit is connected to the first terminal of the first capacitor, the second terminal of the first switching unit is connected to ground, and the control terminal of the first switching unit is connected to the output terminal of the pulse generator.

[0031] The first terminal of the first capacitor is connected to the current source, which is used to output a constant current, and the second terminal of the first capacitor is connected to ground.

[0032] When the pulse generator outputs a first level, the first switching unit is turned off, the current source charges the first capacitor, and the voltage of the first capacitor rises linearly, serving as the sawtooth wave signal output from the output terminal of the ramp generation module; when the pulse generator outputs a second level, the first switching unit is turned on, the first capacitor discharges through the first switching unit, and the voltage of the first capacitor returns to zero.

[0033] In a further embodiment of the present invention, the delay generation module includes a delay generation unit and logic gates;

[0034] The first terminal of the delay generation unit is used to receive a clock signal, and the second terminal of the delay generation unit is connected to the first input terminal of the logic gate; the second input terminal of the logic gate is used to receive a clock signal, and the output terminal of the logic gate is used to output a clock signal with a delay.

[0035] In a further embodiment of the present invention, the power stage circuit includes a second switching unit, a third switching unit, an inductor, and a second capacitor;

[0036] The second switching unit includes a first terminal, a second terminal, and a control terminal. The first terminal of the second switching unit is connected to a power supply, the second terminal of the second switching unit is connected to the first terminal of the inductor, and the control terminal of the second switching unit is used to receive the output of the control module.

[0037] The third switching unit includes a first terminal, a second terminal, and a control terminal. The first terminal of the third switching unit is connected to the first terminal of the inductor and the second terminal of the second switching unit. The second terminal of the third switching unit is connected to ground. The control terminal of the third switching unit is used to receive the output of the control module.

[0038] The second end of the inductor is connected to the first end of the second capacitor;

[0039] The first terminal of the second capacitor serves as the voltage output terminal of the power stage, outputting the first voltage signal, while the second terminal of the second capacitor is connected to ground.

[0040] When the output of the control module is at the first level, the second switch unit is turned on, the third switch unit is turned off, the power supply charges the inductor, the inductor stores energy, and at the same time charges the second capacitor;

[0041] When the output of the control module is at the second level, the second switch unit is turned off, the third switch unit is turned on, the inductor discharges through the third switch unit, and the second capacitor discharges.

[0042] In a further embodiment of the present invention, the power stage circuit further includes:

[0043] A first load resistor and a second load resistor, wherein a first end of the first load resistor is connected to a first end of the second capacitor, a second end of the first load resistor is connected to a first end of the second load resistor, and a second end of the second load resistor is connected to ground.

[0044] In a further embodiment of the present invention, the power stage circuit further includes:

[0045] The second voltage signal output terminal is connected to the second terminal of the first load resistor and is used to provide a second voltage signal to the second input terminal of the error amplifier.

[0046] This application discloses a buck converter circuit. The buck converter circuit includes a multiphase ramp generation module, a parallel comparator module, and a control module. The multiphase ramp generation module outputs N sawtooth wave signals, and the parallel comparator module receives the sawtooth wave signals to output N PWM waves. After a sudden change in the error signal, the buck converter circuit is in a transient state. The control module selects the PWM wave output by the comparator that first experiences a jump in the parallel comparator module as the optimal PWM wave signal and uses it as the output of the control module. Through this scheme, the equivalent switching frequency can be increased by increasing the sampling frequency when the buck converter encounters a transient current jump, thereby improving the dynamic response speed. At the same time, it ensures that the converter maintains the original switching frequency during steady-state operation, effectively controlling switching losses to improve conversion efficiency, thus solving the problem that the aging condition of power semiconductors is difficult to monitor in the prior art. Attached Figure Description

[0047] Figure 1 This is a schematic diagram of the buck converter circuit in an embodiment of the present invention;

[0048] Figure 2 This is a partial structural schematic diagram of the multiphase slope generation module in an embodiment of the present invention;

[0049] Figure 3 This is a partial structural diagram of the control module in an embodiment of the present invention;

[0050] Figure 4 This is a schematic diagram of the signal output of the buck converter in an embodiment of the present invention. Detailed Implementation

[0051] The present invention will now be described in further detail with reference to specific embodiments and accompanying drawings. Similar elements in different embodiments are referred to by associated similar element reference numerals. In the following embodiments, many details are described to facilitate a better understanding of this application. However, those skilled in the art will readily recognize that some features may be omitted in different situations, or may be replaced by other elements, materials, or methods. In some cases, certain operations related to this application are not shown or described in the specification. This is to avoid obscuring the core parts of this application with excessive description. For those skilled in the art, detailed description of these related operations is not necessary; they can fully understand the related operations based on the description in the specification and general technical knowledge in the art.

[0052] Furthermore, the features, operations, or characteristics described in the specification can be combined in any suitable manner to form various embodiments. At the same time, the steps or actions in the method description can be rearranged or adjusted in a manner obvious to those skilled in the art. Therefore, the various orders in the specification and drawings are only for the clear description of a particular embodiment and do not imply a necessary order, unless otherwise stated that a particular order must be followed.

[0053] The serial numbers assigned to components in this document, such as "first" and "second," are used only to distinguish the described objects and have no sequential or technical meaning. The terms "connection" and "linkage" used in this application, unless otherwise specified, include both direct and indirect connections (linkages).

[0054] In low-voltage power supply systems, the buck converter is the core power supply unit, and its dynamic response performance directly determines the stability and reliability of the power supply system. When a large load current transient occurs in the power supply system, in order to avoid excessive voltage drop in the output voltage, which could lead to abnormal operation or even damage to downstream electrical equipment, the buck converter must have a fast dynamic response capability to minimize the voltage drop.

[0055] In practical applications, existing technologies employ voltage-mode pulse-width modulation (PWM) control schemes to control buck converters. However, traditional PWM-controlled buck converters have inherent technical limitations, with their transient response speed restricted by the switching frequency. The duty cycle update of this type of converter can only be completed at the level crossing moment between the error amplifier output signal and the single sawtooth wave signal, fundamentally limiting the potential for improving transient response performance. Increasing the switching frequency would significantly increase the switching losses of the power supply, thereby drastically reducing the energy conversion efficiency of the power system and contradicting the trend towards energy-saving power systems. Using a hysteresis-mode control scheme would result in output voltage overshoot during the transient response. This overshoot would subject the power devices inside the power supply to voltage stress exceeding their rated withstand voltage, potentially causing device damage and severely impacting the reliability and lifespan of the power supply.

[0056] In practical applications, existing technologies typically assess the health of gallium nitride (GaN) devices by monitoring the on-resistance of GaN power semiconductors. However, the on-resistance of GaN power semiconductors is easily affected by temperature, and the change in on-resistance is usually not significant as GaN power semiconductors age, requiring high-precision testing instruments.

[0057] Based on this discovery, a buck converter circuit is disclosed. The buck converter circuit includes a multiphase ramp generation module, a parallel comparator module, and a control module. The multiphase ramp generation module outputs N sawtooth wave signals, and the parallel comparator module receives the sawtooth wave signals to output N PWM waves. After a sudden change in the error signal, the buck converter circuit is in a transient state. The control module selects the PWM wave output by the comparator that first experiences a jump in the parallel comparator module as the optimal PWM wave signal and uses it as the output of the control module. This scheme can increase the equivalent switching frequency by increasing the sampling frequency when the buck converter encounters a transient current jump, thereby improving the dynamic response speed. Simultaneously, it ensures that the converter maintains its original switching frequency during steady-state operation, effectively controlling switching losses to improve conversion efficiency, thus solving the problem of difficulty in monitoring the aging status of power semiconductors in existing technologies.

[0058] The concept of the present invention will be explained in detail below through specific embodiments.

[0059] In some embodiments, please refer to Figure 1 , Figure 1 This is a schematic diagram of the buck converter circuit in an embodiment of the present invention. The buck converter circuit serves as a power supply unit to provide a first voltage signal as the output voltage. This scheme introduces multiple sawtooth waves with consistent frequency and staggered phases, compares them with the output voltage of the error amplifier 100, and performs oversampling processing to generate multiple sets of pulse width modulation (PWM) waves. The optimal PWM wave is then selected from these multiple sets to control the converter. This scheme can increase the equivalent switching frequency when the converter encounters transient current jumps, thereby improving the dynamic response speed. Simultaneously, it ensures that the converter maintains its original switching frequency during steady-state operation, effectively controlling switching losses to improve conversion efficiency.

[0060] The buck converter circuit includes an error amplifier 100, which is the core component of the buck converter's closed-loop voltage regulation control system. Its function is to detect the deviation between the output voltage and the reference voltage, generate an error signal, and adjust the on / off state of the power switch transistors to ultimately stabilize the output voltage. The error amplifier 100 includes a first input terminal, a second input terminal, and an output terminal. The first input terminal of the error amplifier 100 receives the reference voltage. The second input terminal of the error amplifier 100 receives the first voltage signal output by the buck converter circuit. The output terminal of the error amplifier 100 outputs an error signal, which reflects the degree to which the output voltage signal of the buck converter circuit deviates from the reference voltage.

[0061] The buck converter circuit includes a multiphase ramp generation module 200, which is responsible for generating a multiphase sawtooth wave array with consistent frequency and staggered phases, providing input support for the sampling step to achieve fast transient response. The multiphase ramp generation module 200 includes N output terminals for outputting N sawtooth wave signals, which have the same frequency but different phases.

[0062] In some embodiments, please refer to Figure 2 , Figure 2 This is a partial structural schematic diagram of the multiphase ramp generation module 200 in an embodiment of the present invention. The multiphase ramp generation module 200 includes N ramp generation modules 210. Each ramp generation module 210 includes an input terminal and an output terminal. The input terminal of the ramp generation module 210 is used to receive a clock signal, and the output terminal of the ramp generation module 210 is used to output a sawtooth wave signal, so that each ramp generation module 210 generates a sawtooth wave signal, and the sawtooth wave signals generated by different ramp generation modules 210 have the same frequency but different phases.

[0063] The ramp generation module 210 includes a pulse generator 211, a first switching unit 212, a first capacitor 213, and a current source 214. The pulse generator 211 includes an input terminal and an output terminal. It receives a clock signal to output a fixed-width pulse signal, precisely controlling the capacitor discharge time to ensure the stability of the sawtooth wave's reset slope and peak value. The first switching unit 212 includes a first terminal, a second terminal, and a control terminal. The first terminal of the first switching unit 212 is connected to the first terminal of the first capacitor 213, the second terminal of the first switching unit 212 is connected to ground, and the control terminal of the first switching unit 212 is connected to the output terminal of the pulse generator 211. The first terminal of the first capacitor 213 is connected to the current source 214, which outputs a constant current. The second terminal of the first capacitor 213 is connected to ground.

[0064] When the pulse generator 211 outputs the first level, the first switching unit 212 is turned off, and the current source 214 charges the first capacitor 213. The voltage of the first capacitor 213 rises linearly, serving as the sawtooth wave signal output from the ramp generation module 210. When the pulse generator 211 outputs the second level, the first switching unit 212 is turned on, and the first capacitor 213 discharges through the first switching unit 212, causing the voltage of the first capacitor 213 to return to zero.

[0065] The multiphase ramp generation module 200 includes N delay generation modules 220. Each delay generation module 220 includes an input terminal and an output terminal. The input terminal of each delay generation module 220 is used to receive the same clock signal, and the output terminal of each delay generation module 220 is used to output clock signals with different delays. The output terminal of each delay generation module 220 is connected to the input terminal of a ramp generation module 210, so that the multiphase ramp generation module 200 provides N sawtooth wave signals with the same frequency but different phases.

[0066] The delay generation module 220 includes a delay generation unit 221 and a logic gate 222. The first terminal of the delay generation unit 221 is used to receive a clock signal, and the second terminal of the delay generation unit 221 is connected to the first input terminal of the logic gate 222. The second input terminal of the logic gate 222 is used to receive the clock signal, and the output terminal of the logic gate 222 is used to output a clock signal with a delay.

[0067] The buck converter circuit includes a parallel comparator module 300, which has N comparators. Each comparator includes a first input terminal, a second input terminal, and an output terminal. The first input terminal of each comparator is connected to the output terminal of the error amplifier 100, and the second input terminal of each comparator is connected to each output terminal of the multiphase ramp generation module 200. The output terminal of each comparator is used to output N PWM waves.

[0068] The parallel comparator module 300 synchronously compares the outputs of the multiphase ramp generation module 200 and the error amplifier 100 to generate multiple PWM signals, determining whether the buck converter can quickly capture voltage changes. The parallel comparator module 300 synchronously samples and monitors multiple phase-interleaved sawtooth wave signals and the error signal output by the error amplifier 100, detecting level crossing events in real time to achieve oversampling of the buck converter circuit error. For multi-channel PWM wave generation, each comparator generates a corresponding interleaved PWM pulse, providing input for subsequent selection of the optimal control signal. As mentioned in later steps, when rapidly capturing sudden load changes during transients, the comparator that first detects a change in the error signal immediately outputs an updated PWM to control the converter. When the converter encounters transient current jumps, the equivalent switching frequency is increased, thereby improving the dynamic response speed. Simultaneously, it ensures that the converter maintains its original switching frequency during steady-state operation, effectively controlling switching losses to improve conversion efficiency.

[0069] The buck converter circuit includes a control module 400, which has input and output terminals. The input terminal of the control module 400 is connected to a parallel comparator module 300 to receive N PWM wave signals. The output terminal of the control module 400 is used to output the optimal PWM wave signal. The control module 400 determines whether the error signal has a sudden change. If the error signal has not a sudden change, the buck converter circuit is in a steady state, and the control module 400 selects any one of the PWM wave signals as the optimal PWM wave signal as the output of the control module 400. If the error signal has a sudden change, the buck converter circuit is in a transient state, and the control module 400 selects the PWM wave output by the comparator in the parallel comparator module 300 that first shows a jump after the error signal has a sudden change as the optimal PWM wave signal as the output of the control module 400.

[0070] In some embodiments, please refer to Figure 3 , Figure 3 This is a partial structural diagram of the control module 400 in an embodiment of the present invention. The control module 400 includes a sampling circuit 410, which includes an error signal input terminal and a status output terminal. The error signal input terminal is used to receive an error signal, and the status output terminal is used to output a first level or a second level to characterize whether the buck converter circuit is in a steady state or a transient state. The sampling circuit 410 determines whether the error signal undergoes a sudden change to determine whether the buck converter circuit is in a steady state or a transient state.

[0071] The sampling circuit 410 also includes a sampling capacitor 411, a sampling voltage output terminal 412, a sampling selection unit 413, and a sampling switch. The sampling switch includes a first terminal, a second terminal, and a control terminal. The first terminal of the sampling switch is connected to the error signal input terminal. The second terminal of the sampling switch is connected to the first terminal of the sampling capacitor 411. The control terminal of the sampling switch is connected to the output terminal of the sampling selection unit 413 to control the switching on and off of the sampling switch. The first terminal of the sampling capacitor 411 is connected to the sampling voltage output terminal 412, and the second terminal of the sampling capacitor 411 is connected to ground. The sampling selection unit 413 includes an input terminal and an output terminal. The input terminal of the sampling selection unit 413 is used to receive the signal from the status output terminal. When the status output terminal outputs a first level, the output terminal of the sampling selection unit 413 outputs a high-frequency clock signal; when the status output terminal outputs a second level, the output terminal of the sampling selection unit 413 outputs a low-frequency clock signal.

[0072] The sampling voltage output terminal 412 is used to output the voltage of the sampling capacitor 411. Each time the sampling circuit 410 performs a sampling to represent a switching on and off of the sampling switch, the current output voltage of the sampling voltage output terminal 412 is compared with the output voltage of the sampling voltage output terminal 412 during the previous sampling. If the difference between the two is greater than a preset threshold, the buck converter circuit is determined to be in a transient state, and the status output terminal outputs a first level. Otherwise, the buck converter circuit is determined to be in a steady state, and the status output terminal outputs a second level.

[0073] The sampling circuit 410 also includes a sampling voltage register and a sampling voltage comparator. The sampling voltage register is connected to the sampling voltage output terminal 412 and the sampling voltage comparator. The sampling voltage register receives and stores the output voltage of the sampling voltage output terminal 412 after the sampling circuit 410 performs one sampling operation, and provides the sampling voltage comparator with the output voltage of the sampling voltage output terminal 412 from the previous sampling operation when the sampling circuit 410 performs another sampling operation. The sampling voltage comparator includes a first input terminal, a second input terminal, and an output terminal. The first input terminal of the sampling voltage comparator is connected to the sampling voltage output terminal 412, the second input terminal of the sampling voltage comparator is connected to the sampling voltage register, and the output terminal of the sampling voltage comparator is connected to the status output terminal.

[0074] The sampling voltage comparator compares the output voltage of the sampling voltage output terminal 412 with the output voltage of the sampling voltage register whenever the sampling circuit 410 performs a sampling. If the difference between the two is greater than a preset threshold, the buck converter circuit is determined to be in transient state, and the status output terminal outputs a first level. Otherwise, the buck converter circuit is determined to be in steady state, and the status output terminal outputs a second level.

[0075] The buck converter circuit includes a power stage circuit 500, which includes a signal input terminal, a voltage input terminal, and a voltage output terminal. The signal input terminal of the power stage is connected to the output terminal of the control module 400, the voltage input terminal of the power stage is connected to the power supply, and the voltage output terminal of the power stage is used as the output terminal of the buck converter circuit to output a first voltage signal.

[0076] The power stage circuit 500 includes a second switching unit 510, a third switching unit 520, an inductor 530, and a second capacitor 540. The second switching unit 510 includes a first terminal, a second terminal, and a control terminal. The first terminal of the second switching unit 510 is connected to the power supply, the second terminal of the second switching unit 510 is connected to the first terminal of the inductor 530, and the control terminal of the second switching unit 510 is used to receive the optimal PWM wave signal. The third switching unit 520 includes a first terminal, a second terminal, and a control terminal. The first terminal of the third switching unit 520 is connected to the first terminal of the inductor 530 and the second terminal of the second switching unit 510, and the second terminal of the third switching unit 520 is connected to ground. The control terminal of the third switching unit 520 is used to receive the optimal PWM wave signal. The second terminal of the inductor 530 is connected to the first terminal of the second capacitor 540. The first terminal of the second capacitor 540 serves as the voltage output terminal of the power stage, outputting a first voltage signal, and the second terminal of the second capacitor 540 is connected to ground. The power stage circuit 500 also includes a first load resistor 550 and a second load resistor 560. The first end of the first load resistor 550 is connected to the first end of the second capacitor 540, the second end of the first load resistor 550 is connected to the first end of the second load resistor 560, and the second end of the second load resistor 560 is connected to ground.

[0077] When the optimal PWM signal is at the first level, the second switching unit 510 is turned on and the third switching unit 520 is turned off. The power supply charges the inductor 530, which stores energy, and simultaneously charges the second capacitor 540. When the optimal PWM signal is at the second level, the second switching unit 510 is turned off and the third switching unit 520 is turned on. The inductor 530 discharges through the third switching unit 520, and the second capacitor 540 discharges.

[0078] The power stage circuit 500 also includes a second voltage signal output terminal 570, connected to the second terminal of the first load resistor 550, for providing a second voltage signal to the second input terminal of the error amplifier 100. The second voltage signal, as the input to the error amplifier 100, differs from the first voltage signal output from the buck converter as the input to the error amplifier 100 only in the voltage division between the first load resistor 550 and the second load resistor 560. This ensures that regardless of the magnitude of the first voltage signal, the second voltage signal is always a certain proportion of the first voltage signal, allowing for more flexible adjustment of the reference voltage and the sawtooth wave signal magnitude.

[0079] In practical applications, the buck converter circuit operates stably according to the preset timing and control logic. The overall workflow can be divided into two parts: steady-state workflow and transient workflow. The specific implementation steps are as follows.

[0080] After the buck converter is connected to the power supply, the power supply supplies power to the power stage circuit 500. The reference voltage is input to the first input terminal of the error amplifier 100, and the second input terminal of the error amplifier 100 receives the second voltage signal obtained by voltage division of the output voltage. The error amplifier 100 performs difference calculation on the two signals and continuously outputs a stable error signal at the output terminal to characterize the deviation state between the output voltage and the target voltage.

[0081] The multiphase ramp generation module 200 starts working under the drive of a clock signal. An external clock is input to multiple delay generation modules 220. After processing by the delay generation unit 221 and logic gate 222, multiple delayed clock signals with sequentially staggered phases and consistent frequencies are output. Each delayed clock signal is sent to the corresponding ramp generation module 210, which controls the pulse generator 211 to output a fixed-width pulse, thereby driving the first switching unit 212 to periodically turn on and off. When the first switching unit 212 is off, the current source 214 charges the first capacitor 213, and the capacitor voltage rises linearly to form the rising edge of the ramp. When the first switching unit 212 is on, the capacitor discharges rapidly to zero potential, completing one sawtooth wave reset. The multiple ramp generation modules 210 operate synchronously, ultimately outputting a set of multiphase sawtooth wave signals with staggered phases and unified frequencies.

[0082] The parallel comparator module 300 acquires the error signal output from the error amplifier 100 and the multi-channel sawtooth wave signals output from the multiphase ramp generation module 200 in real time. Each comparator compares the sawtooth wave signal and the error signal of the corresponding phase. When the voltage of the sawtooth wave signal intersects with the voltage of the error signal, the output level of the corresponding comparator flips, generating a PWM wave. Under steady-state conditions, the error signal remains constant, and the PWM wave pulse widths output by each comparator are consistent, with uniformly staggered phases.

[0083] The control module 400 continuously acquires multiple PWM wave signals output by the parallel comparator module 300, and simultaneously performs periodic sampling of the error signal through the internal sampling circuit 410. The sampling circuit 410 completes error signal sampling through a sampling switch and a sampling capacitor 411, storing the current sampled voltage and the previous sampled voltage in a sampling voltage register, and the difference is determined by the sampling voltage comparator. When the sampled voltage difference is less than a preset threshold, the sampling circuit 410 outputs a level signal representing a steady state. The control module 400 determines that the converter is in a steady state and selects one of the multiple PWM waves as the optimal PWM wave to output to the power stage circuit 500.

[0084] After the optimal PWM wave is sent to the power stage circuit 500, it controls the second switching unit 510 and the third switching unit 520 to alternately turn on and off: when the PWM wave is high, the second switching unit 510 is on and the third switching unit 520 is off. The input power supply charges the inductor 530 through the second switching unit 510 and simultaneously supplies power to the output capacitor; when the PWM wave is low, the second switching unit 510 is off and the third switching unit 520 is on. The inductor 530 discharges through the third switching unit 520, maintaining a stable output voltage. Throughout the steady-state process, the converter maintains its original switching frequency, the switching losses remain at a low level, and the conversion efficiency is stable.

[0085] When the load current changes abruptly or the output voltage fluctuates rapidly, the error signal output by the error amplifier 100 changes accordingly. The sampling circuit 410 detects that the difference between two consecutive sampled voltages exceeds the preset threshold and immediately outputs a level signal representing the transient state. The control module 400 determines that the converter has entered the transient response stage.

[0086] In transient states, the comparator in the parallel comparator module 300 that first crosses the level with the changed error signal will immediately output the updated PWM wave. The control module 400 quickly identifies and locks onto the PWM wave that first experiences a level transition, and outputs it directly to the power stage circuit 500 as the optimal PWM wave, without waiting for a complete switching cycle, thus significantly reducing the response delay.

[0087] In some embodiments, please refer to Figure 4 , Figure 4 This is a schematic diagram of the signal output of the buck converter in an embodiment of the present invention. EA For the error signal, V Ramp For sawtooth wave signals, V PWM This is a PWM wave signal. During transient regulation, the converter's equivalent sampling frequency increases proportionally with the number of multiphase ramps, resulting in a momentary increase in the equivalent switching frequency. This rapidly corrects the power transistor's on-time, quickly pulling the output voltage back to the target value and effectively suppressing voltage drops and overshoot. Once the output voltage stabilizes and the error signal returns to a constant range, the sampling circuit 410 re-outputs the steady-state signal, the control module 400 switches back to the steady-state selection mode, and the converter resumes constant frequency operation.

[0088] This application discloses a buck converter circuit. The buck converter circuit includes a multiphase ramp generation module 200, a parallel comparator module 300, and a control module 400. The multiphase ramp generation module 200 outputs N sawtooth wave signals, and the parallel comparator module 300 receives the sawtooth wave signals to output N PWM waves. After a sudden change in the error signal, the buck converter circuit is in a transient state. The control module 400 selects the PWM wave output by the comparator in the parallel comparator module 300 that first experiences a jump as the optimal PWM wave signal as the output of the control module 400. Through this scheme, the equivalent switching frequency can be increased by increasing the sampling frequency when the buck converter encounters a transient current jump, thereby improving the dynamic response speed. At the same time, it ensures that the converter maintains the original switching frequency during steady-state operation, effectively controlling switching losses to improve conversion efficiency, thus solving the problem that the aging condition of power semiconductors is difficult to monitor in the prior art.

[0089] The above examples illustrate the present invention only to aid in understanding it and are not intended to limit the scope of the invention. Those skilled in the art can make various simple deductions, modifications, or substitutions based on the principles of this invention.

Claims

1. A buck converter circuit, characterized in that, include: A power stage circuit includes a signal input terminal, a voltage input terminal, and a voltage output terminal; the signal input terminal of the power stage is connected to the output terminal of the control module, the voltage input terminal of the power stage is connected to the power supply, and the voltage output terminal of the power stage is used to output a first voltage signal. An error amplifier is provided, comprising a first input terminal, a second input terminal, and an output terminal. The first input terminal of the error amplifier is used to receive a reference voltage; the second input terminal of the error amplifier is used to receive a first voltage signal output by the buck converter circuit; and the output terminal of the error amplifier outputs an error signal, which reflects the degree to which the voltage signal output by the buck converter circuit deviates from the reference voltage. A multiphase ramp generation module includes N output terminals for outputting N sawtooth wave signals. The N sawtooth wave signals have the same frequency but different phases. The parallel comparator module has N comparators. Each comparator includes a first input terminal, a second input terminal, and an output terminal. The first input terminal of each comparator is connected to the output terminal of the error amplifier. The second input terminal of each comparator is connected to each output terminal of the multiphase ramp generation module. The output terminal of each comparator is used to output N PWM waves. The control module receives N PWM wave signals and determines the state of the buck converter circuit. If the buck converter circuit is in a steady state, the control module selects any one PWM wave signal as the output of the control module. If the buck converter circuit is in a transient state, the control module selects the PWM wave output by the comparator that first jumps after the buck converter circuit transitions from a steady state to a transient state as the output of the control module.

2. The buck converter circuit as described in claim 1, characterized in that, The control module includes: A sampling circuit, the sampling circuit including an error signal input terminal and a status output terminal; The error signal input terminal is used to receive the error signal, and the status output terminal is used to output a first level or a second level, indicating that the buck converter circuit is in a steady state or a transient state. The sampling circuit determines whether the error signal undergoes a sudden change, in order to determine whether the buck converter circuit is in a steady state or a transient state.

3. The buck converter circuit as described in claim 2, characterized in that, The sampling circuit also includes a sampling capacitor, a sampling voltage output terminal, a sampling selection unit, and a sampling switch; The sampling switch includes a first terminal, a second terminal, and a control terminal. The first terminal of the sampling switch is connected to the error signal input terminal; the second terminal of the sampling switch is connected to the first terminal of the sampling capacitor; and the control terminal of the sampling switch is connected to the output terminal of the sampling selection unit to control the switching on and off of the sampling switch. The first terminal of the sampling capacitor is connected to the sampling voltage output terminal, and the second terminal of the sampling capacitor is connected to ground; The sampling selection unit includes an input terminal and an output terminal. The input terminal of the sampling selection unit is used to receive the signal from the status output terminal. When the status output terminal outputs a first level, the output terminal of the sampling selection unit outputs a high-frequency clock signal; when the status output terminal outputs a second level, the output terminal of the sampling selection unit outputs a low-frequency clock signal. The sampling voltage output terminal is used to output the voltage of the sampling capacitor. Each time the sampling circuit performs a sampling, it is represented by the sampling switch being turned on and off once. The current output voltage of the sampling voltage output terminal is compared with the output voltage of the sampling voltage output terminal during the previous sampling. When the difference between the two is greater than a preset threshold, it is determined that the buck converter circuit is in a transient state, and the status output terminal outputs the first level. Otherwise, the buck converter circuit is determined to be in a steady state, and the state output terminal outputs a second level.

4. The buck converter circuit as described in claim 3, characterized in that, The sampling circuit also includes a sampling voltage register and a sampling voltage comparator; The sampling voltage register is connected to the sampling voltage output terminal and the sampling voltage comparator. The sampling voltage register is used to receive and store the output voltage of the sampling voltage output terminal after the sampling circuit performs one sampling, and to provide the sampling voltage comparator with the output voltage of the sampling voltage output terminal during the previous sampling when the sampling circuit performs one sampling. The sampling voltage comparator includes a first input terminal, a second input terminal, and an output terminal. The first input terminal of the sampling voltage comparator is connected to the sampling voltage output terminal, the second input terminal of the sampling voltage comparator is connected to the sampling voltage register, and the output terminal of the sampling voltage comparator is connected to the status output terminal. The sampling voltage comparator is used to compare the output voltage of the sampling voltage output terminal with the output voltage of the sampling voltage register whenever the sampling circuit performs a sampling. When the difference between the two is greater than a preset threshold, it is determined that the buck converter circuit is in a transient state, and the state output terminal outputs a first level. Otherwise, the buck converter circuit is determined to be in a steady state, and the state output terminal outputs a second level.

5. The buck converter circuit as described in claim 1, characterized in that, The multiphase slope generation module includes: There are N ramp generation modules, each ramp generation module includes an input terminal and an output terminal. The input terminal of the ramp generation module is used to receive a clock signal, and the output terminal of the ramp generation module is used to output a sawtooth wave signal. There are N delay generation modules. Each delay generation module includes an input terminal and an output terminal. The input terminal of each delay generation module is used to receive the same clock signal, and the output terminal of each delay generation module is used to output clock signals with different delays. The output of each delay generation module is connected to the input of a ramp generation module, providing the multiphase ramp generation module with N sawtooth wave signals with the same frequency and different phases.

6. The buck converter circuit as described in claim 5, characterized in that, The ramp generation module includes a pulse generator, a first switching unit, a first capacitor, and a current source. The pulse generator includes an input terminal and an output terminal. The pulse generator is used to receive a clock signal and output a pulse signal of fixed width. The first switching unit includes a first terminal, a second terminal, and a control terminal. The first terminal of the first switching unit is connected to the first terminal of the first capacitor, the second terminal of the first switching unit is connected to ground, and the control terminal of the first switching unit is connected to the output terminal of the pulse generator. The first terminal of the first capacitor is connected to the current source, which is used to output a constant current, and the second terminal of the first capacitor is connected to ground. When the pulse generator outputs a first level, the first switching unit is turned off, the current source charges the first capacitor, and the voltage of the first capacitor rises linearly, serving as the sawtooth wave signal output from the output terminal of the ramp generation module; when the pulse generator outputs a second level, the first switching unit is turned on, the first capacitor discharges through the first switching unit, and the voltage of the first capacitor returns to zero.

7. The buck converter circuit as described in claim 5, characterized in that, The delay generation module includes a delay generation unit and logic gates; The first terminal of the delay generation unit is used to receive a clock signal, and the second terminal of the delay generation unit is connected to the first input terminal of the logic gate; the second input terminal of the logic gate is used to receive a clock signal, and the output terminal of the logic gate is used to output a clock signal with a delay.

8. The buck converter circuit as described in claim 1, characterized in that, The power stage circuit includes a second switching unit, a third switching unit, an inductor, and a second capacitor; The second switching unit includes a first terminal, a second terminal, and a control terminal. The first terminal of the second switching unit is connected to a power supply, the second terminal of the second switching unit is connected to the first terminal of the inductor, and the control terminal of the second switching unit is used to receive the output of the control module. The third switching unit includes a first terminal, a second terminal, and a control terminal. The first terminal of the third switching unit is connected to the first terminal of the inductor and the second terminal of the second switching unit. The second terminal of the third switching unit is connected to ground. The control terminal of the third switching unit is used to receive the output of the control module. The second end of the inductor is connected to the first end of the second capacitor; The first terminal of the second capacitor serves as the voltage output terminal of the power stage, outputting the first voltage signal, while the second terminal of the second capacitor is connected to ground. When the output of the control module is at the first level, the second switch unit is turned on, the third switch unit is turned off, the power supply charges the inductor, the inductor stores energy, and at the same time charges the second capacitor; When the output of the control module is at the second level, the second switch unit is turned off, the third switch unit is turned on, the inductor discharges through the third switch unit, and the second capacitor discharges.

9. The buck converter circuit as described in claim 8, characterized in that, The power stage circuit also includes: A first load resistor and a second load resistor, wherein a first end of the first load resistor is connected to a first end of the second capacitor, a second end of the first load resistor is connected to a first end of the second load resistor, and a second end of the second load resistor is connected to ground.

10. The buck converter circuit as described in claim 9, characterized in that, The power stage circuit also includes: The second voltage signal output terminal is connected to the second terminal of the first load resistor and is used to provide a second voltage signal to the second input terminal of the error amplifier.

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