Control system for controlling a flying capacitor

Abstract

The present application relates to a control system for controlling a flying capacitor, in particular to a control system for a switching converter comprising a flying capacitor and a first power switch. The control system comprises a control circuit for generating a first pulse width control signal having a first rising edge and a first falling edge to determine a state of the first power switch. The control system further comprises a sensing circuit for sensing a voltage error of a flying capacitor voltage of the flying capacitor with respect to a target voltage and generating a modulation signal based on the voltage error of the flying capacitor voltage and a correction circuit for receiving the modulation signal and the first pulse width control signal and for modulating the first rising edge and / or the first falling edge based on the modulation signal to provide a corrected first pulse width control signal to the first power switch.

Description

[0001] field

[0002] This disclosure relates to a control system for controlling a flying capacitor; more particularly, it relates to a system and method for controlling a flying capacitor. background

[0003] Multilevel power converters are widely used in applications requiring high power density and efficiency, such as portable devices, wearable electronics, and Internet of Things (IoT) systems. These converters benefit from reduced voltage stress across power switches, lower inductor ripple current, and minimized electromagnetic interference.

[0004] Among multilevel converter topologies, flying capacitor multilevel (FCML) converters are attracting attention due to their ability to achieve a wide range of conversion rates, distribute voltage stress across switches, reduce switching losses, and operate seamlessly in both buck and boost modes.

[0005] FCML converters rely on flying capacitors to distribute voltage across multiple power switches and reduce switching losses. To maintain optimal operation, the flying capacitor voltage must be regulated to a predetermined target, which is half the input voltage in a typical three-level flying capacitor converter. Precise control of this voltage is crucial for preventing excessive voltage stress on the power switches, maintaining the delta-inductor current waveform, and minimizing power losses.

[0006] However, maintaining the flying capacitor voltage at the desired level presents significant challenges. Voltage imbalances can be caused by variations in circuit parameters (e.g., timing mismatches, unbalanced power switch resistors), and parasitic capacitances can lead to misaligned flying capacitor voltages. Furthermore, in practical applications, rapid changes in input voltage or load demand exacerbate the difficulty of flying capacitor regulation. Traditional “natural balancing” mechanisms are often insufficient to track these dynamic changes, resulting in instability and inefficiency. In severe cases, inadequate regulation of the flying capacitor voltage can lead to catastrophic failure of the power switches, as excessive voltage stress across each switch may exceed its rated limits, resulting in thermal runaway or permanent damage.

[0007] Attempts to address these technical challenges include strategies such as differential duty cycle modulation, phase shifting techniques, and external circuitry for balancing the voltage across flying capacitors. While these methods improve performance under certain conditions, they are generally limited by factors such as instability near specific operating points, inefficiencies in some DCM regions, and increased system complexity due to additional hardware requirements.

[0008] Known methods for regulating flying capacitors may perform well in specific operating regions (e.g., continuous conduction mode (CCM) or certain slew rates) but fail in other operating regions (e.g., discontinuous conduction mode (DCM) at high or low slew rates). More specifically, high slew rate (HCR) refers to the output voltage (V... out (Greater than half of the input voltage) In this case, low conversion rate (LCR) is applicable. The situation varies depending on the context. These differences exist in both CCM and DCM, and the effectiveness of modulatory methods depends on the interaction of these regions.

[0009] Therefore, it would be beneficial to provide solutions to one or more of these challenges.

[0010] Overview

[0011] According to a first aspect of this disclosure, a control system for a switching converter is provided, the switching converter including a flying capacitor and a first power switch, the control system comprising: a control circuit configured to generate a first pulse width control signal for controlling the first power switch, the first pulse width control signal determining a state of the first power switch and having a first rising edge and a first falling edge; a sensing circuit configured to sense a voltage error of the flying capacitor voltage of the flying capacitor relative to a target voltage, and to generate a modulation signal based on the voltage error of the flying capacitor voltage; and a correction circuit configured to receive the modulation signal and the first pulse width control signal, and configured to modulate the first rising edge and / or the first falling edge based on the modulation signal to provide a corrected first pulse width control signal to the first power switch, thereby adjusting the flying capacitor voltage of the flying capacitor.

[0012] Optionally, the switch converter includes a second power switch; a control circuit is configured to generate a second pulse width control signal for controlling the second power switch, the second pulse width control signal determining the state of the second power switch and having a second rising edge and a second falling edge; and a correction circuit is configured to receive the second pulse width control signal and is configured to modulate the second rising edge and / or the second falling edge based on the modulation signal to provide a corrected second pulse width control signal to the second power switch.

[0013] Optionally, the switch converter includes a third power switch, and the correction circuit is configured to provide a corrected first pulse width control signal to the third power switch, the state of the third power switch being complementary to the inverse state of the second power switch controlled by the corrected second pulse width control signal; and / or the switch converter includes a fourth power switch, and the correction circuit is configured to provide a corrected second pulse width control signal to the fourth power switch, the state of the fourth power switch being complementary to the inverse state of the first power switch controlled by the corrected first pulse width control signal.

[0014] Optionally, the correction circuit is configured as follows:

[0015] The first rising edge and / or the first falling edge are modulated based on differential duty cycle modulation parameters and / or phase shift parameters; and / or

[0016] The second rising edge and / or the second falling edge are modulated based on differential duty cycle modulation parameters and / or phase shift parameters.

[0017] Optionally, the correction circuit is configured to modulate the first falling edge based on the differential duty cycle modulation parameters; and / or the correction circuit is configured to modulate the second rising edge based on the differential duty cycle modulation parameters and the phase shift parameters; and / or the correction circuit is configured to modulate the second falling edge based on the phase shift parameters.

[0018] Optionally, the correction circuit includes a plurality of delay elements configured to independently modulate one, two, three, or four of the following: a first rising edge; a first falling edge; a second rising edge; and a second falling edge.

[0019] Optionally, the correction circuit is configured to: modulate the first rising edge to be equal to a first constant; modulate the first falling edge to be equal to the differential duty cycle modulation parameter and / or phase shift parameter multiplied by a first modulation variable; modulate the second rising edge to be equal to the sum of the differential duty cycle modulation parameter and / or phase shift parameter multiplied by the first modulation variable; and modulate the second falling edge to be equal to the differential duty cycle modulation parameter and / or phase shift parameter multiplied by the first modulation variable.

[0020] Optionally, the correction circuit is configured to: modulate the first rising edge to be equal to -1 multiplied by the first modulation variable; modulate the first falling edge to be equal to the first constant; modulate the second rising edge to be equal to the first constant; and modulate the second falling edge to be equal to 1 multiplied by the first modulation variable.

[0021] Optionally, a first correction signal to the first power switch is generated based on the following equation:

[0022]

[0023] And / or:

[0024] The first correction signal to the first power switch is generated based on the following equation:

[0025]

[0026] Optionally, at least one of the multiple delay elements can be adjusted based on the modulation signal for precise timing control of the first pulse width control signal and / or the second pulse width control signal.

[0027] Optionally, the sensing circuit includes a transconductance amplifier configured to generate a modulated signal based on a proportional current proportional to the voltage error of the flying capacitor.

[0028] Optionally, the transconductance amplifier includes an integral gain component with an integral current, wherein the modulation signal is based on a combination of proportional current and integral current.

[0029] Optionally, the sensing circuit includes a buffer configured to stabilize a reference signal having a static reference voltage.

[0030] Optionally, the correction circuit includes a comparator circuit configured to compare a reference signal based on the modulation signal with a ramp signal and generate a control signal.

[0031] Optionally, the comparator circuit includes a resistor ladder network configured to adjust the delay of the control signal by comparison with a ramp signal.

[0032] Optionally, the control circuit is configured to regulate the voltage of the flying capacitor, which is configured to operate in continuous conduction mode (CCM) and discontinuous conduction mode (DCM) and across multiple operating regions, including: low slew rate (LCR); high slew rate (HCR); and 50% slew rate.

[0033] Optionally, the converter includes an input voltage, and the sensing circuit is configured to:

[0034] i) Measure the input voltage of the converter; and / or

[0035] ii) Measure the output voltage of the converter.

[0036] Optionally, the control and correction circuits are configured to provide stable regulation of the flying capacitor voltage during the transition between continuous conduction mode (CCM) and discontinuous conduction mode (DCM).

[0037] Optionally, the correction circuit includes a set-reset latch configured to maintain the order of the first correction signal and the second correction signal.

[0038] Optionally, a modulation signal is generated to maintain the voltage across the flying capacitor at approximately half the input voltage of the converter.

[0039] Alternatively, the switch converter is a multilevel converter.

[0040] Alternatively, the switching converter is a buck converter, a boost converter, or a buck-boost converter.

[0041] According to a second aspect of this disclosure, a method for controlling a switch converter is provided, the switch converter including a flying capacitor and a first power switch, the method comprising: generating a first pulse width control signal for controlling the first power switch, the first pulse width control signal determining a state of the first power switch and having a first rising edge and a first falling edge; sensing a voltage error of the flying capacitor relative to a target voltage and generating a modulation signal based on the voltage error of the flying capacitor; and modulating the first rising edge and / or the first falling edge based on the modulation signal to provide a corrected first pulse width control signal to the first power switch, thereby adjusting the flying capacitor voltage of the flying capacitor. Brief description of the attached diagram

[0042] The present disclosure is described in more detail below by way of example and with reference to the accompanying drawings, in which:

[0043] Figure 1A This is a schematic diagram of a known 3-level converter in a demagnetizing state;

[0044] Figure 1B This is a schematic diagram of a known 3-level converter in a magnetizing state;

[0045] Figure 1C This is a schematic diagram of a known 3-level converter in the state of charging a flying capacitor;

[0046] Figure 1D This is a schematic diagram of a known 3-level converter in the state of a flying capacitor discharge;

[0047] Figure 2 Figure 200 shows a known low slew rate pulse width modulation control signal curve for a 3-level converter.

[0048] Figure 3 This is a graph of a known high slew rate pulse width modulation control signal used in a 3-level converter;

[0049] Figure 4A It is a known switching node voltage curve for a 3-level converter;

[0050] Figure 4B This is a known inductor current profile used in a 3-level converter;

[0051] Figure 5 It is a known pulse width modulation active balance curve for active flying capacitors;

[0052] Figure 6 The diagram shows the operating range of the load current for a duty cycle of 604 and inductor 104.

[0053] Figure 7 A diagram of double-edge triangular modulation for a 3-level converter is shown;

[0054] Figure 8 The failure mechanism curve is shown;

[0055] Figure 9 A phase shift control scheme using phase shift control is shown;

[0056] Figure 10 A phase shift control graph depicting the limitations of the phase shift control scheme in an LCR DCM is shown;

[0057] Figure 11 This is a schematic diagram of a system for regulating the voltage of a converter having a flying capacitor, according to a first embodiment of the present disclosure;

[0058] Figure 12 This is a graph of a three-edge modulation operation for edge modulation according to a first embodiment of the present disclosure;

[0059] Figure 13A It is a graph of the first gain distribution of the edge modulation method when the input voltage is constant according to the first embodiment of the present disclosure;

[0060] Figure 13B It is a graph of the second gain distribution when the output voltage of the converter is constant according to the first embodiment of the present disclosure;

[0061] Figure 14 This is a graph of LCR DCM operation according to the first embodiment of this disclosure;

[0062] Figure 15 It is a graph of the HCR DCM operation curve according to the first embodiment of this disclosure;

[0063] Figure 16 This is a diagram of a correction circuit and a sensing circuit for receiving Cfly errors according to a first embodiment of the present disclosure;

[0064] Figure 17This is a schematic diagram of a correction circuit implemented according to a second embodiment of the present disclosure;

[0065] Figure 18 This is a schematic diagram of a correction circuit according to a third embodiment of the present disclosure, which is configured to initiate a one-shot pulse of minimum on-time or minimum off-time.

[0066] Figure 19A This is a schematic diagram of a correction circuit according to a second implementation of the fourth embodiment of the present disclosure;

[0067] Figure 19B This is a schematic diagram of the correction circuit 1900b of the third implementation according to the fifth embodiment of this disclosure; and

[0068] Figure 20 This is a diagram of a second correction circuit and a sensing circuit for receiving Cfly errors according to a sixth embodiment of the present disclosure. Detailed description

[0069] Figure 1A This is a schematic diagram of a known 3-level converter 100 in a demagnetized state. Figure 1B This is a schematic diagram of a known 3-level converter 100 in a magnetized state. Figure 1C This is a schematic diagram of a known 3-level converter 100 in the state of charging a flying capacitor. Figure 1D This is a schematic diagram of a known 3-level converter 100 in the state of a flying capacitor discharge. The known 3-level converter 100 will now be described. Figure 1A , Figure 1B , Figure 1C and Figure 1D Furthermore, these graphs can share commonalities across all components.

[0070] The 3-level converter 100 includes four switches 102a, 102b, 102c, and 102d. The 3-level converter also includes an inductor 104, a flying capacitor 106, and an input voltage source 108.

[0071] Four power switches 102a, 102b, 102c, and 102d are arranged in a half-bridge or similar configuration. A switch may refer to the switch used when the flying capacitor (Cfly) 106 is positioned to generate an intermediate voltage level. An inductor 104 is provided for energy storage, switching frequency filtering, and current control.

[0072] The 3-level converter 100 operates in four states: demagnetization, magnetization, flying capacitor charging (Cfly charging), and flying capacitor discharging (Cfly discharging). A brief explanation based on the described states is now provided.

[0073] The state is defined by the combination of the positions of switches 102a, 102b, 102c and 102d and their effects on inductor 104 and flying capacitor 106.

[0074] The switch status is as follows:

[0075] Demagnetizing (DV) state: Switches 102c and 102d are activated (ON), while switches 102a and 102b are deactivated (OFF). During operation, the inductor current maintains its flow without a voltage 108 applied to inductor 104. The inductor current is maintained but does not contribute to the magnetization of the flying capacitor 106.

[0076] Magnetization (DP) state: Switches 102a and 102b are on, and switches 102c and 102d are off. In operation, inductor 104 is directly connected to the input voltage source 108, thereby magnetizing inductor 104 and increasing its current.

[0077] Cfly charging (D1) state: Switches 102a and 102c are on, and switches 102b and 102d are off. During operation, the flying capacitor charges as it is placed in the circuit path of converter 100, transferring energy to bring its voltage closer to the intermediate voltage of input voltage source 108. Flying capacitor 106 is charged to ensure that the intermediate voltage level is maintained.

[0078] Cfly Discharge (D2) State: Switches 102b and 102d are closed, while switches 102a and 102c are open. During operation, the flying capacitor 106 discharges, supplying energy to the inductor 104 and the output load. The capacitor voltage decreases, ensuring a stable energy delivery to the load.

[0079] Pulse Width Modulation (PWM) control is now described. Two complementary PWM signals can be used to control the switch, allowing control between four states: DV, DP, D1, and D2, ensuring a smooth transition between magnetization, demagnetization, and capacitor balance states. Adjusting the periodic duty cycle of the PWM signals allows control of the output voltage while maintaining the flying capacitor voltage at approximately half the input voltage.

[0080] voltage level

[0081] Fundamentally, the converter processes power by utilizing three different voltage levels:

[0082] Full input voltage (DP state);

[0083] Half-input voltage (with Cfly balanced D1 or D2 state);

[0084] Ground / Zero Voltage (DV State).

[0085] One challenge with the 3-level converter 100 is that precise control of the flying capacitor voltage across the charging and discharging states is crucial for stability. Switching timing mismatches or dynamic load conditions can lead to voltage imbalances or increased losses.

[0086] The 3-level converter 100 has the ability to operate in both buck and boost modes while achieving a wide range of conversion rates. The 3-level converter offers several key advantages over conventional 2-level designs.

[0087] 1. The voltage stress across power switches 102a, 102b, 102c, and 104d is reduced by 50%, and the switch size is actually smaller.

[0088] 2. The frequency of inductor 104 has been doubled.

[0089] 3. The peak value of the current ripple of inductor 104 is reduced to one-quarter of its original value, which reduces inductor losses and size.

[0090] By reducing the size and losses of power switches 102a, 102b, 102c, 102d and inductor 104, the topology of the 3-level converter 100 is an ideal candidate for next-generation power conversion in portable devices. However, these advantages are compromised unless the voltage of the flying capacitor (Cfly) 104 is precisely controlled to half of the input voltage source (Vin) 108.

[0091] Due to the inherent unpredictable nature of the flying capacitor voltage, active control is often essential to ensure the stable and optimal operation of converter 100. This control process is commonly referred to as "balancing." Although the voltage of the flying capacitor 106 can converge to its ideal value in some cases without external disturbances, a process known as "natural balancing," this method is typically slow and unreliable. Therefore, active flying capacitor voltage regulation is imperative for this topology.

[0092] Figure 2 Figure 200 shows a known low slew rate pulse width modulation control signal curve for a 3-level converter 100.

[0093] Figure 3 Figure 300 shows a known high slew rate pulse width modulation control signal curve for a 3-level converter 100.

[0094] The known pulse width modulation (PWM) control signal curves 200 and 300 include PWM control signal pairs 202 and 204 with a phase shift of 180 degrees. The sequence of switches 102a, 102b, 102c, and 102d is managed via PWM, as shown below. Figure 2and Figure 3 As shown. Figure 2 The low conversion rate (LCR) operating mode is described, and Figure 3 The high conversion rate (HCR) operating mode is described, where "high" refers to the duty cycle of the pulse width control signals 202 and 204, and the switch is held on for a longer time than in the LCR mode to allow more energy to be transferred to the output and increase the magnetizing current of the inductor.

[0095] The function of the flying capacitor 106 varies depending on the slew rate and operating conditions. The flying capacitor participates most actively near the boundary between high slew rate (HCR) and low slew rate (LCR), where V... out =0.5*V in Define the boundary. At this boundary, the flying capacitor 106 continuously balances the charge to support energy exchange. However, as the converter delves deeper into HCR operation (V... out Approaching V in Or delve deeper into LCR operations (V out When the value approaches 0, the flying capacitor 106 becomes less involved as the energy exchange requirement of the flying capacitor 106 decreases.

[0096] It is also important to note that HCR does not always imply higher power operation. While HCR corresponds to a higher output voltage, the actual power delivered depends on load demand, which may be low even at higher voltages.

[0097] Figure 4A The known switching node voltage curve 400 is used for the 3-level converter 100. Figure 4B The known inductor current curve 450 is used for the 3-level converter 100.

[0098] Figure 4A and Figure 4B The effects of a misaligned flying capacitor 106 are depicted, where the flying capacitor voltage exceeds the 50% threshold 402 of the input voltage source 108. This imbalance results in proportionally excessive voltage stress on switches 102a, 102b, 102c, and 102d, and a deviation 452 in the current of inductor 104 from the expected boundary 454 of the triangular waveform, which in turn leads to increased RMS current and greater power loss.

[0099] The natural balancing mechanism in a 3-level converter 100 is typically weak, making the flying capacitor 106 prone to deviating from the desired voltage level. Several factors can cause this misalignment, including:

[0100] 1. Mismatched timing between charge and discharge switch states caused by skew in the rise and fall times of the gate driver circuit and other internal timing defects.

[0101] 2. Unequal resistances in field-effect transistors (FETs / switches) result in unequal power outputs.

[0102] 3. Imbalance in common-mode capacitance at the two terminals of the flying capacitor 106.

[0103] 4. Current leakage path that can act on flying capacitor 106.

[0104] Addressing these issues individually is impractical, as mismatches and variations will always exist within the converter 100. Furthermore, in modern portable devices, the voltage across the flying capacitor 106 must dynamically track the rapidly changing input voltage source 108, which may occur during load fluctuations or power-in events. Natural balancing mechanisms are too slow to keep pace with the dynamics of the input voltage source 108.

[0105] Figure 5 The known pulse width modulation active balance curve 500 is used for the active flying capacitor 106.

[0106] Figure 5 A method for differential duty cycle modulation of two PWM signals of converter 100 is described, and a Cfly balancing scheme that fails at approximately 50% slew rate is depicted. Voltage is actively maintained using linear compensation controlled by a flying capacitor 106 with a voltage error of 50% relative to the input voltage. Figure 5 The LCR operation is described, illustrating the balancing action of attempting to charge the capacitor when the voltage is below the ideal 0.5*Vin, which is evident in the opposite shifts of the rising edges of PWM1 and PWM2.

[0107] Figure 6 The operating region curve 600 for duty cycle 604 and load current of inductor 104 is shown.

[0108] A conventional pulse width modulation balanced 500 may fail completely under low current loads or near 50% slew rate because the feedback mechanism changes from negative to positive feedback. Figure 6 The positive operating region 602 where the failure occurred and its relationship with duty cycle 604 are depicted.

[0109] Several techniques have been proposed to overcome this problem, but they have limitations, and they will now be described.

[0110] Figure 7 A double-edge triangular modulation curve 700 for a 3-level converter 100 is shown.

[0111] A triangular waveform is used as a reference to determine when the leading and trailing edges of the PWM signal should switch states. It provides symmetry, ensuring consistent timing and equal opportunities for both edges to contribute to modulation. The leading edge (the start of the pulse) and trailing edge (the end of the pulse) are adjusted relative to the triangular waveform. This generates the PWM signal, where the pulse width is effectively controlled by adjusting the combination of the two edges.

[0112] The double-edge triangular modulation curve 700 depicts the modulation of both the leading and trailing edges using a triangular reference signal via pulse width modulation. By performing triangular modulation, and not just on the trailing edge, the dependence of the flying capacitor 106 on the duty cycle operating region can be eliminated.

[0113] However, this method is ineffective within the discontinuous conduction mode (DCM) of operation. DCM not only improves efficiency under light loads but also prevents reverse current flow. This is crucial for facilitating a safe and reliable battery charging process, as reverse power flow can lead to undesirable excessive voltage stress, posing a risk of damage. Since DCM operation is essential in battery charging chips and other power converters in portable devices, a dual-edge delta modulation 700 solution is unsuitable.

[0114] Figure 8 The failure mechanism curve is shown in graph 800. Figure 8 This shows the failure in the DCM HCR operation. Figure 7 The double-edge triangular modulation scheme is depicted in Figure 800. The failure mechanism curve 800 illustrates that the synchronous modulation of the rising and falling edges of the first PWM signal 802 and / or the second PWM signal 804 does not produce a net change in the flying capacitor current during DCM because the states responsible for charging and discharging the capacitor have equal durations and equal net currents, regardless of the duty cycle shift.

[0115] As previously mentioned, regulation losses in this region can lead to significant stress overload and safe-operating-area (SOA) violations in FETs 102a, 102b, 102c, and 102d, particularly during the transition of input voltage source 108.

[0116] Figure 9 A phase shift control scheme 900 using phase shift control is shown.

[0117] In this configuration, the two PWM signals used to control switches 102a, 102b, 102c, and 102d in the 3-level converter 100 are phase-shifted relative to each other while maintaining a fixed duty cycle. The relative phase shift determines whether the switching signals overlap or separate, which affects the timing of the charging and discharging cycles of the flying capacitor 106.

[0118] Because this technology is independent of the inductor current level, it does not exhibit the instability typically seen around 50% slew rate.

[0119] However, similar to the previous method 700, the phase shift control scheme 900 also exhibits ineffectiveness during LCR DCM operation.

[0120] Figure 10 A phase shift control graph 1000 is shown, depicting the limitations of phase shift control scheme 900 in LCR DCM.

[0121] Phase shift control curve 1000 includes a first line graph 1002 depicting the inductor current (iL), and a first dashed line 1004 depicting the inductor current when the phase shift (Δφ) is equal to zero. Phase shift control curve 1000 includes a second line graph 1006 depicting the flying capacitor current (iC). Phase shift control curve 1000 includes a second dashed line graph 1008 depicting the flying capacitor current when the phase shift (Δφ) is equal to zero.

[0122] In LCR operation, the output voltage can be much smaller than the input voltage. In LCR, the PWM signal controlling the switch has a short duty cycle. The phase shift between two PWM signals causes overlap or separation between the signals, affecting the timing of the charging (D1) and discharging (D2) states of the flying capacitor. However, when the duty cycle is very short (close to 0%), where the PWM signal remains high (on) for a very small portion of the switching cycle, there is a finite overlap time. This reduces the effect of phase shift on the correction current of the flying capacitor. Similarly, in deep high slew rate (HCR) operation, where the duty cycle is very high (close to 100%), meaning the PWM signal remains high (on) for almost the entire switching cycle, the overlap becomes excessive, and the effect of phase shift is reduced. When in the magnetized state, the current of inductor 104 is minimal in LCR. This small current means that during the short intervals where phase shift could produce charging or discharging effects, the flying capacitor 106 receives only a weak correction current.

[0123] When in DCM operation, phase shift method 1000 relies on consistent overlap between PWM signals to induce a net correction current in flying capacitor 106.

[0124] In DCM operation, the inductor current 104 becomes discontinuous, dropping to zero during a portion of the switching cycle. This further limits the effectiveness of the phase-shifting method, especially in LCR.

[0125] However, in DCM, the absence of inductor current at the start of the Cfly charging and Cfly discharging states renders these timing adjustments ineffective in LCR, as there is no energy transfer regulation affecting the capacitor voltage. Therefore, the combination of LCR and DCM exacerbates the limitations of the phase-shifting method.

[0126] Other alternative solutions for balancing the flying capacitor 106 include variations of the solutions 700 and 900 already described, or disadvantageously involve the addition of additional circuitry (e.g., using coupled inductors) or filtering components.

[0127] Figure 11 This is a schematic diagram of a system 1100 for regulating the voltage of a converter 100 having a flying capacitor 106, according to a first embodiment of the present disclosure.

[0128] System 1110 includes control circuitry 1102 configured to generate a first pulse width control signal 1120a to control any combination of power switches 102a, 102b, 102c, or 102d. The first pulse width control signal 1120a determines the state of a first power switch and has a first rising edge and a first falling edge. The control circuitry can be configured to generate a second pulse width control signal 1120b to control power switches 102a, 102b, 102c, and 102d that are different from the power switches controlled by the first control signal 1120a.

[0129] System 1110 may further include a correction circuit 1104 that receives a modulation signal 1112 and a first pulse width control signal 1120a, and is configured to modulate a first rising edge and / or a first falling edge of the first pulse width control signal 1120a based on the sensing signal 1112, and generate a first correction signal 1110a to any one of the power switches 102a, 102b, 102c, and 102d, thereby regulating the voltage of the flying capacitor 106. The correction circuit may receive a second pulse width control signal 1120b, and is configured to modulate a second rising edge and / or a second falling edge based on the modulation signal 1112, and generate a second correction signal 1110b to the power switches 102a, 102b, 102c, and 102d.

[0130] Both PWM signals 1120a and 1120b can initially be generated using a closed-loop PWM scheme. Figures 2-10Unlike any prior art where the PWM can directly control the power switches / FETs 102a, 102b, 102c, 102d, the PWM signals 1120a and 1120b are post-processed in the correction circuit 1104.

[0131] Based on the error information of the flying capacitor 106 obtained by the sensing circuit 1106, the relative positions of the rising and falling edges of the PWM1 signal 1120a and the PWM2 signal 1120b are modulated. Modulation can be performed using an edge modulation method that integrates the strengths of differential duty cycle modulation and phase shift methods to ensure complete control of the flying capacitor in all cases. Furthermore, it overcomes the inherent limitations of both methods, such as instability near 50% operation and ineffectiveness in DCM operation. The edge modulation method can modulate the PWM edges as follows:

[0132] • The rising edge of PWM1 1120a is not modulated in real time.

[0133] The time shift duration of the falling edge of PWM1 1120a is d*Ts, which corresponds to the differential duty cycle modulation time.

[0134] The rising edge of PWM2 is shifted over time for a duration of (d+phi)*Ts, which is the sum of the phase shift and differential duty cycle modulation gain.

[0135] The falling edge of PWM2 is shifted in time by phi*Ts, which corresponds to the time of the phase shift technique.

[0136] in:

[0137] •d represents the adjustment of the duty cycle (on-time) of the PWM signal. “d” can be called the differential duty cycle modulation parameter, and can also be expressed as Δd.

[0138] It originates from the voltage error of the flying capacitor and is designed to correct the imbalance in the charging or discharging cycle of the flying capacitor.

[0139] • This modulation ensures that the flying capacitor reaches its target voltage over time.

[0140] Φ / phi represents the phase shift relative to another PWM signal (e.g., PWM1) applied to the PWM signal. “phi” can be referred to as the phase shift parameter and can also be expressed as…

[0141] • Phase shifting adjusts the relative timing between PWM signals, thereby affecting the overlap or separation of switching states. This is crucial for balancing flying capacitors when duty cycle modulation alone is insufficient (e.g., in high slew rate (HCR) modes of discontinuous conduction (DCM)).

[0142] • Ts is the switching period, which is the duration of a complete PWM cycle (the reciprocal of the switching frequency).

[0143] The edge modulation method results in a 2*d difference in the on-time of the correction signals (CS1) 1110a and (CS2) 1110b. CS1 and CS2 introduce the regulation characteristics of the flying capacitor 106 with differential duty cycle modulation.

[0144] Furthermore, this operation also enhances the system gain by introducing a phase shift characteristic through a time-relative shift of phi*Ts between the centers of the PWM1 1120a and PWM2 1120b pulses. In LCR operation, the relationship between the flying capacitor correction current as a function of circuit parameters (i.e., the gain) can be derived as follows:

[0145]

[0146] in:

[0147] ·i Cfly This represents the net current flowing into or out of the flying capacitor 106.

[0148] ·I L It is the current of inductor 104, that is, the average current flowing through inductor 104 of converter 100.

[0149] • Δd represents the duty cycle change (on-time adjustment) applied to the PWM signal to control the voltage across the flying capacitor 106. Δd can be referred to as the differential duty cycle modulation parameter.

[0150] ·V out This indicates the output voltage of converter 100, which involves the energy transfer required to regulate the voltage of flying capacitor 106.

[0151] ·f s This indicates the switching frequency at which converter 100 cycles through the full-state sequence.

[0152] • L represents the value of the inductor in the converter circuit.

[0153] • D is the duty cycle without applying differential duty cycle.

[0154] · This represents the duty cycle phase shift introduced between PWM signals to regulate the voltage across the flying capacitor 106. It can be referred to as the phase shift parameter.

[0155] However, in HCR operation, the edge correction control signal can be derived from the following formula:

[0156]

[0157] in:

[0158] ·V in This indicates the input voltage source 108 of converter 100.

[0159] Figure 12 This is a graph of a 3-edge modulation operation 1200 for edge modulation according to a first embodiment of the present disclosure.

[0160] The 3-edge modulation plot 1200 depicts two digital correction signals 1110a and 1110b that control the operation of the 3-level converter 100. In this example, the first correction signal controls switches 102a and 102d in a complementary manner, and the second correction signal 1110b also controls switches 102b and 102c in a complementary manner.

[0161] Figure 13A This is a graph showing the first gain distribution 1300 of the edge modulation method when the input voltage source 108 is constant according to the first embodiment of the present disclosure. Figure 13B This is a graph showing the second gain distribution 1350 when the output voltage of the converter 100 is constant according to the first embodiment of the present disclosure.

[0162] The gain relationships of the first gain distributions 1300 and 1350 do not change polarity relative to the positive average current of inductor 104 because other parameters such as inductance, switching frequency, and output voltage are greater than zero. As long as the current of inductor 104 is positive, the polarity remains positive, thereby eliminating instability in the 50% region.

[0163] Figure 14 This is a graph of LCR DCM operation 1400 according to the first embodiment of this disclosure. Figure 15 This is a graph of HCR DCM operation 1500 according to the first embodiment of this disclosure.

[0164] Figure 14 and Figure 15 The effectiveness of the edge correction method in LCR DCM and HCR DCM operation is described. The balancing mechanism used in LCR DCM comes from duty cycle differential. In the LCR 1400, the duration of the Cfly charging state is defined by the pulse width of the first control signal 1110a, while the duration of the discharging state is determined by the pulse width of the second control signal 1110b. The edge correction method implements differential timing between these two pulses based on the Cfly error, thereby changing the net flying capacitor current.

[0165] The ability to regulate in HCR DCM operation 1500 stems from the phase shift characteristics. Since the peak current of inductor 104 is determined by the duration of the overlap between PWM signals 1120a and 1120b, the edge-triggered method simultaneously alters the rising and falling edges of 1120b to transmit control signal 1110b, thereby differentially manipulating the current of Cfly 104 in charging and discharging states, thus controlling the net Cfly current on a cycle-by-cycle basis.

[0166] Figure 16 This is a diagram of a correction circuit 1104 and a sensing circuit 1106 for receiving Cfly voltage 1114 according to a first embodiment of the present disclosure.

[0167] The correction circuit 1104 may include a pair of gates 1602a and 1602b, for example Figure 16 The NOT gate is depicted in the diagram. When the correction circuit receives PWM1 1120a and PWM2 1120b, these signals can then be routed to a pair of gates 1602a, 1602b and a path without a gate.

[0168] The correction circuit 1104 may include multiple edge detection components, such as Figure 16 The four edge detection components 1608a, 1608b, 1608c, and 1608d depicted are circuits or devices that detect and respond to changes in signal states, specifically the rising edge (low-to-high transition) and falling edge (high-to-low transition) of pulse width modulation (PWM) signals 1120a and 1120b.

[0169] The correction circuit 1104 may include one or more delay elements, such as Figure 16 The four delay elements 1610a, 1610b, 1610c, and 1610d depicted are variable delay elements 1610a, 1610b, 1610c, and 1610d responsible for dynamically adjusting the timing of the rising and falling edges of the pulse width modulation (PWM) signal based on a gain-adjusted signal 1112 derived from the flying capacitor voltage error 1114. These delay elements 1610a, 1610b, 1610c, and 1610d introduce precise and adjustable delays to achieve accurate timing control of the PWM signal.

[0170] The correction circuit 1104 may include multiple operators, such as Figure 16Adders 1604b, 1604c, 1604d, and multiplier 1604e are depicted. Adders 1604b, 1604c, and 1604d are arithmetic units for combining multiple inputs (e.g., DC offset) and then a gain-adjusted voltage error signal 1112. Multiplier 1604e doubles the value received from gain 1112.

[0171] exist Figure 16 In the depicted configuration, the correction circuit 1104 can modulate the first rising edge to be equal to a first constant. The correction circuit 1104 can modulate the first falling edge to be equal to the differential duty cycle modulation parameter and / or phase shift parameter multiplied by a first modulation variable. The correction circuit 1104 can modulate the second rising edge to be equal to twice the differential duty cycle modulation parameter and / or phase shift parameter multiplied by the first modulation variable. The correction circuit 1104 can modulate the second falling edge to be equal to the differential duty cycle modulation parameter and / or phase shift parameter multiplied by the first modulation variable.

[0172] Please refer to later Figure 20 Alternative embodiments of these modulations are described.

[0173] The correction circuit 1104 may include set-reset (SR) latches 1612a and 1612b, which operate to recreate a pulse width modulation (PWM) signal based on the flying capacitor error voltage 1114. In this case, the set-reset (SR) latches receive inputs from delay elements 1610a and 1610b.

[0174] The correction circuit 1104 may include minimum pulse logic units 1614a and 1614b, which ensure that the final PWM control signals 1110a and 1110b meet the required timing constraints before they are transmitted to control switches 102a, 102b, 102c, and 102d. The minimum pulse logic units 1614a and 1614b can ensure that the PWM signals have a minimum duration for both the on state (switch closed) and the off state (switch open).

[0175] The sensing circuit 1106 may include an arithmetic unit, such as a subtractor 1604a that receives the sensed voltage signal 1114 and the reference signal 1650. The subtractor 1604a can then transmit the voltage error of the flying capacitor 106 to the gain adjustment 1112, which in turn amplifies the voltage error signal.

[0176] Now available Figure 16A general description of the operation. Four variable delay elements 1610a, 1610b, 1610c, and 1610d control PWM signals 1120a and 1120b: two for the rising and falling edges of PWM1 1120a, and two for the rising and falling edges of PWM2 1120b, as shown. Although the delay for the rising edge of PWM1 1120a remains constant, it nominally matches the delays of the other three elements. The delay element responsible for the rising edge of PWM2 1120b doubles the delay for the input signal compared to the other two variable delay elements 1604d and 1604c, because... Then, the delay edge is reconstructed using SR latch circuits 1612a and 1612b.

[0177] Additionally, a minimum pulse block 1614a can be used to ensure minimum PWM on and off times. This block generates a single pulse using each edge, masking the corresponding signal during the pulse period. For example, the rising edge on PWM 1120a and 1120b will generate a minimum on-time pulse, during which any logic low from the outputs of SR latches 1612a and 1612b will be ignored, thus ensuring a minimum on-time. A similar mechanism applies to the minimum off-time, during which any logic high from the outputs of SR latches 1612a and 1612b will be ignored.

[0178] The correction circuit 1104 is flexible and can switch and simulate the characteristics of other methods because Figure 16 The proposed implementation relies on post-processing the PWM signal using variable delay elements 1610a, 1610b, 1610c, 1610d and their variable inputs 1604b, 1604c, 1604d, 1604e.

[0179] In alternative embodiments, the variable delay input paths 1604b, 1604c, 1604d, 1604d can be rerouted, and alternative flying capacitor regulation schemes, including phase shift or differential duty cycle modulation, can be implemented.

[0180] Figure 17 This is a schematic diagram of a correction circuit 1700 according to a first implementation of a second embodiment of the present disclosure.

[0181] The implemented correction circuit 1700 may include a transconductance (Gm) amplifier 1704 that generates a current proportional to the voltage error of the flying capacitor 106 and produces a voltage difference across a series of two resistors 1708a, 1708b, thereby providing the varying threshold voltage required for modulation. The voltage ramp can be a constant ramp rate and a signal varying proportional to the Cfly error. A significant advantage of this approach is its linearity across the entire operating mode range.

[0182] Reference will be made later in this application. Figures 19A-19B Description and Figure 17 Related alternative embodiments.

[0183] The implemented correction circuit 1700 may include a Vref buffer 1706 that provides a static reference voltage, which in a non-limiting example may be 1V for consistent ramp generation.

[0184] The implemented correction circuit 1700 may include four current-on-capacitor (IonC) delay elements 1702a, 1702b, 1702c, and 1702d, configured to perform delay timing adjustments for the rising and falling edges of PWM1 1120a and PWM2 1120b. The IonC delay elements 1702a, 1702b, 1702c, and 1702d may share any characteristics previously described for delay elements 1610a, 1610b, 1610c, and 1610d. Each IonC delay element 1702a, 1702b, 1702c, and 1702d may include a comparator 1710.

[0185] It will be understood that the IonC delay elements 1702a, 1702c, 1702d are merely one embodiment 1700 of this disclosure, and other alternative delay schemes may be considered. For example, delay elements 1702a, 1702b, 1702c, and 1702d may include comparator circuitry configured to compare a modulated signal with a ramp signal and generate a control signal. While this embodiment utilizes comparator 1710 and a reference signal, alternative delay element designs that do not require a comparator are also possible, such as current-starved delay elements. Current-starved delay elements can control the delay of the PWM signal (e.g., rising and / or falling edges) by limiting the current available for charging or discharging the input capacitor of the gate, where the current “starvation” is controlled by an additional transistor acting as a programmable current source, thereby limiting the amount of current flowing through the gate.

[0186] Those skilled in the art can implement other alternative embodiments, such as: a digital delay line comprising a series of flip-flops or a series of shift registers to propagate an input signal; or a ring oscillator for generating a delay using a circuit loop of an inverter; or a voltage-controlled oscillator (VCO) or a voltage-controlled RC network for dynamically adjusting the delay timing based on a control voltage.

[0187] In the currently implemented correction circuit 1700, the IonC ramp and the varying voltage threshold intersect, and comparator 1710 generates a single pulse to indicate the corresponding edges of PWM signals 1120a and 1120b. The IonC delay element used for the rising edge of PWM1 observes a constant Vref voltage, thus remaining unchanged regardless of the Cfly error. The falling edge delay used for both PWM1 1120a and PWM2 1120b observes a varying voltage Vref+I. gm *R, while the rising edge delay of PWM2 sees this differential voltage twice, i.e., Vref+2*I. gm *R, therefore, the delay difference between the two is double.

[0188] in:

[0189] Vref: Fixed voltage

[0190] I gm Transconducting current,

[0191] R:I gm The resistor flowing in.

[0192] The pulses corresponding to the rising and falling edges of PWM1 1120a / PWM2 1120b are fed to set-reset latches 1612a, 1612b to reconstruct the modulated PWM signals that ultimately control the power switches 102a, 102b, 102c, 102d. To maintain signal integrity, SR latches 1612a, 1612b may need to account for the case where the delayed edge sequence is reversed due to significant Cfly errors, but only if such a case is possible.

[0193] Alternatively, connected to Figure 17 The reference voltage Vref at the bottom of resistor 1708b can also be connected to other points along the 2R resistor network without changing the gain, as long as resistors 1708a and 1708b experience the same current flow. For example, it can be connected at the top node of the 2R network or at any midpoint between the top and bottom nodes. This modification will affect which edges are shifted while maintaining the same gain distribution. The basic principle of this adjustment can be to optimize the simulation implementation for different common-mode voltage ranges or in cases where the flying capacitor 106 inherently tends to drift towards a specific non-ideal voltage.

[0194] In a particular alternative embodiment, when Vref is connected to the central node of the 2R network, the rising edge of PWM1 1120a can be modulated; the falling edge of PWM1 1120a can be left unmodulated; the rising edge of PWM2 1120b can be modulated, and the falling edge of PWM2 1120b can be left unmodulated.

[0195] Figure 18 This is a schematic diagram of a correction circuit 1800 according to a third embodiment of the present disclosure, the correction circuit 1800 being configured to initiate a single pulse of minimum on-time or minimum off-time.

[0196] The correction circuit 1800 may share any of the components previously described using the correction circuit 1104 or the correction circuit 1700 implemented.

[0197] The correction circuit 1800 is configured to generate a single pulse for the minimum on-duration or minimum off-duration signal, thereby masking the output using AND and OR gates. The correction circuit 1800 uses this single pulse to control the PWM outputs 1110a and 1110b, ensuring the signals meet the minimum on-duration / minimum off-duration requirements. If the opposite pulse has not yet engaged, the minimum time pulse is triggered by the corresponding edge signal. For example, the minimum time pulse is generated by the rising or falling edge of the PWM signals 1120a and 1120b.

[0198] The rising edge initiates the turn-on cycle, which triggers the minimum turn-on pulse.

[0199] The falling edge initiates the disconnect cycle, which triggers the minimum disconnect pulse.

[0200] The correction circuit 1800 ensures compliance with the Ton Min and Toff Min requirements by issuing a single pulse when the processed PWM pulse is less than the specified minimum on-time (Ton Min) or minimum off-time (Toff Min) duration. This mechanism effectively masks signals that would otherwise violate these timing constraints, thereby maintaining the integrity and stability of PWM operation.

[0201] Figure 19A This is a schematic diagram of a correction circuit 1900a of a second implementation according to a fourth embodiment of the present disclosure. Figure 19B This is a schematic diagram of a correction circuit 1900b implemented according to a fifth embodiment of the present disclosure.

[0202] The second implementation of the correction circuit 1900a and the third implementation of the correction circuit 1900b may share all the components previously discussed with respect to the first implementation of the correction circuit 1700, and where possible, the reference numerals shall remain the same.

[0203] The second implemented correction circuit 1900a includes a differential transconductance (Gm) amplifier 1902 having a negative node output and a positive node output. The negative node is connected to the delay element 1702d via a first connection 1906. The positive node is connected to the delay element 1702a via a second connection 1908.

[0204] The third implementation of the correction circuit includes a first differential amplifier 1904a with positive polarity (+gm) and a second differential amplifier 1904b with negative polarity (-gm). The negative node is connected to the delay element 1702d via a first connection 1906. The positive node is connected to the delay element 1702a via a second connection 1908. The second differential amplifier 1904b is connected to the delay element 1702d via the first connection 1906. The first differential amplifier 1904a is connected to the delay element 1702a via the second connection 1908.

[0205] The second implementation of the correction circuit 1900a and the third implementation of the correction circuit 1900b may include an integral gain component that generates an integral current.

[0206] The second implementation of the correction circuit 1900a and the third implementation of the correction circuit 1900b do not require the Vref buffer 1706 for signal decoupling.

[0207] Figure 20 This is a diagram of a second correction circuit 2000 and a sensing circuit 1106 for receiving Cfly error 1114 according to a sixth embodiment of the present disclosure.

[0208] The second correction circuit 2000 may share components with the previously described correction circuit 1104, and where possible, all reference numerals shall remain the same.

[0209] The second correction circuit 2000 may include a multiplier 1604f that multiplies the gain 1606 by a negative 1.

[0210] exist Figure 20 In the described configuration, the correction circuit 2000 can modulate the first rising edge to be equal to -1 multiplied by the first modulation variable. The correction circuit 2000 can modulate the first falling edge to be equal to the first constant. The correction circuit 2000 can modulate the second rising edge to be equal to the first constant. The correction circuit 2000 can modulate the second falling edge to be equal to 1 multiplied by the first modulation variable.

[0211] It will be understood that the reference to the first pulse width modulation signal is merely a naming convention; it could refer to PWM11120a or PWM21120b. Similarly, the reference to the second pulse width control signal could refer to PWM21120b or PWM11120a, which was not selected to define the first pulse width modulation signal.

[0212] This disclosure includes, but is not limited to, the following terms.

[0213] Clause 1. A control system for a switching converter, the switching converter including a flying capacitor and a first power switch, the control system comprising:

[0214] A control circuit is configured to generate a first pulse width control signal for controlling the first power switch, the first pulse width control signal determining the state of the first power switch and having a first rising edge and a first falling edge;

[0215] A sensing circuit configured to sense the voltage error of the flying capacitor voltage relative to a target voltage, and to generate a modulation signal based on the voltage error of the flying capacitor voltage; and

[0216] A correction circuit is configured to receive the modulation signal and the first pulse width control signal, and is configured to modulate the first rising edge and / or the first falling edge based on the modulation signal to provide a corrected first pulse width control signal to the first power switch, thereby adjusting the flying capacitor voltage of the flying capacitor.

[0217] Clause 2. The control system pursuant to Clause 1, wherein:

[0218] The switch converter includes a second power switch;

[0219] The control circuit is configured to generate a second pulse width control signal for controlling the second power switch, the second pulse width control signal determining the state of the second power switch and having a second rising edge and a second falling edge; and

[0220] The correction circuit is configured to receive the second pulse width control signal and to modulate the second rising edge and / or the second falling edge based on the modulation signal to provide a corrected second pulse width control signal to the second power switch.

[0221] Clause 3. The control system as described in Clause 2, wherein:

[0222] The switch converter includes a third power switch, and the correction circuit is configured to provide the corrected first pulse width control signal to the third power switch, the state of the third power switch being complementary to the inverse state of the second power switch controlled by the corrected second pulse width control signal; and / or

[0223] The switch converter includes a fourth power switch, and the correction circuit is configured to provide the fourth power switch with the corrected second pulse width control signal, the state of the fourth power switch being complementary to the inverse state of the first power switch controlled by the corrected first pulse width control signal.

[0224] Clause 4. The control system according to Clause 3, wherein the correction circuit is configured as follows:

[0225] The first rising edge and / or the first falling edge are modulated based on differential duty cycle modulation parameters and / or phase shift parameters; and / or

[0226] The second rising edge and / or the second falling edge are modulated based on the differential duty cycle modulation parameters and / or the phase shift parameters.

[0227] Clause 5. The control system as described in Clause 4, wherein:

[0228] The correction circuit is configured to modulate the first falling edge based on the differential duty cycle modulation parameters; and / or

[0229] The correction circuit is configured to modulate the second rising edge based on the differential duty cycle modulation parameters and the phase shift parameters; and / or

[0230] The correction circuit is configured to modulate the second falling edge based on the phase shift parameter.

[0231] Clause 6. The control system according to Clause 5, wherein the correction circuit comprises a plurality of delay elements configured to independently modulate one, two, three, or four of the following:

[0232] The first rising edge;

[0233] The first falling edge;

[0234] The second rising edge; and

[0235] The second falling edge.

[0236] Clause 7. The control system according to Clause 6, wherein the correction circuit is configured to:

[0237] Modulate the first rising edge to be equal to the first constant;

[0238] The first falling edge is modulated to be equal to the differential duty cycle modulation parameter and / or phase shift parameter multiplied by the first modulation variable;

[0239] The second rising edge is modulated to be twice the following: the differential duty cycle modulation parameter and / or phase shift parameter multiplied by the first modulation variable; and

[0240] The second falling edge is modulated to be equal to the differential duty cycle modulation parameter and / or phase shift parameter multiplied by the first modulation variable.

[0241] Clause 8. The control system according to Clause 6, wherein the correction circuit is configured to:

[0242] Modulate the first rising edge to be equal to -1 multiplied by the first modulation variable;

[0243] Modulate the first falling edge to be equal to the first constant;

[0244] Modulate the second rising edge into a first constant;

[0245] The second falling edge is modulated to be equal to 1 multiplied by the first modulation variable.

[0246] Clause 9. The control system according to Clause 6, wherein a first correction signal to the first power switch is generated based on the following equation:

[0247]

[0248] And / or:

[0249] The first correction signal to the first power switch is generated based on the following equation:

[0250]

[0251] Clause 10. The control system according to Clause 6, wherein at least one of the plurality of delay elements is adjustable based on the modulation signal for precise timing control of the first pulse width control signal and / or the second pulse width control signal.

[0252] Clause 11. The control system according to Clause 10, wherein the sensing circuit comprises:

[0253] A transconductance amplifier configured to generate a modulation signal based on a proportional current that is proportional to the voltage error of the flying capacitor.

[0254] Clause 12. The control system according to Clause 11, wherein the transconductance amplifier includes an integral gain component having an integral current, and wherein the ramp signal is based on a combination of the proportional current and the integral current.

[0255] Clause 13. The control system according to Clause 12, wherein the sensing circuit comprises:

[0256] A buffer is configured to stabilize a reference signal with a static reference voltage.

[0257] Clause 14. The control system according to Clause 13, wherein the correction circuit includes a comparator circuit configured to compare the reference signal based on the modulation signal with the ramp signal and generate the control signal.

[0258] Clause 15. The control system according to Clause 14, wherein the comparator circuit includes a resistor ladder network configured to adjust the delay of the control signal by comparison with the ramp signal.

[0259] Clause 16. The control system according to Clause 15, wherein the control circuit is configured to regulate the voltage of the flying capacitor, the flying capacitor being configured to operate in a continuous conduction mode (CCM) and a discontinuous conduction mode (DCM) and across a plurality of operating regions, the plurality of operating regions including:

[0260] Low conversion rate (LCR);

[0261] High conversion efficiency (HCR); and

[0262] 50% conversion rate.

[0263] Clause 17. The control system according to Clause 16, wherein the converter includes an input voltage, and the sensing circuit is configured to:

[0264] Measure the input voltage of the converter; and / or

[0265] Measure the output voltage of the converter.

[0266] Clause 18. The control system according to Clause 17, wherein the control circuit and the correction circuit are configured to provide stable regulation of the flying capacitor voltage during the transition between continuous conduction mode (CCM) and discontinuous conduction mode (DCM).

[0267] Clause 19. The control system according to Clause 18, wherein the modulation signal is generated to maintain the voltage of the flying capacitor at approximately half of the input voltage of the converter.

[0268] Clause 20. A method for controlling a switching converter, the switching converter including a flying capacitor and a first power switch, the method comprising:

[0269] A first pulse width control signal is generated to control the first power switch, the first pulse width control signal determining the state of the first power switch and having a first rising edge and a first falling edge;

[0270] Sensing the voltage error of the flying capacitor relative to the target voltage, and generating a modulation signal based on the voltage error of the flying capacitor; and

[0271] The first rising edge and / or the first falling edge are modulated based on the modulation signal to provide a corrected first pulse width control signal to the first power switch, thereby adjusting the flying capacitor voltage of the flying capacitor.

Claims

1. A control system for a switching converter, the switching converter including a flying capacitor and a first power switch, the control system comprising: A control circuit is configured to generate a first pulse width control signal for controlling the first power switch, the first pulse width control signal determining the state of the first power switch and having a first rising edge and a first falling edge; A sensing circuit configured to sense the voltage error of the flying capacitor voltage relative to a target voltage, and to generate a modulation signal based on the voltage error of the flying capacitor voltage; and A correction circuit is configured to receive the modulation signal and the first pulse width control signal, and is configured to modulate the first rising edge and / or the first falling edge based on the modulation signal to provide a corrected first pulse width control signal to the first power switch, thereby adjusting the flying capacitor voltage of the flying capacitor.

2. The control system according to claim 1, wherein: The switch converter includes a second power switch; The control circuit is configured to generate a second pulse width control signal for controlling the second power switch, the second pulse width control signal determining the state of the second power switch and having a second rising edge and a second falling edge; and The correction circuit is configured to receive the second pulse width control signal and to modulate the second rising edge and / or the second falling edge based on the modulation signal to provide a corrected second pulse width control signal to the second power switch.

3. The control system according to claim 2, wherein: The switch converter includes a third power switch, and the correction circuit is configured to provide the corrected first pulse width control signal to the third power switch, the state of the third power switch being complementary to the inverse state of the second power switch controlled by the corrected second pulse width control signal; and / or The switch converter includes a fourth power switch, and the correction circuit is configured to provide the fourth power switch with the corrected second pulse width control signal, the state of the fourth power switch being complementary to the inverse state of the first power switch controlled by the corrected first pulse width control signal.

4. The control system according to claim 3, wherein, The correction circuit is configured as follows: The first rising edge and / or the first falling edge are modulated based on differential duty cycle modulation parameters and / or phase shift parameters; and / or The second rising edge and / or the second falling edge are modulated based on the differential duty cycle modulation parameters and / or the phase shift parameters.

5. The control system according to claim 4, wherein: The correction circuit is configured to modulate the first falling edge based on the differential duty cycle modulation parameters; and / or The correction circuit is configured to modulate the second rising edge based on the differential duty cycle modulation parameters and the phase shift parameters; and / or The correction circuit is configured to modulate the second falling edge based on the phase shift parameter.

6. The control system according to claim 5, wherein, The correction circuit includes a plurality of delay elements, which are configured to independently modulate one, two, three, or four of the following: The first rising edge; The first falling edge; The second rising edge; and The second falling edge.

7. The control system according to claim 6, wherein: The correction circuit is configured as follows: i) Modulate the first rising edge to be equal to the first constant; ii) Modulate the first falling edge to be equal to the differential duty cycle modulation parameter and / or phase shift parameter multiplied by the first modulation variable; iii) Modulate the second rising edge to twice the following: the differential duty cycle modulation parameter and / or phase shift parameter multiplied by the first modulation variable; and iv) Modulate the second falling edge to be equal to the differential duty cycle modulation parameter and / or phase shift parameter multiplied by the first modulation variable; or The correction circuit is configured as follows: i) Modulate the first rising edge to be equal to -1 multiplied by the first modulation variable; ii) Modulate the first falling edge to be equal to the first constant; iii) Modulate the second rising edge to be equal to the first constant; and iv) Modulate the second falling edge to be equal to 1 multiplied by the first modulation variable.

8. The control system according to claim 6, wherein, A first correction signal is generated for the first power switch based on the following equation: And / or: The first correction signal to the first power switch is generated based on the following equation:

9. The control system according to claim 6, wherein: At least one of the plurality of delay elements can be adjusted based on the modulation signal for precise timing control of the first pulse width control signal and / or the second pulse width control signal; The sensing circuit includes a transconductance amplifier configured to generate a modulation signal based on a proportional current proportional to the voltage error of the flying capacitor; and The transconductance amplifier includes an integral gain component with an integral current, and wherein the ramp signal is based on a combination of the proportional current and the integral current.

10. The control system according to claim 9, wherein, The sensing circuit includes: A buffer is configured to stabilize a reference signal with a static reference voltage.

11. The control system according to claim 10, wherein, The correction circuit includes a comparator circuit configured to compare the reference signal based on the modulation signal with the ramp signal and generate the control signal.

12. The control system according to claim 11, wherein, The comparator circuit includes a resistor ladder network configured to adjust the delay of the control signal by comparison with the ramp signal.

13. The control system according to claim 12, wherein, The control circuit is configured to regulate the voltage of the flying capacitor, which is configured to operate in continuous conduction mode (CCM) and discontinuous conduction mode (DCM) and across multiple operating regions, the multiple operating regions including: Low conversion rate (LCR); High conversion efficiency (HCR); and 50% conversion rate.

14. A method for controlling a switching converter, the switching converter including a flying capacitor and a first power switch, the method comprising: A first pulse width control signal is generated to control the first power switch, the first pulse width control signal determining the state of the first power switch and having a first rising edge and a first falling edge; The voltage error of the flying capacitor relative to the target voltage is sensed, and a modulation signal is generated based on the voltage error of the flying capacitor; and The first rising edge and / or the first falling edge are modulated based on the modulation signal to provide a corrected first pulse width control signal to the first power switch, thereby adjusting the flying capacitor voltage of the flying capacitor.

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