Wide gain range programmable gain amplifier circuit with high precision dB linearity

Abstract

The application discloses a wide gain range programmable gain amplifier circuit with high-precision dB linearity, converts the tuning of the circuit gain into the resistance ratio through a self-biasing circuit, uses the ratio to fit a pseudo-exponential function, realizes fine-tuning of the dB linearity, and uses the characteristics of the circuit itself to take the ratio of the transconductance as coarse tuning, thereby realizing hybrid exponential function control of the circuit gain. Compared with the programmable gain amplifier in the prior art, the application breaks the conventional mode in the closed loop, uses the limitation that the high-performance operational amplifier converts the gain tuning into the resistance ratio, proposes a brand-new open loop mode to control the circuit gain, and realizes the tuning of the wide gain control range under lower power consumption. In addition, the wide gain range programmable gain amplifier circuit proposed by the application can be used in various receivers with the demand of wide gain adjustment range, and is suitable for a wide range of applications.

Description

Technical Field

[0001] This invention belongs to the field of radio frequency receiver technology, and specifically relates to a programmable gain amplifier circuit with high-precision dB linearity and a wide gain range. Background Technology

[0002] In recent years, with the development of big data analytics and artificial intelligence, the demands on signal processing speeds have increased rapidly, and the bandwidth of received signals has continued to grow. This necessitates Automatic Generation Control (AGC) systems to adapt to a wide range of signal bandwidth, operating frequency, and power requirements. AGC systems are widely used in modern communication and signal processing systems, including software-defined radios, state-of-the-art automotive radar systems, millimeter-wave imaging, local area networks (LANs), and wide dynamic range optical receivers. With the development of AGC systems and the diversification of application scenarios, achieving robust variable gain amplifiers with a wider gain range at lower power consumption has become a research hotspot.

[0003] Variable gain amplifiers typically need to achieve a wider gain range. There are generally two ways to achieve a wide-range variable gain amplifier: one is to cascade identical unit amplifiers, and the other is to combine coarse-tuning stages and fine-tuning stages. The first method results in a doubling of power consumption, accumulation of gain error, and attenuation of system bandwidth. Furthermore, it often requires a DC offset cancellation circuit to eliminate the DC offset error caused by multiple cascaded stages. The second method avoids the problems of increased power consumption and error accumulation inherent in cascaded structures, but still faces the challenge of designing high-precision fine-tuning stage circuits and requires attention to the superposition of power consumption. Conventional methods for achieving dB linearity require an additional exponential function relationship generation circuit, further increasing power consumption.

[0004] To improve the robustness of variable gain amplifiers, high-performance operational amplifiers are typically used. These amplifiers utilize the ideal approximation of virtual short and virtual open characteristics to convert gain changes into a closed-loop resistance ratio. However, achieving dB linearity in this approach requires high-performance operational amplifiers, increasing design complexity. Furthermore, the closed-loop operation also needs to consider stability issues within the loop. Summary of the Invention

[0005] To overcome the shortcomings of existing technologies, this invention provides a wide-gain-range programmable gain amplifier circuit with high-precision dB linearity. It converts circuit gain tuning into a resistance ratio through a self-biasing circuit, and uses this ratio to fit a pseudo-exponential function to achieve fine-tuning dB linearity. Furthermore, utilizing the circuit's inherent characteristics, the transconductance ratio is used as a coarse adjustment, achieving hybrid exponential function control of the circuit gain. Compared to existing programmable gain amplifiers, this invention breaks away from the conventional closed-loop operation method, which relies on high-performance operational amplifiers to convert gain tuning into a resistance ratio. It proposes a novel open-loop method for controlling circuit gain, achieving a wide gain control range with lower power consumption. Moreover, the novel wide-gain-range programmable gain amplifier circuit proposed in this invention can be used in various receivers requiring a wide gain adjustment range, making it widely applicable.

[0006] The technical solution adopted by this invention to solve its technical problem is as follows: A wide-gain-range programmable gain amplifier circuit with dB linearity includes a first PMOS transistor M1, a second PMOS transistor M2, a transconductor array module GM, a load array module GML, a common-mode feedback module CMFB1, a self-bias module, and a zero-signal control terminal. S 0. First signal control terminal S 1. Second signal control terminal S 2. Third signal control terminal S 3. Fourth signal control terminal S 4. Fifth signal control terminal S— 3. Sixth signal control terminal S— 4. First electronic switch S1a, second electronic switch S1b, third electronic switch S1c, fourth electronic switch S2a, fifth electronic switch S2b, sixth electronic switch S2c, seventh electronic switch S3a, eighth electronic switch S3b, ninth electronic switch S3c, tenth electronic switch S4a, eleventh electronic switch S4b, twelfth electronic switch S5a, thirteenth electronic switch S5b, fourteenth electronic switch S6a, fifteenth electronic switch S6b, sixteenth electronic switch S7a, seventeenth electronic switch S7b, eighteenth electronic switch S8a, and nineteenth electronic switch S8b; The transconductor array module GM is used to change the equivalent input transconductance; the load array module GML is used to change the equivalent circuit load; the common-mode feedback module CMFB1 is used to ensure the stability of the DC voltage at each node of the circuit; and the self-bias module Self-Bias is used to provide bias current to the main circuit and convert the control gain change into a resistance ratio value. The output of the self-bias module Self-Bias is a voltage signal VBN, which is connected to the current NMOS transistors of the transconductor array module GM and the load array module GML to provide bias voltage. The inputs of the transconductor array module GM include the differential voltage signal positive phase input terminal VIP, the differential voltage signal negative phase input terminal VIN, and the voltage signal VBN; The input to the load array module GML is the voltage signal VBN; The output of the high-precision dB linear wide-gain-range programmable gain amplifier circuit includes a differential voltage signal positive output terminal VOP and a differential voltage signal negative output terminal VON; the sources of the first PMOS transistor M1 and the second PMOS transistor M2 are connected to the power supply voltage VDD, and their drains are connected to the differential voltage signal negative output terminal VON and the differential voltage signal positive output terminal VOP, respectively. The common-mode feedback module CMFB1 is divided into a first common-mode feedback input terminal, a second common-mode feedback input terminal and a third common-mode feedback input terminal. The first common-mode feedback input terminal is connected to VON, the second common-mode feedback input terminal is connected to the common-mode reference voltage VCM, and the third common-mode feedback input terminal is connected to VOP. The output terminal of the common-mode feedback module CMFB1 is connected to the gates of the first PMOS transistor M1 and the second PMOS transistor M2. The transconductor array module GM comprises three layers, each layer consisting of eight field-effect transistors and a resistor array; the first layer consists of field-effect transistors M3a to M10a and resistor array R1 Array a, the second layer consists of field-effect transistors M3b to M10b and resistor array R1 Array b, and the third layer consists of field-effect transistors M3c to M10c and resistor array R1 Array c. The load array module GML comprises three layers, each layer containing four field-effect transistors (FETs); the first layer consists of FETs M10a to M14a, the second layer consists of FETs M10b to M14b, and the third layer consists of FETs M10c to M14c.

[0007] Preferably, the self-biasing module Self-Bias circuit includes a fifteenth PMOS transistor M15, a sixteenth PMOS transistor M16, a common-mode feedback module CMFB2, a four-way comparator Amp1, a resistor R2, a seventeenth NMOS transistor M17, an eighteenth NMOS transistor M18, and a nineteenth NMOS transistor M19. The output of the self-bias module, Self-Bias, is a VBN voltage signal, which is connected to the NMOS current transistor of the programmable gain amplifier circuit to provide bias voltage. The sources of the fifteenth PMOS transistor M15 and the sixteenth PMOS transistor M16 are connected to the power supply voltage VDD, and their drains are connected to the two ends of resistor R2 respectively. The drain of the fifteenth PMOS transistor M15 is connected to the source of the seventeenth NMOS transistor M17, the drain of the sixteenth PMOS transistor M16 is connected to the source of the eighteenth NMOS transistor M18, the source of the seventeenth NMOS transistor M17 is connected to the source of the eighteenth NMOS transistor M18, and the drain of the nineteenth NMOS transistor M19. The source of the nineteenth NMOS transistor M19 is connected to GND. The first common-mode feedback input terminal of the common-mode feedback module CMFB2 is connected to the drain terminal of the fifteenth PMOS transistor M15, and the second common-mode feedback input terminal is connected to the common-mode reference voltage VCM. The three common-mode feedback input terminals are connected to the drain of the sixteenth PMOS transistor M16. The output terminal of the common-mode feedback module CMFB2 is connected to the gates of the fifteenth PMOS transistor M15 and the sixteenth PMOS transistor M16. The gate of the seventeenth NMOS transistor M17 is connected to the positive reference voltage Vref+, and the gate of the eighteenth NMOS transistor M18 is connected to the negative reference voltage Vref-. The four-channel comparator Amp1 is divided into a first positive input terminal, a first negative input terminal, a second positive input terminal, and a second negative input terminal. The first positive input terminal is connected to the drain of the seventeenth NMOS transistor M17, the first negative input terminal is connected to the drain of the eighteenth NMOS transistor M18, the second positive input terminal is connected to the gate of the eighteenth NMOS transistor M18, and the second negative input terminal is connected to the gate of the seventeenth NMOS transistor M17. The output of the four-channel comparator Amp1 is connected to the gate of the nineteenth NMOS transistor M19, and outputs the bias voltage signal VBN. In the Self-Bisa circuit of the self-biasing module, the value of R2 is n times the minimum value in the R1 resistor array.

[0008] Preferably, in the transconductor array module GM, the two ends of resistor array R1 Array a are connected to the sources of M3a and M4a, the two ends of resistor array R1 Array b are connected to the sources of M3b and M4b, and the two ends of resistor array R1 Array c are connected to the sources of M3c and M4c. The drains of M3a and M7a in the transconductor array module GM and the drain of M11a in the load array module are connected to VON; the drains of M3b and M7b in the transconductor array module GM are connected to the input terminal of the twelfth electronic switch S5a, and the drains of M3c and M7c are connected to the input terminal of the thirteenth electronic switch S5b; the drain of M11b in the load array module GML is connected to the input terminal of the sixteenth electronic switch S7a, and the drain of M11c is connected to the input terminal of the seventeenth electronic switch S7b; the output terminals of S5a, S5b, S7a, and S7b are connected to VON; the drains of M4a and M8a in the transconductor array module GM and the drain of M12a in the load array module are connected to VON. VOP; In the transconductor array module GM, the drains of M4b and M8b are connected to the input of the fourteenth electronic switch S6a, and the drains of M4c and M8c are connected to the input of the fifteenth electronic switch S6b. In the load array module GML, the drain of M12b is connected to the input of the eighteenth electronic switch S8a, and the drain of M12c is connected to the input of the nineteenth electronic switch S8b. The outputs of S6a, S6b, S8a, and S8b are connected to VOP; The sources of M7a, M8a, M9a, and M10a are connected; the sources of M7b, M8b, M9b, and M10b are connected; and the sources of M7c, M8c, M9c, and M10c are connected.

[0009] Preferably, in the load array module GML, the drain of M11a is connected to the gate, the drain of M11b is connected to the gate, the drain of M11c is connected to the gate, the drain of M12a is connected to the gate, the drain of M12b is connected to the gate, and the drain of M12c is connected to the gate; the source of M11a, the source of M12a, the drain of M13a, and the drain of M14a are connected, and the source of M11b, the source of M12b, the drain of M13b, and the drain of M14b are connected.

[0010] Preferably, in the transconductor array module GM and the load array module GML, the sources M11c, M12c, M13c, and M14c are connected together, and the sources M5a, M6a, M9a, M10a, M13a, M14a, M5b, M6b, M9b, M10b, M13b, M14b, M5c, M6c, M9c, M10c, M13c, and M14c are connected to GND. In the transconductor array module GM and the load array module GML, the gates M5a, M6a, M9a, M10a, M13a, M14a, M5b, M6b, M9b, M10b, M13b, M14b, M5c, M6c, M9c, M10c, M13c, and M14c are connected to the bias voltage VBN.

[0011] Preferably, the output voltages of the positive output terminal VOP and the negative output terminal VON of the differential voltage signal are 180° out of phase; the input of the wide gain range programmable gain amplifier circuit with high-precision dB linearity includes a positive input terminal VIP and a negative input terminal VIN of the differential voltage signal, and the input voltages of the positive input terminal VIP and the negative input terminal VIN of the differential voltage signal are 180° out of phase.

[0012] Preferably, the field-effect transistors M3a, M3b, M3c, M4a, M4b, and M4c are completely identical; M5a, M5b, M5c, M6a, M6b, and M6c are completely identical; M7a, M7b, M7c, M8a, M8b, and M8c are completely identical; M9a, M9b, M9c, M10a, M10b, and M10c are completely identical; M11a, M11b, M11c, M12a, M12b, and M12c are completely identical; and M13a, M13b, M13c, M14a, M14b, and M14c are completely identical.

[0013] Preferably, the first to nineteenth electronic switches are composed of transistors; different voltages are input to the first to nineteenth electronic switches as needed to control the opening and closing of the electronic switches. When a low voltage is input to the switching transistor, the switching transistor is turned off, and when a high voltage is input to the switching transistor, the switching transistor is turned on.

[0014] Preferably, S1a, S1b, and S1c are controlled by the zero signal terminal. S 0 control, S2a, S2b, and S2c are controlled by the first signal control terminal. S 1. Control: S3a, S3b, and S3c are controlled by the second signal control terminal. S 2. Control, S5a is controlled by the third signal terminal. S 3. Control, S5b is controlled by the fifth signal control terminal. S— 3. Control, S6a is controlled by the fourth signal terminal. S 4. Control, S6b is controlled by the sixth signal terminal. S— 4. Control; The third signal control terminal S 3. Fifth signal control terminal S—3 is a complementary signal; when one is 1, the other is 0; the fourth signal control terminal. S 4. Sixth signal control terminal S— 4 represents complementary signals; when one signal is 1, the other is 0. Preferably, the aspect ratios of the field-effect transistors M3a, M4a, M7a, M8a, M11a, and M12a are 1:1:0.5:0.5:1.5:1.5; and the aspect ratios of the field-effect transistors M3b, M4b, M7b, M8b, M11b, and M12b are 1:1:0.5:0.5:1.5:1.5. The aspect ratio is 1:1:0.5:0.5:1.5:1.5; the aspect ratios of M3c, M4c, M7c, M8c, M11c, and M12c are 1:1:0.5:0.5:1.5:1.5; the aspect ratios of M5a, M6a, M9a, and M10a are... The aspect ratios of M13a and M14a are 1:1:0.5:0.5:1.5:1.5; the aspect ratios of M5b, M6b, M9b, M10b, M13b, and M14b are 1:1:0.5:0.5:1.5:1.5; the aspect ratios of M5c and M6c are... The aspect ratios of M9c, M10c, M13c, and M14c are 1:1:0.5:0.5:1.5:1.5; the aspect ratio of M19 is twice that of M5a, M6a, M5b, M6b, M5c, and M6c; the aspect ratios of M17 and M18 are the same as those of M3a, M4a, M3b, M4b, M3c, and M4c.

[0015] The beneficial effects of this invention are as follows: This invention utilizes a binary weighted switch to achieve precise dB linear gain control by approximating a pseudo-exponential function, eliminating the need for an additional exponential generation circuit. To ensure fine-tuning accuracy, a novel scheme for fitting an inverse pseudo-value function is employed, transforming the tuning method into the ratio of open-loop adjustment resistors. To simultaneously achieve a small gain step size and a wide gain range in the fine-tuning stage, and to minimize power consumption by cascading as few coarse-tuning gain amplifiers as possible, a hybrid gain control scheme combines the inverse pseudo-exponential approximation and the actual exponential approximation in the fine-tuning stage. Compared to traditional methods, this invention achieves both low power consumption and a wide gain control range in a single fine-tuning stage, presenting a novel programmable gain amplifier circuit with high-precision dB linearity and a wide gain range. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of the present invention; Figure 2 This is a schematic diagram illustrating the inventive process concept of an embodiment of the present invention; Figure 2 (a) is the circuit structure of a conventional source degradation structure; Figure 2 (b) is the amplifier transconductance stage circuit structure proposed in this invention; Figure 3 This is a schematic diagram of the Self-Bias circuit of the self-biasing module provided in an embodiment of the present invention; Figure 4 This is a schematic diagram of the parallel circuit in the GM transconductor array structure provided in the embodiment of the present invention; Figure 5 This is a schematic diagram of the parallel circuit in the GML load array structure provided in the embodiment of the present invention; Figure 6 This is the connection method between the GM transconductor array and the switch provided in the embodiment of the present invention. The connection of the parallel GM transconductors to the circuit is controlled by the switches S5a, S5b, S6a, and S6b. Figure 7 This is the connection method between the GML load array and the switch provided in the embodiment of the present invention, which controls whether the parallel GM transconductor is connected to the circuit through switches S7a, S7b, S8a, and S8b. Figure 8 This is a schematic diagram of the resistor array used in one of the arrays of the GM transconductor array provided in the embodiment of the present invention. The resistor array is connected to the circuit by three switches S1a, S2a, and S3a. Figure 9 The simulation results of the amplifier circuit frequency response provided in the embodiment of the present invention demonstrate that the present invention can achieve gain tuning from -26.2 to 0.9 dB while maintaining a consistent bandwidth during gain changes. Figure 10 These are simulation results of the amplifier circuit voltage gain and gain error provided in the embodiments of the present invention. Detailed Implementation

[0017] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0018] This invention provides a wide-gain-range programmable gain amplifier circuit with high-precision dB linearity, comprising a first PMOS transistor M1, a second PMOS transistor M2, a transconductor array module GM, a load array module GML, a common-mode feedback module CMFB1, a self-bias module, and a zero-signal control terminal. S 0. First signal control terminal S 1. Second signal control terminal S 2. Third signal control terminal S3. Fourth signal control terminal S 4. Fifth signal control terminal S— 3. Sixth signal control terminal S— 4; First electronic switch S1a, second electronic switch S1b, third electronic switch S1c, fourth electronic switch S2a, fifth electronic switch S2b, sixth electronic switch S2c, seventh electronic switch S3a, eighth electronic switch S3b, ninth electronic switch S3c, tenth electronic switch S4a, eleventh electronic switch S4b, twelfth electronic switch S5a, thirteenth electronic switch S5b, fourteenth electronic switch S6a, fifteenth electronic switch S6b, sixteenth electronic switch S7a, seventeenth electronic switch S7b, eighteenth electronic switch S8a, nineteenth electronic switch S8b; The self-bias module circuit includes a fifteenth PMOS transistor M15, a sixteenth PMOS transistor M16, a common-mode feedback module CMFB2, a four-way comparator Amp1, a resistor R2, a seventeenth NMOS transistor M17, an eighteenth NMOS transistor M18, and a nineteenth NMOS transistor M19. The transconductor array module GM is used to change the equivalent input transconductance; the load array module GML is used to change the equivalent circuit load; the common-mode feedback module CMFB1 is used to ensure the stability of the DC voltage at each node of the circuit; and the self-bias module Self-Bias is used to provide bias current to the main circuit and convert the control gain change into a resistance ratio value. The inputs of the transconductor array module GM include a differential voltage signal positive input terminal VIP and a differential voltage signal negative input terminal VIN, and its bias current is the NMOS transistor bias voltage signal VBN. The inputs of the load array module GML include its bias current, the NMOS transistor bias voltage signal VBN. The outputs of the high-precision dB linear wide gain range programmable gain amplifier circuit include a differential voltage signal positive output terminal VOP and a differential voltage signal negative output terminal VON. The sources of the first PMOS transistor M1 and the second PMOS transistor M2 are connected to the power supply voltage VDD, and their drains are connected to the differential voltage signal negative output terminal VON and the differential voltage signal positive output terminal VOP, respectively. The common-mode feedback module CMFB1 is divided into a first common-mode feedback input terminal, a second common-mode feedback input terminal, and a third common-mode feedback input terminal. The first common-mode feedback input terminal is connected to VON, the second common-mode feedback input terminal is connected to the common-mode reference voltage VCM, and the third common-mode feedback input terminal is connected to VOP. The output of the common-mode feedback module CMFB1 is connected to the gates of M1 and M2. In the transconductor array module GM, the two ends of resistor array R1 Array a are connected to the sources of M3a and M4a, the two ends of resistor array R1 Array b are connected to the sources of M3b and M4b, and the two ends of resistor array R1 Array c are connected to the sources of M3c and M4c. In transconductor array module GM, the drains of M3a and M7a, and the drain of M11a in the load array module are connected to VON. In transconductor array module GM, the drains of M3b and M7b are connected to the input of switch S5a, and the drains of M3c and M7c are connected to the input of switch S5b. In load array module GML, the drain of M11b is connected to the input of switch S7a, and the drain of M11c is connected to the input of switch S7b. The outputs of S5a, S5b, S7a, and S7b are connected to VON. In transconductor array module GM, the drains of M4a and M8a, and the drain of M12a in the load array module are connected to VON. In the transconductor array module GM, the drains of M4b and M8b are connected to the input of switch S6a, and the drains of M4c and M8c are connected to the input of switch S6b. In the load array module GML, the drain of M12b is connected to the input of switch S8a, and the drain of M12c is connected to the input of switch S8b. The outputs of S6a, S6b, S8a, and S8b are connected to VOP. The sources of M7a, M8a, M9a, and M10a are connected together; the sources of M7b, M8b, M9b, and M10b are connected together; and the sources of M7c, M8c, M9c, and M10c are connected together. In the load array module GML, the drain of M11a is connected to the gate, the drain of M11b is connected to the gate, the drain of M11c is connected to the gate, the drain of M12a is connected to the gate, the drain of M12b is connected to the gate, and the drain of M12c is connected to the gate; the source of M11a, the source of M12a, the drain of M13a, and the drain of M14a are connected, and the source of M11b, the source of M12b, the drain of M13b, and the drain of M14b are connected. In the transconductor array module GM and the load array module GML, the sources M11c, M12c, M13c, and M14c are connected together, and the sources M5a, M6a, M9a, M10a, M13a, M14a, M5b, M6b, M9b, M10b, M13b, M14b, M5c, M6c, M9c, M10c, M13c, and M14c are connected to GND. In the transconductor array module GM and the load array module GML, the gates M5a, M6a, M9a, M10a, M13a, M14a, M5b, M6b, M9b, M10b, M13b, M14b, M5c, M6c, M9c, M10c, M13c, and M14c are connected to the bias voltage VBN. The output of the self-bias module, Self-Bias, is a VBN voltage signal, which is connected to the NMOS current transistor of the programmable gain amplifier circuit to provide bias voltage. The sources of the fifteenth PMOS transistor M15 and the sixteenth PMOS transistor M16 are connected to the power supply voltage VDD, and their drains are connected to the two ends of resistor R2 respectively. The drain of the fifteenth PMOS transistor M15 is connected to the source of the seventeenth NMOS transistor M17, the drain of the sixteenth PMOS transistor M16 is connected to the source of the eighteenth NMOS transistor M18, the source of the seventeenth NMOS transistor M17 is connected to the source of the eighteenth NMOS transistor M18, and the drain of the nineteenth NMOS transistor M19. The source of the nineteenth NMOS transistor M19 is connected to GND. The common-mode feedback module CMFB2 is divided into a first common-mode feedback input terminal, a second common-mode feedback input terminal, and a third common-mode feedback input terminal. The common-mode feedback input is connected to the drain of the fifteenth PMOS transistor M15, the second common-mode feedback input is connected to the common-mode reference voltage VCM, and the third common-mode feedback input is connected to the drain of the sixteenth PMOS transistor M16. The output of the common-mode feedback module CMFB2 is connected to the gates of M15 and M16. The gate of M17 is connected to the positive reference voltage Vref+, and the gate of M18 is connected to the negative reference voltage Vref-. The four-channel comparator Amp1 is divided into a first positive input, a first negative input, a second positive input, and a second negative input. The first positive input is connected to the drain of M17, the first negative input is connected to the drain of M18, the second positive input is connected to the gate of M18, and the second negative input is connected to the gate of M17. The output of the four-channel comparator Amp1 is connected to the gate of M19 and outputs the bias voltage signal VBN. The output of the wide-gain-range programmable gain amplifier circuit with high-precision dB linearity includes a differential voltage signal positive output terminal VOP and a differential voltage signal negative output terminal VON, with the output voltages of the differential voltage signal positive output terminal VOP and the differential voltage signal negative output terminal VON differing by 180° in phase; the input of the wide-gain-range programmable gain amplifier circuit with high-precision dB linearity includes a differential voltage signal positive input terminal VIP and a differential voltage signal negative input terminal VIN, with the input voltages of the differential voltage signal positive input terminal VIP and the differential voltage signal negative input terminal VIN differing by 180° in phase. M3a, M3b, M3c, M4a, M4b, M4c are completely identical; M5a, M5b, M5c, M6a, M6b, M6c are completely identical; M7a, M7b, M7c, M8a, M8b, M8c are completely identical; M9a, M9b, M9c, M10a, M10b, M10c are completely identical; M11a, M11b, M11c, M12a, M12b, M12c are completely identical; M13a, M13b, M13c, M14a, M14b, M14c are completely identical. In the Self-Bisa circuit of the self-biasing module, the value of R2 is n times the minimum value in the R1 resistor array; The first to the nineteenth electronic switches are composed of transistors. Different voltages are input to the first to the nineteenth electronic switches as needed to control the opening and closing of the electronic switches. When a low voltage is input to the switching transistor, the switching transistor is turned off, and when a high voltage is input to the switching transistor, the switching transistor is closed.

[0019] Electronic switches S1a, S2a, and S3a control whether the resistor in R1 Array a is connected to the circuit; electronic switches S1b, S2b, and S3b control whether the resistor in R1 Array b is connected to the circuit; electronic switches S1c, S2c, and S3c control whether the resistor in R1 Array c is connected to the circuit; electronic switches S5a, S6a, S5b, and S6b control whether the transconductor array GM and the load array GML are connected to the circuit. Electronic switches S1a, S1b, and S1c are generated by the zero signal. S 0 control, electronic switches S2a, S2b, and S2c are controlled by the first signal S 1. Control: Electronic switches S3a, S3b, and S3c are controlled by the second signal. S 2. Control: Electronic switch S5a is controlled by the third signal control terminal. S 3. Control, S5b is controlled by the fifth signal control terminal. S— 3. Control, S6a is controlled by the fourth signal terminal. S 4. Control, S6b is controlled by the sixth signal terminal. S— 4. Control; Third signal control terminal S 3. Fifth signal control terminal S— 3 is a complementary signal; when one is 1, the other is 0. The fourth signal control terminal... S 4. Sixth signal control terminal S— 4 represents complementary signals; when one signal is 1, the other is 0. The aspect ratios of M3a, M4a, M7a, M8a, M11a, and M12a are 1:1:0.5:0.5:1.5:1.5, and the aspect ratios of M3b, M4b, M7b, M8b, M11b, and M12b are 1: The aspect ratios of M3c, M4c, M7c, M8c, M11c, and M12c are 1:1:0.5:0.5:1.5:1.5. The aspect ratios of M5a, M6a, M9a, M10a, and M13a are also 1:0.5:0.5:1.5:1.5. The aspect ratio of M14a is 1:1:0.5:0.5:1.5:1.5; the aspect ratios of M5b, M6b, M9b, M10b, M13b, and M14b are 1:1:0.5:0.5:1.5:1.5; the aspect ratios of M5c, M6c, and M9... The aspect ratios of M10c, M13c, and M14c are 1:1:0.5:0.5:1.5:1.5; the aspect ratio of M19 is twice that of M5a, M6a, M5b, M6b, M5c, and M6c; the aspect ratios of M17 and M18 are the same as those of M3a, M4a, M3b, M4b, M3c, and M4c.

[0020] Example: To achieve dB linearity, the low-frequency gain of the circuit typically needs to satisfy a pseudo-valued function variation, such as... Figure 2 As shown in (a), the equivalent Gm of the traditional source degradation structure is expressed as:

[0021] By combining and comparing the above formula with the inverse pseudo-exponential function formula, it is found that when... Figure 2 (b) shows that by subtracting half the transconductance of the common-source MOSFET from the equivalent Gm of the source degradation structure, we can obtain:

[0022] The above formula has a good correspondence with the anti-pseudo-value function. Finally, by using a diode-connected MOSFET as a load, we can obtain the following:

[0023] The final gain formula divides the gain into two parts:

[0024]

[0025] The first part consists of the amplifier circuit. g m1 *R The value of 1 controls the second part, which is controlled by an amplifier circuit. g m1 and diode load circuit g m2 Ratio control.

[0026] like Figure 3 The gain formula for the self-bias circuit shown is:

[0027] When using a four-way comparator circuit to ensure that the input voltage equals the output voltage, that is, when the gain equals 1...

[0028]

[0029] This allows the transconductance of the amplifier tube to be converted into a function related to the resistance.

[0030] A common-mode feedback circuit stabilizes the drain voltages of M17 and M18 at the same voltage as the amplifier transistor in the anti-pseudo-value generation circuit. This is to prevent the output node impedance from being different from the voltage across the amplifier transistor. nR 1. A significant deviation occurs to improve factor detection and adaptive biasing capabilities. Vref is set to a DC voltage difference of 100mV to simulate an AC state equivalent to the circuit. High loop gain is achieved by adjusting the tail current. I B To adjust g m1 This continues until the condition VOUT=Vref is met.

[0031] The dimensions of the amplifying transistor and the tail current transistor are set proportionally to those of the inverse pseudo-value function generation circuit, and the drain voltages of M17 and M18 are set to the same value as the common-mode input voltage of the main circuit. The adaptive bias circuit is used as a current mirror to replicate the tail current gate voltage to the inverse pseudo-value function generation circuit, so that... I B The corresponding gm equals 1 / nR 1. At this point, for the inverse pseudo-exponential function... x 1 is transformed into:

[0032] at this time x The change of 1 depends only on the ratio of the two resistors, realizing the transformation of the independent variable of an open-loop system, and using the ratio of the resistors to realize the fine-tuning function of the PGA. like Figure 4The image shows one of the parallel circuit implementations in a GM transconductor array, as follows: Figure 8 The diagram shows the connection method of the resistor array in this circuit. For example... Figure 5 The diagram shows one of the parallel circuit implementations in a GML load array. For example... Figure 6 , Figure 7 The diagram shows the connection method between the GM transconductor array and the GML load array and the switch.

[0033] Make sure the transconductance of the load transistors M11 and M12 connected to the diodes is consistent with that of the amplifier transistors M3 and M4. Multiply the two parts of the gain formula as a mixed exponential function, and approximate it as the product of an exponential function and a power function.

[0034] When we can through To achieve proportional adjustment, we can implement it as an exponential function.

[0035] Can be used x 1 and x 2. Adjust the gain of the two power functions. The first part is used as the fine-tuning stage, and the second part is used as the coarse-tuning stage. The base α of the power function is determined by the gain range of the first fine-tuning stage. The purpose is to make the gain change range of the fine-tuning stage equal to the step size of the coarse-tuning stage, so as to minimize the gain error and avoid the accumulation of gain error. Control words via the lower three digits S1 Controlling the on / off state of the resistor array switches in the transconductor array GM S1 The size is controlled according to requirements; among which S1 = 2 0 S 0+ 2 1 S 1+2 2 S 2; At this point, the first part of the gain changes as follows:

[0036] Digital control word S2 The control determines whether the transconductor array GM and the load array GML are connected to the circuit. The value of S2 is 0, 1, 2, or 3. When S2 is 0, the second gain is at its maximum; when it is 1 or 2, the second gain is at an intermediate value, the same for both; when S2 is 3, the second gain is at its minimum. To ensure constant circuit bandwidth and current density, a complementary switching structure is used to realize the change of the actual exponential function. At this time, the coarse adjustment can be achieved. α The change of =3 is achieved through two complementary switches. x2 varies between -1 and 1. Therefore, the coarse adjustment step size is approximately 9 dB.

Claims

1. A programmable gain amplifier circuit with dB linearity and a wide gain range, characterized in that, Includes a first PMOS transistor M1, a second PMOS transistor M2, a transconductor array module GM, a load array module GML, a common-mode feedback module CMFB1, a self-bias module, and a zero-signal control terminal. S 0. First signal control terminal S 1. Second signal control terminal S 2. Third signal control terminal S 3. Fourth signal control terminal S 4. Fifth signal control terminal S— 3. Sixth signal control terminal S— 4. First electronic switch S1a, second electronic switch S1b, third electronic switch S1c, fourth electronic switch S2a, fifth electronic switch S2b, sixth electronic switch S2c, seventh electronic switch S3a, eighth electronic switch S3b, ninth electronic switch S3c, tenth electronic switch S4a, eleventh electronic switch S4b, twelfth electronic switch S5a, thirteenth electronic switch S5b, fourteenth electronic switch S6a, fifteenth electronic switch S6b, sixteenth electronic switch S7a, seventeenth electronic switch S7b, eighteenth electronic switch S8a, and nineteenth electronic switch S8b; The transconductor array module GM is used to change the equivalent input transconductance; the load array module GML is used to change the equivalent circuit load; the common-mode feedback module CMFB1 is used to ensure the stability of the DC voltage at each node of the circuit; and the self-bias module Self-Bias is used to provide bias current to the main circuit and convert the control gain change into a resistance ratio value. The output of the self-bias module Self-Bias is a voltage signal VBN, which is connected to the current NMOS transistors of the transconductor array module GM and the load array module GML to provide bias voltage. The inputs of the transconductor array module GM include the differential voltage signal positive phase input terminal VIP, the differential voltage signal negative phase input terminal VIN, and the voltage signal VBN; The input to the load array module GML is the voltage signal VBN; The output of the high-precision dB linear wide-gain-range programmable gain amplifier circuit includes a differential voltage signal positive output terminal VOP and a differential voltage signal negative output terminal VON; the sources of the first PMOS transistor M1 and the second PMOS transistor M2 are connected to the power supply voltage VDD, and their drains are connected to the differential voltage signal negative output terminal VON and the differential voltage signal positive output terminal VOP, respectively. The common-mode feedback module CMFB1 is divided into a first common-mode feedback input terminal, a second common-mode feedback input terminal and a third common-mode feedback input terminal. The first common-mode feedback input terminal is connected to VON, the second common-mode feedback input terminal is connected to the common-mode reference voltage VCM, and the third common-mode feedback input terminal is connected to VOP. The output terminal of the common-mode feedback module CMFB1 is connected to the gates of the first PMOS transistor M1 and the second PMOS transistor M2. The transconductor array module GM comprises three layers, each layer consisting of eight field-effect transistors and a resistor array; the first layer consists of field-effect transistors M3a to M10a and resistor array R1 Array a, the second layer consists of field-effect transistors M3b to M10b and resistor array R1 Array b, and the third layer consists of field-effect transistors M3c to M10c and resistor array R1 Array c. The load array module GML comprises three layers, each layer containing four field-effect transistors (FETs); the first layer consists of FETs M10a to M14a, the second layer consists of FETs M10b to M14b, and the third layer consists of FETs M10c to M14c.

2. The programmable gain amplifier circuit with dB linearity over a wide gain range according to claim 1, characterized in that, The self-bias module circuit includes a fifteenth PMOS transistor M15, a sixteenth PMOS transistor M16, a common-mode feedback module CMFB2, a four-way comparator Amp1, a resistor R2, a seventeenth NMOS transistor M17, an eighteenth NMOS transistor M18, and a nineteenth NMOS transistor M19. The output of the self-bias module, Self-Bias, is a VBN voltage signal, which is connected to the NMOS current transistor of the programmable gain amplifier circuit to provide bias voltage. The sources of the fifteenth PMOS transistor M15 and the sixteenth PMOS transistor M16 are connected to the power supply voltage VDD, and their drains are connected to the two ends of resistor R2 respectively. The drain of the fifteenth PMOS transistor M15 is connected to the source of the seventeenth NMOS transistor M17, the drain of the sixteenth PMOS transistor M16 is connected to the source of the eighteenth NMOS transistor M18, the source of the seventeenth NMOS transistor M17 is connected to the source of the eighteenth NMOS transistor M18, and the drain of the nineteenth NMOS transistor M19. The source of the nineteenth NMOS transistor M19 is connected to GND. The first common-mode feedback input terminal of the common-mode feedback module CMFB2 is connected to the drain terminal of the fifteenth PMOS transistor M15, and the second common-mode feedback input terminal is connected to the common-mode reference voltage VCM. The three common-mode feedback input terminals are connected to the drain of the sixteenth PMOS transistor M16. The output terminal of the common-mode feedback module CMFB2 is connected to the gates of the fifteenth PMOS transistor M15 and the sixteenth PMOS transistor M16. The gate of the seventeenth NMOS transistor M17 is connected to the positive reference voltage Vref+, and the gate of the eighteenth NMOS transistor M18 is connected to the negative reference voltage Vref-. The four-channel comparator Amp1 is divided into a first positive input terminal, a first negative input terminal, a second positive input terminal, and a second negative input terminal. The first positive input terminal is connected to the drain of the seventeenth NMOS transistor M17, the first negative input terminal is connected to the drain of the eighteenth NMOS transistor M18, the second positive input terminal is connected to the gate of the eighteenth NMOS transistor M18, and the second negative input terminal is connected to the gate of the seventeenth NMOS transistor M17. The output of the four-channel comparator Amp1 is connected to the gate of the nineteenth NMOS transistor M19, and outputs the bias voltage signal VBN. In the Self-Bisa circuit of the self-biasing module, the value of R2 is n times the minimum value in the R1 resistor array.

3. The programmable gain amplifier circuit with dB linearity over a wide gain range according to claim 1, characterized in that, In the transconductor array module GM, the two ends of resistor array R1 Array a are connected to the sources of M3a and M4a, the two ends of resistor array R1 Array b are connected to the sources of M3b and M4b, and the two ends of resistor array R1 Array c are connected to the sources of M3c and M4c. The drains of M3a and M7a in the transconductor array module GM and the drain of M11a in the load array module are connected to VON; the drains of M3b and M7b in the transconductor array module GM are connected to the input terminal of the twelfth electronic switch S5a, and the drains of M3c and M7c are connected to the input terminal of the thirteenth electronic switch S5b; the drain of M11b in the load array module GML is connected to the input terminal of the sixteenth electronic switch S7a, and the drain of M11c is connected to the input terminal of the seventeenth electronic switch S7b; the output terminals of S5a, S5b, S7a, and S7b are connected to VON; the drains of M4a and M8a in the transconductor array module GM and the drain of M12a in the load array module are connected to VON. VOP; In the transconductor array module GM, the drains of M4b and M8b are connected to the input of the fourteenth electronic switch S6a, and the drains of M4c and M8c are connected to the input of the fifteenth electronic switch S6b. In the load array module GML, the drain of M12b is connected to the input of the eighteenth electronic switch S8a, and the drain of M12c is connected to the input of the nineteenth electronic switch S8b. The outputs of S6a, S6b, S8a, and S8b are connected to VOP; The sources of M7a, M8a, M9a, and M10a are connected; the sources of M7b, M8b, M9b, and M10b are connected; and the sources of M7c, M8c, M9c, and M10c are connected.

4. The programmable gain amplifier circuit with dB linearity over a wide gain range according to claim 1, characterized in that, In the load array module GML, the drain of M11a is connected to the gate, the drain of M11b is connected to the gate, the drain of M11c is connected to the gate, the drain of M12a is connected to the gate, the drain of M12b is connected to the gate, and the drain of M12c is connected to the gate; the source of M11a, the source of M12a, the drain of M13a, and the drain of M14a are connected, and the source of M11b, the source of M12b, the drain of M13b, and the drain of M14b are connected.

5. The programmable gain amplifier circuit with dB linearity over a wide gain range according to claim 1, characterized in that, In the transconductor array module GM and the load array module GML, the sources M11c, M12c, M13c, and M14c are connected together, and the sources M5a, M6a, M9a, M10a, M13a, M14a, M5b, M6b, M9b, M10b, M13b, M14b, M5c, M6c, M9c, M10c, M13c, and M14c are connected to GND. In the transconductor array module GM and the load array module GML, the gates M5a, M6a, M9a, M10a, M13a, M14a, M5b, M6b, M9b, M10b, M13b, M14b, M5c, M6c, M9c, M10c, M13c, and M14c are connected to the bias voltage VBN.

6. The programmable gain amplifier circuit with dB linearity over a wide gain range according to claim 1, characterized in that, The output voltages of the positive output terminal VOP and the negative output terminal VON of the differential voltage signal are 180° out of phase; the input of the wide gain range programmable gain amplifier circuit with high-precision dB linearity includes the positive input terminal VIP and the negative input terminal VIN of the differential voltage signal, and the input voltages of the positive input terminal VIP and the negative input terminal VIN of the differential voltage signal are 180° out of phase.

7. A programmable gain amplifier circuit with dB linearity over a wide gain range according to claim 1, characterized in that, The field-effect transistors M3a, M3b, M3c, M4a, M4b, and M4c are completely identical; M5a, M5b, M5c, M6a, M6b, and M6c are completely identical; M7a, M7b, M7c, M8a, M8b, and M8c are completely identical; M9a, M9b, M9c, M10a, M10b, and M10c are completely identical; M11a, M11b, M11c, M12a, M12b, and M12c are completely identical; and M13a, M13b, M13c, M14a, M14b, and M14c are completely identical.

8. A programmable gain amplifier circuit with dB linearity over a wide gain range according to claim 1, characterized in that, The first to nineteenth electronic switches are composed of transistors. Different voltages are input to the first to nineteenth electronic switches as needed to control the opening and closing of the electronic switches. When a low voltage is input to the switching transistor, the switching transistor is turned off, and when a high voltage is input to the switching transistor, the switching transistor is closed.

9. A programmable gain amplifier circuit with dB linearity over a wide gain range according to claim 1, characterized in that, S1a, S1b, and S1c are controlled by the zero signal terminal. S 0 control, S2a, S2b, and S2c are controlled by the first signal control terminal. S 1. Control: S3a, S3b, and S3c are controlled by the second signal control terminal. S 2. Control, S5a is controlled by the third signal terminal. S 3. Control, S5b is controlled by the fifth signal control terminal. S— 3. Control, S6a is controlled by the fourth signal terminal. S 4. Control, S6b is controlled by the sixth signal terminal. S— 4. Control; The third signal control terminal S 3. Fifth signal control terminal S— 3 is a complementary signal; when one is 1, the other is 0; the fourth signal control terminal. S 4. Sixth signal control terminal S— 4 represents complementary signals; when one signal is 1, the other is 0.

10. A programmable gain amplifier circuit with dB linearity over a wide gain range according to claim 1, characterized in that, The aspect ratios of the field-effect transistors M3a, M4a, M7a, M8a, M11a, and M12a are 1:1:0.5:0.5:1.5:1.5; the aspect ratios of the field-effect transistors M3b, M4b, M7b, M8b, M11b, and M12b are 1:1:0.5:0.5:1.

5. The aspect ratios are 1:1:0.5:0.5:1.5:1.5; the aspect ratios of M3c, M4c, M7c, M8c, M11c, and M12c are 1:1:0.5:0.5:1.5:1.5; the aspect ratios of M5a, M6a, M9a, M10a, and M1... The aspect ratios of M3a and M14a are 1:1:0.5:0.5:1.5:1.5; the aspect ratios of M5b, M6b, M9b, M10b, M13b, and M14b are 1:1:0.5:0.5:1.5:1.5; the aspect ratios of M5c, M6c, and M... The aspect ratios of M9c, M10c, M13c, and M14c are 1:1:0.5:0.5:1.5:1.5; the aspect ratio of M19 is twice that of M5a, M6a, M5b, M6b, M5c, and M6c; the aspect ratios of M17 and M18 are the same as those of M3a, M4a, M3b, M4b, M3c, and M4c.

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